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| mpc5 65um/d 9/2002 rev 2 mpc565/mpc566 user?s manual
how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments: fax (512) 933-2625 attn: tecd applications engineering motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. contents section number title page number motorola contents iii contents paragraph number title page number chapter 1 overview 1.1 introduction.......................................................................................................... 1-1 1.2 block diagram ..................................................................................................... 1-2 1.2.1 detailed feature list........................................................................................ 1-3 1.3 differences between the mpc565/mpc566 and the mpc555/mpc556 ............ 1-8 1.3.0.1 sram keep-alive power behavior ......................................................... 1-10 1.4 memory map ..................................................................................................... 1-11 chapter 2 signal descriptions 2.1 pad function description..................................................................................... 2-1 2.1.1 mpc565/mpc566 module pin muxing .......................................................... 2-6 2.2 pad module configuration register (pdmcr)................................................... 2-6 2.3 pad module configuration register (pdmcr2)................................................. 2-8 2.4 signal descriptions .............................................................................................. 2-8 2.4.1 usiu pads........................................................................................................ 2-8 2.4.1.1 addr[8:31] / sgpioa[8:31]..................................................................... 2-8 2.4.1.2 data[0:31] / sgpiod[0:31]...................................................................... 2-9 2.4.1.3 irq0 / sgpioc0 ......................................................................................... 2-9 2.4.1.4 irq1 / rsv / sgpioc1 .............................................................................. 2-9 2.4.1.5 irq2 / cr / sgpioc2 / mts ..................................................................... 2-9 2.4.1.6 irq 3/kr / retry / sgpioc3 .............................................................. 2-10 2.4.1.7 irq4 / at2 / sgpioc4 ............................................................................. 2-10 2.4.1.8 irq5 / sgpioc5 / modck1 ................................................................... 2-10 2.4.1.9 irq[6:7] / modck[2:3]........................................................................... 2-11 2.4.1.10 tsiz[0:1] ................................................................................................... 2-11 2.4.1.11 rd / wr .................................................................................................... 2-11 2.4.1.12 burst ...................................................................................................... 2-11 2.4.1.13 bdip .......................................................................................................... 2-11 2.4.1.14 ts............................................................................................................... 2-11 2.4.1.15 ta .............................................................................................................. 2-12 2.4.1.16 tea............................................................................................................ 2-12 2.4.1.17 rstconf / texp .................................................................................... 2-12 contents paragraph number title page number iv mpc565/mpc566 reference manual motorola 2.4.1.18 oe .............................................................................................................. 2-12 2.4.1.19 bi / sts ..................................................................................................... 2-12 2.4.1.20 cs[0:3]....................................................................................................... 2-13 2.4.1.21 we[0:3] / be[0:3] / at[0:3]...................................................................... 2-13 2.4.1.22 poreset / trst ..................................................................................... 2-13 2.4.1.23 hreset .................................................................................................... 2-14 2.4.1.24 sreset..................................................................................................... 2-14 2.4.1.25 sgpioc6 / frz / ptr .............................................................................. 2-14 2.4.1.26 sgpioc7 / irqout / lwp0.................................................................... 2-14 2.4.1.27 bg / vf0 / lwp1 ...................................................................................... 2-15 2.4.1.28 br / vf1 / iwp2 ....................................................................................... 2-15 2.4.1.29 bb / vf2 / iwp3 ....................................................................................... 2-15 2.4.1.30 iwp[0:1] / vfls[0:1]................................................................................ 2-15 2.4.1.31 tms ........................................................................................................... 2-16 2.4.1.32 tdi / dsdi ................................................................................................ 2-16 2.4.1.33 tck / dsck.............................................................................................. 2-16 2.4.1.34 tdo / dsdo ............................................................................................. 2-16 2.4.1.35 jcomp ...................................................................................................... 2-16 2.4.1.36 xtal ......................................................................................................... 2-17 2.4.1.37 extal....................................................................................................... 2-17 2.4.1.38 xfc............................................................................................................ 2-17 2.4.1.39 clkout ................................................................................................... 2-17 2.4.1.40 extclk.................................................................................................... 2-17 2.4.1.41 vddsyn................................................................................................... 2-17 2.4.1.42 vsssyn .................................................................................................... 2-17 2.4.1.43 engclk / buclk .................................................................................. 2-18 2.4.1.44 pull_sel ................................................................................................ 2-18 2.4.2 qsmcm a / qsmcm b / dlcmd2 (j1850) pads...................................... 2-18 2.4.2.1 pcs0 / ss / qgpio0 ................................................................................. 2-19 2.4.2.2 pcs[1:2] / qgpio[1:2] ............................................................................. 2-19 2.4.2.3 pcs3 / qgpio3 / j1850_tx..................................................................... 2-19 2.4.2.4 miso / qgpio4 ........................................................................................ 2-19 2.4.2.5 mosi / qgpio5 ........................................................................................ 2-19 2.4.2.6 sck / qgpio6 .......................................................................................... 2-20 2.4.2.7 txd[1:2] / qgpo[1:2].............................................................................. 2-20 2.4.2.8 rxd[1:2] / qgpi[1:2], rxd1 / qgpi1, rxd2 / j 1850_rx .................. 2-20 2.4.2.9 eck ........................................................................................................... 2-20 2.4.3 mios14 pads................................................................................................. 2-21 2.4.3.1 mda[11, 13, 27, 30] ................................................................................. 2-21 2.4.3.2 mda[12, 14, 28, 31] ................................................................................. 2-21 2.4.3.3 mda[15, 27:31] ........................................................................................ 2-21 contents paragraph number title page number motorola contents v 2.4.3.4 mpwm[0:3] .............................................................................................. 2-21 2.4.3.5 mpwm[16, 18].......................................................................................... 2-21 2.4.3.6 mpwm[17, 19].......................................................................................... 2-22 2.4.3.7 vf[0:2] / mpio32b[0:2]........................................................................... 2-22 2.4.3.8 vfls[0:1] / mpio32b[3:4] ...................................................................... 2-22 2.4.3.9 mpwm[4:5] / mpio32b[5:6]................................................................... 2-22 2.4.3.10 mdo[7:4] / mpio32b[7:10]..................................................................... 2-23 2.4.3.11 mpwm[20:21] / mpio32b[11:12] ........................................................... 2-23 2.4.3.12 c_cntx0 / c_cnrx0 / mpio32b[13:14] ............................................. 2-23 2.4.3.13 mpio32b15............................................................................................... 2-23 2.4.4 32-khz oscillator pads ................................................................................. 2-23 2.4.4.1 xtal32 ..................................................................................................... 2-23 2.4.4.2 extal32................................................................................................... 2-24 2.4.4.3 vddrtc ................................................................................................... 2-24 2.4.4.4 vssrtc .................................................................................................... 2-24 2.4.5 tpu3 a, b, and c pads ................................................................................. 2-24 2.4.5.1 a_tpuch[0:15], b_tpuch[0:15], c_tpuch[0:15] ............................ 2-24 2.4.5.2 t2clk....................................................................................................... 2-24 2.4.6 qadc64 a and b pads ................................................................................. 2-24 2.4.6.1 etrig[1:2]................................................................................................ 2-24 2.4.6.2 an44 / anw / pqb0 ................................................................................ 2-25 2.4.6.3 an45 / anx / pqb1 ................................................................................. 2-25 2.4.6.4 an46 / any / pqb2 ................................................................................. 2-25 2.4.6.5 an47 / anz / pqb3 ................................................................................. 2-25 2.4.6.6 an[48:51] / pqb[4:7] ............................................................................... 2-26 2.4.6.7 an[52:54] / ma[0:2] / pqa[0:2].............................................................. 2-26 2.4.6.8 an[55:59] / pqa[3:7]............................................................................... 2-26 2.4.6.9 an[64:71] / pqb[0:7] ............................................................................... 2-26 2.4.6.10 an[72:74] / ma[0:2] / pqa[0:2].............................................................. 2-27 2.4.6.11 an[75:79] / pqa[3:7]............................................................................... 2-27 2.4.6.12 an[80:87].................................................................................................. 2-27 2.4.6.13 vrh........................................................................................................... 2-27 2.4.6.14 vrl ........................................................................................................... 2-27 2.4.6.15 altref..................................................................................................... 2-27 2.4.6.16 vdda........................................................................................................ 2-28 2.4.6.17 vssa ......................................................................................................... 2-28 2.4.7 toucan a, b, and c pads .......................................................................... 2-28 2.4.7.1 cntx0 ...................................................................................................... 2-28 2.4.7.2 cnrx0 ...................................................................................................... 2-28 2.4.8 readi pads................................................................................................... 2-28 2.4.8.1 mseo ........................................................................................................ 2-28 contents paragraph number title page number vi mpc565/mpc566 reference manual motorola 2.4.8.2 mdo[3:0] .................................................................................................. 2-28 2.4.8.3 mcko ....................................................................................................... 2-29 2.4.8.4 rsti........................................................................................................... 2-29 2.4.8.5 evti .......................................................................................................... 2-29 2.4.8.6 msei.......................................................................................................... 2-29 2.4.8.7 mdi[0:1].................................................................................................... 2-29 2.4.8.8 mcki......................................................................................................... 2-29 2.4.9 uc3f pads ..................................................................................................... 2-30 2.4.9.1 epee.......................................................................................................... 2-30 2.4.9.2 b0epee ..................................................................................................... 2-30 2.4.9.3 vflash.................................................................................................... 2-30 2.4.9.4 vddf ........................................................................................................ 2-30 2.4.9.5 vssf.......................................................................................................... 2-30 2.4.10 global power supplies................................................................................... 2-30 2.4.10.1 nvddl ..................................................................................................... 2-30 2.4.10.2 qvddl ..................................................................................................... 2-31 2.4.10.3 vddh........................................................................................................ 2-31 2.4.10.4 vdd........................................................................................................... 2-31 2.4.10.5 kapwr..................................................................................................... 2-31 2.4.10.6 vddsram1 ............................................................................................. 2-31 2.4.10.7 vddsram2 ............................................................................................. 2-31 2.4.10.8 vddsram3 ............................................................................................. 2-32 2.4.10.9 vss ............................................................................................................ 2-32 2.5 reset state.......................................................................................................... 2-32 2.5.1 pin functionality configuration out of reset ............................................... 2-32 2.5.2 pin state during reset ................................................................................... 2-32 2.5.3 power-on reset and hard reset ................................................................... 2-33 2.5.4 pin reset states.............................................................................................. 2-33 2.6 pad types ........................................................................................................... 2-42 2.7 electrical characteristics ................................................................................... 2-43 2.7.1 target dc characteristics .............................................................................. 2-43 2.7.2 pad measurement criteria ............................................................................. 2-44 2.7.2.1 input buffer ............................................................................................... 2-44 2.7.2.2 output driver............................................................................................. 2-45 2.8 package description .......................................................................................... 2-57 2.8.1 package diagrams.......................................................................................... 2-57 2.8.2 bumped die ................................................................................................... 2-60 2.8.3 mpc565/mpc566 ball diagram................................................................... 2-61 contents paragraph number title page number motorola contents vii chapter 3 central processing unit 3.1 rcpu block diagram ......................................................................................... 3-1 3.2 rcpu key features............................................................................................. 3-3 3.3 instruction sequencer .......................................................................................... 3-3 3.4 independent execution units............................................................................... 3-4 3.4.1 branch processing unit (bpu) ........................................................................ 3-5 3.4.2 integer unit (iu) .............................................................................................. 3-6 3.4.3 load/store unit (lsu) .................................................................................... 3-6 3.4.4 floating-point unit (fpu) ............................................................................... 3-7 3.5 levels of the mpc500 architecture ................................................................... 3-7 3.6 rcpu programming model................................................................................. 3-7 3.7 user instruction set architecture (uisa) register set3-13 3.7.1 general-purpose registers (gprs)................................................................ 3-13 3.7.2 floating-point registers (fprs) .................................................................... 3-13 3.7.3 floating-point status and control register (fpscr).................................... 3-14 3.7.4 condition register (cr) ................................................................................ 3-17 3.7.4.1 condition register cr[0] field definition ............................................... 3-18 3.7.4.2 condition register cr1 field definition .................................................. 3-18 3.7.4.3 condition register crn field ? compare instruction ............................ 3-19 3.7.5 integer exception register (xer)................................................................. 3-19 3.7.6 link register (lr)......................................................................................... 3-20 3.7.7 count register (ctr).................................................................................... 3-20 3.8 vea register set ? time base........................................................................ 3-21 3.9 oea register set............................................................................................... 3-22 3.9.1 machine state register (msr) ...................................................................... 3-22 3.9.2 dae/source instruction service register (dsisr) ...................................... 3-24 3.9.3 data address register (dar) ....................................................................... 3-24 3.9.4 time base facility (tb) ? oea .................................................................. 3-25 3.9.5 decrementer register (dec)......................................................................... 3-25 3.9.6 machine status save/restore register 0 (srr0) .......................................... 3-26 3.9.7 machine status save/restore register 1 (srr1) .......................................... 3-27 3.9.8 general sprs (sprg0?sprg3) ................................................................... 3-27 3.9.9 processor version register (pvr)................................................................. 3-28 3.9.10 implementation-specific sprs ...................................................................... 3-28 3.9.10.1 eie, eid, and nri special-purpose registers.......................................... 3-28 3.9.10.2 floating-point exception cause register (fpecr) .................................. 3-29 3.9.10.3 additional implementation-specific registers.......................................... 3-30 3.10 instruction set .................................................................................................... 3-30 3.10.1 instruction set summary ............................................................................... 3-31 contents paragraph number title page number viii mpc565/mpc566 reference manual motorola 3.10.2 recommended simplified mnemonics.......................................................... 3-37 3.10.3 calculating effective addresses .................................................................... 3-37 3.11 exception model................................................................................................ 3-37 3.11.1 exception classes .......................................................................................... 3-38 3.11.2 ordered exceptions........................................................................................ 3-38 3.11.3 unordered exceptions.................................................................................... 3-38 3.11.4 precise exceptions ......................................................................................... 3-39 3.11.5 exception vector table .................................................................................. 3-39 3.12 instruction timing.............................................................................................. 3-40 3.13 user instruction set architecture (uisa) ......................................................... 3-43 3.13.1 computation modes....................................................................................... 3-43 3.13.2 reserved fields.............................................................................................. 3-43 3.13.3 classes of instructions ................................................................................... 3-43 3.13.4 exceptions...................................................................................................... 3-43 3.13.5 the branch processor .................................................................................... 3-44 3.13.6 instruction fetching ....................................................................................... 3-44 3.13.7 branch instructions ........................................................................................ 3-44 3.13.7.1 invalid branch instruction forms.............................................................. 3-44 3.13.7.2 branch prediction ...................................................................................... 3-44 3.13.8 the fixed-point processor............................................................................. 3-44 3.13.8.1 fixed-point instructions............................................................................. 3-44 3.13.9 floating-point processor................................................................................ 3-45 3.13.9.1 general....................................................................................................... 3-45 3.13.9.2 optional instructions.................................................................................. 3-45 3.13.10 load/store processor ..................................................................................... 3-45 3.13.10.1 fixed-point load with update and store with update instructions ........ 3-45 3.13.10.2 fixed-point load and store multiple instructions .................................... 3-46 3.13.10.3 fixed-point load string instructions......................................................... 3-46 3.13.10.4 storage synchronization instructions ........................................................ 3-46 3.13.10.5 floating-point load and store with update instructions.......................... 3-46 3.13.10.6 floating-point load single instructions.................................................... 3-46 3.13.10.7 floating-point store single instructions.................................................... 3-46 3.13.10.8 optional instructions ................................................................................. 3-47 3.14 virtual environment architecture (vea).......................................................... 3-47 3.14.1 atomic update primitives ............................................................................. 3-47 3.14.2 effect of operand placement on performance .............................................. 3-47 3.14.3 storage control instructions .......................................................................... 3-47 3.14.4 instruction synchronize (isync) instruction................................................... 3-47 3.14.4.1 enforce in-order execution of i/o (eieio) instruction .............................. 3-48 3.14.5 timebase ........................................................................................................ 3-48 3.15 operating environment architecture (oea)..................................................... 3-48 contents paragraph number title page number motorola contents ix 3.15.1 branch processor registers ........................................................................... 3-48 3.15.1.1 machine state register (msr) .................................................................. 3-48 3.15.1.2 branch processors instructions.................................................................. 3-48 3.15.2 fixed-point processor .................................................................................... 3-49 3.15.2.1 special purpose registers.......................................................................... 3-49 3.15.3 storage control instructions .......................................................................... 3-49 3.15.4 exceptions...................................................................................................... 3-49 3.15.4.1 system reset exception and nmi (0x0100) ............................................. 3-49 3.15.4.2 machine check exception (0x0200) ......................................................... 3-50 3.15.4.3 data storage exception (0x0300).............................................................. 3-52 3.15.4.4 instruction storage exception (0x0400) .................................................... 3-52 3.15.4.5 external interrupt (0x0500) ....................................................................... 3-52 3.15.4.6 alignment exception (0x00600) ............................................................... 3-53 3.15.4.7 program exception (0x0700)..................................................................... 3-55 3.15.4.8 floating-point unavailable exception (0x0800) ....................................... 3-56 3.15.4.9 decrementer exception (0x0900).............................................................. 3-57 3.15.4.10 system call exception (0x0c00) .............................................................. 3-58 3.15.4.11 trace exception (0x0d00)......................................................................... 3-59 3.15.4.12 floating-point assist exception (0x0e00) ................................................ 3-60 3.15.4.13 implementation-dependent software emulation exception (0x1000) ..... 3-61 3.15.4.14 implementation-dependent instruction protection exception (0x1300).............................................................. 3-61 3.15.4.15 implementation-specific data protection error exception (0x1400) ....... 3-62 3.15.4.16 implementation-dependent debug exceptions......................................... 3-63 3.15.5 partially executed instructions ...................................................................... 3-65 3.15.6 timer facilities .............................................................................................. 3-65 3.15.7 optional facilities and instructions ............................................................... 3-65 chapter 4 burst buffer controller 2 module 4.1 key features ........................................................................................................ 4-3 4.1.1 biu key features ............................................................................................ 4-3 4.1.2 impu key features ......................................................................................... 4-3 4.1.3 icdu key features (mpc566 only) .............................................................. 4-4 4.1.3.1 decram key features .............................................................................. 4-4 4.1.4 branch target buffer key features ................................................................. 4-4 4.2 class-based compression model main principles.............................................. 4-5 4.2.1 compression model features (mpc566 only) ............................................... 4-5 4.2.2 model limitations (mpc566 only) ................................................................ 4-5 4.2.3 instruction class-based compression algorithm (mpc566 only) ................ 4-6 contents paragraph number title page number x mpc565/mpc566 reference manual motorola 4.2.4 class code compression algorithm rules (mpc566 only) ........................................................................................... 4-7 4.2.5 bypass field compression rules (mpc566 only) ......................................... 4-8 4.2.5.1 branch right segment compression #1...................................................... 4-8 4.2.5.2 branch right segment compression #2...................................................... 4-8 4.2.5.3 right segment zero length compression bypass...................................... 4-9 4.2.6 instruction classes structures and programming (mpc566 only) ................. 4-9 4.2.6.1 global bypass.............................................................................................. 4-9 4.2.6.2 single segment full compression ? class_1 ........................................ 4-10 4.2.6.3 twin segment full compression ? class_2 .......................................... 4-10 4.2.6.4 left segment compression and right segment bypass ? class_3...... 4-11 4.2.6.5 left segment bypass and right segment compression ? class_4...... 4-12 4.2.7 instruction layout programming summary (mpc566 only) ......................................................................................... 4-13 4.2.8 compression process (mpc566 only) .......................................................... 4-13 4.2.9 decompression (mpc566 only) ................................................................... 4-15 4.2.10 compression environment initialization (mpc566 only)4-15 4.2.11 compression/non-compression mode switch (mpc566 only) .................. 4-16 4.2.11.1 compression definition for exception handlers ...................................... 4-16 4.2.11.2 running mixed code................................................................................. 4-16 4.3 operation modes................................................................................................ 4-17 4.3.1 instruction fetch (mpc566 only) ................................................................. 4-17 4.3.1.1 ?decompression off? mode .................................................................... 4-17 4.3.1.2 ?decompression on? mode...................................................................... 4-18 4.3.1.3 show cycles in ?decompression on? mode............................................ 4-18 4.3.2 burst operation of the bbc........................................................................... 4-19 4.3.3 access violation detection............................................................................ 4-19 4.3.4 slave operation.............................................................................................. 4-20 4.3.5 reset behavior............................................................................................... 4-20 4.3.6 debug operation mode ................................................................................. 4-21 4.4 exception table relocation (etr).................................................................... 4-21 4.4.1 etr overview ............................................................................................... 4-21 4.4.2 etr operation............................................................................................... 4-22 4.4.3 enhanced external interrupt relocation (eeir) ........................................... 4-24 4.5 decompressor ram (decram) functionality ............................................... 4-26 4.5.1 vocabulary table storage operation (mpc566 only) .................................. 4-27 4.5.2 general-purpose memory operation............................................................. 4-28 4.5.2.1 memory protection violations................................................................... 4-28 4.5.2.2 decram standby operation mode......................................................... 4-28 4.6 branch target buffer ......................................................................................... 4-29 contents paragraph number title page number motorola contents xi 4.6.1 btb operation............................................................................................... 4-29 4.6.1.1 btb invalidation ....................................................................................... 4-30 4.6.1.2 btb enabling/disabling ........................................................................... 4-30 4.6.1.3 btb inhibit regions.................................................................................. 4-31 4.7 bbc programming model ................................................................................. 4-31 4.7.1 address map .................................................................................................. 4-31 4.7.1.1 bbc special purpose registers (sprs) .................................................... 4-32 4.7.1.2 decram and dccr block ..................................................................... 4-32 4.7.2 bbc register descriptions............................................................................ 4-33 4.7.2.1 bbc module configuration register bbcmcr ...................................... 4-33 4.7.2.2 region base address registers mi_rba[0:3] ......................................... 4-35 4.7.2.3 region attribute registers mi_ra[0:3] ................................................... 4-36 4.7.2.4 global region attribute register mi_gra.............................................. 4-38 4.7.2.5 external interrupt relocation table base address register ? eibadr ............................................................... 4-39 4.7.2.6 decompressor class configuration registers (dccr0-15) (mpc566 only) ..................................................................................... 4-40 chapter 5 unified system interface unit (usiu) 5.1 usiu module overview ...................................................................................... 5-1 5.1.1 address map .................................................................................................... 5-3 5.1.2 usiu special-purpose registers ..................................................................... 5-7 chapter 6 system configuration and protection 6.1 system configuration .......................................................................................... 6-3 6.1.1 usiu pin multiplexing.................................................................................... 6-4 6.1.2 memory mapping ............................................................................................ 6-4 6.1.3 arbitration support .......................................................................................... 6-5 6.2 external master modes ........................................................................................ 6-6 6.2.1 operation in external master modes............................................................... 6-6 6.2.2 address decoding for external accesses........................................................ 6-7 6.3 usiu general-purpose i/o .................................................................................. 6-8 6.4 enhanced interrupt controller ............................................................................. 6-9 6.4.1 key features .................................................................................................... 6-9 6.4.2 interrupt configuration .................................................................................... 6-9 6.4.3 regular interrupt controller operation (mpc555/mpc556 compatible mode)..................................................... 6-11 6.4.4 enhanced interrupt controller ....................................................................... 6-12 contents paragraph number title page number xii mpc565/mpc566 reference manual motorola 6.4.4.1 general operation...................................................................................... 6-12 6.4.4.2 lower priority request masking............................................................... 6-15 6.4.4.3 backward compatibility with mpc555/mpc556..................................... 6-16 6.5 interrupt overhead estimation for enhanced interrupt controller mode ......... 6-18 6.6 hardware bus monitor ...................................................................................... 6-20 6.7 decrementer (dec) ........................................................................................... 6-20 6.8 time base (tb).................................................................................................. 6-21 6.9 real-time clock (rtc)..................................................................................... 6-22 6.10 periodic interrupt timer (pit)........................................................................... 6-22 6.11 software watchdog timer (swt) ..................................................................... 6-23 6.12 freeze operation................................................................................................ 6-25 6.13 low power stop operation................................................................................ 6-25 6.14 system configuration and protection registers ................................................ 6-26 6.14.1 system configuration registers .................................................................... 6-26 6.14.1.1 siu module configuration register (siumcr)....................................... 6-26 6.14.1.2 internal memory map register ................................................................. 6-29 6.14.1.3 external master control register (emcr) ............................................... 6-30 6.14.2 siu interrupt controller registers................................................................. 6-32 6.14.2.1 siu interrupt pending register ................................................................. 6-33 6.14.2.2 siu interrupt pending register 2 .............................................................. 6-33 6.14.2.3 siu interrupt pending register 3 .............................................................. 6-34 6.14.2.4 siu interrupt mask register...................................................................... 6-34 6.14.2.5 siu interrupt mask register 2................................................................... 6-35 6.14.2.6 siu interrupt mask register 3................................................................... 6-36 6.14.2.7 siu interrupt edge level register (siel) ................................................ 6-36 6.14.2.8 siu interrupt vector register .................................................................... 6-36 6.14.2.9 interrupt in-service registers.................................................................... 6-38 6.14.3 system protection registers .......................................................................... 6-39 6.14.3.1 system protection control register (sypcr) .......................................... 6-39 6.14.3.2 software service register (swsr) ........................................................... 6-40 6.14.3.3 transfer error status register (tesr) ...................................................... 6-41 6.14.4 system timer registers ................................................................................. 6-42 6.14.4.1 decrementer register ................................................................................ 6-42 6.14.4.2 time base sprs......................................................................................... 6-43 6.14.4.3 time base reference registers ................................................................. 6-43 6.14.4.4 time base control and status register ..................................................... 6-44 6.14.4.5 real-time clock status and control register........................................... 6-45 6.14.4.6 real-time clock register (rtc) .............................................................. 6-46 6.14.4.7 real-time clock alarm register (rtcal).............................................. 6-46 6.14.4.8 periodic interrupt status and control register (piscr) ........................... 6-46 6.14.4.9 periodic interrupt timer count register (pitc)....................................... 6-47 contents paragraph number title page number motorola contents xiii 6.14.4.10 periodic interrupt timer register (pitr).................................................. 6-47 6.14.5 general-purpose i/o registers ...................................................................... 6-48 6.14.5.1 sgpio data register 1 (sgpiodt1) ....................................................... 6-48 6.14.5.2 sgpio data register 2 (sgpiodt2) ....................................................... 6-49 6.14.5.3 sgpio control register (sgpiocr)........................................................ 6-50 chapter 7 reset 7.1 reset operation.................................................................................................... 7-1 7.1.1 power-on reset ............................................................................................... 7-1 7.1.2 hard reset........................................................................................................ 7-2 7.1.3 soft reset......................................................................................................... 7-3 7.1.4 loss of pll lock ............................................................................................ 7-3 7.1.5 on-chip clock switch..................................................................................... 7-3 7.1.6 software watchdog reset ................................................................................ 7-3 7.1.7 checkstop reset............................................................................................... 7-3 7.1.8 debug port hard reset .................................................................................... 7-4 7.1.9 debug port soft reset...................................................................................... 7-4 7.1.10 jtag reset ...................................................................................................... 7-4 7.2 reset actions summary....................................................................................... 7-4 7.3 data coherency during reset ............................................................................. 7-5 7.4 reset status register............................................................................................ 7-5 7.5 reset configuration ............................................................................................. 7-7 7.5.1 hard reset configuration ................................................................................ 7-7 7.5.2 hard reset configuration word .................................................................... 7-12 7.5.3 soft reset configuration ............................................................................... 7-14 chapter 8 clocks and power control 8.1 system clock sources ......................................................................................... 8-3 8.2 system pll.......................................................................................................... 8-3 8.2.1 frequency multiplication................................................................................. 8-4 8.2.2 skew elimination............................................................................................. 8-4 8.2.3 pre-divider....................................................................................................... 8-4 8.2.4 pll block diagram......................................................................................... 8-4 8.2.5 pll pins .......................................................................................................... 8-6 8.3 system clock during pll loss of lock............................................................. 8-6 8.4 low-power divider ............................................................................................. 8-7 8.5 internal clock signals.......................................................................................... 8-7 8.5.1 general system clocks.................................................................................. 8-10 contents paragraph number title page number xiv mpc565/mpc566 reference manual motorola 8.5.2 clock out (clkout) ................................................................................... 8-13 8.5.3 engineering clock (engclk) ..................................................................... 8-13 8.6 clock source switching..................................................................................... 8-14 8.7 low-power modes............................................................................................. 8-16 8.7.1 entering a low-power mode......................................................................... 8-16 8.7.2 power mode descriptions.............................................................................. 8-17 8.7.3 exiting from low-power modes ................................................................... 8-18 8.7.3.1 exiting from normal-low mode............................................................... 8-19 8.7.3.2 exiting from doze mode .......................................................................... 8-19 8.7.3.3 exiting from deep-sleep mode................................................................ 8-19 8.7.3.4 exiting from power-down mode .............................................................. 8-19 8.7.3.5 low-power modes flow ........................................................................... 8-20 8.8 basic power structure........................................................................................ 8-21 8.8.1 general power supply definitions ................................................................ 8-21 8.8.2 chip power structure..................................................................................... 8-22 8.8.2.1 nvddl ..................................................................................................... 8-22 8.8.2.2 qvddl ..................................................................................................... 8-22 8.8.2.3 vdd........................................................................................................... 8-22 8.8.2.4 vddsyn, vsssyn ................................................................................. 8-22 8.8.2.5 kapwr..................................................................................................... 8-22 8.8.2.6 vdda, vssa............................................................................................ 8-23 8.8.2.7 vflash.................................................................................................... 8-23 8.8.2.8 vddf, vssf ............................................................................................. 8-23 8.8.2.9 vddh........................................................................................................ 8-23 8.8.2.10 vddsram1 ............................................................................................. 8-23 8.8.2.11 vddsram2 ............................................................................................. 8-23 8.8.2.12 vddsram3 ............................................................................................. 8-23 8.8.2.13 vddrtc ................................................................................................... 8-24 8.8.2.14 vss ............................................................................................................ 8-24 8.8.3 keep-alive power.......................................................................................... 8-24 8.8.3.1 keep-alive power configuration .............................................................. 8-24 8.8.3.2 keep-alive power registers lock mechanism......................................... 8-25 8.9 vddsram supply failure detection .............................................................. 8-27 8.10 power-up/down sequencing............................................................................. 8-28 8.11 clocks unit programming model...................................................................... 8-30 8.11.1 system clock control register (sccr)........................................................ 8-30 8.11.2 pll, low-power, and reset-control register (plprcr) ........................... 8-34 8.11.3 change of lock interrupt register (colir)................................................. 8-36 8.11.4 vddsram control register (vsrmcr) ................................................... 8-37 contents paragraph number title page number motorola contents xv chapter 9 external bus interface 9.1 features ................................................................................................................ 9-1 9.2 bus transfer signals ............................................................................................ 9-1 9.3 bus control signals ............................................................................................. 9-2 9.4 bus interface signal descriptions........................................................................ 9-4 9.5 bus operations..................................................................................................... 9-8 9.5.1 basic transfer protocol.................................................................................... 9-8 9.5.2 single beat transfer ........................................................................................ 9-8 9.5.2.1 single beat read flow ................................................................................ 9-9 9.5.2.2 single beat write flow.............................................................................. 9-11 9.5.2.3 single beat flow with small port size...................................................... 9-14 9.5.3 data bus pre-discharge mode ...................................................................... 9-15 9.5.3.1 operating conditions................................................................................. 9-16 9.5.3.2 initialization sequence............................................................................... 9-16 9.5.4 burst transfer ................................................................................................ 9-17 9.5.5 burst mechanism ........................................................................................... 9-18 9.5.6 alignment and packaging of transfers.......................................................... 9-30 9.5.7 arbitration phase ........................................................................................... 9-32 9.5.7.1 bus request ............................................................................................... 9-33 9.5.7.2 bus grant ................................................................................................... 9-33 9.5.7.3 bus busy.................................................................................................... 9-34 9.5.7.4 internal bus arbiter ................................................................................... 9-35 9.5.8 address transfer phase signals..................................................................... 9-37 9.5.8.1 transfer start ............................................................................................. 9-38 9.5.8.2 address bus ............................................................................................... 9-38 9.5.8.3 read/write ................................................................................................. 9-38 9.5.8.4 burst indicator ........................................................................................... 9-38 9.5.8.5 transfer size .............................................................................................. 9-39 9.5.8.6 address types............................................................................................ 9-39 9.5.8.7 burst data in progress ............................................................................... 9-41 9.5.9 termination signals ....................................................................................... 9-42 9.5.9.1 transfer acknowledge............................................................................... 9-42 9.5.9.2 burst inhibit ............................................................................................... 9-42 9.5.9.3 transfer error acknowledge ..................................................................... 9-42 9.5.9.4 termination signals protocol .................................................................... 9-42 9.5.10 storage reservation ....................................................................................... 9-44 9.5.11 bus exception control cycles....................................................................... 9-47 9.5.11.1 retrying a bus cycle ................................................................................. 9-47 9.5.11.2 termination signals protocol summary .................................................... 9-51 9.5.12 bus operation in external master modes...................................................... 9-51 contents paragraph number title page number xvi mpc565/mpc566 reference manual motorola 9.5.13 contention resolution on external bus ........................................................ 9-55 9.5.14 show cycle transactions............................................................................... 9-58 chapter 10 memory controller 10.1 overview............................................................................................................ 10-2 10.2 memory controller architecture ....................................................................... 10-4 10.2.1 associated registers ...................................................................................... 10-5 10.2.2 port size configuration ................................................................................. 10-5 10.2.3 write-protect configuration .......................................................................... 10-5 10.2.4 address and address space checking........................................................... 10-5 10.2.5 burst support ................................................................................................. 10-6 10.2.6 reduced data setup time ............................................................................. 10-6 10.3 chip-select timing .......................................................................................... 10-11 10.3.1 memory devices interface example ........................................................... 10-12 10.3.2 peripheral devices interface example......................................................... 10-13 10.3.3 relaxed timing examples ........................................................................... 10-15 10.3.4 extended hold time on read accesses ...................................................... 10-19 10.3.5 summary of gpcm timing options........................................................... 10-23 10.4 write and byte enable signals ........................................................................ 10-25 10.5 dual mapping of the internal flash eeprom array ..................................... 10-26 10.6 dual mapping of an external flash region .................................................... 10-29 10.7 global (boot) chip-select operation .............................................................. 10-29 10.8 memory controller external master support .................................................. 10-31 10.9 programming model ........................................................................................ 10-34 10.9.1 general memory controller programming notes ....................................... 10-34 10.9.2 memory controller status registers (mstat) ........................................... 10-35 10.9.3 memory controller base registers (br[0] ? br[3]).................................. 10-36 10.9.4 memory controller option registers (or[0] ? or[3]) .............................. 10-38 10.9.5 dual-mapping base register (dmbr) ....................................................... 10-40 10.9.6 dual-mapping option register ................................................................... 10-41 chapter 11 l-bus to u-bus interface (l2u) 11.1 general features ................................................................................................ 11-1 11.2 dmpu features ................................................................................................. 11-2 11.3 l2u block diagram........................................................................................... 11-2 11.4 modes of operation .......................................................................................... 11-3 11.4.1 normal mode................................................................................................. 11-3 11.4.2 reset operation.............................................................................................. 11-4 contents paragraph number title page number motorola contents xvii 11.4.3 peripheral mode............................................................................................. 11-4 11.5 data memory protection.................................................................................... 11-4 11.5.1 functional description................................................................................... 11-5 11.5.2 associated registers ...................................................................................... 11-6 11.5.3 l-bus memory access violations.................................................................. 11-8 11.6 reservation support........................................................................................... 11-8 11.6.1 the reservation protocol............................................................................... 11-8 11.6.2 l2u reservation support .............................................................................. 11-8 11.6.3 reserved location (bus) and possible actions............................................. 11-9 11.7 l-bus show cycle support ............................................................................. 11-10 11.7.1 programming show cycles ......................................................................... 11-10 11.7.2 performance impact......................................................................................11-11 11.7.3 show cycle protocol ....................................................................................11-11 11.7.4 l-bus write show cycle flow.....................................................................11-11 11.7.5 l-bus read show cycle flow..................................................................... 11-12 11.7.6 show cycle support guidelines .................................................................. 11-12 11.8 l2u programming model................................................................................ 11-13 11.8.1 u-bus access ............................................................................................... 11-14 11.8.2 transaction size........................................................................................... 11-14 11.8.3 l2u module configuration register (l2u_mcr) ..................................... 11-15 11.8.4 region base address registers (l2u_rbax)............................................ 11-15 11.8.5 region attribute registers (l2u_rax) ...................................................... 11-16 11.8.6 global region attribute register (l2u_gra)........................................... 11-17 chapter 12 u-bustoimb3businterface(uimb) 12.1 features .............................................................................................................. 12-1 12.2 uimb block diagram ....................................................................................... 12-2 12.3 clock module .................................................................................................... 12-2 12.4 interrupt operation ............................................................................................ 12-4 12.4.1 interrupt sources and levels on imb............................................................ 12-4 12.4.2 imb interrupt multiplexing ........................................................................... 12-4 12.4.3 ilbs sequencing ........................................................................................... 12-5 12.4.4 interrupt synchronizer ................................................................................... 12-6 12.5 programming model .......................................................................................... 12-7 12.5.1 uimb module configuration register (umcr) .......................................... 12-8 12.5.2 test control register (utstcreg) ............................................................... 12-9 12.5.3 pending interrupt request register (uipend)............................................. 12-9 contents paragraph number title page number xviii mpc565/mpc566 reference manual motorola chapter 13 queued analog-to-digital converter (qadc64e) 13.1 features, overview and quick reference diagrams......................................... 13-1 13.1.1 features of the qadc64e (each module).................................................... 13-1 13.1.2 qadc64e block diagrams........................................................................... 13-2 13.1.3 memory map ................................................................................................. 13-4 13.1.4 using the queue and result word table....................................................... 13-7 13.1.5 external multiplexing .................................................................................... 13-7 13.2 programming the qadc64e registers ............................................................. 13-9 13.2.1 qadc64e module configuration register .............................................. 13-10 13.2.1.1 low power stop mode ............................................................................ 13-11 13.2.1.2 freeze mode ............................................................................................ 13-11 13.2.1.3 supervisor/unrestricted address space .................................................. 13-12 13.2.1.4 master/slave operation and multi-module synchronous clocks........... 13-13 13.2.2 qadc64e interrupt register ...................................................................... 13-14 13.2.3 port data register........................................................................................ 13-15 13.2.4 port data direction register........................................................................ 13-16 13.2.5 control register 0........................................................................................ 13-17 13.2.6 control register 1........................................................................................ 13-19 13.2.7 control register 2........................................................................................ 13-21 13.2.8 status registers............................................................................................ 13-24 13.2.9 conversion command word table.............................................................. 13-27 13.2.10 result word table........................................................................................ 13-33 13.3 analog subsystem ........................................................................................... 13-35 13.3.1 analog-to-digital converter operation....................................................... 13-35 13.3.1.1 conversion cycle times.......................................................................... 13-35 13.3.2 channel decode and multiplexer ................................................................ 13-36 13.3.3 sample buffer amplifier ............................................................................. 13-36 13.3.4 digital to analog converter (dac) array .................................................. 13-36 13.3.5 comparator .................................................................................................. 13-37 13.3.6 bias .............................................................................................................. 13-37 13.3.7 successive approximation register ........................................................... 13-37 13.3.8 state machine .............................................................................................. 13-37 13.4 digital subsystem ............................................................................................ 13-38 13.4.1 queue priority.............................................................................................. 13-38 13.4.2 sub-queues that are paused......................................................................... 13-38 13.4.3 boundary conditions ................................................................................... 13-40 13.4.4 scan modes.................................................................................................. 13-41 13.4.4.1 disabled mode......................................................................................... 13-41 13.4.4.2 reserved mode ........................................................................................ 13-42 13.4.4.3 single-scan modes .................................................................................. 13-42 contents paragraph number title page number motorola contents xix 13.4.4.4 software initiated single-scan mode...................................................... 13-43 13.4.4.5 external trigger single-scan mode ........................................................ 13-43 13.4.4.6 external gated single-scan mode........................................................... 13-44 13.4.4.7 periodic/interval timer single-scan mode ............................................. 13-44 13.4.4.8 continuous-scan modes.......................................................................... 13-45 13.4.4.9 software initiated continuous-scan mode.............................................. 13-46 13.4.4.10 external trigger continuous-scan mode ................................................ 13-47 13.4.4.11 external gated continuous-scan mode .................................................. 13-47 13.4.4.12 periodic/interval timer continuous-scan mode..................................... 13-48 13.4.5 qadc64e clock (qclk) generation........................................................ 13-48 13.4.6 periodic/interval timer................................................................................ 13-50 13.4.7 configuration and control using the imb interface................................... 13-51 13.4.7.1 qadc64e bus interface unit ................................................................. 13-51 13.4.7.2 qadc64e bus accessing ....................................................................... 13-52 13.5 trigger and queue interaction examples ........................................................ 13-53 13.5.1 queue priority schemes............................................................................... 13-53 13.5.2 conversion timing schemes ....................................................................... 13-63 13.6 qadc64e integration requirements .............................................................. 13-66 13.6.1 port digital input/output pins ..................................................................... 13-66 13.6.2 external trigger input pins.......................................................................... 13-67 13.6.3 analog power pins....................................................................................... 13-67 13.6.3.1 analog supply filtering and grounding ................................................. 13-69 13.6.4 analog reference pins................................................................................. 13-71 13.6.5 analog input pins ........................................................................................ 13-72 13.6.5.1 analog input considerations ................................................................... 13-73 13.6.5.2 settling time for the external circuit ..................................................... 13-75 13.6.5.3 error resulting from leakage ................................................................. 13-75 13.6.5.4 accommodating positive/negative stress conditions ............................ 13-76 chapter 14 queued serial multi-channel module 14.1 overview............................................................................................................ 14-1 14.2 block diagram ................................................................................................... 14-1 14.2.1 mpc565/mpc566 qsmcm details ............................................................. 14-2 14.3 signal descriptions ............................................................................................ 14-3 14.4 memory maps.................................................................................................... 14-3 14.5 qsmcm global registers................................................................................. 14-6 14.5.1 low-power stop operation ........................................................................... 14-7 14.5.2 freeze operation............................................................................................ 14-7 14.5.3 access protection........................................................................................... 14-7 14.5.4 qsmcm interrupts ........................................................................................ 14-7 contents paragraph number title page number xx mpc565/mpc566 reference manual motorola 14.5.5 qsmcm configuration register (qsmcmmcr) ....................................... 14-9 14.5.6 qsmcm test register (qtest) ................................................................ 14-10 14.5.7 qsmcm interrupt level registers (qdsci_il, qspi_il)........................ 14-10 14.6 qsmcm pin control registers ....................................................................... 14-11 14.6.1 port qs data register (portqs) ............................................................... 14-13 14.6.2 portqs pin assignment register (pqspar) ........................................... 14-13 14.6.3 portqs data direction register (ddrqs) .............................................. 14-15 14.7 queued serial peripheral interface .................................................................. 14-16 14.7.1 qspi registers ............................................................................................ 14-18 14.7.1.1 qspi control register 0 .......................................................................... 14-19 14.7.1.2 qspi control register 1 .......................................................................... 14-21 14.7.1.3 qspi control register 2 .......................................................................... 14-22 14.7.1.4 qspi control register 3 .......................................................................... 14-23 14.7.1.5 qspi status register................................................................................ 14-24 14.7.2 qspi ram................................................................................................... 14-25 14.7.2.1 receive ram .......................................................................................... 14-26 14.7.2.2 transmit ram ......................................................................................... 14-26 14.7.2.3 command ram....................................................................................... 14-26 14.7.3 qspi pins..................................................................................................... 14-27 14.7.4 qspi operation............................................................................................ 14-28 14.7.4.1 enabling, disabling, and halting the qspi ............................................. 14-29 14.7.4.2 qspi interrupts ........................................................................................ 14-30 14.7.4.3 qspi flow ............................................................................................... 14-30 14.7.5 master mode operation ............................................................................... 14-38 14.7.5.1 clock phase and polarity ......................................................................... 14-39 14.7.5.2 baud rate selection................................................................................. 14-39 14.7.5.3 delay before transfer ............................................................................. 14-40 14.7.5.4 delay after transfer ................................................................................ 14-40 14.7.5.5 transfer length........................................................................................ 14-41 14.7.5.6 peripheral chip selects............................................................................ 14-41 14.7.5.7 master wraparound mode ....................................................................... 14-42 14.7.6 slave mode .................................................................................................. 14-42 14.7.6.1 description of slave operation ............................................................... 14-44 14.7.7 slave wraparound mode ............................................................................. 14-45 14.7.8 mode fault................................................................................................... 14-46 14.8 serial communication interface ...................................................................... 14-46 14.8.1 sci registers ............................................................................................... 14-50 14.8.2 sci control register 0................................................................................. 14-51 14.8.3 sci control register 1................................................................................. 14-51 14.8.4 sci status register (scxsr)....................................................................... 14-53 14.8.5 sci data register (scxdr) ........................................................................ 14-55 contents paragraph number title page number motorola contents xxi 14.8.6 sci pins ....................................................................................................... 14-56 14.8.7 sci operation .............................................................................................. 14-56 14.8.7.1 definition of terms.................................................................................. 14-57 14.8.7.2 serial formats.......................................................................................... 14-57 14.8.7.3 baud clock .............................................................................................. 14-58 14.8.7.4 parity checking ....................................................................................... 14-59 14.8.7.5 transmitter operation.............................................................................. 14-59 14.8.7.6 receiver operation .................................................................................. 14-61 14.8.7.7 receiver functional operation ................................................................ 14-63 14.8.7.8 idle-line detection .................................................................................. 14-64 14.8.7.9 receiver wake-up................................................................................... 14-65 14.8.7.10 internal loop mode ................................................................................. 14-66 14.9 sci queue operation....................................................................................... 14-66 14.9.1 queue operation of sci1 for transmit and receive................................... 14-66 14.9.2 queued sci1 status and control registers ................................................. 14-66 14.9.2.1 qsci1 control register........................................................................... 14-66 14.9.2.2 qsci1 status register ............................................................................. 14-68 14.9.3 qsci1 transmitter block diagram ............................................................. 14-69 14.9.4 qsci1 additional transmit operation features ......................................... 14-69 14.9.5 qsci1 transmit flow chart implementing the queue ............................... 14-71 14.9.6 example qsci1 transmit for 17 data bytes .............................................. 14-73 14.9.7 example sci transmit for 25 data bytes ................................................... 14-75 14.9.8 qsci1 receiver block diagram.................................................................. 14-76 14.9.9 qsci1 additional receive operation features........................................... 14-77 14.9.10 qsci1 receive flow chart implementing the queue ............................... 14-79 14.9.11 qsci1 receive queue software flow chart .............................................. 14-80 14.9.12 example qsci1 receive operation of 17 data frames.............................. 14-81 chapter 15 data link controller module (dlcmd2) 15.1 features .............................................................................................................. 15-1 15.2 1.4 background .................................................................................................. 15-2 15.3 1.5 applicable documents................................................................................. 15-2 15.4 1.6 general requirements.................................................................................. 15-2 15.5 logic description .............................................................................................. 15-3 15.5.1 block diagram............................................................................................... 15-3 15.5.2 dlcmd2 operation ...................................................................................... 15-3 15.5.2.1 general....................................................................................................... 15-4 15.5.2.2 logic section description and relation to transceiver ............................ 15-4 15.5.2.3 dlcmd2 transmit/receive operation..................................................... 15-5 15.5.2.4 message transmission............................................................................... 15-6 contents paragraph number title page number xxii mpc565/mpc566 reference manual motorola 15.5.2.5 message reception .................................................................................... 15-7 15.5.2.6 sleep mode ................................................................................................ 15-8 15.5.2.7 debug mode .............................................................................................. 15-8 15.5.2.8 4x speed mode ......................................................................................... 15-8 15.5.2.9 block mode ............................................................................................... 15-8 15.5.2.10 error detection .......................................................................................... 15-9 15.5.2.11 arbitration................................................................................................ 15-10 15.5.2.12 timebase generation ............................................................................... 15-10 15.5.2.13 receive and transmit message buffers .................................................. 15-11 15.5.2.14 bus waveforms generation ..................................................................... 15-11 15.5.2.15 huntzicker encoding ............................................................................... 15-12 15.5.3 tdata link controller module (dlcmd2)................................................ 15-14 15.6 signals overview ............................................................................................. 15-15 15.6.1 j1850 bus waveforms ................................................................................. 15-15 15.6.1.1 start of frame (sof) ............................................................................... 15-16 15.6.1.2 data bits .................................................................................................. 15-16 15.6.1.3 ?0? bit....................................................................................................... 15-16 15.6.1.4 ?1? bit....................................................................................................... 15-17 15.6.1.5 end of data (eod) .................................................................................. 15-17 15.6.1.6 normalization bit .................................................................................... 15-17 15.6.1.7 end of frame (eof) ................................................................................ 15-17 15.6.1.8 break........................................................................................................ 15-18 15.6.2 general symbol transmission ..................................................................... 15-18 15.6.3 general symbol reception .......................................................................... 15-18 15.6.4 support for external transceiver................................................................ 15-18 15.7 operating modes.............................................................................................. 15-19 15.7.1 power off..................................................................................................... 15-20 15.7.2 reset............................................................................................................. 15-20 15.7.3 run............................................................................................................... 15-21 15.7.4 dlcmd2 stop and lpstop .................................................................... 15-21 15.7.4.1 dlcmd2 stop mode ............................................................................ 15-21 15.7.4.2 dlcmd2 lpstop mode........................................................................ 15-21 15.7.5 dlcmd2 debug ...................................................................................... 15-22 15.8 cpu interface .................................................................................................. 15-25 15.8.1 parallel interface requirements................................................................... 15-25 15.8.2 reset operation............................................................................................ 15-26 15.9 operational information .................................................................................. 15-26 15.9.1 initialization ................................................................................................. 15-27 15.9.1.1 ste p1?initializemcr.. ....................................................................... 15-27 15.9.1.2 ste p2?initializeilrandivrregistersifinterruptsemployed ......... 15-27 15.9.1.3 ste p3?initializesctlandsdataregisters ..................................... 15-27 contents paragraph number title page number motorola contents xxiii 15.9.1.4 ste p4?enabledlcmd2byex iting debug mode ........................... 15-27 15.9.2 transmitting a message ............................................................................... 15-27 15.9.3 receiving a message ................................................................................... 15-28 15.9.4 receiving a message in block mode .......................................................... 15-29 15.9.5 transmitting a message in block mode ...................................................... 15-29 15.9.6 receiving a message in 4x mode ............................................................... 15-29 15.9.7 transmitting a message in 4x mode............................................................ 15-30 15.10 programming model ........................................................................................ 15-30 15.10.1 module configuration register (mcr)....................................................... 15-31 15.10.2 interrupt pending register (ipr) ................................................................. 15-33 15.10.3 interrupt level register (ilr)..................................................................... 15-34 15.10.4 interrupt vector register (ivr) ................................................................... 15-35 15.10.5 symbol timing control and pre-scaler register (sctl)........................... 15-35 15.10.6 symbol timing data register (sdata) ..................................................... 15-37 15.10.7 transmit command register (cmd) .......................................................... 15-39 15.10.8 transmit data register (tdata)................................................................ 15-42 15.10.9 txfifo command load sequences............................................................ 15-42 15.10.10 transmit data register (tdata)................................................................ 15-43 15.10.11 receive status register (stat)................................................................... 15-44 15.10.12 receive data register (rdata) ................................................................. 15-47 15.10.13 completion code ......................................................................................... 15-47 15.10.14 bus errors .................................................................................................... 15-50 15.10.15 data link controller module (dlcmd2) .................................................. 15-52 15.11 mask programmable bus error (berr) functionality................................... 15-53 15.11.1 berr_plug = 0 ........................................................................................ 15-53 15.11.2 berr_plug = 1 ........................................................................................ 15-53 15.12 interrupt ........................................................................................................... 15-54 15.12.1 dlcmd2 interrupts .................................................................................... 15-54 15.12.2 interrupt structure........................................................................................ 15-56 15.13 in-frame response .......................................................................................... 15-57 15.13.1 ifr operation .............................................................................................. 15-57 15.13.2 ifr abort conditions .................................................................................. 15-59 15.13.3 ifr types..................................................................................................... 15-59 15.13.3.1 type 1 ifr ............................................................................................... 15-60 15.13.3.2 1.type 2 ifr ............................................................................................ 15-60 15.13.3.3 type 3 ifr ............................................................................................... 15-60 15.14 system overview ............................................................................................. 15-61 15.15 test operation.................................................................................................. 15-61 15.15.1 test configuration register (tcr).............................................................. 15-61 15.16 module i/o signals .......................................................................................... 15-62 15.16.1 signal descriptions ...................................................................................... 15-62 contents paragraph number title page number xxiv mpc565/mpc566 reference manual motorola 15.16.2 external connections................................................................................... 15-62 15.16.3 signal functions .......................................................................................... 15-62 15.16.3.1 cl2tx...................................................................................................... 15-62 15.16.3.2 cl2rx...................................................................................................... 15-63 chapter 16 can 2.0b controller module 16.1 features .............................................................................................................. 16-2 16.2 external pins ...................................................................................................... 16-2 16.3 toucan architecture........................................................................................ 16-3 16.3.1 tx/rx message buffer structure ................................................................... 16-3 16.3.1.1 common fields for extended and standard format frames..................... 16-4 16.3.1.2 fields for extended format frames .......................................................... 16-5 16.3.1.3 fields for standard format frames ........................................................... 16-6 16.3.1.4 serial message buffers .............................................................................. 16-6 16.3.1.5 message buffer activation/deactivation mechanism............................... 16-7 16.3.1.6 message buffer lock/release/busy mechanism ...................................... 16-7 16.3.2 receive mask registers................................................................................. 16-7 16.3.3 bit timing...................................................................................................... 16-9 16.3.3.1 configuring the toucan bit timing........................................................ 16-9 16.3.4 error counters.............................................................................................. 16-10 16.3.5 time stamp .................................................................................................. 16-12 16.4 toucan operation.......................................................................................... 16-12 16.4.1 toucan reset ............................................................................................. 16-13 16.4.2 toucan initialization ................................................................................. 16-13 16.4.3 transmit process.......................................................................................... 16-14 16.4.3.1 transmit message buffer deactivation ................................................... 16-15 16.4.3.2 reception of transmitted frames............................................................ 16-15 16.4.4 receive process ........................................................................................... 16-15 16.4.4.1 receive message buffer deactivation..................................................... 16-16 16.4.4.2 locking and releasing message buffers................................................. 16-17 16.4.5 remote frames ............................................................................................ 16-17 16.4.6 overload frames.......................................................................................... 16-18 16.5 special operating modes................................................................................. 16-18 16.5.1 debug mode ................................................................................................ 16-18 16.5.2 low-power stop mode ................................................................................ 16-19 16.5.3 auto power save mode ............................................................................... 16-21 16.6 interrupts .......................................................................................................... 16-21 16.7 programmer?s model ....................................................................................... 16-22 16.7.1 toucan module configuration register.................................................... 16-26 16.7.2 toucan test configuration register ......................................................... 16-28 contents paragraph number title page number motorola contents xxv 16.7.3 toucan interrupt configuration register .................................................. 16-28 16.7.4 control register 0........................................................................................ 16-29 16.7.5 control register 1........................................................................................ 16-30 16.7.6 prescaler divide register............................................................................. 16-31 16.7.7 control register 2........................................................................................ 16-32 16.7.8 free running timer..................................................................................... 16-33 16.7.9 receive global mask registers................................................................... 16-33 16.7.10 receive buffer 14 mask registers .............................................................. 16-34 16.7.11 receive buffer 15 mask registers .............................................................. 16-34 16.7.12 error and status register ............................................................................. 16-34 16.7.13 interrupt mask register ............................................................................... 16-37 16.7.14 interrupt flag register ................................................................................. 16-37 16.7.15 error counters.............................................................................................. 16-38 chapter 17 modular input/output subsystem (mios14) 17.1 block diagram ................................................................................................... 17-1 17.2 mios14 key features ....................................................................................... 17-2 17.2.1 submodule numbering, naming and addressing ......................................... 17-5 17.2.2 pin naming convention ................................................................................ 17-6 17.3 mios14 configuration ...................................................................................... 17-7 17.3.1 mios14 signals........................................................................................... 17-10 17.3.2 mios14 bus system ................................................................................... 17-10 17.3.3 read/write and control bus ........................................................................ 17-10 17.3.4 request bus ................................................................................................. 17-11 17.3.5 counter bus set ........................................................................................... 17-11 17.4 mios14 programmer?s model ........................................................................ 17-11 17.4.1 bus error support ........................................................................................ 17-11 17.4.2 wait states ................................................................................................... 17-11 17.5 mios14 i/o ports ............................................................................................ 17-13 17.6 mios14 bus interface submodule (mbism)................................................. 17-13 17.6.1 mios14 bus interface (mbism) registers ................................................ 17-13 17.6.1.1 mios14 test and pin control register (mios14tpcr) ....................... 17-14 17.6.1.2 mios14 vector register (mios14vect) ............................................. 17-15 17.6.1.3 mios14 module and version number register ..................................... 17-15 17.6.1.4 mios14 module configuration register (mios14mcr)...................... 17-15 17.7 mios14 counter prescaler submodule (mcpsm)......................................... 17-16 17.7.1 mcpsm features......................................................................................... 17-17 17.7.1.1 mcpsm pin functions ............................................................................ 17-17 17.7.1.2 modular i/o bus (miob) interface......................................................... 17-17 17.7.2 effect of reset on mcpsm ...................................................................... 17-18 contents paragraph number title page number xxvi mpc565/mpc566 reference manual motorola 17.7.3 mcpsm registers ....................................................................................... 17-18 17.7.3.1 mcpsm registers organization ............................................................. 17-18 17.7.3.2 mcpsmscr ? mcpsm status/control register ................................. 17-18 17.8 mios14 modulus counter submodule (mmcsm) ........................................ 17-19 17.8.1 mmcsm features ....................................................................................... 17-22 17.8.1.1 mmcsm pin functions........................................................................... 17-22 17.8.2 mmcsm prescaler ...................................................................................... 17-22 17.8.3 modular i/o bus (miob) interface............................................................. 17-23 17.8.4 effect of reset on mmcsm..................................................................... 17-23 17.8.5 mmcsm registers ...................................................................................... 17-23 17.8.5.1 mmcsm register organization.............................................................. 17-24 17.8.5.2 mmcsm up-counter register (mmcsmcnt) .................................... 17-25 17.8.5.3 mmcsm modulus latch register (mmcsmml)................................. 17-25 17.8.5.4 mmcsmscrd ? mmcsm status/control register (duplicated)........................................................................... 17-26 17.8.5.5 mmcsm status/control register (mmcsmscr)................................. 17-26 17.9 mios14 double action submodule (mdasm)............................................. 17-28 17.9.1 mdasm features........................................................................................ 17-29 17.9.1.1 mdasm pin functions ........................................................................... 17-30 17.9.2 mdasm description................................................................................... 17-30 17.9.3 mdasm modes of operation ..................................................................... 17-31 17.9.3.1 disable (dis) mode................................................................................. 17-32 17.9.3.2 input pulse width measurement (ipwm) mode..................................... 17-32 17.9.4 input period measurement (ipm) mode...................................................... 17-33 17.9.5 input capture (ic) mode ............................................................................. 17-35 17.9.5.1 output compare (ocb and ocab) modes............................................ 17-35 17.9.5.2 single shot output pulse operation ........................................................ 17-36 17.9.5.3 single output compare operation .......................................................... 17-37 17.9.5.4 output port bit operation........................................................................ 17-38 17.9.5.5 output pulse width modulation (opwm) mode.................................... 17-38 17.9.6 modular i/o bus (miob) interface............................................................. 17-41 17.9.7 effect of reset on mdasm ..................................................................... 17-42 17.9.8 mdasm registers ...................................................................................... 17-42 17.9.8.1 mdasm registers organization ............................................................ 17-42 17.9.8.2 mdasm dataa (mdasmar) register bits......................................... 17-44 17.9.8.3 mdasm datab (mdasmbr) register bits ......................................... 17-45 17.9.9 mdasmscrd ? mdasm status/control register (duplicated) ........... 17-46 17.9.10 mdasmscr ? mdasm status/control register ................................... 17-46 17.10 mios14 pulse width modulation submodule (mpwmsm).......................... 17-49 17.10.1 mpwmsm terminology............................................................................. 17-50 17.10.2 mpwmsm features .................................................................................... 17-50 contents paragraph number title page number motorola contents xxvii 17.10.3 mpwmsm description............................................................................... 17-51 17.10.3.1 clock selection........................................................................................ 17-52 17.10.3.2 counter .................................................................................................... 17-52 17.10.3.3 period register......................................................................................... 17-53 17.10.3.4 pulse width registers .............................................................................. 17-54 17.10.3.5 0% and 100% duty cycles ...................................................................... 17-55 17.10.3.6 pulse/frequency range table.................................................................. 17-55 17.10.3.7 mpwmsm status and control register (scr) ...................................... 17-57 17.10.3.8 mpwmsm interrupt ............................................................................... 17-57 17.10.3.9 mpwmsm port functions ...................................................................... 17-57 17.10.3.10 mpwmsm data coherency.................................................................... 17-57 17.10.4 modular input/output bus (mios14) interface.......................................... 17-58 17.10.5 effect of reset on mpwmsm ................................................................. 17-58 17.10.6 mpwmsm registers................................................................................... 17-58 17.10.6.1 mpwmsm registers organization......................................................... 17-58 17.10.6.2 mpwmperr ? mpwmsm period register........................................ 17-60 17.10.6.3 mpwmpulr ? mpwmsm pulse width register .............................. 17-61 17.10.6.4 mpwmcntr ? mpwmsm counter register .................................... 17-62 17.10.6.5 mpwmscr ? mpwmsm status/control register ............................. 17-63 17.11 mios14 16-bit parallel port i/o submodule (mpiosm) ............................... 17-66 17.11.1 mpiosm features ....................................................................................... 17-66 17.11.2 mpiosm pin functions .............................................................................. 17-66 17.11.3 mpiosm description .................................................................................. 17-67 17.11.3.1 mpiosm port function........................................................................... 17-67 17.11.3.2 non-bonded mpiosm pads ................................................................... 17-67 17.11.4 modular i/o bus (miob) interface............................................................. 17-67 17.11.5 effect of reset on mpiosm .................................................................... 17-68 17.11.6 mpiosm testing ......................................................................................... 17-68 17.11.7 mpiosm registers...................................................................................... 17-68 17.11.8 mpiosm register organization ................................................................. 17-68 17.11.8.1 mpiosmdr ? mpiosm data register ............................................... 17-68 17.11.8.2 mpiosmddr ? mpiosm data direction register ............................ 17-69 17.12 mios14 interrupts ........................................................................................... 17-69 17.12.1 mios14 interrupt structure......................................................................... 17-69 17.12.2 mios14 interrupt request submodule (mirsm) ...................................... 17-70 17.12.3 mirsm0 interrupt registers ....................................................................... 17-72 17.12.3.1 mios14sr0 interrupt status register .................................................... 17-72 17.12.3.2 mios14er0 interrupt enable register................................................... 17-72 17.12.3.3 mios14rpr0 interrupt request pending register ................................ 17-73 17.12.4 mirsm1 interrupt registers ....................................................................... 17-73 17.12.4.1 mios14sr1 interrupt status register .................................................... 17-73 contents paragraph number title page number xxviii mpc565/mpc566 reference manual motorola 17.12.4.2 mios14er1 interrupt enable register................................................... 17-74 17.12.4.3 mios14rpr1 interrupt request pending register ................................ 17-74 17.12.5 interrupt control section (ics) ................................................................... 17-75 17.12.6 mbism interrupt registers ......................................................................... 17-76 17.12.6.1 mios14 interrupt level register 0 (mios14lvl0).............................. 17-76 17.12.6.2 mios14 interrupt level register 1 (mios14lvl1).............................. 17-76 17.13 mios14 function examples ........................................................................... 17-77 17.13.1 mios14 input double edge pulse width measurement............................. 17-77 17.13.2 mios14 input double edge period measurement...................................... 17-78 17.13.3 mios14 double edge single output pulse generation.............................. 17-79 17.13.4 mios14 output pulse width modulation with mdasm .......................... 17-80 17.13.5 mios14 input pulse accumulation............................................................. 17-82 17.14 real-time clock submodule (mrtcsm) ...................................................... 17-82 17.14.1 mrtcsm overview description ................................................................ 17-82 17.14.1.1 mrtcsm terminology........................................................................... 17-82 17.14.1.2 mrtcsm features .................................................................................. 17-83 17.14.1.3 mrtcsm pad functions......................................................................... 17-84 17.14.2 mrtcsm description................................................................................. 17-84 17.14.2.1 oscillator.................................................................................................. 17-84 17.14.2.2 standby supply and power switch.......................................................... 17-85 17.14.2.3 counter chain.......................................................................................... 17-86 17.14.2.4 15-bit prescaler ....................................................................................... 17-86 17.14.2.5 32-bit free-running counter .................................................................. 17-86 17.14.2.6 15-bit prescaler and 32-bit free-running counter buffers ................... 17-86 17.14.3 modes of operation ..................................................................................... 17-87 17.14.3.1 enabling the mrtcsm ........................................................................... 17-87 17.14.3.2 15-bit prescaler and 32-bit free-running counter buffer updates....... 17-87 17.14.3.3 read of 15-bit prescaler and 32-bit free-running counter buffers...... 17-88 17.14.3.4 write to 15-bit prescaler and 32-bit free-running counter buffers ..... 17-89 17.14.4 mrtcsm interrupt...................................................................................... 17-89 17.14.5 chip wake-up feature ................................................................................ 17-90 17.14.6 modular i/o bus (miob) interface............................................................. 17-90 17.14.6.1 low power mode ? peripheral bus clock running ............................. 17-90 17.14.6.2 low power mode ? peripheral bus clock stopped .............................. 17-90 17.14.7 effect of standby mode on mrtcsm ........................................................ 17-91 17.14.8 effect of reset on mrtcsm ................................................................... 17-91 17.14.9 mrtcsm registers..................................................................................... 17-92 17.14.10 mrtcsm register organization ................................................................ 17-92 17.14.10.1 mrtcsm free-running counter high buffer (mrtcfrch) register bits ........................................................................................ 17-92 contents paragraph number title page number motorola contents xxix 17.14.10.2 mrtcsm free-running counter low buffer (mrtcfrcl) register bits ........................................................................................ 17-93 17.14.10.3 mrtcsm prescaler counter buffer (mrtcpr) register bits .............. 17-93 17.14.10.4 mrtcsmscr ? mrtcsm status/control register............................ 17-93 chapter 18 time processor unit 3 18.1 overview............................................................................................................ 18-2 18.2 tpu3 components............................................................................................. 18-2 18.2.1 time bases..................................................................................................... 18-2 18.2.2 timer channels.............................................................................................. 18-3 18.2.3 scheduler ....................................................................................................... 18-3 18.2.4 microengine ................................................................................................... 18-3 18.2.5 host interface................................................................................................. 18-3 18.2.6 parameter ram ............................................................................................. 18-3 18.3 tpu operation ................................................................................................... 18-4 18.3.1 event timing ................................................................................................. 18-4 18.3.2 channel orthogonality................................................................................... 18-4 18.3.3 interchannel communication......................................................................... 18-5 18.3.4 programmable channel service priority ....................................................... 18-5 18.3.5 coherency ...................................................................................................... 18-5 18.3.6 emulation support ......................................................................................... 18-5 18.3.7 tpu3 interrupts ............................................................................................. 18-6 18.3.8 prescaler control for tcr1 ........................................................................... 18-6 18.3.9 prescaler control for tcr2 ........................................................................... 18-8 18.4 programming model .......................................................................................... 18-9 18.4.1 tpu module configuration register........................................................... 18-13 18.4.2 tpu3 test configuration register .............................................................. 18-14 18.4.3 development support control register....................................................... 18-14 18.4.4 development support status register ......................................................... 18-16 18.4.5 tpu3 interrupt configuration register ....................................................... 18-16 18.4.6 channel interrupt enable register............................................................... 18-17 18.4.7 channel function select registers .............................................................. 18-18 18.4.8 host sequence registers.............................................................................. 18-19 18.4.9 host service request registers ................................................................... 18-20 18.4.10 channel priority registers ........................................................................... 18-21 18.4.11 channel interrupt status register ................................................................ 18-21 18.4.12 link register................................................................................................ 18-22 18.4.13 service grant latch register....................................................................... 18-22 18.4.14 decoded channel number register ............................................................ 18-22 18.4.15 tpu3 module configuration register 2...................................................... 18-23 contents paragraph number title page number xxx mpc565/mpc566 reference manual motorola 18.4.16 tpu module configuration register 3........................................................ 18-25 18.4.17 tpu3 test registers .................................................................................... 18-25 18.4.18 tpu3 parameter ram................................................................................. 18-26 18.5 time functions ................................................................................................ 18-28 chapter 19 dual-port tpu3 ram (dptram) 19.1 features .............................................................................................................. 19-2 19.2 dptram configuration and block diagram ................................................... 19-3 19.3 programming model .......................................................................................... 19-3 19.3.1 dptram module configuration register (dptmcr) ............................... 19-4 19.3.2 dptram test register ................................................................................. 19-6 19.3.3 ram base address register (rambar) .................................................... 19-6 19.3.4 misr high (misrh) and misr low (misrl)........................................... 19-7 19.3.5 misc counter (miscnt) ............................................................................. 19-7 19.4 operation ........................................................................................................... 19-8 19.4.1 normal operation .......................................................................................... 19-8 19.4.2 standby operation ......................................................................................... 19-8 19.4.3 reset operation.............................................................................................. 19-8 19.4.4 stop operation ............................................................................................... 19-9 19.4.5 freeze operation............................................................................................ 19-9 19.4.6 tpu3 emulation mode operation................................................................. 19-9 19.5 multiple input signature calculator (misc)................................................... 19-10 chapter 20 cdr3 flash (uc3f) eeprom 20.1 introduction........................................................................................................ 20-1 20.1.1 features of the cdr3 flash eeprom (uc3f) ........................................ 20-3 20.1.2 glossary of terms used................................................................................. 20-4 20.2 uc3f interface .................................................................................................. 20-5 20.2.1 external interface........................................................................................... 20-5 20.3 programmer?s model ......................................................................................... 20-6 20.3.0.1 uc3f eeprom module control register addressing ............................ 20-6 20.3.1 uc3f eeprom control registers ............................................................... 20-7 20.3.2 uc3f eeprom configuration register (uc3fmcr) ................................ 20-7 20.3.3 uc3f eeprom extended configuration register (uc3fmcre)............ 20-10 20.3.4 uc3f eeprom high voltage control register (uc3fctl).................... 20-14 20.3.5 uc3f eeprom array addressing............................................................. 20-18 20.3.6 uc3f eeprom shadow row .................................................................... 20-18 20.3.6.1 reset configuration word (uc3fcfig)................................................. 20-19 contents paragraph number title page number motorola contents xxxi 20.3.7 uc3f eeprom 512-kbyte array configuration....................................... 20-22 20.4 operation ......................................................................................................... 20-23 20.4.1 reset............................................................................................................. 20-23 20.4.2 register read and write operation ............................................................. 20-24 20.4.3 array read operation.................................................................................. 20-24 20.4.3.1 array on-page read operation............................................................... 20-25 20.4.4 shadow row select read operation ........................................................... 20-25 20.4.5 array program/erase interlock write operation ......................................... 20-25 20.4.6 high voltage operations.............................................................................. 20-25 20.4.6.1 overview of program/erase operation ................................................... 20-25 20.4.7 programming ............................................................................................... 20-26 20.4.7.1 program sequence ................................................................................... 20-26 20.4.7.2 program shadow information.................................................................. 20-29 20.4.7.3 program suspend ..................................................................................... 20-29 20.4.8 erasing ......................................................................................................... 20-30 20.4.8.1 erase sequence ........................................................................................ 20-31 20.4.8.2 erasing shadow information words........................................................ 20-33 20.4.8.3 erase suspend.......................................................................................... 20-33 20.4.9 stop operation ............................................................................................. 20-34 20.4.10 disabled ....................................................................................................... 20-34 20.4.11 censored accesses and non-censored accesses........................................ 20-35 20.4.11.1 setting and clearing censor .................................................................... 20-36 20.4.11.2 setting censor.......................................................................................... 20-37 20.4.11.3 clearing censor ....................................................................................... 20-37 20.4.11.4 switching the uc3f eeprom censorship........................................... 20-38 20.4.12 background debug mode or freeze operation........................................... 20-39 chapter 21 calram operation 21.1 definitions and acronyms ................................................................................. 21-1 21.1.1 key feature list............................................................................................. 21-2 21.2 calram introduction...................................................................................... 21-3 21.3 modes of operation ........................................................................................... 21-7 21.3.1 reset............................................................................................................... 21-7 21.3.2 one-cycle mode............................................................................................ 21-7 21.3.2.1 calram access/privilege violations..................................................... 21-7 21.3.3 two-cycle mode ........................................................................................... 21-8 21.3.4 standby operation/keep-alive power ......................................................... 21-8 21.3.5 stop operation ............................................................................................... 21-8 21.3.6 overlay mode operation .............................................................................. 21-8 21.3.6.1 overlay mode configuration..................................................................... 21-9 contents paragraph number title page number xxxii mpc565/mpc566 reference manual motorola 21.3.6.2 priority of overlay regions..................................................................... 21-14 21.3.6.3 normal (non-overlay) access to overlay regions ................................ 21-15 21.3.6.4 calibration write cycle flow.................................................................. 21-15 21.4 register definitions ......................................................................................... 21-15 21.4.1 calram module configuration register (crammcr)......................... 21-16 21.4.2 calram region base address registers (cram_rbax) ..................... 21-19 21.4.3 calram overlay configuration register (cramovlcr).................... 21-21 21.4.4 calram ownership trace register (cramotr) .................................. 21-21 chapter 22 development support 22.1 program flow tracking ..................................................................................... 22-1 22.1.1 program trace cycle ..................................................................................... 22-2 22.1.1.1 instruction queue status pins ? vf [0:2] ................................................ 22-3 22.1.1.2 history buffer flushes status pins? vfls [0:1]..................................... 22-4 22.1.1.3 queue flush information special case ..................................................... 22-4 22.1.2 program trace when in debug mode............................................................ 22-4 22.1.3 sequential instructions marked as indirect branch....................................... 22-5 22.1.4 the external hardware.................................................................................. 22-5 22.1.4.1 synchronizing the trace window to the cpu internal events ................. 22-6 22.1.4.2 detecting the trace window start address............................................... 22-7 22.1.4.3 detecting the assertion/negation of vsync........................................... 22-7 22.1.4.4 detecting the trace window end address................................................ 22-7 22.1.4.5 compress ................................................................................................... 22-8 22.1.5 instruction fetch show cycle control........................................................... 22-8 22.2 watchpoints and breakpoints support............................................................... 22-8 22.2.1 internal watchpoints and breakpoints ......................................................... 22-10 22.2.1.1 restrictions .............................................................................................. 22-13 22.2.1.2 byte and half-word working modes ...................................................... 22-13 22.2.1.3 examples.................................................................................................. 22-14 22.2.1.4 context dependent filter......................................................................... 22-15 22.2.1.5 ignore first match ................................................................................... 22-16 22.2.1.6 generating six compare types ............................................................... 22-16 22.2.2 instruction support ...................................................................................... 22-17 22.2.2.1 load/store support .................................................................................. 22-18 22.2.3 watchpoint counters.................................................................................... 22-22 22.2.3.1 trap enable programming....................................................................... 22-22 22.3 development system interface ........................................................................ 22-23 22.3.1 debug mode support................................................................................... 22-25 22.3.1.1 debug mode enable vs. debug mode disable ....................................... 22-27 22.3.1.2 entering debug mode.............................................................................. 22-27 contents paragraph number title page number motorola contents xxxiii 22.3.1.3 the check stop state and debug mode.................................................. 22-30 22.3.1.4 saving machine state upon entering debug mode................................. 22-30 22.3.1.5 running in debug mode ......................................................................... 22-30 22.3.1.6 exiting debug mode................................................................................ 22-31 22.4 development port ............................................................................................ 22-31 22.4.1 development port pins ................................................................................ 22-32 22.4.2 development serial clock ........................................................................... 22-32 22.4.3 development serial data in......................................................................... 22-32 22.4.4 development serial data out ...................................................................... 22-33 22.4.5 freeze signal................................................................................................ 22-33 22.4.5.1 sgpio6/frz/ptr pin............................................................................. 22-33 22.4.5.2 iwp[0:1]/vfls[0:1] pins........................................................................ 22-33 22.4.5.3 vfls[0:1]_mpio32b[3:4] pins ............................................................. 22-33 22.4.6 development port registers ........................................................................ 22-33 22.4.6.1 development port shift register ............................................................. 22-34 22.4.6.2 trap enable control register .................................................................. 22-34 22.4.6.3 development port registers decode ....................................................... 22-34 22.4.6.4 development port serial communications ? clock mode selection.... 22-35 22.4.6.5 development port serial communications ? trap enable mode.......... 22-37 22.4.6.6 serial data into development port ? trap enable mode ...................... 22-37 22.4.6.7 serial data out of development port ? trap enable mode .................. 22-38 22.4.6.8 development port serial communications ? debug mode .................. 22-39 22.4.6.9 serial data into development port.......................................................... 22-39 22.4.6.10 serial data out of development port...................................................... 22-40 22.4.6.11 fast download procedure........................................................................ 22-41 22.5 software monitor debugger support .............................................................. 22-43 22.5.1 freeze indication.......................................................................................... 22-43 22.6 development support registers ...................................................................... 22-43 22.6.1 register protection....................................................................................... 22-44 22.6.2 comparator a?d value registers (cmpa?cmpd).................................... 22-45 22.6.3 comparator e?f value registers................................................................. 22-46 22.6.4 breakpoint address register (bar) ........................................................... 22-46 22.6.5 comparator g?h value registers (cmpg?cmph) ................................... 22-47 22.6.6 i-bus support control register ................................................................... 22-47 22.6.7 l-bus support control register 1 ............................................................... 22-49 22.6.8 l-bus support control register 2 ............................................................... 22-50 22.6.9 breakpoint counter a value and control register ..................................... 22-52 22.6.10 breakpoint counter b value and control register...................................... 22-53 22.6.11 exception cause register (ecr)................................................................. 22-53 22.6.12 debug enable register (der)..................................................................... 22-55 22.6.13 development port data register (dpdr) ................................................... 22-57 contents paragraph number title page number xxxiv mpc565/mpc566 reference manual motorola chapter 23 readi module 23.1 overview............................................................................................................ 23-1 23.1.1 general description ....................................................................................... 23-1 23.1.2 feature summary list.................................................................................... 23-2 23.1.3 functional block diagram............................................................................. 23-3 23.1.4 modes of operation ....................................................................................... 23-4 23.1.4.1 readi reset configuration...................................................................... 23-5 23.1.4.2 security ...................................................................................................... 23-5 23.1.4.3 disabled ..................................................................................................... 23-5 23.1.5 parametrics..................................................................................................... 23-5 23.1.6 programmer?s model ..................................................................................... 23-6 23.1.7 messages........................................................................................................ 23-6 23.1.8 terms and definitions.................................................................................... 23-8 23.2 programming model .......................................................................................... 23-9 23.2.1 register map.................................................................................................. 23-9 23.2.1.1 user mapped register ............................................................................... 23-9 23.2.1.2 tool mapped registers ............................................................................ 23-10 23.2.1.3 device id (did) register........................................................................ 23-11 23.2.1.4 development control (dc) register ....................................................... 23-11 23.2.1.5 rcpu development access modes ........................................................ 23-12 23.2.1.6 user base address (uba) register ........................................................ 23-13 23.2.1.7 read/write access (rwa) register ........................................................ 23-13 23.2.1.8 upload/download information (udi) register....................................... 23-15 23.2.1.9 data trace attributes 1 and 2 (dta1 and dta2) registers ................... 23-17 23.2.2 accessing memory mapped locations via the auxiliary port .................................................................................... 23-18 23.2.3 accessing readi tool mapped registers via the auxiliary port ............. 23-19 23.2.4 partial register updates............................................................................... 23-20 23.2.5 programming considerations ...................................................................... 23-20 23.2.5.1 program trace guidelines ....................................................................... 23-20 23.2.5.2 compressed code mode guidelines ....................................................... 23-21 23.2.5.3 reset sequence guidelines...................................................................... 23-22 23.2.5.4 bdm guidelines...................................................................................... 23-23 23.3 pin interface .................................................................................................... 23-23 23.3.1 functional description................................................................................. 23-23 23.3.1.1 pins implemented .................................................................................... 23-23 23.3.2 functional block diagram........................................................................... 23-24 23.3.2.1 message priority ...................................................................................... 23-25 23.3.2.2 pin protocol ............................................................................................. 23-25 23.3.2.3 messages.................................................................................................. 23-27 contents paragraph number title page number motorola contents xxxv 23.3.2.4 message formats ..................................................................................... 23-31 23.3.2.5 rules of messages ................................................................................... 23-33 23.3.2.6 examples.................................................................................................. 23-34 23.3.2.7 non-temporal ordering of transmitted messages ................................. 23-35 23.3.3 readi reset configuration........................................................................ 23-36 23.3.3.1 reset configuration for debug mode ..................................................... 23-37 23.3.3.2 reset configuration for non-debug mode ............................................. 23-37 23.3.3.3 secure mode ............................................................................................ 23-37 23.3.3.4 disabled mode......................................................................................... 23-37 23.3.3.5 guidelines for transmitting input messages .......................................... 23-38 23.4 program trace................................................................................................. 23-38 23.4.1 branch trace messaging.............................................................................. 23-39 23.4.1.1 rcpu instructions that cause btm messages ....................................... 23-39 23.4.2 review of rcpu instruction execution...................................................... 23-39 23.4.2.1 rcpu pipeline and execution model ..................................................... 23-39 23.4.2.2 rcpu branch trace indicators ............................................................... 23-42 23.4.3 btm message formats................................................................................ 23-43 23.4.3.1 direct branch messages .......................................................................... 23-43 23.4.3.2 indirect branch messages........................................................................ 23-44 23.4.3.3 program trace correction message ........................................................ 23-45 23.4.3.4 error message (queue overflow) ........................................................... 23-47 23.4.3.5 program trace synchronization messages.............................................. 23-48 23.4.3.6 direct branch synchronization message................................................. 23-49 23.4.3.7 indirect branch synchronization message .............................................. 23-50 23.4.3.8 direct branch synchronization message with compressed code ......... 23-50 23.4.3.9 indirect branch synchronization message with compressed code........ 23-50 23.4.3.10 relative addressing................................................................................. 23-51 23.4.4 btm operation............................................................................................ 23-51 23.4.4.1 btm capture and encoding algorithm .................................................. 23-51 23.4.4.2 instruction fetch snooping...................................................................... 23-52 23.4.4.3 instruction execution tracking ............................................................... 23-52 23.4.4.4 instruction flush cases............................................................................ 23-55 23.4.5 btm queueing ............................................................................................ 23-55 23.4.6 timing diagram........................................................................................... 23-56 23.4.7 program trace guidelines ........................................................................... 23-59 23.5 data trace ....................................................................................................... 23-59 23.5.1 data trace for the load/store bus (l-bus) ................................................. 23-59 23.5.2 data trace message formats....................................................................... 23-59 23.5.2.1 data write message................................................................................. 23-60 23.5.2.2 data read message.................................................................................. 23-60 23.5.2.3 data trace synchronization messages .................................................... 23-60 contents paragraph number title page number xxxvi mpc565/mpc566 reference manual motorola 23.5.2.4 data write synchronization message...................................................... 23-61 23.5.2.5 data read synchronization messaging ................................................... 23-61 23.5.2.6 relative addressing................................................................................. 23-62 23.5.3 error message (queue overflow)................................................................ 23-62 23.5.4 data trace operation ................................................................................... 23-62 23.5.5 data trace windowing ................................................................................ 23-63 23.5.6 special l-bus cases ..................................................................................... 23-64 23.5.7 data trace queuing ..................................................................................... 23-65 23.5.8 throughput and latency.............................................................................. 23-65 23.5.8.1 assumptions for throughput analysis.................................................... 23-65 23.5.8.2 throughput calculations ......................................................................... 23-65 23.5.9 timing diagrams ......................................................................................... 23-66 23.6 read/write access........................................................................................... 23-67 23.6.1 functional description................................................................................. 23-67 23.6.2 write operation to memory mapped locations and mpc500 registers ................................................................................... 23-70 23.6.2.1 single write operation ............................................................................ 23-70 23.6.2.2 block write operation............................................................................. 23-70 23.6.3 read operation to memory mapped locations and mpc500 registers ................................................................................... 23-72 23.6.3.1 single read operation ............................................................................. 23-72 23.6.3.2 block read operation.............................................................................. 23-72 23.6.4 read/write access to internal readi registers ........................................ 23-73 23.6.4.1 write operation ....................................................................................... 23-73 23.6.4.2 read operation ........................................................................................ 23-74 23.6.5 error handling ............................................................................................. 23-74 23.6.5.1 access alignment.................................................................................... 23-74 23.6.5.2 l-bus address error ................................................................................ 23-74 23.6.5.3 l-bus data error ...................................................................................... 23-74 23.6.6 exception sequences ................................................................................... 23-75 23.6.7 secure mode ................................................................................................ 23-75 23.6.8 error messages ............................................................................................ 23-75 23.6.8.1 read/write access error ......................................................................... 23-75 23.6.8.2 invalid message ....................................................................................... 23-76 23.6.8.3 invalid access opcode ............................................................................ 23-76 23.6.9 faster read/write accesses with default attributes.................................. 23-77 23.6.10 throughput and latency.............................................................................. 23-77 23.6.10.1 assumptions for throughput analysis.................................................... 23-77 23.7 timing diagrams ............................................................................................. 23-79 23.8 watchpoint support ........................................................................................ 23-82 23.8.1 watchpoint messaging................................................................................. 23-82 contents paragraph number title page number motorola contents xxxvii 23.8.1.1 watchpoint source field.......................................................................... 23-83 23.8.2 error message (watchpoint overrun).......................................................... 23-83 23.8.3 synchronization ........................................................................................... 23-83 23.8.4 timing diagrams ......................................................................................... 23-84 23.9 ownership trace ............................................................................................. 23-84 23.9.1 ownership trace messaging........................................................................ 23-84 23.9.2 error message (queue overflow)................................................................ 23-85 23.9.2.1 otm flow ............................................................................................... 23-85 23.9.2.2 otm queueing........................................................................................ 23-86 23.9.3 timing diagram........................................................................................... 23-86 23.10 rcpu development access ........................................................................... 23-87 23.10.1 rcpu development access messaging...................................................... 23-88 23.10.1.1 dsdi message ......................................................................................... 23-88 23.10.1.2 dsdo message ....................................................................................... 23-88 23.10.1.3 bdm status message .............................................................................. 23-89 23.10.1.4 error message (invalid message)............................................................ 23-89 23.10.2 rcpu development access operation ....................................................... 23-89 23.10.2.1 enabling rcpu development access via readi pins ......................... 23-90 23.10.2.2 enabling background debug mode (bdm) via readi pins................. 23-91 23.10.2.3 entering background debug mode (bdm) via readi pins................. 23-91 23.10.2.4 non-debug mode access of rcpu development access ..................... 23-91 23.10.2.5 rcpu development access flow diagram............................................ 23-91 23.10.3 throughput................................................................................................... 23-93 23.10.4 timing diagrams ......................................................................................... 23-94 23.11 power management ........................................................................................ 23-96 23.11.1 functional description................................................................................. 23-96 23.11.2 low power modes ....................................................................................... 23-97 23.12 application notes .......................................................................................... 23-97 23.12.1 automotive calibration ............................................................................... 23-97 23.12.1.1 calibration variable acquisition ............................................................. 23-97 23.12.2 calibration variables located in contiguous memory locations .............. 23-98 23.12.2.1 data read messaging .............................................................................. 23-98 23.12.2.2 read/write access................................................................................... 23-98 23.12.3 calibration variables not located in contiguous memory locations........ 23-99 23.12.3.1 data write messaging ............................................................................. 23-99 23.12.3.2 read/write access................................................................................. 23-100 23.12.3.3 calibration constant tuning.................................................................. 23-100 23.12.4 uc3f programming guideline flowchart via readi read/write access................................................................................. 23-101 contents paragraph number title page number xxxviii mpc565/mpc566 reference manual motorola chapter 24 ieee 1149.1-compliant interface (jtag) 24.1 ieee 1149.1 test access port (tap) and joint test action group (jtag) .................................................................................... 24-1 24.2 ieee 1149.1 test access port ........................................................................... 24-1 24.2.1 overview........................................................................................................ 24-2 24.2.1.1 tap controller................................................................................. 24-3 24.2.1.2 boundary scan register ............................................................................ 24-4 24.2.2 instruction register...................................................................................... 24-22 24.2.2.1 extest .................................................................................................. 24-23 24.2.2.2 sample/preload .............................................................................. 24-23 24.2.2.3 bypass................................................................................................... 24-23 24.2.2.4 clamp.................................................................................................... 24-24 24.2.3 hi-z ............................................................................................................. 24-24 24.3 mpc565/mpc566 restrictions ....................................................................... 24-24 24.3.1 non-scan chain operation.......................................................................... 24-25 24.3.2 motorola mpc565/mpc566 bsdl description......................................... 24-26 appendix a internal memory map a.1 index of memory map tables............................................................................. a-1 appendix b clock and board guidelines b.1 mpc565/mpc566 family power distribution....................................................e-2 b.2 pll and crystal oscillator external components ..............................................e-4 b.3 crystal oscillator external components .............................................................e-4 b.3.1 kapwr filtering ............................................................................................e-5 b.3.2 pll external components...............................................................................e-6 b.3.3 pll off-chip capacitor cxfc.......................................................................e-6 b.4 pll and clock oscillator external components layout requirements .............e-7 b.4.1 traces and placement ......................................................................................e-7 b.4.2 grounding/guarding........................................................................................e-7 b.5 mios14 rtc oscillator ......................................................................................e-8 contents paragraph number title page number motorola contents xxxix appendix c tpu3 rom functions c.1 overview............................................................................................................. d-1 c.2 programmable time accumulator (pta) ........................................................... d-4 c.3 queued output match tpu3 function (qom) .................................................. d-6 c.4 table stepper motor (tsm)................................................................................ d-8 c.5 frequency measurement (fqm) .......................................................................d-11 c.6 universal asynchronous receiver/transmitter (uart).................................. d-13 c.7 new input capture/transition counter (nitc)................................................ d-16 c.8 multiphase motor commutation (comm) ...................................................... d-18 c.9 hall effect decode (halld) .......................................................................... d-20 c.10 multichannel pulse-width modulation (mcpwm) ......................................... d-22 c.11 fast quadrature decode tpu3 function (fqd) .............................................. d-29 c.12 period/pulse-width accumulator (ppwa)....................................................... d-32 c.13 output compare (oc) ...................................................................................... d-34 c.14 pulse-width modulation (pwm)...................................................................... d-36 c.15 discrete input/output (dio)............................................................................. d-38 c.16 synchronized pulse-width modulation (spwm)............................................. d-40 c.17 read/write timers and pin tpu3 function (rwtpin) .................................. d-42 c.18 id tpu3 function (id)..................................................................................... d-44 c.19 serial input/output port (siop) ....................................................................... d-46 c.19.1 parameters..................................................................................................... d-46 c.19.1.1 chan_control .................................................................................. d-49 c.19.1.2 bit_d ....................................................................................................... d-49 c.19.1.3 half_period ....................................................................................... d-49 c.19.1.4 bit_count ............................................................................................ d-49 c.19.1.5 xfer_size.............................................................................................. d-49 c.19.1.6 siop_data ............................................................................................. d-50 c.19.2 host cpu initialization of the siop function ............................................. d-50 c.19.3 siop function performance ......................................................................... d-51 c.19.3.1 xfer_size greater than 16 .................................................................. d-51 c.19.3.2 data positioning........................................................................................ d-51 c.19.3.3 data timing .............................................................................................. d-52 appendix d memory access timing contents paragraph number title page number xl mpc565/mpc566 reference manual motorola appendix e electrical characteristics e.1 package ............................................................................................................... g-2 e.2 emi characteristics ............................................................................................ g-3 e.2.1 reference documents ..................................................................................... g-3 e.2.2 definitions and acronyms .............................................................................. g-3 e.2.3 emi testing specifications............................................................................. g-3 e.3 thermal characteristics ...................................................................................... g-3 e.3.1 thermal references ........................................................................................ g-6 e.4 esd protection ................................................................................................... g-6 e.5 dc electrical characteristics.............................................................................. g-7 e.6 oscillator and pll electrical characteristics................................................... g-12 e.7 flash electrical characteristics......................................................................... g-12 e.8 power-up/down sequencing............................................................................ g-13 e.8.1 power-up/down option a ........................................................................... g-14 e.8.2 power-up/down option b ........................................................................... g-17 e.9 issues regarding power sequence ................................................................... g-19 e.9.1 application of poreset or hreset ........................................................ g-19 e.9.2 keep-alive ram.......................................................................................... g-19 e.10 ac timing ........................................................................................................ g-21 e.10.1 debug port timing ....................................................................................... g-46 e.11 pin electrical characteristics ............................................................................ g-49 e.11.1 ac electrical characteristics........................................................................ g-49 e.12 reset timing.................................................................................................. g-51 e.13 ieee 1149.1 electrical characteristics............................................................. g-55 e.14 qadc64e electrical characteristics................................................................ g-58 e.15 qsmcm electrical characteristics .................................................................. g-60 e.16 gpio electrical characteristics ........................................................................ g-63 e.17 tpu3 electrical characteristics........................................................................ g-64 e.18 toucan electrical characteristics................................................................... g-65 e.19 mios timing characteristics ........................................................................... g-65 e.19.1 mpwmsm timing characteristics .............................................................. g-66 e.19.2 mmcsm timing characteristics ................................................................. g-68 e.19.3 mdasm timing characteristics .................................................................. g-71 e.20 mpiosm timing characteristics ..................................................................... g-74 figures figure number title page number motorola figures xliii 1-1 mpc565/mpc566 block diagram ............................................................................. 1-2 1-2 memory map............................................................................................................. 1-12 1-3 internal memory block ............................................................................................ 1-13 2-1 pdmcr ? pads module configuration register...................................................... 2-6 2-2 pdmcr2 ? pads module configuration register 2 ................................................ 2-8 2-3 input propagation delay ........................................................................................... 2-44 2-4 input levels............................................................................................................... 2- 45 2-5 output propagation delay......................................................................................... 2-45 2-6 output levels and timing ........................................................................................ 2-46 2-7 mpc565/mpc566 package footprint (1 of 2) ......................................................... 2-58 2-8 figure 2-5 mpc565/mpc566 package footprint (2 of 2)........................................ 2-59 2-9 mpc565/mpc566 redistributed bump map ........................................................... 2-60 2-10 mpc565/mpc566 ball diagram .............................................................................. 2-61 2-11 mpc565/mpc566 ball diagram legend ................................................................. 2-62 2-12 mpc565/mpc566 ball map (black and white, page 1).......................................... 2-63 2-13 mpc565/mpc566 ball map (black and white, page 2).......................................... 2-64 2-14 mpc565/mpc566 ball map (black and white, page 3).......................................... 2-65 2-15 mpc565/mpc566 ball map (black and white, page 4).......................................... 2-66 3-1 rcpu block diagram................................................................................................. 3-2 3-2 sequencer data path ................................................................................................... 3-4 3-3 rcpu programming model ....................................................................................... 3-9 3-4 gprs ? general-purpose registers......................................................................... 3-13 3-5 fprs? floating-point registers .............................................................................. 3-14 3-6 fpscr ? floating-point status and control register............................................. 3-15 3-7 cr ? condition register ......................................................................................... 3-17 3-8 xer ? integer exception register.......................................................................... 3-19 3-9 lr ? link register.................................................................................................. 3-20 3-10 ctr ? count register............................................................................................. 3-21 3-11 tb ? time base (read only) spr ......................................................................... 3-21 3-12 machine state register ............................................................................................. 3-22 3-13 dsisr ? dae/source instruction service register ............................................... 3-24 3-14 dar ? data address register ................................................................................ 3-25 3-15 tb ? time base (write only)................................................................................. 3-25 3-16 dec ? decrementer register.................................................................................. 3-26 3-17 srr0 ? machine status save/restore register 0 ................................................... 3-26 figures figure number title page number xliv mpc565/mpc566 reference manual motorola 3-18 srr1 ? machine status save/restore register 1 ................................................... 3-27 3-19 sprg0?sprg3 ? general special-purpose registers 0?3 .................................... 3-27 3-20 pvr ? processor version register.......................................................................... 3-28 3-21 fpecr ? floating-point exception cause register ............................................... 3-29 3-22 basic instruction pipeline ......................................................................................... 3-42 4-1 bbc module block diagram...................................................................................... 4-2 4-2 instruction compression alternatives (mpc566 only).............................................. 4-6 4-3 compressed address format (mpc566 only) ........................................................... 4-7 4-4 branch right segment compression #1 ..................................................................... 4-8 4-5 branch right segment compression #2 ..................................................................... 4-9 4-6 global bypass instruction layout............................................................................... 4-9 4-7 class_1 instruction layout.................................................................................... 4-10 4-8 class_2 instruction layout.................................................................................... 4-11 4-9 class_3 instruction layout.................................................................................... 4-12 4-10 class_4 instruction layout.................................................................................... 4-13 4-11 code compression process ....................................................................................... 4-14 4-12 code decompression process ................................................................................... 4-15 4-13 suggested routine for operation mode switches .................................................... 4-17 4-14 exception table entries mapping............................................................................. 4-22 4-15 external interrupt vectors splitting .......................................................................... 4-26 4-16 decram interfaces block diagram ....................................................................... 4-27 4-17 btb block diagram ................................................................................................. 4-30 4-18 mpc565/mpc566 memory map.............................................................................. 4-31 4-19 bbcmcr ? bbc module configuration register spr 560 ................................. 4-33 4-20 mi_rba0 ? region base address register spr 784 mi_rba1 spr 785, mi_rba2 spr 786, mi_rba3 spr 787 ......................... 4-35 4-21 mi_ra0 ? region attribute register spr 816 mi_ra1spr 817, mi_ra2 spr 818, mi_ra3 spr 819 .................................. 4-36 4-22 mi_gra ? global region attribute register spr 528 ......................................... 4-38 4-23 eibadr ? external interrupt relocation table base address register spr 529. 4-39 4-24 dccr01? decompressor class configuration registers ...................................... 4-41 5-1 block diagram ............................................................................................................ 5-3 6-1 system configuration and protection logic............................................................... 6-3 6-2 mpc565/mpc566 memory map................................................................................ 6-5 6-3 sgpio cell ................................................................................................................. 6- 9 6-4 mpc565/mpc566 interrupt structure ...................................................................... 6-10 6-5 lower priority request masking?one bit diagram............................................... 6-15 6-6 mpc565/mpc566 interrupt controller block diagram........................................... 6-17 6-7 typical interrupt handler routine ............................................................................ 6-19 6-8 rtc block diagram.................................................................................................. 6-22 6-9 pit block diagram ................................................................................................... 6-23 figures figure number title page number motorola figures xlv 6-10 swt state diagram .................................................................................................. 6-24 6-11 swt block diagram................................................................................................. 6-25 6-12 siumcr?siu module configuration register ..................................................... 6-26 6-13 immr?internal memory mapping register spr 638 ........................................... 6-29 6-14 emcr?external master control register ............................................................. 6-31 6-15 sipend?siu interrupt pending register .............................................................. 6-33 6-16 sipend2?siu interrupt pending register 2 ......................................................... 6-33 6-17 sipend3?siu interrupt pending register3 .......................................................... 6-34 6-18 simask?siu interrupt mask register ................................................................. 6-35 6-19 simask2?siu interrupt mask register2 ............................................................. 6-35 6-20 simask3?siu interrupt mask register3 ............................................................. 6-36 6-21 siel?siu interrupt edge level register .............................................................. 6-36 6-22 sivec?siu interrupt vector register ................................................................... 6-37 6-23 example of sivec register usage for interrupt table handling............................ 6-38 6-24 sisr2?interrupt in-service register 2 .................................................................. 6-39 6-25 sisr3?interrupt in-service register 3 .................................................................. 6-39 6-26 sypcr?system protection control register ........................................................ 6-40 6-27 swsr?software service register ......................................................................... 6-41 6-28 tesr?transfer error status register .................................................................... 6-41 6-29 dec?decrementer register spr 22....................................................................... 6-43 6-30 tb?time base (reading) spr 268, 269 ................................................................ 6-43 6-31 tb?time base (writing) spr 284, 285 ................................................................. 6-43 6-32 tbref0?time base reference register 0............................................................. 6-44 6-33 tbref1?time base reference register 1 ............................................................ 6-44 6-34 tbscr?time base control and status register.................................................... 6-44 6-35 rtcsc?real-time clock status and control register ......................................... 6-45 6-36 rtc ?real-time clock register ........................................................................... 6-46 6-37 rtcal?real-time clock alarm register............................................................. 6-46 6-38 piscr?periodic interrupt status and control register .......................................... 6-46 6-39 pitc?periodic interrupt timer count .................................................................... 6-47 6-40 pitr?periodic interrupt timer register................................................................. 6-48 6-41 sgpiodt1?sgpio data register 1 ...................................................................... 6-48 6-42 sgpiodt2?sgpio data register 2 ...................................................................... 6-49 6-43 sgpiocr?sgpio control register ...................................................................... 6-50 7-1 rsr ? reset status register ..................................................................................... 7-6 7-2 reset configuration basic scheme............................................................................. 7-8 7-3 reset configuration sampling scheme for ?short? poreset assertion, limp mode disabled ...................................... 7-9 7-4 reset configuration timing for ?short? poreset assertion, limp mode enabled............................................ 7-10 figures figure number title page number xlvi mpc565/mpc566 reference manual motorola 7-5 reset configuration timing for ?long? poreset assertion, limp mode disabled ........................................... 7-10 7-6 reset configuration sampling timing requirements .............................................. 7-11 7-7 rcw? reset configuration word .......................................................................... 7-12 8-1 clock unit block diagram ......................................................................................... 8-2 8-2 main system oscillator crystal configuration........................................................... 8-3 8-3 system pll block diagram ....................................................................................... 8-5 8-4 mpc565/mpc566 clocks........................................................................................... 8-8 8-5 general system clocks select .................................................................................. 8-11 8-6 divided system clocks timing diagram ................................................................. 8-12 8-7 clocks timing for dfnh = 1 (or dfnl = 0).......................................................... 8-13 8-8 clock source switching flow chart......................................................................... 8-15 8-9 mpc565/mpc566 low-power modes flow diagram............................................. 8-20 8-10 basic power supply configuration........................................................................... 8-24 8-11 external power supply scheme ................................................................................ 8-25 8-12 keep-alive register key state diagram .................................................................. 8-27 8-13 no standby, no kapwr, all system power-on/off.............................................. 8-28 8-14 standby and kapwr, other power-on/off ............................................................ 8-29 8-15 sccr ? system clock and reset control register................................................ 8-30 8-16 plprcr ? pll, low-power, and reset-control register .................................... 8-34 8-17 colir ? change of lock interrupt register.......................................................... 8-36 8-18 vsrmcr ? vddsram control register ............................................................ 8-37 9-1 input sample window................................................................................................. 9-2 9-2 mpc565/mpc566 bus signals................................................................................... 9-3 9-3 basic transfer protocol............................................................................................... 9-8 9-4 basic flow diagram of a single beat read cycle ..................................................... 9-9 9-5 single beat read cycle ? basic timing ? zero wait states..................................... 9-10 9-6 single beat read cycle ? basic timing ? one wait state ....................................... 9-11 9-7 basic flow diagram of a single beat write cycle................................................... 9-12 9-8 single beat basic write cycle timing ? zero wait states....................................... 9-13 9-9 single beat basic write cycle timing ? one wait state ......................................... 9-14 9-10 single beat 32-bit data write cycle timing ? 16-bit port size .............................................................. 9-15 9-11 read cycle followed by write cycle when pre-discharge mode is enabled, and ehtr bit is set .......................................................................... 9-17 9-12 basic flow diagram of a burst-read cycle........................................................... 9-20 9-13 burst-read cycle ? 32-bit port size ? zero wait state ........................................... 9-21 9-14 burst-read cycle ? 32-bit port size ? one wait state ............................................ 9-22 9-15 burst-read cycle ? 32-bit port size ? wait states between beats.......................... 9-23 9-16 burst-read cycle ? 16-bit port size ........................................................................ 9-24 9-17 basic flow diagram of a burst-write cycle ............................................................ 9-25 figures figure number title page number motorola figures xlvii 9-18 burst-write cycle, 32-bit port size, zero wait states (only for external master memory controller service support) ........................ 9-26 9-19 burst-inhibit read cycle, 32-bit port size (emulated burst) .................................. 9-27 9-20 non-wrap burst with three beats............................................................................ 9-28 9-21 non-wrap burst with one data beat ....................................................................... 9-29 9-22 internal operand representation .............................................................................. 9-30 9-23 interface to different port size devices .................................................................. 9-31 9-24 bus arbitration flowchart ........................................................................................ 9-33 9-25 master signals basic connection ............................................................................. 9-34 9-26 bus arbitration timing diagram .............................................................................. 9-35 9-27 internal bus arbitration state machine .................................................................... 9-37 9-28 termination signals protocol basic connection....................................................... 9-43 9-29 termination signals protocol timing diagram ........................................................ 9-43 9-30 reservation on local bus ........................................................................................ 9-45 9-31 reservation on multilevel bus hierarchy................................................................ 9-46 9-32 retry transfer timing ? internal arbiter.................................................................. 9-48 9-33 retry transfer timing ? external arbiter................................................................. 9-49 9-34 retry on burst cycle ................................................................................................ 9-50 9-35 basic flow of an external master read access ....................................................... 9-52 9-36 basic flow of an external master write access....................................................... 9-53 9-37 peripheral mode: external master reads from mpc565/mpc566 ? two wait states ......................................................... 9-54 9-38 peripheral mode: external master writes to mpc565/mpc566 ?two wait states............................................................... 9-55 9-39 flow of retry of external master read access........................................................ 9-57 9-40 retry of external master access (internal arbiter).................................................. 9-58 9-41 instruction show cycle transaction ......................................................................... 9-60 9-42 data show cycle transaction ................................................................................... 9-61 10-1 memory controller function within the usiu ........................................................ 10-1 10-2 memory controller block diagram .......................................................................... 10-2 10-3 mpc565/mpc566 simple system configuration .................................................... 10-3 10-4 bank base address and match structure.................................................................. 10-4 10-5 a 4-2-2-2 burst read cycle (one wait state between bursts)................................ 10-9 10-6 4 beat burst read with short setup time (zero wait state).................................. 10-10 10-7 gpcm?memory devices interface ........................................................................ 10-12 10-8 memory devices interface basic timing (acs = 00,trlx = 0).......................... 10-13 10-9 peripheral devices interface ................................................................................... 10-14 10-10 peripheral devices basic timing (acs = 11,trlx = 0)....................................... 10-14 10-11 relaxed timing ? read access (acs = 11, scy = 1, trlx = 1) ...................... 10-16 10-12 relaxed timing ? write access (acs = 10, scy = 0, csnt = 0, trlx = 1)... 10-17 10-13 relaxed timing ? write access (acs = 11, scy = 0, csnt = 1, trlx = 1)... 10-18 figures figure number title page number xlviii mpc565/mpc566 reference manual motorola 10-14 relaxed timing ? write access (acs = 00, scy = 0, csnt = 1, trlx = 1 .... 10-19 10-15 consecutive accesses (write after read, ehtr = 0) ........................................... 10-20 10-16 consecutive accesses (write after read, ehtr = 1) ........................................... 10-21 10-17 consecutive accesses (read after read from different banks, ehtr = 1)........ 10-22 10-18 consecutive accesses (read after read from same bank, ehtr = 1) ............... 10-23 10-19 aliasing phenomenon illustration........................................................................... 10-28 10-20 synchronous external master configuration for gpcm-handled memory devices .............................................................. 10-32 10-21 synchronous external master basic access (gpcm controlled).......................... 10-33 10-22 mstat ? memory controller status register...................................................... 10-35 10-23 br[0] ? br[3] ? memory controller base registers 0 ? 3 ................................. 10-36 10-24 or[0] ? or[3] ? memory controller option registers 1:3 ................................ 10-38 10-25 dmbr ? dual-mapping base register ................................................................ 10-40 10-26 dmor ? dual-mapping option register............................................................. 10-41 11-1 l2u bus interface block diagram ........................................................................... 11-3 11-2 dmpu basic functional diagram ............................................................................ 11-5 11-3 region base address example ................................................................................. 11-7 11-4 l2u_mcr ? l2u module configuration register spr 568............................... 11-15 11-5 l2u_rbax ? l2u region x base address register spr 792 ? 795 .................. 11-16 11-6 l2u_rax ? l2u region x attribute register spr 824 ? 827 ........................... 11-16 11-7 l2u_gra ? l2u global region attribute register spr 536 ............................ 11-17 12-1 uimb interface module block diagram .................................................................. 12-2 12-2 imb clock ? full-speed imb bus ........................................................................... 12-3 12-3 imb clock ? half-speed imb bus........................................................................... 12-3 12-4 interrupt synchronizer signal flow .......................................................................... 12-4 12-5 time-multiplexing protocol for irq pins ................................................................ 12-5 12-6 interrupt synchronizer block diagram..................................................................... 12-7 12-7 umcr ? uimb module configuration register ................................................... 12-8 12-8 uipend ? pending interrupt request register...................................................... 12-9 13-1 dual qadc64es on mpc565/mpc566................................................................... 13-3 13-2 block diagram of qadc64e ................................................................................... 13-4 13-3 ccw queue and result table block diagram......................................................... 13-7 13-4 example of external multiplexing............................................................................ 13-8 13-5 qadcmcr ? module configuration register ................................................... 13-10 13-6 qadcint ? qadc interrupt register ................................................................ 13-14 13-7 interrupt levels on irq with ilbs ........................................................................ 13-15 13-8 portqa ? port a data register portqb ? port b data register ..................................................................... 13-16 13-9 ddrqa ? port a data direction register ddrqb ? port b data direction register ...................................................... 13-17 13-10 qacr0 ? control register ................................................................................... 13-17 figures figure number title page number motorola figures xlix 13-11 qacr1 ? control register 1 ................................................................................ 13-19 13-12 qacr2 ? control register 2 ................................................................................ 13-21 13-13 qasr0 ? status register 0 ................................................................................... 13-24 13-14 qadc64e queue status transition ....................................................................... 13-26 13-15 qasr1 ? status register 1 ................................................................................... 13-26 13-16 qadc64e conversion queue operation ............................................................... 13-28 13-17 ccw ? conversion command word table.......................................................... 13-30 13-18 rjurr ? right justified, unsigned result format ............................................. 13-34 13-19 ljsrr ? left justified, signed result format ..................................................... 13-34 13-20 ljurr ? left justified, unsigned result register .............................................. 13-34 13-21 qadc64e analog subsystem block diagram ...................................................... 13-35 13-22 conversion timing.................................................................................................. 13-36 13-23 qadc64e queue operation with pause ............................................................... 13-39 13-24 qadc64e clock subsystem functions ................................................................. 13-49 13-25 bus cycle accesses ................................................................................................ 13-52 13-26 ccw priority situation 1........................................................................................ 13-55 13-27 ccw priority situation 2........................................................................................ 13-56 13-28 ccw priority situation 3........................................................................................ 13-56 13-29 ccw priority situation 4........................................................................................ 13-57 13-30 ccw priority situation 5........................................................................................ 13-57 13-31 ccw priority situation 6........................................................................................ 13-58 13-32 ccw priority situation 7........................................................................................ 13-58 13-33 ccw priority situation 8........................................................................................ 13-59 13-34 ccw priority situation 9........................................................................................ 13-59 13-35 ccw priority situation 10...................................................................................... 13-60 13-36 ccw priority situation 11 ...................................................................................... 13-60 13-37 ccw freeze situation 12 ....................................................................................... 13-61 13-38 ccw freeze situation 13 ....................................................................................... 13-61 13-39 ccw freeze situation 14 ....................................................................................... 13-61 13-40 ccw freeze situation 15 ....................................................................................... 13-62 13-41 ccw freeze situation 16 ....................................................................................... 13-62 13-42 ccw freeze situation 17 ....................................................................................... 13-62 13-43 ccw freeze situation 18 ....................................................................................... 13-62 13-44 ccw freeze situation 19 ....................................................................................... 13-63 13-45 external trigger mode (positive edge) timing with pause .................................. 13-63 13-46 gated mode, single-scan timing........................................................................... 13-65 13-47 gated mode, continuous scan timing ................................................................... 13-66 13-48 equivalent analog input circuitry.......................................................................... 13-68 13-49 errors resulting from clipping............................................................................... 13-69 13-50 star-ground at the point of power supply origin .................................................. 13-71 13-51 electrical model of an a/d input pin ..................................................................... 13-72 figures figure number title page number l mpc565/mpc566 reference manual motorola 13-52 external multiplexing of analog signal sources ................................................... 13-74 13-53 input pin subjected to negative stress ................................................................... 13-77 13-54 input pin subjected to positive stress..................................................................... 13-77 14-1 qsmcm block diagram .......................................................................................... 14-2 14-2 qsmcm interrupt levels ......................................................................................... 14-8 14-3 qspi interrupt generation ........................................................................................ 14-9 14-4 qsmcmmcr ? qsmcm configuration register ................................................ 14-9 14-5 qdsci_il ? qsm2 dual sci interrupt level register....................................... 14-10 14-6 qspi_il ? qspi interrupt level register ........................................................... 14-11 14-7 portqs ? port qs data register ........................................................................ 14-13 14-8 pqspar ? portqs pin assignment register .................................................... 14-14 14-9 ddrqs ? portqs data direction register ....................................................... 14-15 14-10 qspi block diagram .............................................................................................. 14-17 14-11 spcr0 ? qspi control register 0........................................................................ 14-20 14-12 spcr1 ? qspi control register 1........................................................................ 14-21 14-13 spcr2 ? qspi control register 2........................................................................ 14-22 14-14 spcr3 ? qspi control register........................................................................... 14-23 14-15 spsr ? qspi status register................................................................................ 14-24 14-16 qspi ram .............................................................................................................. 14-25 14-17 cr[0:f] ? command ram................................................................................... 14-27 14-18 flowchart of qspi initialization operation ............................................................ 14-32 14-19 flowchart of qspi master operation (part 1) ........................................................ 14-33 14-20 flowchart of qspi master operation (part 2) ........................................................ 14-34 14-21 flowchart of qspi master operation (part 3) ........................................................ 14-35 14-22 flowchart of qspi slave operation (part 1) .......................................................... 14-36 14-23 flowchart of qspi slave operation (part 2) .......................................................... 14-37 14-24 sci transmitter block diagram ............................................................................. 14-48 14-25 sci receiver block diagram.................................................................................. 14-49 14-26 sccxr0 ? sci control register 0........................................................................ 14-51 14-27 sccxr1 ? sci control register 1........................................................................ 14-52 14-28 scxsr ? scix status register.............................................................................. 14-54 14-29 scxdr ? sci data register ................................................................................. 14-56 14-30 start search example .............................................................................................. 14-63 14-31 qsci1cr ? qsci1 control register.................................................................... 14-66 14-32 qsci1sr ? qsci1 status register....................................................................... 14-68 14-33 queue transmitter block enhancements................................................................ 14-69 14-34 queue transmit flow.............................................................................................. 14-71 14-35 queue transmit software flow .............................................................................. 14-72 14-36 queue transmit example for 17 data bytes .......................................................... 14-74 14-37 queue transmit example for 25 data frames........................................................ 14-75 14-38 queue receiver block enhancements .................................................................... 14-76 figures figure number title page number motorola figures li 14-39 queue receive flow ............................................................................................... 14-79 14-40 queue receive software flow................................................................................ 14-80 14-41 queue receive example for 17 data bytes............................................................ 14-81 15-1 dlcmd2 block diagram......................................................................................... 15-3 15-2 typical transmit/receive operation ........................................................................ 15-5 15-3 vpw signal waveforms ......................................................................................... 15-15 15-4 huntzicker waveform message .............................................................................. 15-16 15-5 start of frame symbol ............................................................................................ 15-16 15-6 passive ?0? and active ?0? ..................................................................................... 15-16 15-7 passive ?1? and active ?1?...................................................................................... 15-17 15-8 end of data symbol ................................................................................................ 15-17 15-9 end of frame symbol ............................................................................................. 15-17 15-10 break symbol controller module (dlcmd2)....................................................... 15-18 15-11 support for external transceiver ........................................................................... 15-19 15-12 dlcmd2 operation modes ................................................................................... 15-20 15-13 stop power mode (no stop bit set) .................................................................. 15-23 15-14 debug power mode (ifeezeb or soft_frz) ................................................. 15-23 15-15 stop power mode (stop bit set) ........................................................................ 15-24 15-16 lpstop power mode............................................................................................. 15-24 15-17 mcr? module configuration register................................................................. 15-31 15-19 interrupt request logic path .................................................................................. 15-33 15-18 ipr ? interrupt pending register .......................................................................... 15-33 15-20 ilr ? interrupt level register r ........................................................................... 15-34 15-21 ivr ? interrupt vector register ............................................................................ 15-35 15-22 sctl ? symbol timing control and pre-scaler register.................................... 15-35 15-23 sdata? symbol timing data register ............................................................... 15-37 15-24 dlcmd2 sdata block diagram ......................................................................... 15-38 15-25 cmd? transmit command register .................................................................... 15-39 15-26 tdata? transmit data register.......................................................................... 15-43 15-27 txfifo block diagram .......................................................................................... 15-44 15-28 stat? receive status register............................................................................. 15-44 15-30 rxfifo block diagram.......................................................................................... 15-47 15-29 rdata? receive data register ........................................................................... 15-47 15-31 completion code byte bit definitions ................................................................... 15-48 15-32 sof symbol too short ........................................................................................... 15-51 15-33 short bit too short ................................................................................................. 15-51 15-34 long bit too long.................................................................................................. 15-52 15-35 eod and eof too short ........................................................................................ 15-52 15-36 normalization bit too short................................................................................... 15-52 15-37 normalization bit too long ................................................................................... 15-53 15-38 interrupt request multiplex timing ....................................................................... 15-56 figures figure number title page number lii mpc565/mpc566 reference manual motorola 15-39 dlcmd2 interrupt vector generation (irq_plug = 1)...................................... 15-57 15-40 types of ifr............................................................................................................ 15-6 0 15-41 j1850 node ............................................................................................................. 15-6 1 15-42 dlcmd2 external connections............................................................................. 15-62 16-1 toucan block diagram........................................................................................... 16-1 16-2 typical can network .............................................................................................. 16-3 16-3 extended id message buffer structure .................................................................... 16-4 16-4 standard id message buffer structure ..................................................................... 16-4 16-5 can controller state diagram............................................................................... 16-12 16-6 interrupt levels on irq with ilbs.......................................................................... 16-22 16-7 toucan message buffer memory map................................................................. 16-26 16-8 canmcr ? toucan module configuration register........................................ 16-26 16-9 canicr ? toucan interrupt configuration register ........................................ 16-28 16-10 canctrl0 ? control register 0 ........................................................................ 16-29 16-11 canctrl1 ? control register 1 ........................................................................ 16-30 16-12 presdiv ? prescaler divide register ................................................................. 16-31 16-13 canctrl2 ? control register 2 ........................................................................ 16-32 16-14 timer ? free running timer register ............................................................... 16-33 16-15 rxgmskhi ? receive global mask register high rxgmsklo ? receive global mask register low ...................................... 16-33 16-16 estat ? error and status register....................................................................... 16-34 16-17 imask ? interrupt mask register........................................................................ 16-37 16-18 iflag ? interrupt flag register .......................................................................... 16-37 16-19 rxectr ? receive error counter txectr ? transmit error counter.................................................................. 16-38 17-1 mpc565/mpc566 mios14 block diagram ............................................................ 17-2 17-2 mios14 memory map............................................................................................ 17-12 17-3 mios14tpcr ? test and pin control register ................................................... 17-14 17-4 mios14vect ? vector register ......................................................................... 17-15 17-5 mios14vnr ? mios14 module/version number register ............................... 17-15 17-6 mios14mcr? module configuration register................................................... 17-15 17-7 mcpsm block diagram ......................................................................................... 17-17 17-8 mcpsmscr ? mcpsm status/control register ................................................ 17-18 17-9 mmcsm block diagram........................................................................................ 17-21 17-10 mmcsm modulus up-counter.............................................................................. 17-21 17-11 mmcsmcnt ? mmcsm up-counter register ................................................. 17-25 17-12 mmcsmml ? mmcsm modulus latch register.............................................. 17-25 17-13 mmcsmscr ? mmcsm status/control register.............................................. 17-26 17-14 mdasm block diagram ........................................................................................ 17-29 17-15 input pulse width measurement example.............................................................. 17-33 17-16 input period measurement example....................................................................... 17-34 figures figure number title page number motorola figures liii 17-17 mdasm input capture example ........................................................................... 17-35 17-18 single shot output pulse example ......................................................................... 17-37 17-19 single shot output transition example ................................................................. 17-38 17-20 mdasm output pulse width modulation example .............................................. 17-40 17-21 mdasmar ? mdasm dataa register ............................................................. 17-44 17-22 mdasmbr ? mdasm datab register ............................................................. 17-45 17-23 mdasmscr ? mdasm status/control register............................................... 17-46 17-24 mpwmsm block diagram .................................................................................... 17-50 17-25 mpwmperr ? mpwmsm period register....................................................... 17-61 17-26 mpwmpulr ? mpwmsm pulse width register.............................................. 17-62 17-27 mpwmcntr ? mpwmsm counter register.................................................... 17-63 17-28 mpwmcntr ? mpwmsm counter register.................................................... 17-64 17-29 mpiosm 1-bit block diagram............................................................................... 17-66 17-30 mpiosm ? register organization........................................................................ 17-68 17-31 mpiosmdr ? mpiosm data register............................................................... 17-68 17-32 mpiosmddr ? mpiosm data direction register............................................ 17-69 17-33 mios14 interrupt structure .................................................................................... 17-70 17-34 mios14sr0 ? interrupt status register............................................................... 17-72 17-35 mios14er0 ? interrupt enable register ............................................................. 17-72 17-36 mios14rpr0 ? interrupt request pending register........................................... 17-73 17-37 mios14sr1 ? interrupt status register............................................................... 17-74 17-38 mios14er1 ? interrupt enable register ............................................................. 17-74 17-39 mios14rpr1 ? interrupt request pending register........................................... 17-75 17-40 mios14lvl0 ? mios14 interrupt level register 0........................................... 17-76 17-41 mios14lvl1 ? mios14 interrupt level register 1........................................... 17-76 17-42 mios14 example: double capture pulse width measurement............................. 17-78 17-43 mios14 example: double capture period measurement...................................... 17-79 17-44 mios14 example: double edge output compare................................................. 17-80 17-45 mios14 example: pulse width modulation output .............................................. 17-81 17-46 mrtcsm block diagram ...................................................................................... 17-83 17-47 mios rtc oscillator circuit ................................................................................. 17-85 17-48 selection of vt_vddrtc ............................................................................................. 17-85 17-49 15-bit prescaler and 32-bit free-running counter buffer updates ...................... 17-87 17-50 mrtcsm? register organization........................................................................ 17-92 17-51 mrtcsmfrch ? mrtcsm 32-bit counter high buffer register................... 17-92 17-52 mrtcsmfrcl ? mrtcsm 32-bit counter low buffer register ................... 17-93 17-53 mrtcpr ? mrtcsm prescaler counter buffer register................................... 17-93 17-54 mrtcsmscr ? mrtcsm status/control register ........................................... 17-93 18-1 tpu3 block diagram................................................................................................ 18-2 18-2 tpu3 interrupt levels .............................................................................................. 18-6 18-3 tcr1 prescaler control ............................................................................................ 18-8 figures figure number title page number liv mpc565/mpc566 reference manual motorola 18-4 tcr2 prescaler control ............................................................................................ 18-9 18-5 tpumcr ? tpu module configuration register ............................................... 18-13 18-6 dscr ? development support control register ................................................. 18-14 18-7 dssr ? development support status register .................................................... 18-16 18-8 ticr ? tpu3 interrupt configuration register ................................................... 18-16 18-9 cier ? channel interrupt enable register........................................................... 18-17 18-10 cfsr0 ? channel function select register 0 ...................................................... 18-18 18-11 cfsr1 ? channel function select register 1 ...................................................... 18-18 18-12 cfsr2 ? channel function select register 2 ...................................................... 18-18 18-13 cfsr3 ? channel function select register 3 ...................................................... 18-19 18-14 hsqr0 ? host sequence register 0..................................................................... 18-19 18-15 hsqr1 ? host sequence register 1..................................................................... 18-19 18-16 hsrr0 ? host service request register 0 .......................................................... 18-20 18-17 hsrr1 ? host service request register 1 .......................................................... 18-20 18-18 cpr0 ? channel priority register 0 ..................................................................... 18-21 18-19 cpr1 ? channel priority register 1 ..................................................................... 18-21 18-20 cisr ? channel interrupt status register ............................................................ 18-22 18-21 tpumcr2 ? tpu module configuration register 2 .......................................... 18-23 18-22 tpumcr3 ? tpu module configuration register 3 .......................................... 18-25 19-1 dptram configuration........................................................................................... 19-3 19-2 dptram memory map ........................................................................................... 19-4 19-3 dptmcr ? dpt module configuration register .................................................. 19-5 19-4 rambar ? ram array base address register................................................... 19-6 19-5 misrh ? multiple input signature register high ................................................. 19-7 19-6 misrl ? multiple input signature register low .................................................. 19-7 19-7 miscnt ? misc counter ...................................................................................... 19-7 20-1 block diagram for a 512-kbyte uc3f module configuration ................................ 20-2 20-2 uc3fmcr ? uc3f eeprom configuration register ......................................... 20-7 20-3 uc3fmcre? uc3f eeprom extended configuration register ..................... 20-11 20-4 uc3fctl? uc3f eeprom high voltage control register.............................. 20-14 20-5 pegood valid time.............................................................................................. 20-17 20-6 shadow information................................................................................................ 20-19 20-7 uc3fcfig ? hard reset configuration word..................................................... 20-20 20-8 512-kbyte array configurations ............................................................................ 20-23 20-9 program state diagram ........................................................................................... 20-28 20-10 erase state diagram................................................................................................ 20-32 20-11 censorship states and transitions........................................................................... 20-39 21-1 system block diagram ............................................................................................. 21-3 21-2 mpc565/mpc566 memory map with calram address ranges ........................ 21-4 21-3 standby power supply configuration for calram array..................................... 21-6 21-4 calram_a array .................................................................................................. 21-9 figures figure number title page number motorola figures lv 21-5 calram_a module overlay map of flash (clps = 0)...................................... 21-10 21-6 calram_b and calram_a address map (when clps = 0)......................... 21-11 21-7 calram module overlay map of flash (clps = 1) .......................................... 21-12 21-8 calram_b and calram_a address map (when clps = 1 for both calram_a and calram_b)............................ 21-13 21-9 crammcr ? calram module configuration register.................................. 21-17 21-10 cram_rba0-7 ? calram region base address register ............................ 21-20 21-11 cramovlcr ? calram overlay configuration register............................. 21-21 21-12 cramotr ? calram ownership trace register ........................................... 21-22 22-1 watchpoints and breakpoint support in the cpu................................................... 22-10 22-2 partially supported watchpoint/breakpoint example ............................................ 22-15 22-3 instruction support general structure .................................................................... 22-18 22-4 load/store support general structure .................................................................... 22-21 22-5 functional diagram of mpc565/mpc566 debug mode support.......................... 22-24 22-6 debug mode logic ................................................................................................. 22-26 22-7 debug mode reset configuration .......................................................................... 22-28 22-8 asynchronous clock serial communications ........................................................ 22-36 22-9 synchronous self clock serial communication..................................................... 22-36 22-10 enabling clock mode following reset .................................................................. 22-37 22-11 download procedure code example ...................................................................... 22-42 22-12 slow download procedure loop ............................................................................ 22-42 22-13 fast download procedure loop.............................................................................. 22-42 22-14 cmpa?cmpd ? comparator a?d value register spr 144 ? spr 147............. 22-45 22-15 cmpe?cmpf ? comparator e?f value registers spr 152, 153 ....................... 22-46 22-16 bar ? breakpoint address register spr 159 ..................................................... 22-46 22-17 cmpg?cmph ? comparator g?h value registers spr 154, 155 ..................... 22-47 22-18 ictrl ? i-bus support control register spr 158 .............................................. 22-47 22-19 lctrl1 ? l-bus support control register 1 spr 156....................................... 22-49 22-20 lctrl2 ? l-bus support control register 2 spr 157....................................... 22-50 22-21 counta ? breakpoint counter a value and control register spr 150 ........... 22-52 22-22 countb ? breakpoint counter b value and control register spr 151 ........... 22-53 22-23 ecr ? exception cause register spr 148 .......................................................... 22-54 22-24 der ? debug enable register spr 149 .............................................................. 22-55 23-1 readi functional block diagram........................................................................... 23-4 23-2 readi_otr ? readi ownership trace register ............................................. 23-10 23-3 readi_did ? readi device id register ......................................................... 23-11 23-4 readi_dc ? readi development control (dc) register ............................... 23-11 23-5 readi_uba ? readi user base address register .......................................... 23-13 23-6 readi_rwa ? readi read/write access register.......................................... 23-14 23-7 readi_udi ? readi upload/download information register ........................ 23-16 23-8 rwd field configuration ....................................................................................... 23-17 figures figure number title page number lvi mpc565/mpc566 reference manual motorola 23-9 readi_dta 1 ? readi data trace attributes 1 register readi_dta 2 ? readi data trace attributes 2 register ........................... 23-17 23-10 enabling program trace out of system reset ........................................................ 23-22 23-11 functional diagram of pin interface....................................................................... 23-24 23-12 auxiliary pin packet structure for program trace indirect branch message ........ 23-26 23-13 msei/mseo transfers ........................................................................................... 23-27 23-14 transmission sequence of messages ...................................................................... 23-34 23-15 readi module enabled ......................................................................................... 23-36 23-16 readi module disabled........................................................................................ 23-38 23-17 rcpu instruction flow........................................................................................... 23-40 23-18 direct branch message format............................................................................... 23-43 23-19 indirect branch message format ............................................................................ 23-44 23-20 indirect branch message format with compressed code...................................... 23-44 23-21 bit pointer format with compressed code ............................................................ 23-44 23-22 program trace correction message format ........................................................... 23-47 23-23 error message (queue overflow) format .............................................................. 23-48 23-24 direct branch synchronization message format ................................................... 23-49 23-25 indirect branch synchronization message format ................................................. 23-50 23-26 direct branch synchronization message format with compressed code ............ 23-50 23-27 indirect branch synchronization message format with compressed code.......... 23-50 23-28 relative address generation and re-creation ....................................................... 23-51 23-29 vf state decoding .................................................................................................. 23-53 23-30 btm encoding flow .............................................................................................. 23-54 23-31 btm encoding flow ? compressed code support.............................................. 23-55 23-32 direct branch message ........................................................................................... 23-56 23-33 indirect branch message......................................................................................... 23-56 23-34 indirect branch message with compressed code.................................................. 23-57 23-35 program trace correction message........................................................................ 23-57 23-36 error message (program/data/ownership trace overrun) .................................... 23-57 23-37 direct branch synchronization message ................................................................ 23-58 23-38 indirect branch synchronization message ............................................................. 23-58 23-39 direct branch synchronization message with compressed code......................... 23-58 23-40 indirect branch synchronization message with compressed code ...................... 23-59 23-41 data write message format.................................................................................... 23-60 23-42 data read message format .................................................................................... 23-60 23-43 data write synchronization message format ........................................................ 23-61 23-44 data read synchronization message format ......................................................... 23-61 23-45 error message (queue overflow) format .............................................................. 23-62 23-46 data trace flow diagram for non-pipelined access............................................. 23-63 23-47 date write message ................................................................................................ 23-66 23-48 data read message ................................................................................................. 23-66 figures figure number title page number motorola figures lvii 23-49 data write synchronization message ..................................................................... 23-66 23-50 data read synchronization message...................................................................... 23-67 23-51 error message (program/data/ownership trace overrun) .................................... 23-67 23-52 target ready message ............................................................................................ 23-68 23-53 read register message ........................................................................................... 23-68 23-54 write register message .......................................................................................... 23-68 23-55 read/write response message ............................................................................... 23-68 23-56 read/write access flow diagram.......................................................................... 23-69 23-57 error message (read/write access error) format ................................................. 23-76 23-58 error message (invalid message) format............................................................... 23-76 23-59 error message (invalid access opcode) format .................................................... 23-76 23-60 block write access................................................................................................. 23-79 23-61 block read access.................................................................................................. 23-79 23-62 device ready for upload/download request message ......................................... 23-80 23-63 upload request message ........................................................................................ 23-80 23-64 download request message ................................................................................... 23-81 23-65 upload/download information message ................................................................ 23-81 23-66 error message (invalid access opcode) ................................................................ 23-82 23-67 watchpoint message format................................................................................... 23-83 23-68 error message (watchpoint overrun) format ........................................................ 23-83 23-69 watchpoint message ............................................................................................... 23-84 23-70 error message (watchpoint overrun) ..................................................................... 23-84 23-71 ownership trace message format.......................................................................... 23-85 23-72 error message format............................................................................................. 23-85 23-73 ownership trace message ...................................................................................... 23-86 23-74 error message (program/data/ownership trace overrun) .................................... 23-86 23-75 rcpu development access multiplexing between readi and bdm pins ........ 23-87 23-76 dsdi message format............................................................................................ 23-88 23-77 dsdo message format .......................................................................................... 23-88 23-78 bdm status message format ................................................................................. 23-89 23-79 error message (invalid message) format............................................................... 23-89 23-80 rcpu development access flow diagram ........................................................... 23-92 23-81 rcpu development access timing diagram ? debug mode entry out-of-reset ............................................................................................. 23-94 23-82 transmission sequence of dsdx data messages .................................................. 23-95 23-83 error message (invalid message) ........................................................................... 23-95 23-84 dsdi data message (assert non-maskable breakpoint) ...................................... 23-95 23-85 dsdi data message (cpu instruction ? rfi) ........................................................ 23-96 23-86 dsdo data message (cpu data out) ................................................................... 23-96 23-87 programming uc3f flash via readi r/w access (sheet 1 of 2) ..................... 23-102 23-88 programming uc3f flash via readi r/w access (sheet 2 of 2) ..................... 23-103 figures figure number title page number lviii mpc565/mpc566 reference manual motorola 24-1 pin requirement on jtag ........................................................................................ 24-1 24-2 test logic block diagram ........................................................................................ 24-3 24-3 tap controller state machine .................................................................................. 24-4 24-4 bypass register....................................................................................................... 24-24 b-1 power distribution diagram ? 2.6 v ........................................................................e-2 b-2 power distribution diagram ? 5 v and analog........................................................e-3 b-3 crystal oscillator circuit ............................................................................................e-4 b-4 rc filter example ......................................................................................................e-5 b-5 bypass capacitors example (alternative) ..................................................................e-5 b-6 rc filter example ......................................................................................................e-6 b-7 lc filter example (alternative) .................................................................................e-6 b-8 pll off-chip capacitor example ..............................................................................e-7 b-9 mios rtc oscillator circuit .....................................................................................e-8 c-1 tpu3 memory map ................................................................................................... d-1 c-2 two possible siop configurations.......................................................................... d-46 c-3 siop function data transition example................................................................. d-52 e-1 option a power-up sequence without keep-alive supply ................................... g-15 e-2 option a power-up sequence with keep-alive supply ........................................ g-15 e-3 option a power-down sequence without keep-alive supply .............................. g-16 e-4 option a power-down sequence with keep-alive supply ................................... g-16 e-5 option b power-up sequence without keep-alive supply ................................... g-17 e-6 option b power-up sequence with keep-alive supply ........................................ g-18 e-7 option b power-down sequence without keep-alive supply .............................. g-18 e-8 option b power-down sequence with keep-alive supply .................................... g-19 e-9 generic timing examples........................................................................................ g-21 e-10 clkout pin timing .............................................................................................. g-29 e-11 synchronous output signals timing ....................................................................... g-30 e-12 predischarge timing ................................................................................................ g-31 e-13 synchronous active pull-up and open drain outputs signals timing....................................................................................... g-32 e-14 synchronous input signals timing .......................................................................... g-33 e-15 input data timing in normal case.......................................................................... g-34 e-16 external bus read timing (gpcm controlled ? acs = ?00?) ............................... g-35 e-17 external bus read timing (gpcm controlled ? trlx = ?0? acs = ?10?)........... g-36 e-18 external bus read timing (gpcm controlled ? trlx = ?0? acs = ?11?) ........... g-37 e-19 external bus read timing (gpcm controlled ? trlx = ?1?, acs = ?10?, acs = ?11?) ............................ g-38 e-20 address show cycle bus timing ............................................................................ g-39 e-21 address and data show cycle bus timing............................................................. g-40 e-22 external bus write timing (gpcm controlled ? trlx = ?0?, csnt = ?0?)......... g-41 e-23 external bus write timing (gpcm controlled ? trlx = ?0?, csnt = ?1?)......... g-42 figures figure number title page number motorola figures lix e-24 external bus write timing (gpcm controlled ? trlx = ?1?, csnt = ?1?)......... g-43 e-25 external master read from internal registers timing ........................................... g-44 e-26 external master write to internal registers timing ............................................... g-45 e-27 interrupt detection timing for external edge sensitive lines ............................... g-46 e-28 debug port clock input timing............................................................................... g-47 e-29 debug port timings ................................................................................................. g-48 e-30 auxiliary port data input timing diagram ............................................................. g-49 e-31 auxiliary port data output timing diagram .......................................................... g-50 e-32 enable auxiliary from rsti ................................................................................... g-50 e-33 disable auxiliary from rsti.................................................................................. g-50 e-34 reset timing ? configuration from data bus ......................................................... g-52 e-35 reset timing ? data bus weak drive during configuration ................................. g-53 e-36 reset timing ? debug port configuration .............................................................. g-54 e-37 jtag test clock input timing ................................................................................ g-55 e-38 jtag test access port timing diagram ................................................................. g-56 e-39 boundary scan (jtag) timing diagram ................................................................ g-57 e-40 qspi timing ? master, cpha = 0 .......................................................................... g-61 e-41 qspi timing ? master, cpha = 1 .......................................................................... g-62 e-42 qspi timing ? slave, cpha = 0............................................................................. g-62 e-43 qspi timing ? slave, cpha = 1............................................................................. g-63 e-44 tpu3 timing ........................................................................................................... g-64 e-45 mcpsm enable to vs_pclk pulse timing diagram............................................ g-66 e-46 mpwmsm minimum output pulse example timing diagram ............................. g-67 e-47 mcpsm enable to mpwmo output pin rising edge timing diagram .............. g-67 e-48 mpwmsm enable to mpwmo output pin rising edge timing diagram.......... g-68 e-49 mpwmsm interrupt flag to mpwmo output pin falling edgetiming diagram .......................................................................................... g-68 e-50 mmcsm minimum input pin (either load or clock)timing diagram ................ g-69 e-51 mmcsm clock pin to counter bus increment timing diagram .......................... g-70 e-52 mmcsm load pin to counter bus reloadtiming diagram ................................. g-70 e-53 mmcsm counter bus reload to interrupt flag setting timing diagram ............ g-70 e-54 mmcsm prescaler clock select to counter bus increment timing diagram .................................................................................................. g-71 e-55 mdasm minimum input pin timing diagra ......................................................... g-72 e-56 mdasm input pin to counter bus capture timing diagram ............................... g-72 e-57 mdasm input pin to mdasm interrupt flag timing diagram............................ g-72 e-58 mdasm minimum output pulse width timing diagram ..................................... g-73 e-59 counter bus to mdasm output pin change timing diagram .............................. g-73 e-60 counter bus to mdasm interrupt flag setting timing diagram .......................... g-73 e-61 mpiosm input pin to mpiosm_dr (data register) timing diagram ................ g-74 figures lx mpc565/mpc566 reference manual motorola tables table number title page number motorola tables lxvii 1-1 differences between modules of the mpc555/mpc556 and the mpc565/mpc566 ..................................................................................... 1-8 2-1 mpc565/mpc566 pad function summary................................................................ 2-1 2-2 mpc565/mpc566 module pin sharing description.................................................. 2-6 2-3 pdmcr bit descriptions............................................................................................ 2-7 2-4 pdmcr2 field descriptions ...................................................................................... 2-8 2-5 dlcmd2 / qsmcm b sci2 pin mux control ....................................................... 2-18 2-6 pin reset state........................................................................................................... 2-33 2-7 functional pad types ................................................................................................ 2-42 2-8 other pad types ........................................................................................................ 2-42 2-9 target dc electrical characteristics ......................................................................... 2-43 2-10 pin names and ball assignments ............................................................................. 2-47 3-1 rcpu execution units ............................................................................................... 3-5 3-2 supervisor-level sprs ............................................................................................. 3-10 3-3 development support sprs...................................................................................... 3-12 3-4 fpscr bit categories............................................................................................... 3-14 3-5 fpscr bit descriptions............................................................................................ 3-15 3-6 floating-point result flags in fpscr...................................................................... 3-17 3-7 bit settings for cr0 field of cr .............................................................................. 3-18 3-8 bit settings for cr1 field of cr .............................................................................. 3-18 3-9 crn field bit settings for compare instructions ..................................................... 3-19 3-10 integer exception register bit descriptions............................................................. 3-20 3-11 time base field definitions (read only) ................................................................ 3-21 3-12 machine state register bit descriptions .................................................................. 3-22 3-13 floating-point exception mode bits......................................................................... 3-24 3-14 time base field (write only) bit descriptions........................................................ 3-25 3-15 uses of sprg0?sprg3............................................................................................ 3-27 3-16 processor version register bit descriptions ............................................................ 3-28 3-17 eie, eid, and nri registers ................................................................................. 3-28 3-18 fpecr bit descriptions ........................................................................................... 3-29 3-19 instruction set summary........................................................................................... 3-31 3-20 mpc565/mpc566 exception classes ...................................................................... 3-38 3-21 exception vector offset table ................................................................................. 3-39 3-22 instruction latency and blockage............................................................................. 3-42 3-23 floating-point exception mode encoding................................................................ 3-48 tables table number title page number lxviii mpc565/mpc566 reference manual motorola 3-24 settings caused by reset ......................................................................................... 3-49 3-25 register settings following an nmi ........................................................................ 3-50 3-26 machine check exception processor actions .......................................................... 3-51 3-27 register settings following a machine check exception........................................ 3-51 3-28 register settings following external interrupt ....................................................... 3-53 3-29 register settings for alignment exception ............................................................. 3-54 3-30 register settings following program exception ..................................................... 3-56 3-31 register settings following a floating-point unavailable exception..................... 3-57 3-32 register settings following a decrementer exception ........................................... 3-58 3-33 register settings following a system call exception............................................. 3-59 3-34 register settings following a trace exception ........................................................ 3-59 3-35 register settings following floating-point assist exceptions ................................ 3-60 3-36 register settings following a software emulation exception................................. 3-61 3-37 register settings following an instruction protection exception ............................ 3-62 3-38 register settings following a data protection error exception............................... 3-63 3-39 register settings following a debug exception ...................................................... 3-64 3-40 register settings for l-bus breakpoint instances .................................................... 3-64 4-1 exception addresses mapping.................................................................................. 4-23 4-2 exception relocation page offset ............................................................................ 4-24 4-3 bbc sprs ................................................................................................................. 4-32 4-4 bbcmcr bbc module configuration register bit descriptions ......................... 4-33 4-5 mi_rba[0:3] registers bit descriptions................................................................ 4-36 4-6 mi_ra[0:3] registers bit descriptions .................................................................. 4-36 4-7 region size programming possible values .............................................................. 4-37 4-8 mi_gra global region attribute register bits description ................................. 4-38 4-9 eibadr external interrupt relocation table base address register bit descriptions............................................................... 4-40 4-10 dccr0-dccr15 decompressor class configuration registers bit descriptions (mpc566 only)......................................................................... 4-42 4-11 instruction layout encoding (mpc566 only).......................................................... 4-43 5-1 address map ............................................................................................................... 5-3 5-2 usiu special-purpose registers ................................................................................ 5-7 5-3 mpc565/mpc566 address format for spr access from external bus ................... 5-8 6-1 usiu pin multiplexing control .................................................................................. 6-4 6-2 sgpio configuration.................................................................................................. 6-8 6-3 priority of interrupt sources?regular operation ................................................... 6-12 6-4 priority of interrupt sources?enhanced operation................................................. 6-13 6-5 interrupt latency estimation for three typical cases ............................................. 6-18 6-6 decrementer time-out periods ................................................................................ 6-21 6-7 siumcr bit descriptions ....................................................................................... 6-27 6-8 debug pins configuration......................................................................................... 6-28 tables table number title page number motorola tables lxix 6-9 general pins configuration....................................................................................... 6-28 6-10 single-chip select field pin configuration.............................................................. 6-28 6-11 multi-level reservation control pin configuration ................................................ 6-29 6-12 immr bit descriptions ........................................................................................... 6-30 6-13 emcr bit descriptions ........................................................................................... 6-31 6-14 siu interrupt controller ? bit acronym definitions................................................ 6-33 6-15 sypcr bit descriptions .......................................................................................... 6-40 6-16 swsr bit descriptions............................................................................................ 6-41 6-17 tesr bit descriptions............................................................................................. 6-42 6-18 tbscr bit descriptions .......................................................................................... 6-44 6-19 rtcsc bit descriptions .......................................................................................... 6-45 6-20 piscr bit descriptions ........................................................................................... 6-47 6-21 pitc bit descriptions .............................................................................................. 6-47 6-22 pit bit descriptions................................................................................................. 6-48 6-23 sgpiodt1 bit descriptions.................................................................................... 6-49 6-24 sgpiodt2 bit descriptions.................................................................................... 6-49 6-25 sgpiocr bit descriptions...................................................................................... 6-50 6-26 data direction control.............................................................................................. 6-51 7-1 reset action taken for each reset cause ................................................................. 7-4 7-2 reset configuration word and data corruption/coherency ...................................... 7-5 7-3 reset status register bit descriptions........................................................................ 7-6 7-4 reset configuration options....................................................................................... 7-7 7-5 rcw bit descriptions .............................................................................................. 7-12 8-1 reset clocks source configuration ............................................................................ 8-9 8-2 tmbclk divisions.................................................................................................. 8-10 8-3 status of clock source .............................................................................................. 8-16 8-4 power mode control bit settings ............................................................................ 8-17 8-5 power mode descriptions ........................................................................................ 8-17 8-6 power mode wake-up operation ............................................................................ 8-18 8-7 power supplies......................................................................................................... 8-21 8-8 kapwr registers and key registers ...................................................................... 8-26 8-9 sccr bit descriptions ............................................................................................. 8-31 8-10 com and cqds bits functionality ......................................................................... 8-33 8-11 plprcr bit descriptions........................................................................................ 8-34 8-12 colir bit descriptions........................................................................................... 8-37 8-13 vsrmcr bit descriptions ...................................................................................... 8-37 9-1 mpc565/mpc566 siu signals .................................................................................. 9-4 9-2 data bus requirements for read cycles ................................................................. 9-31 9-3 data bus contents for write cycles ......................................................................... 9-32 9-4 priority between internal and external masters over external bus ......................... 9-36 9-5 burst length and order............................................................................................. 9-39 tables table number title page number lxx mpc565/mpc566 reference manual motorola 9-6 burst/tsize encoding ......................................................................................... 9-39 9-7 address type pins..................................................................................................... 9-40 9-8 address types definition.......................................................................................... 9-41 9-9 termination signals protocol.................................................................................... 9-51 10-1 timing attributes summary ................................................................................... 10-11 10-2 programming rules for timing strobes ................................................................. 10-23 10-3 write enable/byte enable signals function........................................................... 10-26 10-4 memory controller functionality from reset........................................................ 10-30 10-5 boot bank fields values after hard reset............................................................. 10-30 10-6 memory controller address map ........................................................................... 10-34 10-7 mstat bit descriptions........................................................................................ 10-35 10-8 br[0] ? br[3] bit descriptions............................................................................. 10-36 10-9 brx[v] reset value............................................................................................... 10-37 10-10 or[0] ? or[3] bit descriptions ............................................................................ 10-38 10-11 dmbr bit descriptions.......................................................................................... 10-40 10-12 dmor bit descriptions.......................................................................................... 10-41 11-1 dmpu registers ....................................................................................................... 11-7 11-2 reservation snoop support..................................................................................... 11-10 11-3 l2u_mcr lshow modes ................................................................................... 11-10 11-4 l2u show cycle support chart ............................................................................. 11-13 11-5 l2u (ppc) register decode ................................................................................... 11-14 11-6 hex address for spr cycles ................................................................................. 11-14 11-7 l2u_mcr bit descriptions .................................................................................. 11-15 11-8 l2u_rbax bit descriptions ................................................................................. 11-16 11-9 l2u_rax bit descriptions.................................................................................... 11-17 11-10 l2u_gra bit descriptions................................................................................... 11-18 12-1 stop and hspeed bit functionality...................................................................... 12-3 12-2 bus cycles and system clock cycles....................................................................... 12-3 12-3 ilbs signal functionality ......................................................................................... 12-5 12-4 irqmux functionality ............................................................................................ 12-6 12-5 uimb interface register map .................................................................................. 12-7 12-6 umcr bit descriptions........................................................................................... 12-8 12-7 uipend bit descriptions ......................................................................................... 12-9 13-1 qadc64e_a address map...................................................................................... 13-5 13-2 qadc64e_b address map...................................................................................... 13-6 13-3 multiplexed analog input channels ......................................................................... 13-8 13-4 analog input channels.............................................................................................. 13-9 13-5 qadcmcr bit descriptions ................................................................................. 13-10 13-6 qadc64e bus error response .............................................................................. 13-13 13-7 qadcint bit descriptions.................................................................................... 13-14 13-8 qacr0 bit descriptions ........................................................................................ 13-17 tables table number title page number motorola tables lxxi 13-9 prescaler fsysclk divide-by values................................................................... 13-18 13-10 qacr1 bit descriptions ........................................................................................ 13-19 13-11 queue 1 operating modes ...................................................................................... 13-20 13-12 qacr2 bit descriptions ........................................................................................ 13-21 13-13 queue 2 operating modes ...................................................................................... 13-22 13-14 pause response ....................................................................................................... 13-24 13-15 queue status............................................................................................................ 13- 24 13-16 qasr1 bit descriptions ......................................................................................... 13-27 13-17 ccw bit descriptions ............................................................................................ 13-30 13-18 input sample times ................................................................................................ 13-31 13-19 multiplexed channel assignments and pin designations ...................................... 13-31 13-20 qadc64e clock programmability ........................................................................ 13-50 13-21 trigger events ......................................................................................................... 13-5 4 13-22 status bits................................................................................................................ 13-54 13-23 external circuit settling time to 1/2 lsb (10-bit conversions).......................... 13-75 13-24 error resulting from input leakage (ioff).......................................................... 13-76 14-1 dlcmd2 / qsmcm_b sci2 pin mux control .................................................... 14-2 14-2 qsmcm pins on qsmcm_a and qsmcm_b....................................................... 14-3 14-3 qsmcm_a and qsmcm_b register map............................................................. 14-4 14-4 qsmcm_a global registers ................................................................................... 14-6 14-5 qsmcm_b global registers ................................................................................... 14-6 14-6 interrupt levels ......................................................................................................... 14- 8 14-7 qsmcmmcr bit descriptions.............................................................................. 14-10 14-8 qdsci_il bit descriptions.................................................................................... 14-11 14-9 qspi_il bit descriptions ....................................................................................... 14-11 14-10 qsmcm pin control registers .............................................................................. 14-11 14-11 effect of ddrqs on qspi pin function ............................................................... 14-12 14-12 qsmcm_a pin functions...................................................................................... 14-14 14-13 qsmcm_b pin functions ...................................................................................... 14-14 14-14 pqspar bit descriptions....................................................................................... 14-15 14-15 ddrqs bit descriptions ........................................................................................ 14-16 14-16 qspi register map ................................................................................................. 14-18 14-17 spcr0 bit descriptions......................................................................................... 14-20 14-18 bits per transfer ..................................................................................................... 14-20 14-19 spcr1 bit descriptions......................................................................................... 14-21 14-20 spcr2 bit descriptions......................................................................................... 14-23 14-21 spcr3 bit descriptions......................................................................................... 14-23 14-22 spsr bit descriptions ........................................................................................... 14-24 14-23 command ram bit descriptions.......................................................................... 14-27 14-24 qspi pin functions ................................................................................................. 14-28 14-25 example sck frequencies with a 40-mhz imb3 clock........................................ 14-40 tables table number title page number lxxii mpc565/mpc566 reference manual motorola 14-26 sci registers........................................................................................................... 14- 50 14-27 sccxr0 bit descriptions ...................................................................................... 14-51 14-28 sccxr1 bit descriptions ...................................................................................... 14-52 14-29 scxsr bit descriptions......................................................................................... 14-54 14-30 scxdr bit descriptions ........................................................................................ 14-56 14-31 sci pin functions ................................................................................................... 14-56 14-32 serial frame formats .............................................................................................. 14-57 14-33 examples of scix baud rates ................................................................................ 14-59 14-34 effect of parity checking on data size .................................................................. 14-59 14-35 qsci1cr bit descriptions .................................................................................... 14-67 14-36 qsci1sr bit descriptions..................................................................................... 14-68 15-1 dlcmd2 requirements ........................................................................................... 15-2 15-2 digital filter output.................................................................................................. 15-9 15-3 receive windows.................................................................................................... 15-13 15-4 transmit windows ................................................................................................. 15-13 15-5 cpu/dlcmd2 transfers ....................................................................................... 15-25 15-6 dlcmd2 memory map ......................................................................................... 15-30 15-7 mcr bit descriptions............................................................................................. 15-31 15-8 freeze bit field description ................................................................................... 15-32 15-9 interrupt pending register (ipr) bit descriptions ................................................. 15-33 15-10 interrupt level register (ilr) bit descriptions ..................................................... 15-34 15-11 interrupt levels ....................................................................................................... 15-3 4 15-12 interrupt vector register (ivr) bit descriptions ................................................... 15-35 15-13 symbol timing control and pre-scaler bit descriptions....................................... 15-35 15-14 dlcmd2 pre-scaler rate selection ...................................................................... 15-36 15-15 symbol timing data register (sdata) bit descriptions ..................................... 15-37 15-16 timing parameter table .......................................................................................... 15-38 15-17 transmit command register (cmd) bit descriptions .......................................... 15-39 15-18 general commands................................................................................................. 15-40 15-19 type and destination of accompanying byte commands ..................................... 15-41 15-20 rxfifo commands ................................................................................................ 15-42 15-21 command load sequences ..................................................................................... 15-43 15-22 transmit data register (tdata) bit descriptions ................................................ 15-44 15-23 receive status register (stat) bit descriptions................................................... 15-45 15-24 rxfifo status......................................................................................................... 15-45 15-25 data link idle status............................................................................................... 15-46 15-26 transmitter shorted status ...................................................................................... 15-46 15-27 txfifo underrunning status ................................................................................. 15-46 15-28 txfifo status......................................................................................................... 15-46 15-29 receive data register (rdata) bit descriptions ................................................. 15-47 15-30 receive error status................................................................................................ 15-48 tables table number title page number motorola tables lxxiii 15-31 rxfifo overrun status .......................................................................................... 15-48 15-32 transmitter action status........................................................................................ 15-49 15-33 ifr bit status.......................................................................................................... 15-4 9 15-34 ifr with/without a crc bit status ....................................................................... 15-49 15-35 error code status, , ................................................................................................ 15-49 15-36 interrupt operations ................................................................................................ 15-55 15-37 interrupt levels ....................................................................................................... 15-5 6 15-38 ifr aborted conditions.......................................................................................... 15-59 15-39 signal names .......................................................................................................... 15-62 16-1 common extended/standard format frames .......................................................... 16-4 16-2 message buffer codes for receive buffers.............................................................. 16-5 16-3 message buffer codes for transmit buffers ............................................................ 16-5 16-4 extended format frames .......................................................................................... 16-6 16-5 standard format frames ........................................................................................... 16-6 16-6 receive mask register bit values ............................................................................ 16-8 16-7 mask examples for normal/extended messages .................................................... 16-8 16-8 example system clock, can bit rate and s-clock frequencies ........................... 16-9 16-9 interrupt levels ....................................................................................................... 16-22 16-10 toucan register map ........................................................................................... 16-23 16-11 canmcr bit descriptions ................................................................................... 16-27 16-12 canicr bit descriptions ..................................................................................... 16-29 16-13 canctrl0 bit descriptions ................................................................................ 16-29 16-14 rx mode[1:0] configuration ................................................................................ 16-30 16-15 transmit pin configuration..................................................................................... 16-30 16-16 canctrl1 bit descriptions ................................................................................. 16-31 16-17 presdiv bit descriptions .................................................................................... 16-32 16-18 canctrl2 bit descriptions ................................................................................ 16-32 16-19 timer bit descriptions ........................................................................................ 16-33 16-20 rxgmskhi, rxgmsklo bit descriptions......................................................... 16-34 16-21 estat bit descriptions ......................................................................................... 16-35 16-22 transmit bit error status ........................................................................................ 16-36 16-23 fault confinement state encoding ......................................................................... 16-36 16-24 imask bit descriptions........................................................................................ 16-37 16-25 iflag bit descriptions......................................................................................... 16-37 16-26 rxectr, txectr bit descriptions ..................................................................... 16-38 17-1 mios14 configuration description.......................................................................... 17-7 17-2 mios14 i/o ports ................................................................................................... 17-13 17-3 mbism registers ................................................................................................... 17-13 17-4 mios14tpcr bit descriptions.............................................................................. 17-14 17-5 mios14vect bit descriptions ............................................................................. 17-15 17-6 mios14vnr bit descriptions ............................................................................... 17-15 tables table number title page number lxxiv mpc565/mpc566 reference manual motorola 17-7 mios14mcr bit descriptions............................................................................... 17-16 17-8 mcpsm register address map.............................................................................. 17-18 17-9 mcpsmscr bit descriptions................................................................................ 17-19 17-10 clock prescaler setting ........................................................................................... 17-19 17-11 mmcsm address map........................................................................................... 17-24 17-12 mmcsmcnt bit descriptions .............................................................................. 17-25 17-13 mmcsmml bit descriptions ................................................................................ 17-26 17-14 mmcsmscr bit descriptions .............................................................................. 17-27 17-15 mmcsmcnt edge sensitivity.............................................................................. 17-27 17-16 mmcsmcnt clock signal ................................................................................... 17-27 17-17 prescaler values ...................................................................................................... 17-28 17-18 mdasm modes of operation ............................................................................... 17-31 17-19 mdasm pwm example output frequencies/resolutions at fsys = 40 mhz .... 17-40 17-20 mdasm address map ........................................................................................... 17-42 17-21 mdasmar bit descriptions ................................................................................. 17-44 17-22 mdasmbr bit descriptions ................................................................................. 17-45 17-23 mdasmscr bit descriptions ............................................................................... 17-47 17-24 mdasm mode selects ........................................................................................... 17-48 17-25 mdasm counter bus selection............................................................................. 17-48 17-26 pwm pulse/frequency ranges (in hz) using /1 or /256 option (40 mhz) .......... 17-56 17-27 mpwmsm address map ....................................................................................... 17-58 17-28 mpwmperr bit descriptions .............................................................................. 17-61 17-29 mpwmpulr bit descriptions .............................................................................. 17-62 17-30 mpwmcntr bit descriptions.............................................................................. 17-63 17-31 mpwmscr bit descriptions ................................................................................. 17-64 17-32 pwmsm output pin polarity selection ................................................................. 17-65 17-33 prescaler values ...................................................................................................... 17-65 17-34 mpiosm i/o pin function ..................................................................................... 17-67 17-35 mpiosmdr bit descriptions ................................................................................ 17-68 17-36 mpiosmddr bit descriptions ............................................................................. 17-69 17-37 mios14sr0 bit description .................................................................................. 17-72 17-38 mios14er0 bit descriptions ................................................................................ 17-73 17-39 mios14pr0 bit descriptions................................................................................. 17-73 17-40 mios14sr1 bit descriptions................................................................................. 17-74 17-41 mios14er1 bit descriptions ................................................................................ 17-74 17-42 mios14pr1 bit descriptions................................................................................. 17-75 17-43 mbism interrupt registers address map .............................................................. 17-76 17-44 mios14lvl0 bit descriptions .............................................................................. 17-76 17-45 mios14lvl1 bit descriptions .............................................................................. 17-77 17-46 mrtcsmfrch bit descriptions .......................................................................... 17-92 17-47 mrtcsmfrcl bit descriptions........................................................................... 17-93 tables table number title page number motorola tables lxxv 17-48 mrtcpr bit descriptions...................................................................................... 17-93 17-49 mrtcsmscr bit descriptions ............................................................................. 17-94 17-50 interrupt rate selection .......................................................................................... 17-94 18-1 tpu memory map .................................................................................................... 18-1 18-2 enhanced tcr1 prescaler divide values ................................................................. 18-7 18-3 tcr1 prescaler values.............................................................................................. 18-7 18-4 tcr2 counter clock source .................................................................................... 18-8 18-5 tcr2 prescaler control ............................................................................................ 18-9 18-6 tpu3 register map ................................................................................................ 18-10 18-7 tpumcr bit description....................................................................................... 18-13 18-8 dscr bit descriptions ........................................................................................... 18-15 18-9 dssr bit descriptions............................................................................................ 18-16 18-10 ticr bit description .............................................................................................. 18-17 18-11 cier bit descriptions ............................................................................................ 18-17 18-12 cfsrx bit descriptions.......................................................................................... 18-19 18-13 hsqrx bit descriptions ......................................................................................... 18-20 18-14 hssrx bit descriptions.......................................................................................... 18-20 18-15 cprx bit description.............................................................................................. 18-21 18-16 channel priorities.................................................................................................... 18-21 18-17 cisr bit descriptions............................................................................................. 18-22 18-18 tpumcr2 bit descriptions ................................................................................... 18-23 18-19 entry table bank location ..................................................................................... 18-24 18-20 system clock frequency/minimum guaranteed detected pulse ........................... 18-24 18-21 tpumcr3 bit descriptions ................................................................................... 18-25 18-22 parameter ram address offset map .................................................................... 18-26 19-1 dptram register map............................................................................................ 19-4 19-2 dptmcr bit settings............................................................................................... 19-5 19-3 rambar bit settings.............................................................................................. 19-6 20-1 uc3f external interface signals .............................................................................. 20-5 20-2 uc3f register programmer?s mode ........................................................................ 20-6 20-3 uc3fmcr bit descriptions ..................................................................................... 20-8 20-4 uc3fmcre bit descriptions ................................................................................ 20-12 20-5 uc3fctl bit descriptions .................................................................................... 20-14 20-6 rcw bit descriptions ............................................................................................ 20-20 20-7 program interlock state descriptions ..................................................................... 20-28 20-8 erase interlock state descriptions .......................................................................... 20-32 20-9 levels of censorship............................................................................................... 20-35 20-10 eeprom modes and censorship status ................................................................ 20-36 21-1 priorities of overlay regions.................................................................................. 21-14 21-2 calram a and b control registers .................................................................... 21-15 21-3 crammcr bit descriptions ................................................................................. 21-17 tables table number title page number lxxvi mpc565/mpc566 reference manual motorola 21-4 crammcr privilege bit assignment for 8-kbyte array blocks ........................ 21-19 21-5 crammcr bit descriptions ................................................................................. 21-20 21-6 rgn_size encoding ............................................................................................. 21-20 21-7 cramovlcr bit descriptions ............................................................................ 21-21 22-1 vf pins instruction encodings ................................................................................. 22-3 22-2 vf pins queue flush encodings .............................................................................. 22-4 22-3 vfls pin encodings................................................................................................. 22-4 22-4 detecting the trace buffer start point ...................................................................... 22-7 22-5 fetch show cycles control....................................................................................... 22-8 22-6 instruction watchpoints programming options...................................................... 22-17 22-7 load/store data events........................................................................................... 22-19 22-8 load/store watchpoints programming options ..................................................... 22-19 22-9 the check stop state and debug mode ................................................................. 22-30 22-10 trap enable data shifted into development port shift register ........................... 22-38 22-11 debug port command shifted into development port shift register ................... 22-38 22-12 status / data shifted out of development port shift register ............................... 22-39 22-13 debug instructions / data shifted into development port shift register .............. 22-40 22-14 development support programming model ........................................................... 22-44 22-15 development support registers read access protection....................................... 22-45 22-16 development support registers write access protection...................................... 22-45 22-17 cmpa-cmpd bit descriptions .............................................................................. 22-46 22-18 cmpe-cmpf bit descriptions............................................................................... 22-46 22-19 bar bit descriptions ............................................................................................. 22-46 22-20 cmpg-cmph bit descriptions.............................................................................. 22-47 22-21 ictrl bit descriptions .......................................................................................... 22-47 22-22 isct_ser bit descriptions.................................................................................... 22-49 22-23 lctrl1 bit descriptions ....................................................................................... 22-49 22-24 lctrl2 bit descriptions ....................................................................................... 22-51 22-25 breakpoint counter a value and control register (counta)............................. 22-53 22-26 breakpoint counter b value and control register (countb)............................ 22-53 22-27 ecr bit descriptions.............................................................................................. 22-54 22-28 der bit descriptions.............................................................................................. 22-56 23-1 readi reset configuration options ....................................................................... 23-5 23-2 public messages ........................................................................................................ 23-6 23-3 vendor-defined messages ........................................................................................ 23-7 23-4 terms and definitions ............................................................................................... 23-8 23-5 readi_otr bit descriptions ............................................................................... 23-10 23-6 tool mapped register space .................................................................................. 23-10 23-7 readi_did bit descriptions ................................................................................ 23-11 23-8 readi_dc bit descriptions.................................................................................. 23-12 23-9 rcpu development access modes ....................................................................... 23-12 tables table number title page number motorola tables lxxvii 23-10 readi_uba bit descriptions ............................................................................... 23-13 23-11 readi_rwa read/write access bit descriptions ............................................... 23-14 23-12 readi_udi bit descriptions ................................................................................ 23-16 23-13 read access status ................................................................................................. 23-16 23-14 write access status................................................................................................. 23-16 23-15 readi_dta 1 and 2 bit descriptions................................................................ 23-18 23-16 data trace values ................................................................................................... 23-18 23-17 description of readi pins..................................................................................... 23-23 23-18 msei/mseo protocol ............................................................................................ 23-25 23-19 public messages supported .................................................................................... 23-27 23-20 error codes ............................................................................................................. 23- 29 23-21 vendor-defined messages supported ..................................................................... 23-30 23-22 message field sizes ................................................................................................ 23-31 23-23 indirect branch message......................................................................................... 23-35 23-24 direct branch message ........................................................................................... 23-35 23-25 readi reset configuration options ..................................................................... 23-36 23-26 vf instruction type encoding ................................................................................ 23-42 23-27 vf queue flush information .................................................................................. 23-42 23-28 vfls history buffer flush encoding .................................................................... 23-43 23-29 bit address format ................................................................................................. 23-45 23-30 program trace correction due to a mispredicted branch...................................... 23-45 23-31 program trace correction due to an exception ..................................................... 23-46 23-32 special l-bus case handling .................................................................................. 23-64 23-33 throughput comparison for fpm and rpm mdo/mdi configurations .............. 23-78 23-34 watchpoint source .................................................................................................. 23-83 23-35 power management mechanism overview ............................................................ 23-97 24-1 boundary scan bit definition................................................................................... 24-5 24-2 instruction decoding............................................................................................... 24-22 a-1 spr (special purpose registers) ............................................................................... a-2 a-2 uc3f flash array ...................................................................................................... a-4 a-3 decram sram array ............................................................................................ a-4 a-4 bbc (burst buffer controller module) ..................................................................... a-5 a-5 usiu (unified system interface unit) ...................................................................... a-5 a-6 cdr3 flash control registers eeprom (uc3f) .................................................. a-10 a-7 dptram ab and c control registers ................................................................... a-10 a-8 dlcmd2 (data link controller module)................................................................a-11 a-9 dptram memory arrays........................................................................................a-11 a-10 time processor unit 3 a and b (tpu3 a and b).....................................................a-11 a-11 qadc64e a and b (queued analog-to-digital converter)................................... a-15 a-12 qsmcm a and b (queued serial multi-channel module) .................................... a-17 a-13 time processor unit 3 c (tpu3_c) ........................................................................ a-20 tables table number title page number lxxviii mpc565/mpc566 reference manual motorola a-14 mios14 (modular input/output subsystem) .......................................................... a-22 a-15 toucan a, b and c (can 2.0b controller).......................................................... a-29 a-16 uimb (u-bus to imb bus interface) ...................................................................... a-34 a-17 calram_a and calram_b control registers ................................................. a-34 a-18 calram_b and calram_a array.................................................................... a-36 b-1 external components value for different crystals (q1) ...........................................e-4 c-1 bank 0 functions ....................................................................................................... d-2 c-2 bank 1 functions ....................................................................................................... d-3 c-3 pta parameters .......................................................................................................... d-5 c-4 qom bit encoding .................................................................................................... d-6 c-5 qom parameters........................................................................................................ d-7 c-6 tsm parameters ? master mode ............................................................................. d-9 c-7 tsm parameters ? slave mode ............................................................................. d-10 c-8 fqm parameters ...................................................................................................... d-12 c-9 uart transmitter parameters................................................................................. d-14 c-10 uart receiver parameters ..................................................................................... d-15 c-11 nitc parameters...................................................................................................... d-17 c-12 comm parameters .................................................................................................. d-19 c-13 halld parameters ................................................................................................. d-21 c-14 mcpwm parameters ? master mode.................................................................... d-23 c-15 mcpwm parameters ? slave edge-aligned mode .............................................. d-24 c-16 mcpwm parameters ? slave ch a non-inverted center-aligned mode ............ d-25 c-17 mcpwm parameters ? slave ch b non-inverted center-aligned mode ............ d-26 c-18 mcpwm parameters ? slave ch a inverted center-aligned mode .................... d-27 c-19 mcpwm parameters ? slave ch b non-inverted center-aligned mode ............ d-28 c-20 fqd parameters ? primary channel...................................................................... d-30 c-21 fqd parameters ? secondary channel.................................................................. d-31 c-22 ppwa parameters .................................................................................................... d-33 c-23 oc parameters ......................................................................................................... d-35 c-24 pwm parameters ..................................................................................................... d-37 c-25 dio parameters........................................................................................................ d-39 c-26 spwm parameters ................................................................................................... d-41 c-27 rwtpin parameters................................................................................................ d-44 c-28 id parameters........................................................................................................... d-45 c-29 siop parameters ...................................................................................................... d-48 c-30 siop function valid chan_control options ........................................................ d-49 c-31 siop state timing ................................................................................................... d-51 d-1 memory access times using different buses ........................................................... f-2 d-2 instruction timing examples for different buses ...................................................... f-2 e-1 absolute maximum ratings (vss = 0v) .................................................................. g-1 e-2 thermal characteristics ............................................................................................. g-3 tables table number title page number motorola tables lxxix e-3 esd protection........................................................................................................... g-6 e-4 dc electrical characteristics ..................................................................................... g-7 e-5 oscillator and pll ................................................................................................... g-12 e-6 array program and erase characteristics ................................................................ g-12 e-7 censor cell program and erase characteristics .................................................. g-13 e-8 flash module life .................................................................................................... g-13 e-10 bus operation timing.............................................................................................. g-22 e-11 interrupt timing ....................................................................................................... g-46 e-12 debug port timing................................................................................................... g-46 e-13 readi ac electrical characteristics...................................................................... g-49 e-14 reset timing......................................................................................................... g-51 e-15 jtag timing............................................................................................................ g-55 e-16 qadc64e conversion characteristics.................................................................... g-58 e-17 qspi timing ............................................................................................................ g-60 e-18 gpio timing............................................................................................................ g-63 e-19 tpu3 timing ........................................................................................................... g-64 e-20 toucan timing ...................................................................................................... g-65 e-21 mcpsm timing characteristics .............................................................................. g-65 e-22 mpwmsm timing characteristics ......................................................................... g-66 e-23 mmcsm timing characteristics............................................................................. g-68 e-24 mdasm timing characteristics ............................................................................. g-71 e-25 mpiosm timing characteristics ............................................................................ g-74 tables lxxx mpc565/mpc566 reference manual motorola motorola chapter 1. overview 1-1 chapter 1 overview the purpose of this section is to give an overview of the mpc565/mpc566 microcontroller, including the features, modules, pins, memory map. the module mix of the microcontroller is shown in figure 1-1 and section 1.2.1, ?detailed feature list.? the remaining sections of the manual describe on-chip modules. the mpc565/mpc566 has duplicates of several modules, including tpu3, toucan, qsmcm, qadc64, calram, uc3f, and dptram. 1.1 introduction the major features of the mpc565/mpc566, a member of the motorola mpc500 risc microcontroller family, are as follows: an mpc500 core with fpu and bbc 36 kbytes of static ram (two calram modules) ? 8 kbytes of normal access or overlay access (sixteen 512-byte regions) ? 4 kbytes in calram_a, 4 kbytes in calram_b 1 mbyte of flash memory (uc3f) unified system integration unit (usiu), a flexible memory controller, and improved interrupt controller three time processor units (tpu3) ? tpu3_a and tpu3_b are connected to dptram_ab (6 kbytes) ? tpu3_c is connected to dptram_c (4 kbytes) a 22-timer channel modular i/o system (mios14) ? same as mios1 plus a real-time clock sub-module (mrtcsm), 4 counter sub-modules (mcsm), and 4 pwm sub-modules (mpwmsm) three toucan modules (toucan_a, toucan_b, toucan_c) two enhanced queued analog to digital converters (qadc64e_a, qadc64e_b) with analog multiplexors (amux) for 40 total analog channels. these modules are configured so each module can access all 40 of the analog inputs to the part. 1-2 mpc565/mpc566 reference manual motorola block diagram two queued serial multi-channel modules (qsmcm_a, qsmcm_b), each of which contains a queued serial peripheral interface (qspi) and 2 serial controller interfaces (sci/uart) a j1850 (dlcmd2) communications module a nexus debug port (class 3) ? ieee-isto 5001-1999 jtag and background debug mode (bdm) 1.2 block diagram figure 1-1 shows the modules on the mpc565/mpc566. figure 1-1. mpc565/mpc566 block diagram e-bus mpc500 core l-bus u-bus imb3 flash 512 kbytes + fp usiu flash 512 kbytes l2u i/f uimb qsmcm mios14 dptram 6kbytes readi jtag tpu3 qadc64e qsmcm tpu3 dptram 4kbytes tpu3 tou dlcmd2 32k calram_a 4-kbyte overlay 4-kbyte calram_b 4-kbyte overlay can to u can to u can w/amux qadc64e w/amux buffer burst controller 2 decram (4kbytes) 28 kbytes sram no overlay motorola chapter 1. overview 1-3 block diagram 1.2.1 detailed feature list the mpc565/mpc566 key features are as follows: 40 mhz operation (56 mhz operation is optional for the mpc566) -40 ? 125 c ambient temperature or -40 ?85 c 2.6 v 0.1 v external bus ? external bus is compatible with external memory devices operating from 2.5 v to 3.4 v. ? extended voltage range (2.7 ? 3.4 v) degrades data drive timing by 1.1 ns on date writes. 2.6 0.1 v internal logic 5-v i/o (5.0 0.25 v) high-performance cpu system high-performance core ? powerpc single issue integer core ? precise exception model ? floating point ? extensive system debug support ? on-chip watchpoints and breakpoints ? program flow tracking ? background debug mode (bdm) ? code compression (mpc566 only) ? compression reduces usage of internal or external flash memory ? compression optimized for automotive (non-cached) applications ? new compression scheme decreases code size to 40% ?50% of source note 4-kbyte static decram can be used as memory if compression is not used. mpc500 system interface (usiu, bbc, l2u) ? periodic interrupt timer, bus monitor, clocks, decrementer and time base ? clock synthesizer, power management, reset controller ? external bus tolerates 5-v inputs, provides 2.6-v outputs ? enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40 internal interrupts ? ieee 1149.1 jtag test access port 1-4 mpc565/mpc566 reference manual motorola block diagram ? bus supports multiple master designs ? flexible memory protection units in bbc (impu) and l2u (dmpu) ? flexible chip selects via memory controller ? 24-bit address and 32-bit data buses ? four- to 16-mbyte (data) or 4-gbyte (instruction) region size support ? four-beat transfer bursts, two-clock minimum bus transactions ? use with sram, eprom, flash and other peripherals ? byte selects or write enables ? 32-bit address decodes with bit masks ? four instruction regions ? four data regions ? default attributes available in one global entry ? attribute support for speculative accesses ? exception vector table relocation features allow exception table to be relocated to following locations: ? 0x0000 0000 - 0x0000 1fff (normal mpc500 exception table location) ? 0x0001 0000 - 0x0001 1fff (0 + 64 kbytes; second page of internal flash) ? second internal flash module ? internal sram ? 0x0fff_0100 (external memory space; normal mpc500 exception table location) ? usiu supports dual-mapping of flash to move part of internal flash memory to external bus for development fully static design four major power saving modes ? on, doze, sleep, and deep sleep one mbyte flash ? two uc3f modules, 512 kbytes each ? page mode read ? block (64-kbyte) erasable ? external 4.75- to 5.25-v v pp program and erase power supply 36-kbyte static calibration ram (calram) ? composed of 4-kbyte and 32-kbyte calram modules ? fast access: one clock ? keep-alive power motorola chapter 1. overview 1-5 block diagram ? soft defect detection (sdd) ? 4-kbyte calibration (overlay) ram per module (8 kbytes total) ? eight 512-byte overlay regions per module (16 regions total) nexus/ieee ? isto 5001-1999 debug port (class 3) ? 9- or 16-pin interface general-purpose i/o support ? address (24) and data (32) pins can be used as gpio in single-chip mode ? 16gpioinmios14 ? many peripheral pins can be used as gpio when not used as primary functions ? 5-v outputs with slew rate control integrated i/o system true 5-v i/o three time processing units (tpu3) ? 16 channels each ? each tpu3 is a microcoded timer subsystem ? one 6-kbyte and one 4-kbyte dual-port tpu ram (dptram), one (6-kbyte) shared by two tpu3 modules for tpu microcode and the 4-kbyte dedicated to the third tpu3 for microcode. 22-channel mios timer (mios14) ? 6 modulus counter submodules (mcsm). ? four additional mcsm submodules compared to mios1 ? 10 double action submodule (dasm). ? 12 dedicated pwm submodules (pwmsm) ? four additional pwm submodules compared to mios1 (shared with mios gpio pins) ? mios real-time clock submodule (mrtcsm) provides low power clock/counter ? requires external 32-khz crystal ? uses four pins: two for 32-khz crystal, two for power/ground. two queued analog-to-digital converter modules (qadc64e_a, qadc64e_b) with amuxes providing a total of 40 analog channels. ? 40 input channels on two modules with internal multiplexing (amuxes) ? each qadc64e can see all 40 input channels ? 10 bit a/d converter with internal sample/hold ? typical conversion time is 4 s (250-kbyte samples/sec) 1-6 mpc565/mpc566 reference manual motorola block diagram ? two conversion command queues of variable length ? automated queue modes initiated by: ? external edge trigger/level gate ? software command ? periodic/interval timer, assignable to both queue 1 and 2 ? 64 result registers in each qadc64e module ? synchronized clock mode allows both qadc64es to see the same conversion clock. this allows the two modules to look like one large qadc with four queues. ? conversions alternate reference (altref) pin. this pin can be connected to a different reference voltage ? output data is right or left justified, signed or unsigned message data link controller (dlcmd2) module ? two pins muxed with qsmcmb pins. muxing controlled by qsmcmb pcs3 pin assignment register ? sae j1850 class b data communications network interface compatible and iso compatible for low-speed ( < 125 kbps) serial data communications in automotive applications ? 10.4 kbps variable pulse width (vpw) bit format ? digital noise filter, collision detection ? hardware cyclical redundancy check (crc) generation and checking ? block mode receive and transmit supported ? 4x receive mode supported (41.6 kbps) ? digital loopback mode ? in-frame response (ifr) types 0, 1, 2, and 3 supported ? dedicated register for symbol timing adjustments ? inter-module bus 3 (imb3) slave interface ? power-saving imb3 stop mode with automatic wakeup on network activity ? power-saving imb3 clockdis mode ? debug mode available through imb3 freeze signal or user controllable soft_frz bit ? polling and imb3 interrupt generation with vector lookup available three toucanmodules (toucan_a, toucan_b, toucan_c) ? 16 message buffers each, programmable i/o modes ? maskable interrupts motorola chapter 1. overview 1-7 block diagram ? programmable loopback for self-test operation ? independent of the transmission medium (external transceiver is assumed) ? open network architecture, multimaster concept ? high immunity to emi ? short latency time for high-priority messages ? low power sleep mode, with programmable wake up on bus activity ? toucan_c pins shared with mios14 gpio pins two queued serial modules with one queued-spi and two sci each (qsmcm_a, qsmcm_b) ? qsmcm_a matches full mpc555/mpc556 qsmcm functionality ? qsmcm_b has pins muxed with dlcmd2 module ? two pins are muxed with dlcmd2 (j1850) transmit and receive pins (b_pcs3_j1850_tx and b_rxd2_j1850_rx) ? qsmcm_b vs j1850 mux control provided by qpapcs3 bit in qsmcm pin assignment register (pqspar) ? queued-spi ? provides full-duplex communication port for peripheral expansion or interprocessor communication ? up to 32 preprogrammed transfers, reducing overhead ? synchronous serial interface with baud rate of up to system clock / 4 ? four programmable peripheral-select pins support up to 16 devices ? special wrap-around mode allows continuous sampling of a serial peripheral for efficient interfacing to serial analog-to-digital (a/d) converters ?sci ? uart mode provides nrz format and half- or full-duplex interface ? 16 register receive buffer and 16 register transmit buffer on one sci ? advanced error detection, and optional parity generation and detection ? word length programmable as 8 or 9 bits ? separate transmitter and receiver enable bits, and double buffering of data ? wake-up functions allow the cpu to run uninterrupted until either a true idle line is detected, or a new address byte is received available in package or bumped die plastic ball grid array (pbga) packaging ? 352/388 ball pbga ? 27 mm x 27 mm body size ? 1.0 mm ball pitch 1-8 mpc565/mpc566 reference manual motorola differences between the mpc565/mpc566 and the mpc555/mpc556 1.3 differences between the mpc565/mpc566 and the mpc555/mpc556 the mpc565/mpc566 is an enhanced version of the mpc555/mpc556. most functional features of the mpc555/mpc556 are unchanged on the mpc565/mpc566. table 1-1 shows the high level differences. table 1-1. differences between modules of the mpc555/mpc556 and the mpc565/mpc566 module mpc555/mpc556 mpc565/mpc566 cpu core no change bbc bbc bbc with improved code compression 1 1 available on some options. l2u no change sram 26-kbytes 36-kbyte calram with overlay features flash 448-kbyte cmf 1-mbyte uc3f (new programming, etc.) usiu usiu usiu with enhanced interrupt controller jtag no change readi none new module uimb no change qadc64 2 qadc64 (16 channels on each qadc for 32 total channels) 2 qadc64e w/amuxes (40 channels accessible from either qadc64e) qsmcm (1) no change (2) dlcmd2 (j1850) none 1 mios mios1 mios14: mios1 with real-time clock (mrtcsm), 4 more pwmsms and 4 more mcsms toucan (2) no change (3) tpu3 (2) no change (3) dptram (6-kbytes) no change (6-kbytes, 4-kbytes) power supplies ? 40 mhz with two power supplies: nominal 3.3-v to 5.0-v power supplies 56 mhz with two power supplies: 5.0-v i/o, 2.6-v internal logic motorola chapter 1. overview 1-9 differences between the mpc565/mpc566 and the mpc555/mpc556 the following are additional differences between the mpc565/mpc566 and the mpc555/mpc556. spi (miso, mosi, and sck) pin drive. ? mpc565/mpc566 provides 21-ns rise/fall with 200-pf load using cmos (20%/70%) levels gpio on modck1 pin outputs only 2.6 v ? modck1 pin is in keep-alive power section with no 5-v rail available ? 5.0-v compatibility modes ? input is 5-v friendly ? 2.6-v output has less slew rate control ? 2.6-v: v oh = 2.3 v power supplies for external bus pins ?q vddl is quiet supply to hold non-switching outputs quiet even when noisy supply (n vddl )sags ?q vddl supplies pre-drive and other pad logic ?n vddl only supplies final pmos driver stage ?q vddl and n vddl shorted on customer board after filtering pull-up and pull-down changes during poreset and hreset ? all 2.6-v/5-v pads (external bus: address/data/control) pull down at reset ? all 5-v pads pull up at reset ? additional control granularity in the pdmcr register no pull-ups on qsmcm sci receive pads a_rxd1_qgpi1, a_rxd2_qgpi2, b_rxd1_qgpi1 pins do not have weak pull-up during reset or any other time clkout has 3 drive strength options ? better matches drive to requirements to reduce emi ? 25, 50, 100 pf instead of 45 and 90 pf change reset value of engclk to maximum divide (crystal/128) ? for a 4-mhz crystal, this is 31.25 khz ? engclk is selectable between 2.6 v and 5 v a daisy chain between uc3f modules allows either module to provide the reset configuration word (rcw) censorship operation ? a rcw bit controls whether or not the entire uc3f can be erased while censorship is violated 1-10 mpc565/mpc566 reference manual motorola differences between the mpc565/mpc566 and the mpc555/mpc556 bbc sprs (ppc regs) access in two clocks instead of one clock calram internal protection block size is 8 kbytes ? instead of four kbytes on mpc555/mpc556 lram calram causes machine check exception instead of data storage interrupt (dsi) exception in certain cases ? for non-overlay cpu core accesses, a dsi exception is taken ? for overlay accesses and any non-core access (slave mode), a machine check exception is taken calram causes dsi exception only if the data relocation (dr) bit in the core machine state register, msr[dr], is set. refer to table 3-12. ? l2u on mpc555/mpc556 already followed this protocol, but the lram did not. now all l-bus peripherals follow this protocol. ? the msr[dr] bit is described in section 3.9.1, ?machine state register (msr),? for more information. four additional prds control bits were added to the usiu to allow more granularity of prds control on a part bbc includes a 4-kbyte decram that can be used if compression is not used or is not available. 1.3.0.1 sram keep-alive power behavior the sram has three keep-alive power pins (v ddsram1 ,v ddsram2 , and v ddsram3 ). these pins provide keep-alive power to the sram arrays in the calram modules and the dptram modules. the v ddsram1 pin powers the 32-kbyte calram_a during keep-alive while power is off to the mpc565/mpc566 (except for the keep-alive power supplies). calram_a keeps all of its 32 kbytes powered during power down. the v ddsram2 pin powers the 4-kbyte calram_b module. the v ddsram3 pin powers the dptram modules during keep-alive as well as during normal operation. the calram modules only power their arrays from the v ddsram pins during keep-alive. during normal operation, they are powered by the normal internal v dd of the part. the dptram modules (6 kbytes and 4 kbytes) and the 4-kbyte decram in the bbc module power their arrays via the v ddsram3 pin during keep-alive and are supplied by v dd during normal operation. motorola chapter 1. overview 1-11 memory map 1.4 memory map the internal memory map is organized as a single 4-mbyte block. this is shown in figure 1-3. this block can be moved to one of eight different locations. the internal memory space is divided into the following sections: flash memory (1 mbyte) ? u-bus memory static ram memory (36 kbytes calram) ? l-bus memory control registers and imb3 modules (64 kbytes), partitioned as ? usiu and flash control registers ? uimb interface and imb3 modules ? calram and readi control registers (l-bus control register space) the internal memory block can reside in one of eight possible 4-mbyte memory spaces. these eight locations are the first eight 4-mbyte memory blocks starting with address 0x0000 0000, as shown in figure 1-2. there is a user programmable register in the usiu to configure the internal memory map to one of the eight possible locations. programmability of internal memory map location allows multiple chip system. the imb3 address space block in figure 1-3 shows memory allocation for imb3 modules. it does not show the actual memory space required for individual modules. all modules are mapped to the low address, numerically, of the memory allocated for that module in the imb3 address space. 1-12 mpc565/mpc566 reference manual motorola memory map figure 1-2. memory map 0x0000 0000 0xffff ffff 0x0100 0000 0x00ff ffff 0x01ff ffff 0x00c0 0000 0x00bf ffff 0x0080 0000 0x007f ffff 0x0040 0000 0x003f ffff 0x01c0 0000 0x01bf ffff 0x0140 0000 0x013f ffff 0x0180 0000 0x017f ffff internal 4-mbyte memory block (resides in one of eight locations) motorola chapter 1. overview 1-13 memory map figure 1-3. internal memory block calram/ readi control 256 bytes 0x38 00ff 0x38 0100 reserved (l-bus control) ~32 kbytes 4-kbyte overlay section 0x30 7fff 0x2f ffff 0x30 0000 0x3f 6fff 0x3f 7000 0x08 0000 0x3f 7fff 0x3f 8000 0x00 0000 usiu & flash control 16 kbytes uimb i/f & imb modules 32 kbytes 0x07 ffff 0x10 0000 calram_a (32 kbyte) reserved for flash (2,016 kbytes) 0x2f bfff 0x30 8000 0x37 ffff reserved for imb 480 kbytes reserved (l-bus mem) 444 kbytes 0x38 4000 uc3f_b flash 512 kbytes 0x38 0000 0x38 3fff 0x0f ffff uc3f_a flash 512 kbytes 0x2f c000 calram_b (4 kbyte) 0x3f ffff all 4-kbytes can be 0x2f 7fff ox2f 8000 overlay section 0x30 0000 0x30 7fff dptram_ab (6 kbytes) qsmcm_a (1 kbytes) mios14 (4 kbytes) toucan_a (1 kbytes) toucan_b (1 kbytes) uimb control registers (128 bytes) tpu3_a (1 kbytes) tpu3_b (1 kbytes) qadc64_a (1 kbytes) qadc64_b (1 kbytes) dptram_ab reserved (2 kbytes) usiu control registers uc3f_a control uc3f_b control 0x2f c000 0x2f c87f qsmcm_b (1 kbytes) 0x30 7900 0x30 7000 0x30 6000 0x30 5800 0x30 5400 0x30 4c00 0x30 4800 0x30 4400 0x30 4000 0x30 3800 0x30 2000 0x30 7400 dptram_c (4 kbytes) 0x30 1000 dptram_c 0x30 0040 reserved (1 kbytes) reserved (896 bytes) tpu3_c (1 kbytes) 0x30 5c00 0x30 7800 dlcmd2 (16 bytes) 0x2f c800 0x2f c840 0x30 7f80 toucan_c (1 kbytes) reserved (3952 bytes) 0x30 0080 0x30 0090 0x30 5000 registers (64 bytes) registers (64 bytes) decram 0x2f 8fff 0x2f 9000 4kbytes 0x2f 9fff reserved bbc control registers 0x2f a000 8kbytes (64 bytes) (64 bytes) 1-14 mpc565/mpc566 reference manual motorola memory map motorola chapter 2. signal descriptions 2-1 chapter 2 signal descriptions this chapter describes the mpc565/mpc566 microprocessor?s external signals. it contains a description of individual signals, showing their behavior, when the signal is an input or an output, and which signals are multiplexed with other signals. a bar over a signal name indicates that the signal is active low?for example, ta (transfer acknowledge). active-low signals are referred to as asserted (active) when they are low and negated when they are high. signals that are not active low, such as addr[8:31] (address bus signals) and data[0:31] (data bus signals) are referred to as asserted when they are high and negated when they are low. refer to appendix e, ?electrical characteristics? for detailed electrical and mechanical information for each signal. 2.1 pad function description table 2-1 is a summary of the signals used by each functional pad of the mpc565/mpc566. table 2-1. mpc565/mpc566 pad function summary functional group description signals 1 number of signals 5v / 2.6 v address lines (16 mbytes address space) addr[8:31] / sgpioa[8:31] 24 2.6-v bus/ 5-v gpio data bus data[0:31] / sgpiod[0:31 32 2-2 mpc565/mpc566 reference manual motorola padfunctiondescription external interrupts irq0 /sgpioc0 1 2.6-v bus/2.6-v gpi0 2 irq1 /rsv /sgpioc1 6 2.6-v bus/ 5-v gpio irq2 /cr /sgpioc2/mts irq3 /kr /retry / sgpioc3 irq4 /at2/sgpioc4 irq [6:7] / modck[2:3] irq5 / modck1 / spgioc5 1 2.6 v bus control tsiz[0:1] 11 2.6 v rd/wr burst bdip ts ta tea oe rstconf / texp bi /sts development and debug support ptr / frz / sgpioc6 7 2.6-v bus/ 5-v gpio irq_out / lwp0 / sgpioc7 bg /vf0/lwp1 br /vf1/iwp2 bb /vf2/iwp3 vfls[0:1] / iwp[0:1] chip selects cs[0:3] 4 2.6 v write enables / byte enables we [0:3] / be [0:3] / at[0:3] 4 2.6 v reset pins poreset /trst 3 2.6 v hreset sreset table 2-1. mpc565/mpc566 pad function summary (continued) functional group description signals 1 number of signals 5v / 2.6 v motorola chapter 2. signal descriptions 2-3 pad function description jtag/bdm tms 5 2.6 v tdi / dsdi tck / dsck tdo / dsdo jcomp readi port mcko 12 2.6 v mdo[3:0] mseo mcki mdi[1:0] msei evti rsti mdo[7:4] shared with mpio32b[7:10] clocks and pll xtal 9 2.6 v extal xfc kapwr clkout extclk engclk vddsyn vsssyn dlcmd2 (j1850) j1850_tx shared with pcs3 and rxd2 of qsmcm_b 5v j1850_rx toucan_a cntx0_a 2 5v cnrx0_a toucan_b cntx0_b 2 5v cnrx0_b toucan_c cntx0_c 2 5v cnrx0_c table 2-1. mpc565/mpc566 pad function summary (continued) functional group description signals 1 number of signals 5v / 2.6 v 2-4 mpc565/mpc566 reference manual motorola padfunctiondescription uc3f flash eeprom epee 5 5-v vflash, others 2.6 v b0epee vflash vddf vssf calram, dptram vddsram[1:3] 3 2.6 v qadc64_a qadc64_b etrig[1:2] 47 5v an44/anw/pqb0 an45/anx/pqb1 an46/any/pqb2 an47/anz/pqb3 an[48:51] / pqb[4:7] an[52:54] / ma[0:2] / pqa[0:2] an[55:59] / pqa[3:7] an[64:71] / pqb[0:7] an[72:74] / ma[0:2] / pqa[0:2] an[75:79] / pqa[3:7] an[80:87] vrh vrl altref vdda vssa qsmcm_a pcs0 / ss /qgpio0 12 5v pcs[1:3] / qgpio[1:3] miso / qgpio4 mosi / qgpio5 sck / qgpio6 txd[1:2] / qgpo[1:2] rxd[1:2] / qgpi[1:2] eck table 2-1. mpc565/mpc566 pad function summary (continued) functional group description signals 1 number of signals 5v / 2.6 v motorola chapter 2. signal descriptions 2-5 pad function description qsmcm_b pcs3 / j1850_tx 11 5v rxd2 / j1850_rx pcs0 / ss /qgpio0 pcs[1:2] miso / qgpio4 mosi / qgpio5 sck / qgpio6 txd[1:2] / qgpo[1:2] rxd1 / qgpi1, eck mios14 mpio32b13 / c_cntx0 25 5v mpio32b14 / c_cnrx0 mpio32b15 mda[11:15] mda[27:31] mpwm[0:3] mpwm[16:19] mpio32b[5:6, 11:12] / mpwm[4:5, 20:21] mpio32b[0:2] / vf[0:2] 5 2.6-v / 5-v gpio mpio32b[3:4] / vfls[0:1] mpio32b[7:10] / readi:mdo[7:4] 4 5v/2.6v mrtcsm: ?vddrtc ?vssrtc ?extal32 ?xtal32 4 2.6 v tpu3_a a_tpuch[0:15] 16 5v tcr2 1 tpu3_b b_tpuch[0:15] 16 5v tcr2 1 tpu3_c c_tpuch[0:15] 16 5v tcr2 1 1 a forward slash ( / ) implies that the corresponding functions are multiplexed on the pin. 2 this pin was 5-v gpio on mask set k85h. table 2-1. mpc565/mpc566 pad function summary (continued) functional group description signals 1 number of signals 5v / 2.6 v 2-6 mpc565/mpc566 reference manual motorola pad module configuration register (pdmcr) 2.1.1 mpc565/mpc566 module pin muxing table 2-2 describes the pin multiplexing that occurs between different modules of the mpc565/mpc566. 2.2 pad module configuration register (pdmcr) bits in the pdmcr (which resides in the siu memory map) control the slew rate and weak pull-up/pull-down characteristics of some pins. the contents of the pdmcr are illustrated below. the poreset /trst signal resets all the pdmcr bits asynchronously. table 2-2. mpc565/mpc566 module pin sharing description pin name modules sharing pins c_cntx0 with mpio32b13 c_cnrx0 with mpio32b14 toucan_c shared with mios14 gpio mdo_4 with mpio32b10 mdo_5 with mpio32b9 mdo_6 with mpio32b8 mdo_7 with mpio32b7 readi shared with mios14 gpio mpwm20 with mpio32b11 mpwm21 with mpio32b12 mpwm4 with mpio32b5 mpwm5 with mpio32b6 mios14 pwm submodule shared with mios14 gpio vf0 with mpio32b0, vf1 with mpio32b1, vf2 with mpio32b2, vf pins shared with mios14 gpio vfls0 with mpio32b3 vfls1 with mpio32b4 vfls shared with mios14 gpio b_pcs3 with j1850_tx, b_rxd2 with j1850_rx qsmcm_b pins are muxed with dlcmd2 (j1850) transmit and receive pins. see section 2.4.2, ?qsmcm a / qsmcm b / dlcmd2 (j1850) pads.? msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 slrc reserved prds sprds t2clk_pu pull_dis reser ved hreset : 000000 0 0 0 000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 spull_dis reserved hreset : 000000 0 0 0 000000 0 figure 2-1. pdmcr ? pads module configuration register 0x2f c03c motorola chapter 2. signal descriptions 2-7 pad module configuration register (pdmcr) table 2-3 contains bit descriptions for the pdmcr. table 2-3. pdmcr bit descriptions bit(s) name description 0 slrc0 controls the slew rate of pins on the tpu3, qadc64, and usiu_gpio0. 0 slow slew rate for pins. (200 nsec). 1 normal slew rate for pins. 1 slrc1 controls the slew rate of pins on the qspi, toucan_a, and toucan_b. 0 slow slew rate for pins. (50 nsec). 1 normal slew rate for pins. 2 slrc2 controls the slew rate of pins on the qsci in qsmcm_a and qsmcm_b. 0 slow slew rate for pins. (200 ns). 1 normal slew rate for pins. 3 slrc3 controls the slew rate of pins on the mios14, and toucan_c 0 slow slew rate for pins. (50 ns for toucan_c, 200 nsec for others). 1 normal slew rate for pins. 4:5 ? reserved 6 prds disables weak pull-up-or-down devices enabled at the assertion of poreset /trst or hreset . the following pads are affected by this bit: all sgpio, all tpu3 except for t2clk with gpio. the pads are shown in table 2-6. 0 enable weak pull-up/pull-down devices on pads controlled by this signal. 1 disable weak pull-up/pull-down devices on pads controlled by this signal. 7 sprds disables weak pull up-or-down devices enabled at the assertion of poreset /trst or hreset . the following pads are affected by this bit: bdip ,ta ,ts ,tea , rd/wr ,br ,bg ,bb ,tsiz, bi /sts , burst . the pads are shown in table 2-6. 0 enable weak pull-up/pull-down devices on pads controlled by this signal. 1 disable weak pull-up/pull-down devices on pads controlled by this signal. 8 t2clk_pu controls the pull-up on the tpu t2clk pins. 0 pull-ups are enabled if the t2clk pins are defined as inputs 1 pull-ups are disabled on the t2clk pins 9:14 pull_dis disables weak pull up-or-down devices enabled at the assertion of poreset /trst or hreset . the following pads are affected by these bits: pull_dis0 (bit 9): all mios input pins except c_cntx0/mpio32b[13] and c_cnrx0/mpio32b[14] 1 pull_dis1 (bit 10): all qsmcm input pins 2 pull_dis2 (bit 11): all qadc input pins, except etrig1 and etrig2 3 pull_dis3 (bit 12): all toucan input pins 4 pull_dis4 (bit 13): readi module input pins pull_dis5 (bit 14): etrig1 and etrig2 5 0 enable weak pull-up/pull-down devices on pads controlled by this signal. 1 disable weak pull-up/pull-down devices on pads controlled by this signal. 1 etrig1, etrig2 in mask set k85h. 2 none in mask set k85h. 3 toucan_a, toucan_b in mask set k85h. 4 toucan_c and mios mpio32b13 and mpio32b14 in mask set k85h. 5 reserved in mask set k85h. 15 ? reserved 16:17 spull_dis disables weak pull up-or-down devices enabled at the assertion of poreset /trst or hreset . the following pads are affected by these bits: spull_dis0 (bit 16): irq5_sgpio5_modck1 spull_dis1 (bit 17): jtag/bdm pins (tms, tdi/dsdi, jcomp, tck/dsck) 0 enable weak pull-up/pull-down devices on pads controlled by this signal. 1 disable weak pull-up/pull-down devices on pads controlled by this signal. 31:18 ? reserved 2-8 mpc565/mpc566 reference manual motorola pad module configuration register (pdmcr2) 2.3 pad module configuration register (pdmcr2) the pdmcr2 controls the pre-discharge circuitry for the data bus. this allows for 5v friendliness on the data bus. 2.4 signal descriptions the pad ring supports 352 functional pins (388 including all power and ground). this section describes each pin and the functionality it supports. a forward slash (/) in a signal name indicates the separation of one functionality from another functionality. because the pin names exactly reflect the names from the ball maps (figure 2-12 through figure 2-15), separate functionality in pin names is indicated by an underscore (_) rather than a forward slash. 2.4.1 usiu pads 2.4.1.1 addr[8:31] / sgpioa[8:31] pin name: addr_sgpioa8 through addr_sgpioa31 (24 pins) address bus [8:31] ? specifies the physical address of the bus transaction. the address is driven onto the bus and kept valid until a transfer acknowledge is received from the slave. addr8 is the most significant signal for this bus. msb 0 123456789101112131415 predis_en reserved hreset : 0 000000000 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved hreset : 0 000000000 000000 figure 2-2. pdmcr2 ? pads module configuration register 20x2f c038 table 2-4. pdmcr2 field descriptions bit(s) name description 0 predis_en predis_en 0 bus pre-discharge disabled 1 bus pre-discharge enabled 1:31 ? reserved motorola chapter 2. signal descriptions 2-9 signal descriptions port sgpioa [8:31] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.1.2 data[0:31] / sgpiod[0:31] pin name: data_sgpiod0 through data_sgpiod31 (32 pins) data bus [0:31] ? provides the general-purpose data path between the chip and all other devices. although the data path is a maximum of 32 bits wide, it can be sized to support 8-, 16-, or 32-bit transfers. data[0] is the msb of the data bus. port sgpiod [0:31] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.1.3 irq 0 / sgpioc0 pin name: irq0_b_sgpioc0 interrupt request [0] ? one of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the rcpu. irq [0] is a nonmaskable interrupt (nmi). port sgpioc[0] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.1.4 irq 1 /rsv /sgpioc1 pin name: irq1_b_rsv_b_sgpioc1 interrupt request [1]? one of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the rcpu. reservation ? this line used together with the address bus to indicate that the internal core initiated a transfer as a result of a stwcx or a lwarx instruction. port sgpioc [1] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.1.5 irq 2 /cr /sgpioc2/mts pin name: irq2_b_cr_b_sgpioc2_mts_b interrupt request [2]? one of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the rcpu. cancel reservation ? instructs the chip to clear its reservation, some other master has touched its reserved space. an external bus snooper would assert this signal. 2-10 mpc565/mpc566 reference manual motorola signal descriptions port sgpioc [2] ? this function allows the pins to be used as general-purpose inputs/outputs. memory transfer start ? this pin is the transfer start signal from the mpc565/mpc566 memory controller to allow external memory access by an external bus master. 2.4.1.6 irq 3 /kr /retry / sgpioc3 pin name: irq3_b_kr_b_retry_b_sgpioc3 interrupt request [3] ? one of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the rcpu. kill reservation ? in case of a bus cycle initiated by a stwcx instruction issued by the cpu core to a non-local bus on which the storage reservation has been lost, this signal is used by the non-local bus interface to back-off the cycle. retry ? indicates to a master that the cycle is terminated but should be repeated. as an input, it is driven by the external slave to retry a cycle. port sgpioc [3] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.1.7 irq4 /at2/sgpioc4 pin name: irq4_b_at2_sgpioc4 interrupt request [4] ? one of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the rcpu. address type [2] ? a bit from the address type bus which indicates one of the 16 ?address types? to which the address applies. the address type signals are valid at the rising edge of the clock in which the special transfer start (sts ) is asserted. port sgpioc [4] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.1.8 irq 5 / sgpioc5 / modck1 pin name: irq5_b_sgpioc5_modck1 interrupt request [5] ? one of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the rcpu. port sgpioc [5] ? this function allows the pins to be used as general-purpose inputs/outputs. mode clock [1] ? sampled at the negation of poreset /trst in order to configure the phase-locked loop (pll)/clock mode of operation. motorola chapter 2. signal descriptions 2-11 signal descriptions 2.4.1.9 irq [6:7] / modck[2:3] pin names: irq6_b_modck2, irq7_b_modck3 (2 pins) interrupt request [6:7] ? one of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the rcpu. mode clock [2:3] ? sampled at the negation of poreset /trst in order to configure the pll/clock mode of operation. 2.4.1.10 tsiz[0:1] pin names: tsiz0, tsiz1 (2 pins) transfer size [0:1] ? indicates the size of the requested data transfer in the current bus cycle. 2.4.1.11 rd / wr pin name: rd_wr_b read/write ? indicates the direction of the data transfer for a transaction. a logic one indicates a read from a slave device; a logic zero indicates a write to a slave device. 2.4.1.12 burst pin name: burst_b burst indicator ? indicates whether the current transaction is a burst transaction or not. 2.4.1.13 bdip pin name: bdip_b burst data in progress ? indicates to the slave that there is a data beat following the current data beat. 2.4.1.14 ts pin name: ts_b transfer start ? indicates the start of a bus cycle that transfers data to/from a slave device. this signal is driven by the master only when it has gained ownership of the bus. every master should negate this signal before the bus is relinquished. this pin is an active low signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. 2-12 mpc565/mpc566 reference manual motorola signal descriptions 2.4.1.15 ta pin name: ta_b transfer acknowledge ? this line indicates that the slave device addressed in the current transaction has accepted the data transferred by the master (write) or has driven the data bus with valid data (read). the slave device negates the ta signal after the end of the transaction and immediately three-states it to avoid contentions on the line if a new transfer is initiated addressing other slave devices. this pin is an active low signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. 2.4.1.16 tea pin name: tea_b transfer error acknowledge ? this signal indicates that a bus error occurred in the current transaction. the mcu asserts this signal when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. the assertion of tea causes the termination of the current bus cycle, regardless of the state of tea . an external pull-up device is required to negate tea quickly, before a second error is detected. that is, the pin must be pulled up within one clock cycle of the time it was three-stated by the mpc565/mpc566. 2.4.1.17 rstconf /texp pin name: rstconf_b_texp reset configuration ? input. this input line is sampled by the chip during the assertion of the hreset signal in order to sample the reset configuration. if the line is asserted, the configuration mode is sampled from the external data bus. when this line is negated, the configuration mode adopted by the chip is the default one. timer expired ? output. this output line reflects the status of the texps bit in the plprcr register in the usiu. this indicates an expired timer value. 2.4.1.18 oe pin name: oe_b output enable ? this output line is asserted when a read access to an external slave controlled by the gpcm in the memory controller is initiated by the chip. 2.4.1.19 bi /sts pin name: bi_b_sts_b motorola chapter 2. signal descriptions 2-13 signal descriptions burst inhibit ? this bidirectional, active low, three-state line indicates that the slave device addressed in the current burst transaction is not able to support burst transfers. when the chip drives out the signal for a specific transaction, it asserts or negates bi during the transaction according to the value specified in the appropriate control registers. negation of the signal occurs after the end of the transaction followed by the immediate three-state. this pin is an active low signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. special transfer start ? this output signal is driven by the chip to indicate the start of a transaction on the external bus or signals the beginning of an internal transaction in showcycle mode. 2.4.1.20 cs [0:3] pin names: cs0_b through cs3_b (4 pins) chip select [0:3] ? these output signals enable peripheral or memory devices at programmed addresses if defined appropriately in the memory controller. cs [0] can be configured to be the global chip select for the boot device. 2.4.1.21 we [0:3] / be [0:3] / at[0:3] pin names: we_b_at0 through we_b_at3 (4 pins) write enable[0:3]/byte enable[0:3] ? this output line is asserted when a write access to an external slave controlled by the memory controller is initiated by the chip. it can be optionally be asserted on all read and write accesses. see webs bit definition in table 10-8. we 0/be 0 is asserted if the data lane data[0:7] contains valid data to be stored by the slave device. we 1/be 1 is asserted if the data lane data[8:15] contains valid data to be stored by the slave device. we 2/be 2 is asserted if the data line data[16:23] contains valid data to be stored by the slave device. we 3/be 3 is asserted if the data lane data[24:31] contains valid data to be stored by the slave device. address type [0:3] ? indicates one of the 16 address types to which the address applies. the address type signals are valid at the rising edge of the clock in which the special transfer start (sts ) is asserted. 2.4.1.22 poreset /trst pin name: poreset_b_trst_b power-on reset ? this pin should be activated as a result of a voltage failure on the keep-alive power pins. the pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. the internal poreset /trst signal is asserted only if poreset /trst is asserted for more than 100 ns. see chapter 7, ?reset,? for more details on timing. 2-14 mpc565/mpc566 reference manual motorola signal descriptions test reset ? this input provides asynchronous reset to the test logic (jtag). 2.4.1.23 hreset pin name: hreset_b hard reset ? the chip can detect an external assertion of hreset only if it occurs while the chip is not asserting reset. after negation of hreset or sreset is detected, a 16-cycle period is taken before testing the presence of an external reset. the internal hreset signal is asserted only if hreset is asserted for more than 100 ns. to meet external timing requirements, an external pull-up device is required to negate hreset .see chapter 7, ?reset,? for more details on timing. 2.4.1.24 sreset pin name: sreset_b soft reset ? the chip can detect an external assertion of sreset only if it occurs while the chip is not asserting reset. after negation of hreset or sreset is detected, a 16-cycle period is taken before testing the presence of an external soft reset. to meet external timing requirements, an external pull-up device is required to negate sreset .see chapter 7, ?reset,? for more details on timing. 2.4.1.25 sgpioc6 / frz / ptr pin name: sgpioc6_frz_ptr_b port sgpioc [6] ? this function allows the pins to be used as general-purpose inputs/outputs. freeze ? indicates that the rcpu is in debug stopped mode. program trace ? indicates an instruction fetch is taking place in order to allow program flow tracking. 2.4.1.26 sgpioc7 / irqout /lwp0 pin name: sgpioc7_irqout_b_lwp0 port sgpioc [7] ? this function allows the pin to be used as general-purpose inputs/outputs. interrupt out ? indicates that an interrupt has been requested to all external devices. load/store watchpoint [0] ? this output line reports the detection of a data watchpoint in the program flow executed by the rcpu. see chapter 22, ?development support,? for more details. motorola chapter 2. signal descriptions 2-15 signal descriptions 2.4.1.27 bg /vf0/lwp1 pin name: bg_b_vf0_lwp1 bus grant ? indicates external data bus status. is asserted low when the arbiter of the external bus grants to the specific master the ownership of the bus. visible instruction queue flush status ? this output line together with vf[1] and vf[2] is output by the chip when program instruction flow tracking is required. vfs report the number of instructions flushed from the instruction queue in the internal core. see chapter 22, ?development support,? for more details. load/store watchpoint [1] ? this output line reports the detection of a data watchpoint in the program flow executed by the rcpu. 2.4.1.28 br /vf1/iwp2 pin name: br_b_vf1_iwp2 bus request ? indicates that the data bus has been requested for external cycle. visible instruction queue flush status [1] ? this output line together with vf[1] and vf[2] is output by the chip when program instruction flow tracking is required. vfs report the number of instructions flushed from the instruction queue in the internal core. see chapter 22, ?development support,? for more details. instruction watchpoint [2] ? this output line reports the detection of an instruction watchpoint in the program flow executed by the rcpu. 2.4.1.29 bb /vf2/iwp3 pin name: bb_b_vf2_iwp3 bus busy ? indicates that the master is using the bus. this pin is an active low signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. visible instruction queue flush status [2] ? this output line together with vf[0] and vf[1] is output by the chip when a program instructions flow tracking is required. vf report the number of instructions flushed from the instruction queue in the internal core. instruction watchpoint [3] ? this output line reports the detection of an instruction watchpoint in the program flow executed by the internal core. 2.4.1.30 iwp[0:1] / vfls[0:1] pin names: iwp0_vfls0 through iwp1_vfls1 (2 pins) 2-16 mpc565/mpc566 reference manual motorola signal descriptions instruction watchpoint [0:1] ? these output lines report the detection of an instruction watchpoint in the program flow executed by the rcpu. visible history buffer flush status [0:1] ? these signals are output by the chip to enable program instruction flow tracking. they report the number of instructions flushed from the history buffer in the rcpu. see chapter 22, ?development support,? for details. 2.4.1.31 tms pin name: tms test mode select ? this input controls test mode operations for on-board test logic (jtag). 2.4.1.32 tdi / dsdi pin name: tdi_dsdi test data in ? this input is used for serial test instructions and test data for on-board test logic (jtag). development serial data input ? this input line is the data in for the debug port interface. see chapter 22, ?development support,? for details. 2.4.1.33 tck / dsck pin name: tck_dsck test clock ? this input provides a clock for on-board test logic (jtag). development serial clock ? this input line is the clock for the debug port interface. see chapter 22, ?development support,? for details. 2.4.1.34 tdo / dsdo pin name: tdo_dsdo test data out ? this output is used for serial test instructions and test data for on-board test logic (jtag). development serial data output ? this output line is the data-out line of the debug port interface. see chapter 22, ?development support,? for details. 2.4.1.35 jcomp pin name: jcomp jtag compliancy ? this signal enables the ieee1149.1 jtag circuitry in the mpc565/mpc566. this pin was trst on the k85h mask set of the mpc565. motorola chapter 2. signal descriptions 2-17 signal descriptions 2.4.1.36 xtal pin name: xtal xtal ? this output line is one of the connections to an external crystal for the internal oscillator circuitry. 2.4.1.37 extal pin name: extal extal ? this line is one of the connections to an external crystal for the internal oscillator circuitry. if this pin is unused, it must be grounded. 2.4.1.38 xfc pin name: xfc external filter capacitance ? this input line is the connection pin for an external capacitor filter for the pll circuitry. 2.4.1.39 clkout pin name: clkout clock out ? this output line is the clock system frequency. the clkout drive strength can be configured to full strength, half strength, quarter strength, or disabled. the drive strength is configured using the com[0:1] bits and cqds bits in the sccr register in the usiu. 2.4.1.40 extclk pin name: extclk extclk ? input. this is the external frequency source for the chip. if this is unused, the pin must be grounded. 2.4.1.41 vddsyn pin name: vddsyn vddsyn ? this is the power supply of the pll circuitry. 2.4.1.42 vsssyn pin name: vsssyn vsssyn ? this is the ground reference of the pll circuitry. 2-18 mpc565/mpc566 reference manual motorola signal descriptions 2.4.1.43 engclk / buclk pin name: engclk_buclk engclk ? this is the engineering clock output. drive voltage can be configured to 2.6 v, 5 v (with slew-rate control) or disabled. the drive voltage is configured using the eeclk[0:1] bits in the sccr register in the siu. buclk ? when the chip is in limp mode, it is operating from a less precise on-chip ring oscillator to allow the system to continue minimum functionality until the system clock is fixed. this backup clock can be seen externally if selected by the values of the eeclk[0:1] bits in the sccr register in the usiu. 2.4.1.44 pull_sel pin name: pull_sel pull select ? this pin determines whether the pull devices on the mios and tpu pins are pull-ups or pull-downs. when pull-ups are selected, the pull-ups are to 5.0 v. the following mios pins always have pull down resistors unless disabled in the pdmcr register: vf[0:2]/mpio32b[0:2], vfls[0:1]/mpio32b[3:4], and mdo[7:4]/mpio32b[7:10]. 2.4.2 qsmcm a / qsmcm b / dlcmd2 (j1850) pads the mpc565/mpc566 has two qsmcm modules, qsmcm a and qsmcm b. qsmcm a has identical function to the mpc555/mpc556?s qsmcm a module. qsmcm b has its rxd2 and pcs[3] pins muxed with the dlcmd2 (j1850) module. the muxing of the pins is controlled by the qpapcs3 bit in the qsmcm_b pin assignment register (pqspar ), according to table 2-5. the muxed pins default to the dlcmd2 function at reset. because the normal function of the pcs pins within the qsmcm require that this bit be written before the pcs pin is used, the muxing appears transparent to both the qsmcm b and the dlcmd2 modules. however, only one of the modules, dlcmd2 or qsmcm b can use the pins in a system. because of this muxed function on qsmcm b, the general-purpose input and output functions are not available on the b_pcs[3] and b_rxd2 pins table 2-5. dlcmd2 / qsmcm b sci2 pin mux control qpapcs3 bit value qsmcm_b / dlcmd2 pin function 0 b_pcs[3] / j1850_tx pin assigned to j1850_tx. b_rxd2 / j1850_rx pin assigned to j1850_rx. pins are assigned to dlcmd2 (j1850_tx and j1850_rx) 1 b_pcs[3] / j1850_tx pin assigned to pcs[3]. b_rxd2 / j1850_rx pin assigned to b_rxd2. pins are assigned to qsmcm b sci2 (b_pcs[3] and b_rxd2) motorola chapter 2. signal descriptions 2-19 signal descriptions 2.4.2.1 pcs0 / ss / qgpio0 pin names: a_pcs0_ss_b_qgpio0, b_pcs0_ss_b_qgpio0 (2 pins, one for each module) pcs [0] ? this signal provides qspi peripheral chip select 0. ss ? assertion of this bidirectional signal places the qspi in slave mode. port qgpio [0] ? when this pin is not needed for a qspi application it can be configured as a general-purpose input/output. 2.4.2.2 pcs[1:2] / qgpio[1:2] pin names: a_pcs1_qgpio1, a_pcs2_qgpio2, b_pcs1_qgpio1, b_pcs2_qgpio2 (4 pins, two for each module) pcs [1:2] ? these signals provide two qspi peripheral chip selects. port qgpio [1:2] ? when these pins are not needed for qspi applications they can be configured as general-purpose input/outputs. 2.4.2.3 pcs3 / qgpio3 / j1850_tx pin names: a_pcs3_qgpio3, b_pcs3_j1850_tx (2 pins, one for each module) pcs [3] ? these signals provide two qspi peripheral chip selects. port qgpio [3] ? when the qsmcm_a pcs3 pin is not needed for qspi applications it can be configured as a general-purpose input/output. j1850_tx ? the qsmcm_b pcs3 pin can be configured as the j1850 transmit pin for the dlcmc2 module. 2.4.2.4 miso / qgpio4 pin names: a_miso_qgpio4, b_miso_qgpio4 (2 pins, one for each module) master-in slave-out (miso) ? this bidirectional signal furnishes serial data input to the qspi in master mode, and serial data output from the qspi in slave mode. port qgpio [4] ? when this pin is not needed for a qspi application it can be configured as a general-purpose input/output. 2.4.2.5 mosi / qgpio5 pin names: a_mosi_qgpio5, b_mosi_qgpio5 (2 pins, one for each module) master-out slave-in (mosi) ? this bidirectional signal furnishes serial data output from the qspi in master mode and serial data input to the qspi in slave mode. 2-20 mpc565/mpc566 reference manual motorola signal descriptions port qgpio [5] ? when this pin is not needed for a qspi application it can be configured as a general-purpose input/output. 2.4.2.6 sck / qgpio6 pin names: a_sck_qgpio6, b_sck_qgpio6 (2 pins, one for each module) sck ? this bidirectional signal furnishes the clock from the qspi in master mode or furnishes the clock to the qspi in slave mode. port qgpio [6] ? when this pin is not needed for a qspi application, it can be configured as a general-purpose input/output. when the qspi is enabled for serial transmitting, the pin can not function as a gpio. 2.4.2.7 txd[1:2] / qgpo[1:2] pin names: a_txd1_qgpo1, b_txd1_qgpo1, a_txd2_qgpo2, b_txd2_qgpo2 (4 pins, two for each module) transmit data [1:2] ? these output signals are the serial data outputs from the sci1 and sci2. port qgpo [1:2] ? when these pins are not needed for a sci applications, they can be configured as general-purpose outputs. when the transmit enable bit in the sci control register is set to a logic 1, these pins can not function as general-purpose outputs 2.4.2.8 rxd[1:2] / qgpi[1:2], rxd1 / qgpi1, rxd2 / j 1850_rx pin names: a_rxd1_qgpi1, a_rxd2_qgpi2, b_rxd1_qgpi1, b_rxd2_j1850_rx (4 pins, two for each module) receive data [1:2] ? these input signals furnish serial data inputs to the sci1 and sci2. port qgpi [1:2] ? when these pins are not needed for sci1 applications, they can be configured as general-purpose inputs. when the receive enable bit in the sci control register is set to a logic 1, these pins cannot function as general-purpose inputs. j1850_rx ? the qsmcm_b rxd2 pin can be configured as the j1850 transmit pin for the dlcmc2 module. 2.4.2.9 eck pin name: b_eck external baud clock (eck) ? this signal provides an external baud clock used by sci1 and sci2. (note: this pin is not usable on the mpc565/mpc566.) motorola chapter 2. signal descriptions 2-21 signal descriptions 2.4.3 mios14 pads some of the mios14 signals are shared with other functions. only one function can be used at a time. these extra functions include debug (vf[0:2], vfls[0:1]), readi (mdo[7:4]), toucan (c_cntx0, c_cnrx0), and the additional mios14 functions mpwm[4:5, 20:21], and 32kclkout. for additional information about mios14 testing and pin usage, see section 17.6.1.1, ?mios14 test and pin control register (mios14tpcr).? 2.4.3.1 mda[11, 13, 27, 30] pin names: mda11, mda13, mda27, mda30 (4 pins) double action ? each of these pins provide a path for two 16-bit input captures and two 16-bit output compares. clock input ? each of these pins provide a clock input to the modulus counter submodule. mda11 can be used as the clock input to the mmcsm6 modulus counter. mda13 can be used as the clock input to the mmcsm22 modulus counter. 2.4.3.2 mda[12, 14, 28, 31] pin names: mda12, mda14, mda28, mda31(4 pins) double action ? each of these pins provide a path for two 16-bit input captures and two 16-bit output compares. load input ? each of these pins provide a load input to the modulus counter submodule. mda12 can be used as the load input to the mmcsm6 modulus counter. mda14 can be used as the load input to the mmcsm22 modulus counter. 2.4.3.3 mda[15, 27:31] pin names: mda15, mda27 through mda31 (6 pins) double action ? each of these pins provide a path for two 16-bit input captures and two 16-bit output compares. 2.4.3.4 mpwm[0:3] pin names: mpwm0 through mpwm3 (4 pins) pulse width modulation [0:3] ? these pins provide variable pulse width output signals at a wide range of frequencies. 2.4.3.5 mpwm[16, 18] pin names: mpwm16, mpwm18 (2 pins) 2-22 mpc565/mpc566 reference manual motorola signal descriptions pulse width modulation [16, 18] ? these pins provide variable pulse width output signals at a wide range of frequencies. clock input ? each of these pins provide a clock input to the modulus counter submodule. mpwm16 can be used as the clock input to the mmcsm6 modulus counter. mpwm18 can be used as the clock input to the mmcsm22 modulus counter. 2.4.3.6 mpwm[17, 19] pin names: mpwm17, mpwm19 (2 pins) pulse width modulation [17, 19] ? these pins provide variable pulse width output signals at a wide range of frequencies. load input ? each of these pins provide a load input to the modulus counter submodule. mpwm17 can be used as the load input to the mmcsm6 modulus counter. mpwm19 can be used as the load input to the mmcsm22 modulus counter. 2.4.3.7 vf[0:2] / mpio32b[0:2] pin names: vf0?mpio32b0, vf1?mpio32b1, vf2?mpio32b2 (3 pins) visible instruction queue flush status [0:2] ? these lines output by the chip when program instruction flow tracking is required. vf reports the number of instructions flushed from the instruction queue in the internal core. port mios gpio [0:2] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.3.8 vfls[0:1] / mpio32b[3:4] pin names: vfls0_mpio32b3, vfls1_mpio32b4 (2 pins) visible history buffer flush status [0:1] ? these signals are output by the chip to allow program instruction flow tracking. they report the number of instructions flushed from the history buffer in the rcpu. see chapter 22, ?development support,? for details. mios gpio [3:4] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.3.9 mpwm[4:5] / mpio32b[5:6] pin names: mpwm4_mpio32b5, mpwm5_mpio32b6 (2 pins) pulse width modulation [4:5] ? these pins provide variable pulse width output signals at a wide range of frequencies. motorola chapter 2. signal descriptions 2-23 signal descriptions port mios gpio [5:6] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.3.10 mdo[7:4] / mpio32b[7:10] pin names: mdo_7_mpio32b7, mdo_6_mpio32b8, mdo_5_mpio32b9, mdo_4_mpio32b10 (4 pins) port mios gpio [7:10] ? this function allows the pins to be used as general-purpose inputs/outputs. readi (nexus) data out ? this function allows the pins to be used by the readi modules as nexus data output pins. 2.4.3.11 mpwm[20:21] / mpio32b[11:12] pin names: mpwm20_mpio32b11, mpwm21_mpio32b12 (2 pins) pulse width modulation [20:21] ? these pins provide variable pulse width output signals at a wide range of frequencies. port mios gpio [11:12] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.3.12 c_cntx0 / c_cnrx0 / mpio32b[13:14] pin names: c_cntx0_mpio32b13, c_cnrx0_mpio32b14 (2 pins) port mios gpio [13:14] ? this function allows the pins to be used as general-purpose inputs/outputs. toucan_c receive/transmit ? these pins provide the receive and transmit pins for the toucan_c module. 2.4.3.13 mpio32b15 pin name: mpio32b15 port mios gpio [15] ? this function allows the pins to be used as general-purpose inputs/outputs. 2.4.4 32-khz oscillator pads 2.4.4.1 xtal32 pin name: xtal32 2-24 mpc565/mpc566 reference manual motorola signal descriptions xtal32 ? this output line is one of the connections to an external 32-khz crystal for the mios14 real-time clock submodule (mrtcsm). 2.4.4.2 extal32 pin name: extal32 extal32 ? this line is one of the connections to an external 32-khz crystal for the internal oscillator circuitry used by the mrtcsm. if this pin is unused, it must be grounded. 2.4.4.3 vddrtc pin name: vddrtc vddrtc ? this is the power supply of the 32-khz oscillator circuitry and the mrtcsm. 2.4.4.4 vssrtc pin name: vssrtc vssrtc ? this is the power supply of the 32-khz oscillator circuitry. 2.4.5 tpu3 a, b, and c pads 2.4.5.1 a_tpuch[0:15], b_tpuch[0:15], c_tpuch[0:15] pin name: a_tpuch0 through a_tpuch15 (16 pins for tpu3_a), b_tpuch0 through b_tpuch15 (16 pins for tpu3_b), c_tpuch0 through c_tpuch15 (16 pins for tpu3_c) tpu channels a, b, and c ? these signals provide each tpu3 with 16 input/output programmable timed events. 2.4.5.2 t2clk pin names: a_t2clk (1 pin for tpu3_a), b_t2clk (1 pin for tpu3_b), c_t2clk (1 pin for tpu3_c) t2clk ? this signal is used to clock or gate the timer count register 2 (tcr2) within the tpu. this pin is an output-only in special test mode. 2.4.6 qadc64 a and b pads 2.4.6.1 etrig[1:2] pin names: etrig1, etrig2 (2 pins) motorola chapter 2. signal descriptions 2-25 signal descriptions etrig [1:2] ? these are the external trigger inputs to the qadc64 a and b modules. etrig[1] can be configured to be used by both qadc64 a and qadc64 b. likewise, etrig[2] can be used for both qadc64 b and qadc64 a. the trigger input signals are associated with the scan queues. 2.4.6.2 an44 / anw / pqb0 pin name: an44_anw_a_pqb0 analog channel [44] ? internally multiplexed input-only analog channels. passed on as a separate signal to the qadc64e. multiplexed analog input (anw) ? externally multiplexed analog input. port a_pqb [0] ? when this pin is not needed for qadc converter functions, it can be used as a general-purpose input or output. 2.4.6.3 an45 / anx / pqb1 pin name: an45_anx_a_pqb1 analog channel [45] ? internally multiplexed input-only analog channels. passed on as a separate signal to the qadc64e. multiplexed analog input (anx) ? externally multiplexed analog input. port a_pqb [1] ? when this pin is not needed for qadc converter functions, it can be used as a general-purpose input or output. 2.4.6.4 an46 / any / pqb2 pin name: an46_any_a_pqb2 analog channel [46] ? internally multiplexed input-only analog channel. the input is passed on as a separate signal to the qadc64e. multiplexed analog input (any) ? externally multiplexed analog input. port a_pqb [2] ?when this pin is not needed for qadc converter functions, it can be used as a general-purpose input or output. 2.4.6.5 an47 / anz / pqb3 pin name: an47_anz_a_pqb3 analog input [47] ? internally multiplexed input-only analog channel. the input is passed on as a separate signal to the qadc64e. multiplexed analog input (anz) ? externally multiplexed analog input. 2-26 mpc565/mpc566 reference manual motorola signal descriptions port a_pqb [3] ? when this pin is not needed for qadc converter functions, it can be used as a general-purpose input or output. 2.4.6.6 an[48:51] / pqb[4:7] pin name: an48_a_pqb4 through an51_a_pqb7 (4 pins) analog input [48:51] ? analog input channel. the input is passed on as a separate signal to the qadc64e. port a_pqb [4:7] ? when this pin is not needed for qadc converter functions, it can be used as a general-purpose input or output. 2.4.6.7 an[52:54] / ma[0:2] / pqa[0:2] pin names: an52_a_ma0_pqa0 through an54_a_ma2_pqa2 (3 pins) analog input [52:54] ? input-only. the input is passed on a separate signal to the qadc64e. multiplexed address [0:2] ? output. provides a three-bit multiplexed address output to the external multiplexer chip to allow selection of one of the eight inputs. port a_pqa [0:2] ? when this pin is not needed for qadc converter functions, it can be used as a general-purpose input or output. 2.4.6.8 an[55:59] / pqa[3:7] pin names: an55_a_pqa3 through an59_a_pqa7 (5 pins) analog input [55:59] ? input-only. the input is passed on as a separate signal to the qadc64e. port a_pqa [3:7] ? when this pin is not needed for qadc converter functions, it can be used as a general-purpose input or output. 2.4.6.9 an[64:71] / pqb[0:7] pin names: an64_b_pqb0 through an71_b_pqb7 (8 pins) analog input [55:59] ? input-only. the input is passed on as a separate signal to the qadc64e. port b_pqb [3:7] ? when this pin is not needed for qadc converter functions, it can be used as a general-purpose input or output. motorola chapter 2. signal descriptions 2-27 signal descriptions 2.4.6.10 an[72:74] / ma[0:2] / pqa[0:2] pin names: an72_b_ma0_pqa0 through an74_b_ma2_pqa2 (3 pins) analog input [72:74] ? input-only. the input is passed on as a separate signal to the qadc64e. multiplexed address [0:2] ? output. provides a three-bit multiplexed address output to the external multiplexer chip to allow selection of one of the eight inputs. port b_pqa [0:2] ? when this pin is not needed for qadc converter functions, it can be used as a general-purpose input or output. 2.4.6.11 an[75:79] / pqa[3:7] pin names: an75_b_pqa3 through an79_b_pqa7 (5 pins) analog input [75:79] ? input-only. the input is passed on as a separate signal to the qadc64e. port b_pqa [3:7] ? when this pin is not needed for qadc converter functions, it can be used as a general-purpose input or output. 2.4.6.12 an[80:87] pin names: an80 through an87 (8 pins) analog input [80:87] ? input-only. the input is passed on as a separate signal to the qadc64e by the amux. 2.4.6.13 vrh pin name: vrh vrh ? input pin for high reference voltage for the qadc64_a and qadc64_b modules. 2.4.6.14 vrl pin name: vrl vrl ? input pin for low reference voltage for the qadc64_a and qadc64_b modules. 2.4.6.15 altref pin name: altref altref ? input pin for alternate reference voltage for the qadc64_a and qadc64_b modules. 2-28 mpc565/mpc566 reference manual motorola signal descriptions 2.4.6.16 vdda pin name: vdda vdda ? power supply input to analog subsystems of the qadc64_a and qadc64_b modules. 2.4.6.17 vssa pin name: vssa vssa ? input. ground level for analog subsystems of the qadc64_a and qadc64_b modules. 2.4.7 toucan a, b, and c pads 2.4.7.1 cntx0 pin names: a_cntx0 (1 pin for can a), b_cntx0 (1 pin for can b), c_cntx0_mpio32b13 (1pinforcanc,muxedwithamios14gpio) toucan transmit data 0 ? this signal is the serial data output. 2.4.7.2 cnrx0 pin names: a_cnrx0 (1 pin for can a), b_cnrx0 (1 pin for can b), c_cnrx0_mpio32b14 (1pinforcanc,muxedwithamios14gpio) toucan receive data ? this signal furnishes serial input data. 2.4.8 readi pads some readi pads are shared with mios14 functions, see 2.4.3 ?mios14 pads.? 2.4.8.1 mseo pin name: mseo_b mseo ? message start/end out (mseo ) is an output pin that indicates when a message on the mdo pins has started, when a variable length packet has ended, and when the message has ended. external latching of mseo occurs on the rising edge of mcko. 2.4.8.2 mdo[3:0] pin names: mdo_3 through mdo_0 (4 pins) motorola chapter 2. signal descriptions 2-29 signal descriptions message data output [3:0] ? message data out (mdo[7:0] or mdo[1:0]) are output pins used for uploading otm, btm, dtm, and read/write accesses. external latching of mdo occurs on the rising edge of mcko. eight pins are implemented; four (mdo[7:4]) are shared with mios14 gpio. 2.4.8.3 mcko pin name: mcko mcko ? output. message clock-out (mcko) is a free-running output clock to development tools for timing of mdo and mseo pin functions. mcko is the same as the mcu system clock. 2.4.8.4 rsti pin name: rsti_b rsti ? reset in. rsti is the nexus port reset input. 2.4.8.5 evti pin name: evti_b evti ? event in (evti) is level sensitive when configured for breakpoint generation, otherwise it is edge sensitive. 2.4.8.6 msei pin name: msei_b msei ? message start/end input. the msei input is a nexus input pin which indicates when a message on the mdi pins has started, when a variable length packet has ended, and when the message has ended. internal latching of msei occurs on the rising edge of mcki. 2.4.8.7 mdi[0:1] pin names: mdi_0, mdi_1 message data input [0:1] ? mdi[0] or mdi[1] are nexus input pins used for downloading configuration information, writes to user resources, and so forth. internal latching of mdi will occur on the rising edge of mcki. 2.4.8.8 mcki pin name: mcki mcki ? message clock input. mcki is the nexus message clock input. 2-30 mpc565/mpc566 reference manual motorola signal descriptions 2.4.9 uc3f pads 2.4.9.1 epee pin name: epee epee ? input. this external program/erase enable control signal externally controls the program or erase operations. when low, program or erase operations in both of the uc3f modules (uc3f_512ka and uc3f_512kb) are disabled. 2.4.9.2 b0epee pin name: b0epee b0epee ? input. this control signal externally controls the program or erase operations of block 0 of uc3f_512ka. when low, program or erase operations are disabled in block 0 of the uc3f_512ka module. 2.4.9.3 vflash pin name: vflash vflash ? input. flash supply voltage (5-v supply) used during all operations of the uc3f. 2.4.9.4 vddf pin name: vddf vddf ? flash core voltage input (2.6-v supply). 2.4.9.5 vssf pin name: vssf vssf ? flash core zero supply input. 2.4.10 global power supplies 2.4.10.1 nvddl pin name: nvddl nvddl ? noisy 2.6-v voltage supply input. this supplies the final output stage of the 2.6-v pad output drivers. motorola chapter 2. signal descriptions 2-31 signal descriptions the nvddl and qvddl supplies should be connected to the same power supply in a user's system. 2.4.10.2 qvddl pin name: qvddl qvddl ? quiet 2.6-v voltage supply input. this supplies all pad logic and pre-driver circuitry, except for the final output stage of the 2.6-v pad output drivers. the nvddl and qvddl supplies should be connected to the same power supply in a user's system. 2.4.10.3 vddh pin name: vddh vddh ? 5-v voltage supply input. 2.4.10.4 vdd pin name: vdd vdd ? 2.6-v voltage supply input for internal logic. 2.4.10.5 kapwr pin name: kapwr keep-alive power ? 2.6-v voltage supply input for the oscillator and keep-alive registers. 2.4.10.6 vddsram1 pin name: vddsram1 sram keep-alive power ? 2.6-v voltage supply input for the keep-alive section of the calram_a (32k) module. this pin supplies only keep-alive power to the calram_a (32k) module. run current is supplied by normal vdd. 2.4.10.7 vddsram2 pin name: vddsram2 sram keep-alive power ? 2.6-v voltage supply input for the calram_b (4 kbyte) module. this pin supplies only keep-alive power to the calram_b (4 kbyte) module. run current is supplied by normal vdd. 2-32 mpc565/mpc566 reference manual motorola reset state 2.4.10.8 vddsram3 pin name: vddsram3 sram keep-alive power ? 2.6-v voltage supply input for the arrays in the dptram_ab (6 kbytes), dptram_c (4 kbytes), and the bbc decram (4 kbytes) modules. this pin supplies only keep-alive power to both dptram arrays and the decram module. run current is supplied by normal vdd. 2.4.10.9 vss pin name: vss vss ? ground level reference input. 2.5 reset state during reset, a 130-a (maximum) resistor ?weakly pulls? all input pins, with the exception of the power-supply and clock-related pins, to a value based on conditions described in appendix e, ?electrical characteristics.? in reset state, all i/o pins become inputs, and all outputs except for clkout, hreset ,andsreset arepulledonlybythe pull-up/pull-down. 2.5.1 pin functionality configuration out of reset the reset configuration word in the siumcr defines the post-reset functionality of some multiplexed pins. for details on these pins and how they are configured, refer to section 7.5.2, ?hard reset configuration word.? the 2.6-v related pins have selectable output buffer drive strengths that are controlled by the com0 bit in the usiu?s system clock and reset control register (sccr). the control is as follows: 0 = 2.6-v bus pins full drive (50-pf load)* 1 = 2.6-v bus pins reduced drive (25-pf load) * the bus pin drive selectability definition is inverted from the selectability of the pin control in the pdmcr register (for the tpu, qadc64e, usiu (sgpio), qspi, toucan, qsci, and mios pins). 2.5.2 pin state during reset while hreset is asserted, the reset-configuration value is latched from the data bus into various bits on the part. the function of many pins depends upon the value latched. if the value on the data bus changes, then the function of various pins may also change. this is especially true if the reset configuration word (rcw) comes from the flash, because the flash does not drive the rcw until 256 clocks after the start of hreset . however, the pins must not cause any spurious conditions or consume an excessive amount of power motorola chapter 2. signal descriptions 2-33 reset state during reset. to prevent these conditions, the pins need to have a defined reset state. table 2-6 describes the reset state of the pins based on pin functionality. all pins are initialized to a ?reset state? during reset. this state remains active until reset is negated or until software disables the pull-up or pull-down device based on the pin functionality. upon assertion of the corresponding bits in the pin control registers and negation of reset, the pin acquires the functionality that was programmed. 2.5.3 power-on reset and hard reset power-on reset and hard reset affect the functionality of the pins out of reset. (during soft reset, the functionality of the pins is unaltered.) upon assertion of the power-on reset signal (poreset /trst ) the functionality of the pin is not yet known. the weak pull-up or weak pull-down resistors are enabled. the reset configuration word configures the system, and towards the end of reset the pin functionality is known. based upon the pin functionality, the pull-up or pull-down devices are either disabled immediately at the negation of reset or remain enabled, as shown in table 2-6. because hard reset can occur when a bus cycle is pending, the pdmcr bits that enable and disable the pull-up or pull-down resistors are set or reset synchronously to eliminate contention on the pins. (poreset /trst affects these bits asynchronously.) 2.5.4 pin reset states table 2-6 summarizes the reset states of all pins on the mpc565/mpc566. note that pd refers to a weak pull-down, pu_2.6v refers to a weak pull-up to 2.6 v, and pu_5v refers to a weak pull-up to 5 v. all control of the weak-pull devices is in the pdmcr, described in table 2-3. warning 2.6-v inputs are 5-v tolerant, but 2.6-v outputs are not. do not connect 2.6-v outputs to a driver or pull-up greater than 3.1 v. table 2-6. pin reset state pin function port voltage reset state function after poreset /trst or hreset usiu addr[8:31]/ sgpioa[8:31] addr[8:31] 1 i/o 2.6 v pd until reset negates 2 controlled by sc bit in the reset config word. see table 6-10. sgpioa[8:31] 3 i/o 5 v pd until prds is set 2-34 mpc565/mpc566 reference manual motorola reset state data[0:31]/ sgpiod[0:31] data[0:31] 1 i/o 2.6 v pd until reset negates controlled by sc bit in the reset config word. see table 6-10. sgpiod[0:31] 3 i/o 5 v pd until prds is set irq0 / sgpioc0 irq 0 i 2.6 v pin floats during reset, ext. pu required. irq 0 sgpioc0 i/o 2.6 v 4 pin floats during reset irq1 / rsv / sgpioc1 irq 1 i 2.6 v pd until reset negates 2, 5 irq 1 rsv 1 o 2.6 v pd until reset negates 2 sgpioc1 3 i/o 5 v pd until prds is set irq2 / cr / sgpioc2/ mts irq 2 i 2.6 v pd until reset negates 2,5 irq 2 cr i 2.6 v pd until reset negates 2,5 sgpioc2 3 i/o 5 v pd until prds is set mts 1 o 2.6 v pd until prds negates irq3 / kr ,retry / sgpioc3 irq 3 i 2.6 v pd until reset negates 2,5 irq 3 kr ,retry 1 i/o 2.6 v pd when driver not enabled 6 sgpioc3 3 i/o 5 v pd until prds is set irq4 / at2/ sgpioc4 irq 4 i 2.6 v pd until reset negates 2,5 irq 4 at2 1 o 2.6 v pd until reset negates 2 sgpioc4 i/o 5 v pd until prds is set irq5 / sgpioc5/ modck1 7 irq 5 i 2.6 v pu_2.6v until reset negates 2, 8 modck1 until reset negates sgpioc5 1 i/o 2.6 v pu_2.6v until spull_dis0 is set modck1 i 2.6 v pu_2.6v until reset negates 2 irq [6:7]/ modck[2:3] 7 irq [6:7] i 2.6 v pu_2.6v until sprds is set 9 modck[2:3] until reset negates modck[2:3] i 2.6 v pu_2.6v until reset negates tsiz[0:1] tsiz[0:1] 1 i/o 2.6 v pd when driver not enabled or until sprds is set tsiz[0:1] rd / wr rd/wr 1 i/o 2.6 v pu_2.6v when driver not enabled or until sprds is set rd/wr burst burst 1 i/o 2.6 v pu_2.6v when driver not enabled or until sprds is set burst bdip bdip 1 i/o 2.6 v pu_2.6v when driver not enabled or until sprds is set bdip table 2-6. pin reset state (continued) pin function port voltage reset state function after poreset /trst or hreset motorola chapter 2. signal descriptions 2-35 reset state ts 9 ts 1 i/o 2.6 v pu_2.6v when driver not enabled or until sprds is set an external pull-up is required in order to guarantee the pin does not assert between bus cycles. ts ta 9 ta 1 i/o 2.6 v pu_2.6v when driver not enabled or until sprds is set ta tea tea 1 i/o 2.6 v pu_2.6v when driver not enabled or until sprds is set an external pull-up is required in order to negate the pin in appropriate time tea rstconf / texp 7 rstconf i 2.6 v pu_2.6v when driver not enabled or until sprds is set rstconf until reset negates. following reset, thefunctionis defined by the rctx bit in the siumcr. see table 6-7. texp 1 o2.6v oe oe 1 o 2.6 v pu_2.6v until reset negates oe bi /sts bi 1 i/o 2.6 v pu_2.6v when driver not enabled or until sprds is set controlled by dbgc in the reset config word. see tab l e 6 - 8. sts 1 o2.6v cs [0:3] cs [0:3] 1 o 2.6 v pu_2.6v until reset negates cs [0:3] we [0:3] / be [0:3]/ at[0:3] we [0:3] / be [0:3] 1 o 2.6 v pu_2.6v when driver not enabled or until sprds is set controlled by bit atwc (bit 12) of the reset configuration word. see tab l e 6 - 7. at[0:3] 1 o2.6v poreset / trst 7, 10 poreset /trst i2.6v ? poreset /trst hreset 7 hreset i/o 2.6 v 11 pu_2.6v when driver not enabled an external pull-up is required in order to negate the pin in appropriate time hreset sreset 7 sreset i/o 2.6 v 12 pu_2.6v when driver not enabled an external pull-up is required in order to negate the pin in appropriate time sreset table 2-6. pin reset state (continued) pin function port voltage reset state function after poreset /trst or hreset 2-36 mpc565/mpc566 reference manual motorola reset state sgpioc6/ frz/ ptr sgpioc6 3 i/o 5 v pd until prds is set ptr frz 1 o 2.6 v pd until reset negates 2 ptr 1 o 2.6 v pd until reset negates 2 sgpioc7/ irqout / lwp0 sgpioc7 3 i/o 5 v pd until prds is set lwp0 irqout 1 o2.6v lwp0 1 o2.6v bg / vf0/ lwp1 bg 1 i/o 2.6 v pu_2.6v when driver not enabled or until sprds is set controlled by dbgc in reset config word. see tab l e 6 - 8. vf0 1 o2.6v lwp1 1 o2.6v br / vf1/ iwp2 br 1 i/o 2.6 v pu_2.6v when driver not enabled or until sprds is set controlled by dbgc in reset config word. see tab l e 6 - 8. vf1 1 o2.6v iwp2 1 o2.6v bb / vf2/ iwp3 bb4 1 i/o 2.6 v pu_2.6v when driver not enabled or until sprds is set controlled by dbgc in reset config word. see tab l e 6 - 8 vf2 1 o2.6v iwp3 1 o2.6v iwp[0:1]/ vfls[0:1] iwp[0:1] 1 o 2.6 v output only, no weak pull controlled by dbgc in the reset config word. see tab l e 6 - 8. vfls[0:1] 1 o2.6v tms tms i 2.6 v pu_2.6v until spull_dis1 is set tms tdi/ dsdi tdi i 2.6 v pu_2.6v until spull_dis1 is set controlled by dbpc in reset config word. see tab l e 6 - 9 dsdi i 2.6 v tck/ dsck tck i 2.6 v pd until spull_dis1 is set controlled by dbpc in reset config word. see tab l e 6 - 9 dsck i 2.6 v tdo/ dsdo tdo 1 o 2.6 v ? controlled by dbpc in reset config word. see tab l e 6 - 9 dsdo 1 o2.6v jcomp jcomp 12 i2.6v ? jcomp xtal 7 xtal i 2.6 v ? xtal extal 7 extal i 2.6 v ? extal xfc xfc i 2.6 v ? xfc clkout clkout 1 o 2.6 v ? clkout table 2-6. pin reset state (continued) pin function port voltage reset state function after poreset /trst or hreset motorola chapter 2. signal descriptions 2-37 reset state extclk 7 extclk i 2.6 v ? extclk engclk/ buclk engclk 1 , 3 o 2.6 / 5 v ? engclk (2.6 v) buclk 1 o2.6v ? vddsyn vddsyn i 2.6 v ? vddsyn vsssyn vsssyn i 0 v ? vsssyn pull_sel 13 pull_sel i 5 v pu_5 pull_sel qsmcm_a / qsmcm_b / dlcmd2 a_pcs0/ ss / qgpio0 pcs0 i/o 5 v pu_5v until pull_dis1 is set a_qgpio0 ss i/o 5 v qgpio0 i/o 5 v a_pcs[1:3]/ qgpio[1:3] pcs[1:3] i/o 5 v pu_5v until pull_dis1 is set a_qgpio[1:3] qgpio[1:3] i/o 5 v a_miso/ qgpio4 miso i/o 5 v pu_5v until pull_dis1 is set a_qgpio4 qgpio4 i/o 5 v a_mosi/ qgpio5 mosi i/o 5 v pu_5v until pull_dis1 is set a_qgpio5 qgpio5 i/o 5 v a_sck/ qgpio6 sck i/o 5 v pu_5v until pull_dis1 is set a_qgpio6 qgpio6 i/o 5 v a_txd[1:2]/ qgpo[1:2] txd[1:2] o 5 v pu_5v until pull_dis1 is set a_qgpo[1:2] qgpo[1:2] o 5 v a_rxd[1:2]/ qgpi[1:2] rxd[1:2] i 5 v none a_qgpi[1:2] qgpi[1:2] i 5 v b_pcs0/ ss / qgpio0 pcs0 i/o 5 v pu_5v until pull_dis1 is set b_qgpio0 ss i/o 5 v qgpio0 i/o 5 v b_pcs[1:2]/ qgpio[1:2] pcs[1:2] i/o 5 v pu_5v until pull_dis1 is set b_qgpio[1:2] qgpio[1:2] i/o 5 v b_pcs3/ j1850_tx pcs3 i/o 5 v pu_5v until pull_dis1 is set j1850_tx j1850_tx i/o 5 v b_miso/ qgpio4 miso i/o 5 v pu_5v until pull_dis1 is set b_qgpio4 qgpio4 i/o 5 v table 2-6. pin reset state (continued) pin function port voltage reset state function after poreset /trst or hreset 2-38 mpc565/mpc566 reference manual motorola reset state b_mosi/ b_qgpio5 mosi i/o 5 v pu_5v until pull_dis1 is set b_qgpio5 qgpio5 i/o 5 v b_sck/ qgpio6 sck i/o 5 v pu_5v until pull_dis1 is set b_qgpio6 qgpio6 i/o 5 v b_txd[1:2]/ qgpo[1:2] txd[1:2] o 5 v pu_5v until pull_dis1 is set b_qgpo[1:2] qgpo[1:2] o 5 v b_rxd1/ qgpi1 rxd1 i 5 v none b_qgpi1 qgpi1 i 5 v b_rxd2/ j1850_rx rxd2 i 5 v none j1850_rx j1850_rx i 5 v b_eck b_eck i 5 v pu_5v until pull_dis1 is set ? mios14 mda[11:15], [27:31] mda[11:15], [27:31] i/o 5 v pull device enabled until pull_dis0 is set 14 mda[11:15], [27:31] mpwm[0:3], [16:19] mpwm[0:3], [16:19] i/o 5v pull device enabled until pull_dis0 is set 14 mpwm[0:3], [16:19] vf[0:2]/ mpio32b[0:2] vf[0:2] 1 o 2.6 v pull down until pull_dis0 is set mpio32b[0:2] mpio32b[0:2] 3 i/o 5v vfls[0:1]/ mpio32b[3:4] vfls[0:1] 1 o 2.6 v pull down until pull_dis0 is set mpio32b[3:4] mpio32b[3:4] 3 i/o 5v mpwm[4:5]/ mpio32b[5:6] mpwm[4:5] i/o 5v pull device enabled until pull_dis0 is set 14 mpio32b[5:6] mpio32b[5:6] i/o 5v mdo[7:4]/ mpio32b[7:10] mdo[7:4] 1 o 2.6 v pull down until pull_dis0 is set controlled by readi enable (evti and mdi0) mpio32b[7:10] 3 i/o 5v mpwm[20:21]/ mpio32b[11:12] mpwm[20:21] i/o 5v pull device enabled until pull_dis0 is set 14 motorola chapter 2. signal descriptions 2-39 reset state xtal32 xtal32 i 2.6 v ? xtal32 vddrtc vddrtc i 2.6 v ? vddrtc vssrtc vssrtc i 0 v ? vssrtc tpu3_a / tpu3_b / tpu3_c a_tpuch[0:15] a_tpuch[0:15] i/o 5 v pull device enabled until prds is set 14 a_tpuch[0:15] a_t2clk a_t2clk i/o 5 v pull up enabled until t2clk_pu is set a_t2clk b_tpuch[0:15] b_tpuch[0:15] i/o 5 v pull device enabled until prds is set 14 b_tpuch[0:15] b_t2clk b_t2clk i/o 5 v pull up enabled until t2clk_pu is set b_t2clk c_tpuch[0:15] c_tpuch[0:15] i/o 5 v pull device enabled until prds is set 14 c_tpuch[0:15] c_t2clk c_t2clk i/o 5 v pull up enabled until t2clk_pu is set c_t2clk qadc64_a / qadc64_b etrig[1:2] etrig[1:2] i 5 v pd until pull_dis0 is set etrig[1:2] an44/ anw / a_pqb0 an44 i 5 v pu_5v until prds is set an44 anw i 5 v pu_5v until prds is set a_pqb0 i 5 v pu_5v until prds is set an45/ anx/ a_pqb1 an45 i 5 v pu_5v until prds is set an45 anx i 5 v pu_5v until prds is set a_pqb1 i 5 v pu_5v until prds is set an46/ any/ a_pqb2 an46 i 5 v pu_5v until prds is set an46 any i 5 v pu_5v until prds is set a_pqb2 i 5 v pu_5v until prds is set an47/ anz/ a_pqb3 an47 i 5 v pu_5v until prds is set an47 anz i 5 v pu_5v until prds is set a_pqb3 i 5 v pu_5v until prds is set an[48:51]/ a_pqb[4:7] an[48:51] i 5 v pu_5v until prds is set an[48:51] a_pqb[4:7] i 5 v pu_5v until prds is set table 2-6. pin reset state (continued) pin function port voltage reset state function after poreset /trst or hreset 2-40 mpc565/mpc566 reference manual motorola reset state an[52:54]/ a_ma[0:2]/ pqa[0:2] an[52:54] i 5 v pu_5v until prds is set an[52:54] a_ma[0:2] i 5 v pu_5v until prds is set a_pqa[0:2] i/o 5 v pu_5v until prds is set an[55:59]/ a_pqa[3:7] an[55:59] i 5 v pu_5v until prds is set an[55:59] a_pqa[3:7] i/o 5 v pu_5v until prds is set an[64:71]/ b_pqb[0:7] an[64:71] i 5 v pu_5v until prds is set an[64:71] b_pqb[0:7] i 5 v pu_5v until prds is set an[72:74]/ b_ma[0:2]/ b_pqa[0:2] an[72:74] i 5 v pu_5v until prds is set an[72:74] b_ma[0:2] i 5 v pu_5v until prds is set b_pqa[0:2] i/o 5 v pu_5v until prds is set an[75:79]/ b_pqa[3:7] an[75:79] i 5 v pu_5v until prds is set an[75:79] b_pqa[3:7] i/o 5 v pu_5v until prds is set an[80:87] an[80:87] i 5 v none an[80:87] vrh vrh i 5 v ? vrh vrl vrl i ? ? vrl vdda vdda i 5 v ? vdda vssa vssa i ? ? vssa toucan_a / toucan_b a_cntx0 a_cntx0 o 5 v pu_5v until pull_dis2 is set a_cntx0 b_cntx0 b_cntx0 o 5 v pu_5v until pull_dis2 is set b_cntx0 a_cnrx0 a_cnrx0 i 5 v pu_5v until pull_dis2 is set a_cnrx0 b_cnrx0 b_cnrx0 i 5 v pu_5v until pull_dis2 is set b_cnrx0 uc3f epee epee i 2.6 v pu_2.6v epee b0epee b0epee i 2.6 v pu_2.6v b0epee vflash vflash i 5 v ? vflash vddf vddf i 2.6 v ? vddf vssf vssf i 2.6 v ? vssf readi mseo mseo 1 o 2.6 v pu_2.6v while rsti is asserted mseo mdo3 mdo3 1 o 2.6 v pu_2.6v while rsti is asserted mdo3 table 2-6. pin reset state (continued) pin function port voltage reset state function after poreset /trst or hreset motorola chapter 2. signal descriptions 2-41 reset state mdo2 mdo2 1 o 2.6 v pu_2.6v while rsti is asserted mdo2 mdo1 mdo1 1 o 2.6 v pu_2.6v while rsti is asserted mdo1 mdo0 mdo0 1 o 2.6 v pu_2.6v while rsti is asserted mdo0 mcko mcko 1 o 2.6 v pu_2.6v while rsti is asserted mcko rsti rsti i 2.6 v pd until pull_dis4 is set rsti evti evti i 2.6 v pu_2.6v until pull_dis4 is set evti msei msei i 2.6 v pu_2.6v until pull_dis4 is set msei mdi1 mdi1 i 2.6 v pu_2.6v until pull_dis4 is set mdi1 mdi0 mdi0 i 2.6 v pu_2.6v until pull_dis4 is set mdi0 mcki mcki i 2.6 v pu_2.6v until pull_dis4 is set mcki global power supplies qvddl qvddl i 2.6 v ? qvddl nvddl nvddl i 2.6 v ? nvddl vddh vddh i 5 v ? vddh vdd vdd i 2.6 v ? vdd vss vss i 0 v ? vss kapwr 8 kapwr i 2.6 v ? kapwr vddsram[1:3] vddsram[1:3] i 2.6 v ? vddsram[1:3] 1 2.6-v outputs cannot be connected to a pull-up or driver greater than 3.1 v. 2 during reset, the output enable to the pad driver is negated and the pd is active. after reset is negated, the pd is disabled. 3 neither a pull-up to greater than 3.1 v or an external output that can drive greater than 3.1 v should be connected to this pin while the 2.6-v driver is enabled. 4 5 v on mask set k85h. 5 requires a pull-up to 2.6 v if interrupts are ever enabled for this irq input. 6 pull-up/pull-down is active when pin is defined as an input and/or during reset; therefore, output enable is negated. this also means that external pull-up/pull-down is not required unless specified. 7 powered by kapwr (keep-alive power supply). 8 the modck[1:3] are shared functions with irq[5:7] . if irq[5:7] are used as interrupts, the interrupt source should be removed during poreset /trst to insure the modck pins are in the correct state on the rising edge of poreset /trst . 9 an active negate signal that requires an external pull-up resister. on dual-voltage, type-4 pads, hysteresis is always enabled on the 5-v input buffer. hysteresis affects only the 2.6-v input buffers on which it is enabled. 10 poreset only on mask set k85h. 11 5-v tolerant, even when in output mode. 12 trst in mask set k85h. 13 a_eck in mask set k85h. 14 whether the pull device is a pull-up or a pull-down is determined by the state of the pull_sel pin. table 2-6. pin reset state (continued) pin function port voltage reset state function after poreset /trst or hreset 2-42 mpc565/mpc566 reference manual motorola pad types 2.6 pad types pad types are based on functional characteristics (see table 2-7); however, even pads with the same functionality may differ in their electrical characteristics. all 5-v inputs have hysteresis. refer to figure 2-3. table 2-7. functional pad types type name voltage dir. delay (ns) drive strength (rise/fall) drive load (pf) weak devices hysteresis in out 1 1 output delay includes pad prop delay (out) + rise/fall time. fast; slow fast; slow pu; pd 1 pad_5vsa 5 v io 5 17 ; 400 10 ; 200 50 ; 50 selectable selectable 2 pad_5vfa 5 v io 5 17 ; 100 10 ; 40 50 ; 50 selectable selectable 16 ; 100 9 ; 40 45 ; 45 27 ; 110 18 ; 47 90 ; 90 3 pad_26v 2.6 v io 4 5 ; 5 2.9 ; 2.9 25 ; 50 selectable selectable 4 pad_26v5vs 2.6 v io 4 5 ; 5 2.9 ; 2.9 25 ; 50 pd selectable selectable 5 v io 5 17 ; 400 10 ; 200 50 ; 50 pd selectable enabled 5 pad_5vh 5 v io 5 30 ; 400 21 ; 200 200 ; 50 selectable selectable 6 pad_5vido 5 v i 5 na na na na selectable 7 pad_extclk 2.6 v i na na na na na 8 pad_e_xtal_oscpll 2.6 v io na na na ; na na ; na na na 9 pad_e_xtal_osc32 2.6 v io na na na ; na na ; na na na 10 pad_26vf 2.6 v io 4 5 ; 5 2.3 ; 2.3 25 ; 50 selectable selectable 11 pad_26vs5vr 2.6 v io 4 11 ; 11 7 ; 7 25 ; 50 pd selectable selectable 5 v io 5 12 ; 50 6 ; 25 25 ; 25 pd selectable enabled table 2-8. other pad types name voltage used for pad_vddh 5 v vddh pad_nvddl 2.6 v nvddl pad_qvddl 2.6 v qvddl pad_vddint 2.6 v vdd, vddsram[1:3], vddf, vddsyn, vddrtc motorola chapter 2. signal descriptions 2-43 electrical characteristics 2.7 electrical characteristics 2.7.1 target dc characteristics these dc characteristics are not all inclusive and do not apply to any individual pad. electrical characteristics may have other requirements. in the case of a conflict, appendix e ?electrical characteristics? gives the actual electrical characteristics of any particular signal, and table 2-9 shows general capabilities of the pads. pad_vdda 5 v vdda pad_vss vss pad_vssint vssa, vssf, vrl pad_vsssyn vsssyn, vssrtc pad_vflashvrh 5 v vflash, vrh, altref pad_kapwr 2.6 v kapwr pad_xfc 2.6 v xfc table 2-9. target dc electrical characteristics spec characteristic symbol min max unit 1 2.6-v supply voltage vddi 2.5 2.7 v 2 5-v supply voltage vddh 4.75 5.25 v 3 2.6-v input-high voltage vih_l 2.0 vddh + 0.3 v 4 5-v input-high voltage vih_h 0.7 * vddh vddh + 0.3 v 5 2.6-v input-low voltage vil_l vss - 0.3 0.8 v 6 5-v input-low voltage vil_h vss - 0.3 0.48 * vddh v 7 input hysteresis vhys 500 (target spec) mv 8 mode select/pull-up/pull-down current iact 20 130 a 9 input leakage current (pull-up/pull-down inactive) iinact ? 2.5 a 10 2.6-v output high voltage [ioh_l = -1 ma] (ioh_l = -2 ma) voh_l [2.4] [2.3] ?v 11 5-v output high voltage (ioh_h = -2 ma) voh_h vddh - 0.7 ? v 12 2.6-v output low voltage [iol_l = 3.2 ma] (iol_l =2ma) vol_l ? [0.5] [0.45] v 13 5-v output low voltage (iol_h = 2 ma) vol_h ? 0.5 v table 2-8. other pad types (continued) name voltage used for 2-44 mpc565/mpc566 reference manual motorola electrical characteristics 2.7.2 pad measurement criteria pad rise/fall times are measured between vol and voh of the output driver. (for 2.6-v drivers, lowest minimum voh is used.) pad propagation delays for outputs are measured at vdd/2 for internal signals to vol or voh at pin load. propagation delays for inputs are measured from vil for a falling input or vih for a rising input at the pin, to vdd/2 at internal signal load. rise/fall times for the input signal at the internal signal load are measured from 10% to 90% of vdd. the rise/fall time for the input signal at the pad shall be 2 ns for the full swing from vss to vdd. all inputs except the oscillator are 5-v friendly. minimum-input buffer hysteresis is 500 mv. weak pull-up current is measured at vil and weak pull-down current is measured at vih. 2.7.2.1 input buffer 1. voltages received above vih minimum guarantee a logical ?1? response. 2. voltages received below vil maximum guarantee a logical ?0? response. 3. received voltages that fall between the two thresholds may be interpreted by the input buffer as a ?1?, as a ?0?, or as an indeterminate state. figure 2-3 and figure 2-4 illustrate input propagation delay and levels. figure 2-3. input propagation delay pad input buffer pad pad di input propagation delay measured from pad to di_line. motorola chapter 2. signal descriptions 2-45 electrical characteristics figure 2-4. input levels 2.7.2.2 output driver figure 2-5 and figure 2-6 illustrate output propagation delay and levels. 1 package parasitic resistance and inductance have been added to simulation delay path. figure 2-5. output propagation delay vih limits guaranteed 1 guaranteed 0 vil (max) vil (min) pin input vih (max) vih (min.) within vih spec within vil spec buffer output (non-inverting) vil limits cout pad do pad 2-46 mpc565/mpc566 reference manual motorola electrical characteristics figure 2-6. output levels and timing do output delay tota l 0.5 pad rising tota l output delay falling voh vol motorola chapter 2. signal descriptions 2-47 electrical characteristics table 2-10. pin names and ball assignments pin list pin name ball pad type data[0:31]/sgpiod[0:31] data_sgpiod0 af3 26v5vs data_sgpiod1 ae4 26v5vs data_sgpiod2 af4 26v5vs data_sgpiod3 ae5 26v5vs data_sgpiod4 af5 26v5vs data_sgpiod5 ae6 26v5vs data_sgpiod6 af6 26v5vs data_sgpiod7 ae7 26v5vs data_sgpiod8 af7 26v5vs data_sgpiod9 ae8 26v5vs data_sgpiod10 af8 26v5vs data_sgpiod11 ae9 26v5vs data_sgpiod12 af9 26v5vs data_sgpiod13 ae10 26v5vs data_sgpiod14 af10 26v5vs data_sgpiod15 ae11 26v5vs data_sgpiod16 af11 26v5vs data_sgpiod17 ae12 26v5vs data_sgpiod18 af12 26v5vs data_sgpiod19 ad13 26v5vs data_sgpiod20 ac12 26v5vs data_sgpiod21 ad12 26v5vs data_sgpiod22 ac11 26v5vs data_sgpiod23 ad11 26v5vs data_sgpiod24 ac10 26v5vs data_sgpiod25 ad10 26v5vs data_sgpiod26 ad9 26v5vs data_sgpiod27 ac8 26v5vs data_sgpiod28 ad8 26v5vs data_sgpiod29 ac7 26v5vs data_sgpiod30 ad7 26v5vs data_sgpiod31 ad6 26v5vs 2-48 mpc565/mpc566 reference manual motorola electrical characteristics addr[8:31]/sgpioa[8:31] addr_sgpioa8 u3 26v5vs addr_sgpioa9 v3 26v5vs addr_sgpioa10 v4 26v5vs addr_sgpioa11 w3 26v5vs addr_sgpioa12 w4 26v5vs addr_sgpioa13 y3 26v5vs addr_sgpioa14 y4 26v5vs addr_sgpioa15 aa3 26v5vs addr_sgpioa16 u1 26v5vs addr_sgpioa17 u2 26v5vs addr_sgpioa18 v1 26v5vs addr_sgpioa19 v2 26v5vs addr_sgpioa20 w1 26v5vs addr_sgpioa21 w2 26v5vs addr_sgpioa22 y1 26v5vs addr_sgpioa23 y2 26v5vs addr_sgpioa24 aa1 26v5vs addr_sgpioa25 aa2 26v5vs addr_sgpioa26 ab1 26v5vs addr_sgpioa27 ab2 26v5vs addr_sgpioa28 ac1 26v5vs addr_sgpioa29 ad1 26v5vs addr_sgpioa30 aa4 26v5vs addr_sgpioa31 ab3 26v5vs irq0 /sgpioc0 irq0_b_sgpioc0 af16 26v irq1 /rsv / sgpioc1 irq1_b_rsv_b_sgpioc1 af13 26v5vs irq2 ]/ cr / sgpioc2 / mts irq2_b_cr_b_sgpio2_mts ad16 26v5vs irq3 /kr ,retry / sgpioc3 irq3_b_kr_b_retry_b_sgpioc3 ae13 26v5vs irq4 /at2 / sgpioc4 irq4_b_at2_sgpioc4 ad14 26v5vs irq5 / sgpioc5 / modck1 irq5_b_sgpioc5_modck1 ad25 26v5vs irq [6:7] / modck[2:3] irq6_b_modck2 ab24 26v irq7_b_modck3 ac25 26v table 2-10. pin names and ball assignments (continued) pin list pin name ball pad type motorola chapter 2. signal descriptions 2-49 electrical characteristics tsiz[0:1] tsiz0 ad19 26v tsiz1 af19 26v rd/wr rd_wr_b ae15 26v burst burst_b ae19 26v bdip bdip_b ae21 26v ts ts_b ae20 26v ta ta_b af20 26v tea tea_b ad15 26v rstconf / texp rstconf_b_texp ab25 26v oe oe_b ae16 26v bi /sts bi_b_sts_b ac19 26v cs[0:3] cs0_b ae18 26v cs1_b ad18 26v cs2_b af18 26v cs3_b ac18 26v we [0:3] / be [0:3] / at[0:3] we0_b_be0_b_at0 ae17 26v we1_b_be1_b_at1 ac16 26v we2_b_be2_b_at2 ad17 26v we3_b_be3_b_at3 af17 26v porese t/trst 1 poreset_b_trst_b aa23 26v hreset hreset_b ab23 26v (rev0); 5vsa (reva) sreset sreset_b ac24 26v (rev0); 5vsa (reva) sgpioc6 / frz / ptr sgpioc6_frz_ptr_b t4 26v5vs sgpioc7 / irqout / lwp0 sgpioc7_irqout_b_lwp0 ac14 26v5vs bg /vf0 / lwp1 bg_b_vf0_lwp1 af14 26v br /vf1 / iwp2 br_b_vf1_iwp2 af15 26v bb /vf2 / iwp3 bb_b_vf2_iwp3 ae14 26v iwp[0:1] / vfls[0:1] iwp0_vfls0 t3 26v iwp1_vfls1 r4 26v tms tms n1 26v tdi/dsdi tdi_dsdi m1 26v tck/dsck tck_dsck l2 26v table 2-10. pin names and ball assignments (continued) pin list pin name ball pad type 2-50 mpc565/mpc566 reference manual motorola electrical characteristics tdo/dsdo tdo_dsdo r2 26v jcomp 2 jcomp_b p2 26v xtal xtal aa26 extal_oscpll extal extal ab26 extal_oscpll xfc xfc ad26 xfc clkout clkout ad21 26vf extclk extclk y24 extclk vddsyn vddsyn ae26 vddint vsssyn vsssyn ac26 vsssyn engclk / buclk engclk_buclk af22 26v5vsr pull_sel 3 pullsel w26 5vfa qsmcm_a a_pcs0 / ss / qgpio0 a_pcs0_ss_b_qgpio0 v23 5vfa a_pcs[1:3] / qgpio[1:3] a_pcs1_qgpio1 w25 5vfa a_pcs2_qgpio2 u23 5vfa a_pcs3_qgpio3 u26 5vfa a_miso / qgpio4 a_miso_qgpio4 t24 5vh a_mosi / qgpio5 a_mosi_qgpio5 u25 5vh a_sck / qgpio6 a_sck_qgpio6 t26 5vh a_txd[1:2] / qgpo[1:2] a_txd1_qgpo1 t23 5vsa a_txd2_qgpo2 v24 5vsa a_rxd[1:2] / qgpi[1:2] a_rxd1_qgpi1 u24 5vido a_rxd2_qgpi2 v25 5vido b_pcs0 / ss / qgpio0 b_pcs0_ss_b_qgpio0 n25 5vfa b_pcs[1:2] / qgpio[1:2] b_pcs1_qgpio1 n26 5vfa b_pcs2_qgpio2 r24 5vfa b_pcs3 / j1850_tx b_pcs3_j1850_tx p25 5vfa b_miso / qgpio4 b_miso_qgpio4 p24 5vh b_mosi / qgpio5 b_mosi_qgpio5 p26 5vh b_sck / qgpio6 b_sck_qgpio6 r23 5vh b_txd[1:2] / qgpo[1:2] b_txd1_qgpo1 r25 5vsa b_txd2_qgpo2 r26 5vsa b_rxd1 / qgpi1 b_rxd1_qgpi1 v26 5vido table 2-10. pin names and ball assignments (continued) pin list pin name ball pad type motorola chapter 2. signal descriptions 2-51 electrical characteristics b_rxd2 / j1850_rx b_rxd2_j1850_rx t25 5vsa b_eck b_eck p23 5vsa mios14 / toucan_c mda[11:15], mda[27:31] mda11 f25 5vsa mda12 g23 5vsa mda13 f26 5vsa mda14 k24 5vsa mda15 k23 5vsa mda27 g24 5vsa mda28 g25 5vsa mda29 g26 5vsa mda30 h23 5vsa mda31 h24 5vsa mpwm[0:3], [16:19] mpwm0 h25 5vsa mpwm1 h26 5vsa mpwm2 j24 5vsa mpwm3 j23 5vsa mpwm16 j25 5vsa mpwm17 e26 5vsa mpwm18 f24 5vsa mpwm19 l25 5vsa vf[0:2] / mpio32b[0:2] vf0_mpio32b0 l26 26v5vs vf1_mpio32b1 m23 26v5vs vf2_mpio32b2 m24 26v5vs vfls[0:1] / mpio32b[3:4] vfls0_mpio32b3 m26 26v5vs vfls1_mpio32b4 n24 26v5vs mpwm[4:5] / mpio32b[5:6] mpwm4_mpio32b5 m25 5vsa mpwm5_mpio32b6 f23 5vsa mdo[7:4] / mpio32b[7:10] mdo7_mpio32b7 p1 26v5vs mdo6_mpio32b8 n3 26v5vs mdo5_mpio32b9 n4 26v5vs mdo4_mpio32b10 n2 26v5vs table 2-10. pin names and ball assignments (continued) pin list pin name ball pad type 2-52 mpc565/mpc566 reference manual motorola electrical characteristics mpwm[20:21] / mpio32b[11:12] mpwm20_mpio32b11 j26 5vsa mpwm21_mpio32b12 k25 5vsa c_cntx0 / mpio32b13 c_cntx0_mpio32b13 k26 5vfa c_cnrx0 / mpio32b14 c_cnrx0_mpio32b14 l23 5vsa mpio32b15 mpio32b15 l24 5vsa extal32 extal32 d1 26v xtal32 xtal32 e1 26v vddrtc vddrtc c1 vddint vssrtc vssrtc f1 vsssyn tpu3_a / tpu3_b / tpu3_c a_tpuch[0:15] a_tpuch0 d20 5vsa a_tpuch1 a21 5vsa a_tpuch2 a16 5vsa a_tpuch3 d17 5vsa a_tpuch4 a17 5vsa a_tpuch5 b17 5vsa a_tpuch6 a18 5vsa a_tpuch7 d18 5vsa a_tpuch8 b18 5vsa a_tpuch9 c18 5vsa a_tpuch10 a19 5vsa a_tpuch11 b19 5vsa a_tpuch12 c19 5vsa a_tpuch13 d19 5vsa a_tpuch14 a20 5vsa a_tpuch15 c20 5vsa a_t2clk a_t2clk b20 5vsa table 2-10. pin names and ball assignments (continued) pin list pin name ball pad type motorola chapter 2. signal descriptions 2-53 electrical characteristics b_tpuch[0:15] b_tpuch0 d26 5vsa b_tpuch1 e24 5vsa b_tpuch2 d25 5vsa b_tpuch3 b21 5vsa b_tpuch4 c21 5vsa b_tpuch5 a22 5vsa b_tpuch6 b22 5vsa b_tpuch7 b23 5vsa b_tpuch8 c23 5vsa b_tpuch9 d21 5vsa b_tpuch10 a23 5vsa b_tpuch11 c22 5vsa b_tpuch12 a24 5vsa b_tpuch13 b24 5vsa b_tpuch14 a25 5vsa b_tpuch15 c26 5vsa b_t2clk b_t2clk e25 5vsa c_tpuch[0:15] c_tpuch0 k3 5vsa c_tpuch1 k2 5vsa c_tpuch2 k1 5vsa c_tpuch3 j3 5vsa c_tpuch4 k4 5vsa c_tpuch5 j2 5vsa c_tpuch6 j1 5vsa c_tpuch7 h2 5vsa c_tpuch8 h3 5vsa c_tpuch9 h1 5vsa c_tpuch10 g1 5vsa c_tpuch11 g2 5vsa c_tpuch12 g3 5vsa c_tpuch13 j4 5vsa c_tpuch14 f2 5vsa c_tpuch15 f3 5vsa table 2-10. pin names and ball assignments (continued) pin list pin name ball pad type 2-54 mpc565/mpc566 reference manual motorola electrical characteristics c_t2clk c_t2clk h4 5vsa qadc64_a / qadc64_b etrig[1:2] etrig1 c16 5vsa etrig2 b16 5vsa an44] / anw / a_pqb0 an44_anw_a_pqb0 b3 5vsa an45 / anx / a_pqb1 an45_anx_a_pqb1 c4 5vsa an46 / any / a_pqb2 an46_any_a_pqb2 c7 5vsa an47 / anz / a_pqb3 an47_anz_a_pqb3 d8 5vsa an[48:51] / a_pqb[4:7] an48_a_pqb4 a7 5vsa an49_a_pqb5 b7 5vsa an50_a_pqb6 c8 5vsa an51_a_pqb7 d9 5vsa an[52:54] / a_ma[0:2] / pqa[0:2] an52_a_ma0_pqa0 b8 5vsa an53_a_ma1_pqa1 a8 5vsa an54_a_ma2_pqa2 c9 5vsa an[55:59] / a_pqa[3:7] an55_a_pqa3 d10 5vsa an56_a_pqa4 b9 5vsa an57_a_pqa5 c10 5vsa an58_a_pqa6 b10 5vsa an59_a_pqa7 d11 5vsa an[64:71] / b_pqb[0:7] an64_b_pqb0 a2 5vsa an65_b_pqb1 a14 5vsa an66_b_pqb2 b14 5vsa an67_b_pqb3 a13 5vsa an68_b_pqb4 d14 5vsa an69_b_pqb5 b13 5vsa an70_b_pqb6 c14 5vsa an71_b_pqb7 c13 5vsa an[72:74] / b_ma[0:2] / pqa[0:2] an72_b_ma0_pqa0 a12 5vsa an73_b_ma1_pqa1 b12 5vsa an74_b_ma2_pqa2 d13 5vsa table 2-10. pin names and ball assignments (continued) pin list pin name ball pad type motorola chapter 2. signal descriptions 2-55 electrical characteristics an[75:79] / b_pqa[3:7] an75_b_pqa3 c12 5vsa an76_b_pqa4 a11 5vsa an77_b_pqa5 b11 5vsa an78_b_pqa6 d12 5vsa an79_b_pqa7 c11 5vsa an[80:87] an80 a6 5vsa an81 b6 5vsa an82 d7 5vsa an83 c6 5vsa an84 a5 5vsa an85 b5 5vsa an86 d6 5vsa an87 c5 5vsa vrh vrh a3 vflashvrh vrl vrl a4 vssint altref altref b4 vflashvrh vdda vdda a9 vdda vssa vssa a10 vssint toucan_a / toucan_b a_cntx0 a_cntx0 y25 5vfa b_cntx0 b_cntx0 e2 5vfa a_cnrx0 a_cnrx0 aa24 5vsa b_cnrx0 b_cnrx0 c17 5vsa uc3f epee epee af21 26v b0epee b0epee ad20 26v vflash vflash w24 vflashvrh vddf vddf y23 vddint vssf vssf aa25 vssint table 2-10. pin names and ball assignments (continued) pin list pin name ball pad type 2-56 mpc565/mpc566 reference manual motorola electrical characteristics readi mseo mseo_b t2 26v mdo3 mdo_3 t1 26v mdo2 mdo_2 r3 26v mdo1 mdo_1 r1 26v mdo0 mdo_0 p4 26v mcko mcko p3 26v rsti rsti_b m3 26v evti evti_b m2 26v msei msei_b m4 26v mdi1 mdi_1 l3 26v mdi0 mdi_0 l1 26v mcki mcki l4 26v global power supplies nvddl nvddl f4, u4, ac9, ac13, d22, w23, ac15, ac17 nvddl qvddl qvddl ab4, ac3, ad2, ae1, a15, b15, c15, d15, ac23, ae25, af26, ad24 qvddl vddh vddh ac6, d16, n23, ac20, d5 vddh kapwr kapwr y26 kapwr vddsram1 vddsram1 e3 vddint vddsram2 vddsram2 d2 vddint vddsram3 vddsram3 g4 vddint vdd vdd d24, e23, ac21, ad22, ae23, af24, a1, b2, b26, c25, c3, d4, ac5, ad4, ae3, af2 vddint table 2-10. pin names and ball assignments (continued) pin list pin name ball pad type motorola chapter 2. signal descriptions 2-57 package description 2.8 package description 2.8.1 package diagrams the package for the mpc565/mpc566 is the 352/388 pbga (27 x 27 mm, 1.0 mm ball pitch). it has a total of 388 balls: 36 ground and 352 in the four perimeter rows. the ball footprint is shown in figure 2-7. vss vss a26, b25, ac22, d23, b1, n14, n15, n16, d3, m14, m15, m16, c2, e4, l14, l15, l16, p14, p15, p16, ad23, ae24, af25, l11, l12, l13, m11, m12, m13, n11, n12, n13, p11, p12, p13, r11, r12, r13, t11, t12, t13, ac4, ad3, ae2, af1, r14, r15, r16, t14, t15, t16, c24 vss nc no_connect ae22, af23, ac2, ad5 1 poreset only on mask set k85h. 2 trst in mask set k85h. 3 a_eck in mask set k85h. table 2-10. pin names and ball assignments (continued) pin list pin name ball pad type 2-58 mpc565/mpc566 reference manual motorola package description 1 note: top down view figure 2-7. mpc565/mpc566 package footprint (1 of 2) motorola chapter 2. signal descriptions 2-59 package description figure 2-8. figure 2-5 mpc565/mpc566 package footprint (2 of 2) 2-60 mpc565/mpc566 reference manual motorola package description 2.8.2 bumped die the mpc565/mpc566 is available as known good die (kgd) in a bumped die configuration. the bump pitch is 7 mils and the bump configuration is shown in figure 2-9. figure 2-10 and figure 2-11 show the categories of function pins. figure 2-12 through figure 2-15 show the pins in a larger diagram in black and white. figure 2-9. mpc565/mpc566 redistributed bump map 7miltracepitch vss vssrtc extal32 xtal32 vddrtc vddsram1 vddsram2 vddsram3 b_cntx0 c_t2clk c_tpuch15 c_tpuch14 c_tpuch13 c_tpuch12 c_tpuch11 c_tpuch10 c_tpuch9 c_tpuch8 c_tpuch7 c_tpuch6 c_tpuch5 c_tpuch4 c_tpuch3 c_tpuch2 c_tpuch1 c_tpuch0 mcki mdi_0 tck_dsck mdi_1 msei_b tdi_dsdi evti_b rsti_b tms mdo_4_mpio32b10 mdo_5_mpio32b9 mdo_6_mpio32b8 mdo_7_mpio32b7 nvddl vss jcomp mcko mdo_0 mdo_1 tdo_dsdo mdo_2 mdo_3 mseo_b nvddl vss iwp0_vfls0 iwp1_vfls1 addr_sgpioa16 addr_sgpioa17 sgpioc6_frx_ptr_b addr_sgpioa8 addr_sgpioa18 nvddl vss addr_sgpioa19 addr_sgpioa9 addr_sgpioa10 addr_sgpioa20 addr_sgpioa21 addr_sgpioa11 addr_sgpioa12 addr_sgpioa22 nvddl vss addr_sgpioa23 addr_sgpioa13 addr_sgpioa24 addr_sgpioa25 addr_sgpioa14 addr_sgpioa15 addr_sgpioa30 addr_sgpioa26 nvddl vss addr_sgpioa27 addr_sgpioa31 addr_sgpioa28 addr_sgpioa29 qvddl vss qvddl vss qvddl vdd vdd vddh data_sgpioa0 data_sgpioa29 data_sgpioa1 data_sgpioa2 nvddl vss data_sgpioa3 data_sgpioa27 data_sgpioa4 data_sgpioa28 data_sgpioa31 data_sgpioa5 nvddl vss data_sgpioa6 data_sgpioa30 data_sgpioa7 data_sgpioa25 data_sgpioa8 data_sgpioa24 data_sgpioa9 data_sgpioa10 nvddl vss data_sgpioa26 data_sgpioa22 data_sgpioa11 data_sgpioa12 data_sgpioa13 data_sgpioa20 data_sgpioa14 data_sgpioa23 nvddl vss data_sgpioa15 data_sgpioa16 data_sgpioa21 data_sgpioa17 nvddl vss data_sgpioa18 data_sgpioa19 irq3_b_kr_b_retry_b_sgpioc3 irq4_b_at2_sgpioc4 irq1_b_rsv_b_sgpioc1 sgpioc7_irqout_b_lwp0 bb_b_vf2_iwp3 bg_b_vf0_lwp1 nvddl vss br_b_vf1_iwp2 rd_wr_b oe_b tea_b irq2_b_cr_b_sgpioc2 irq0_b_sgpioc0 we_b_at0 we_b_at1 we_b_at2 we_b_at3 vss nvddl cs0_b cs1_b cs2_b cs3_b burst_b bi_b_sts_b tsizo tsiz1 nvddl vss ts_b ta_b bdip_b b0epee epee nvddl vdd2 clkout vss engclk_buclk vddh5 vdd2 qvddl qvddl vss qvddl irq5_b_sgpioc5_modck1 irq6_b_modck2 irq7_b_modck3 hreset_b rstconf_b_texp sreset_b poreset_b_trst_b vss extclk vss vddsyn xfc vsssyn extal xtal kapwr nvddl vddf a_cnrxo vssf a_cntxo vflash a_pcs0_ss_b_qgpio0 pullsel a_pcs1_qgpio1 a_txd2_qgpo2 a_pcs2_qgpio2 a_rxd2_qpi2 b_rxd1_qgp01 a_rxd1_qpi1 a_mosi_qgpio5 a_pcs3_qgpio3 a_miso_qgpio4 a_sck_qgpio6 b_pcs2_qgpio2 b_rxd2_j1850_rx a_txd1_qgpo1 b_txd2_qgpo2 b_txd1_qgp01 b_eck b_sck_qgpio6 b_mosi_qgpio5 b_miso_qgpio4 b_pcs3_j1850_tx b_pcs1_qgpio1 b_pcs0_ss_b_qgpio0 vfls1_mpio32b4 vddh1 vfls0_mpio32b3 vf2_mpio32b2 vss nvddl vf1_mpio32b1 vf0_mpio32b0 mpwm4_mpio32b5 mpwm19 32kclkout_mpio32b15 c_cnrx0_mpio32b14 c_cntx0_mpio32b13 mpwm21_mpio32b12 mpwm20_mpio32b11 mda15 mda14 mpwm16 mpwm3 mpwm2 mpwm1 mpwm0 mda31 mda30 mda29 mda28 mda27 mda13 mda12 mda11 mpwm18 mpwm17 b_t2clk b_tpuch1 b_tpuch0 mpwm5_mpio32b6 vss vdd3 vdd3 vss vss b_tpuch2 b_tpuch15 b_tpuch14 b_tpuch13 b_tpuch12 b_tpuch11 b_tpuch10 b_tpuch9 b_tpuch8 b_tpuch7 b_tpuch6 b_tpuch5 b_tpuch4 b_tpuch3 a_tpuch1 a_tpuch0 a_t2clk a_tpuch15 a_tpuch14 a_tpuch13 a_tpuch12 a_tpuch11 a_tpuch10 a_tpuch9 a_tpuch8 a_tpuch7 a_tpuch6 a_tpuch5 a_tpuch4 a_tpuch3 a_tpuch2 etrig1 etrig2 qvddl vss qvddl vddh2 b_an59_pqa7 b_an58_pqa6 b_an57_pqa5 b_an56_pqa4 b_an55_pqa3 b_an54_ma2_pqa2 b_an53_ma1_pqa1 b_an52_ma0_pqa0 b_an51_pqb7 b_an50_pqb6 b_an49_pqb5 b_an48_pqb4 b_an3_anz_pqb3 b_an2_any_pqb2 b_an1_anx_pqb1 b_an0_anw_pqb0 vssa vdda a_an59_pqa7 a_an58_pqa6 a_an57_pqa5 a_an56_pqa4 a_an55_pqa3 a_an54_ma2_pqa2 a_an53_ma1_pqa1 a_an52_ma0_pqa0 a_an51_pqb7 a_an50_pqb6 a_an49_pqb5 a_an48_pqb4 a_an3_anz_pqb3 a_an2_any_pqb2 amux_0 amux_1 amux_2 amux_3 amux_4 amux_5 amux_6 amux_7 vrl altref vrh a_an1_anx_pqb1 a_an0_anw_pqb0 nvddl vss b_cnrx0 vddh3 vdd4 motorola chapter 2. signal descriptions 2-61 package description 2.8.3 mpc565/mpc566 ball diagram the ball diagram of the mpc565/mpc566 is shown in figure 2-10. figure 2-10. mpc565/mpc566 ball diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a vdd an64_b_pqb0 vrh vrl an84 an80 an48_a_pqb4 an53_a_ma1_p qa1 vdda vssa an76_b_pqa4 an72_b_ma0_p qa0 an67_b_pqb3 an65_b_pqb1 qvddl a_tpuch2 a_tpuch4 a_tpuch6 a_tpuch10 a_tpuch14 a_tpuch1 b_tpuch5 b_tpuch10 b_tpuch12 b_tpuch14 vss a b vss vdd an44_anw_a_p qb0 altref an85 an81 an49_a_pqb5 an52_a_ma0_p qa0 an56_a_pqa4 an58_a_pqa6 an77_b_pqa5 an73_b_ma1_p qa1 an69_b_pqb5 an66_b_pqb2 qvddl etrig2 a_tpuch5 a_tpuch8 a_tpuch11 a_t2clk b_tpuch3 b_tpuch6 b_tpuch7 b_tpuch13 vss vdd b c vddrtc vss vdd an45_anx_a_p qb1 an87 an83 an46_any_a_p qb2 an50_a_pqb6 an54_a_ma2_p qa2 an57_a_pqa5 an79_b_pqa7 an75_b_pqa3 an71_b_pqb7 an70_b_pqb6 qvddl etrig1 b_cnrx0 a_tpuch9 a_tpuch12 a_tpuch15 b_tpuch4 b_tpuch11 b_tpuch8 vss vdd b_tpuch15 c d extal32 vddsram2 vss vdd vddh an86 an82 an47_anz_a_p qb3 an51_a_pqb7 an55_a_pqa3 an59_a_pqa7 an78_b_pqa6 an74_b_ma2_p qa2 an68_b_pqb4 qvddl vddh a_tpuch3 a_tpuch7 a_tpuch13 a_tpuch0 b_tpuch9 nvddl vss vdd b_tpuch2 b_tpuch0 d e xtal32 b_cntx0 vddsram1 vss vdd b_tpuch1 b_t2clk mpwm17 e f vssrtc c_tpuch14 c_tpuch15 nvddl mpwm5_mpio3 2b6 mpwm18 mda11 mda13 f g c_tpuch10 c_tpuch11 c_tpuch12 vddsram3 mda12 mda27 mda28 mda29 g h c_tpuch9 c_tpuch7 c_tpuch8 c_t2clk mda30 mda31 mpwm0 mpwm1 h j c_tpuch6 c_tpuch5 c_tpuch3 c_tpuch13 mpwm3 mpwm2 mpwm16 mpwm20_mpio 32b11 j k c_tpuch2 c_tpuch1 c_tpuch0 c_tpuch4 mda15 mda14 mpwm21_mpio 32b12 c_cntx0_mpio 32b13 k l mdi_0 tck_dsck mdi_1 mcki vss vss vss vss vss vss c_cnrx0_mpio 32b14 mpio32b15 mpwm19 vf0_mpio32b0 l m tdi_dsdi evti_b rsti_b msei_b vss vss vss vss vss vss vf1_mpio32b1 vf2_mpio32b2 mpwm4_mpio3 2b5 vfls0_mpio32b 3 m n tms mdo_4_mpio32 b10 mdo_6_mpio32 b8 mdo_5_mpio32 b9 vss vss vss vss vss vss vddh vfls1_mpio32b 4 b_pcs0_ss_b_ qgpio0 b_pcs1_qgpio 1 n p mdo_7_mpio32 b7 jcomp mcko mdo_0 vss vss vss vss vss vss b_eck b_miso_qgpio 4 b_pcs3_j1850_ tx b_mosi_qgpio 5 p r mdo_1 tdo_dsdo mdo_2 iwp1_vfls1 vss vss vss vss vss vss b_sck_qgpio6 b_pcs2_qgpio 2 b_txd1_qgpo1 b_txd2_qgpo2 r t mdo_3 mseo_b iwp0_vfls0 sgpioc6_frz_ ptr_b vss vss vss vss vss vss a_txd1_qgpo1 a_miso_qgpio 4 b_rxd2_j1850_ rx a_sck_qgpio6( c3f_clk) t u addr_sgpioa1 6 addr_sgpioa1 7 addr_sgpioa8 nvddl a_pcs2_qgpio 2 a_rxd1_qpi1(c 3f_sup1) a_mosi_qgpio 5 a_pcs3_qgpio 3(c3f_iout) u v addr_sgpioa1 8 addr_sgpioa1 9 addr_sgpioa9 addr_sgpioa1 0 a_pcs0_ss_b_ qgpio0 a_txd2_qgpo2 a_rxd2_qpi2(c 3f_sup2) b_rxd1_qgpi1 v w addr_sgpioa2 0 addr_sgpioa2 1 addr_sgpioa1 1 addr_sgpioa1 2 nvddl vflash a_pcs1_qgpio 1 pullsel w y addr_sgpioa2 2 addr_sgpioa2 3 addr_sgpioa1 3 addr_sgpioa1 4 vddf extclk a_cntxo kapwr y aa addr_sgpioa2 4 addr_sgpioa2 5 addr_sgpioa1 5 addr_sgpioa3 0 poreset_b a_cnrxo vssf xtal aa ab addr_sgpioa2 6 addr_sgpioa2 7 addr_sgpioa3 1 qvddl hreset_b irq6_b_modck 2 rstconf_b_te xp extal ab ac addr_sgpioa2 8 nc qvddl vss vdd vddh data_sgpiod2 9 data_sgpiod2 7 nvddl data_sgpiod2 4 data_sgpiod2 2 data_sgpiod2 0 nvddl sgpioc7_irqo ut_b_lwp0 nvddl we_b_at1 nvddl cs3_b bi_b_sts_b vddh vdd vss qvddl sreset_b irq7_b_modck 3 vsssyn ac ad addr_sgpioa2 9 qvddl vss vdd nc data_sgpiod3 1 data_sgpiod3 0 data_sgpiod2 8 data_sgpiod2 6 data_sgpiod2 5 data_sgpiod2 3 data_sgpiod2 1 data_sgpiod1 9 irq4_b_at2_sg pioc4 tea_b irq2_b_cr_b_s gpioc2 we_b_at2 cs1_b tsiz0 b0epee clkout vdd vss qvddl irq5_b_sgpioc 5_modck1 xfc ad ae qvddl vss vdd data_sgpiod1 data_sgpiod3 data_sgpiod5 data_sgpiod7 data_sgpiod9 data_sgpiod1 1 data_sgpiod1 3 data_sgpiod1 5 data_sgpiod1 7 irq3_b_kr_b_r etry_b_sgpio c3 bb_b_vf2_iwp3 rd_wr_b oe_b we_b_at0 cs0_b burst_b ts_b bdip_b nc vdd vss qvddl vddsyn ae af vss vdd data_sgpiod0 data_sgpiod2 data_sgpiod4 data_sgpiod6 data_sgpiod8 data_sgpiod1 0 data_sgpiod1 2 data_sgpiod1 4 data_sgpiod1 6 data_sgpiod1 8 irq1_b_rsv_b_ sgpioc1 bg_b_vf0_lwp 1 br_b_vf1_iwp2 irq0_b_sgpioc 0 we_b_at3 cs2_b tsiz1 ta_b epee engclk_buclk nc vdd vss qvddl af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 _trst_b note: this is a top down view of the balls. 2-62 mpc565/mpc566 reference manual motorola package description figure 2-11. mpc565/mpc566 ball diagram legend group name color code address bus bus control chip select clock/pll data bus debug flash interrupts jtag mios nc nvddl nvss qadc a qadc b qsm a qsm b qvddl readi readi reset sram toucan a toucan b tpu3 a tpu3 b tpu3 c vdd vddh vss write enable motorola chapter 2. signal descriptions 2-63 package description figure 2-12. mpc565/mpc566 ball map (black and white, page 1) 12345678910111213 a vdd an64_b_pqb0 vrh vrl an84 an80 an48_a_pqb4 an53_a_ma1_pq a1 vdda vssa an76_b_pqa4 an72_b_ma0_pq a0 an67_b_pqb3 b vss vdd an44_anw_a_p qb0 altref an85 an81 an49_a_pqb5 an52_a_ma0_pq a0 an56_a_pqa4 an58_a_pqa6 an77_b_pqa5 an73_b_ma1_pq a1 an69_b_pqb5 c vddrtc vss vdd an45_anx_a_pq b1 an87 an83 an46_any_a_pq b2 an50_a_pqb6 an54_a_ma2_pq a2 an57_a_pqa5 an79_b_pqa7 an75_b_pqa3 an71_b_pqb7 d extal32 vddsram2 vss vdd vddh an86 an82 an47_anz_a_pq b3 an51_a_pqb7 an55_a_pqa3 an59_a_pqa7 an78_b_pqa6 an74_b_ma2_pq a2 e xtal32 b_cntx0 vddsram1 vss f vssrtc c_tpuch14 c_tpuch15 nvddl g c_tpuch10 c_tpuch11 c_tpuch12 vddsram3 h c_tpuch9 c_tpuch7 c_tpuch8 c_t2clk j c_tpuch6 c_tpuch5 c_tpuch3 c_tpuch13 k c_tpuch2 c_tpuch1 c_tpuch0 c_tpuch4 l mdi_0 tck_dsck mdi_1 mcki vss vss vss m tdi_dsdi evti_b rsti_b msei_b vss vss vss n tms mdo_4_mpio32b 10 mdo_6_mpio32b 8 mdo_5_mpio32b 9 vss vss vss note: this pinout is a top down view of the package. 2-64 mpc565/mpc566 reference manual motorola package description figure 2-13. mpc565/mpc566 ball map (black and white, page 2) p mdo_7_mpio32b 7 jcomp mcko mdo_0 vss vss vss r mdo_1 tdo_dsdo mdo_2 iwp1_vfls1 vss vss vss t mdo_3 mseo_b iwp0_vfls0 sgpioc6_frz_p tr_b vss vss vss u addr_sgpioa16 addr_sgpioa17 addr_sgpioa8 nvddl v addr_sgpioa18 addr_sgpioa19 addr_sgpioa9 addr_sgpioa10 w addr_sgpioa20 addr_sgpioa21 addr_sgpioa11 addr_sgpioa12 y addr_sgpioa22 addr_sgpioa23 addr_sgpioa13 addr_sgpioa14 aa addr_sgpioa24 addr_sgpioa25 addr_sgpioa15 addr_sgpioa30 ab addr_sgpioa26 addr_sgpioa27 addr_sgpioa31 qvddl ac addr_sgpioa28 nc qvddl vss vdd vddh data_sgpiod29 data_sgpiod27 nvddl data_sgpiod24 data_sgpiod22 data_sgpiod20 nvddl ad addr_sgpioa29 qvddl vss vdd nc data_sgpiod31 data_sgpiod30 data_sgpiod28 data_sgpiod26 data_sgpiod25 data_sgpiod23 data_sgpiod21 data_sgpio d19 ae qvddl vss vdd data_sgpiod1 data_sgpiod3 data_sgpiod5 data_sgpiod7 data_sgpiod9 data_sgpiod11 data_sgpiod13 data_sgpiod15 data_sgpiod17 irq3_b_kr_b_r etry_b_sgpioc 3 af vss vdd data_sgpiod0 data_sgpiod2 data_sgpiod4 data_sgpiod6 data_sgpiod8 data_sgpiod10 data_sgpiod12 data_sgpiod14 data_sgpiod16 data_sgpi od18 irq1_b_rsv_b_ sgpioc1 123456789101112 13 note: this pinout is a top down view of the package. motorola chapter 2. signal descriptions 2-65 package description figure 2-14. mpc565/mpc566 ball map (black and white, page 3) 14 15 16 17 18 19 20 21 22 23 24 25 26 an65_b_pqb1 qvddl a_tpuch2 a_tpuch4 a_tpuch6 a_tpuch10 a_tpuch14 a_tpuch1 b_tpuch5 b_tpuch10 b_tpuch12 b_tpuch14 vss a an66_b_pqb2 qvddl etrig2 a_tpuch5 a_tpuch8 a_tpuch11 a_t2clk b_tpuch3 b_tpuch6 b_tpuch7 b_tpuch13 vss vdd b an70_b_pqb6 qvddl etrig1 b_cnrx0 a_tpuch9 a_tpuch12 a_tpuch15 b_tpuch4 b_tpuch11 b_tpuch8 vss vdd b_tpuch15 c an68_b_pqb4 qvddl vddh a_tpuch3 a_tpuch7 a_tpuch13 a_tpuch0 b_tpuch9 nvddl vss vdd b_tpuch2 b_tpuch0 d vdd b_tpuch1 b_t2clk mpwm17 e mpwm5_mpio32 b6 mpwm18 mda11 mda13 f mda12 mda27 mda28 mda29 g mda30 mda31 mpwm0 mpwm1 h mpwm3 mpwm2 mpwm16 mpwm20_mpio3 2b11 j mda15 mda14 mpwm21_mpio3 2b12 c_cntx0_mpio3 2b13 k vss vss vss c_cnrx0_mpio3 2b14 mpio32b15 mpwm19 vf0_mpio32b0 l vss vss vss vf1_mpio32b1 vf2_mpio32b2 mpwm4_mpio32 b5 vfls0_mpio32b 3 m vss vss vss vddh vfls1_mpio32b 4 b_pcs0_ss_b_q gpio0 b_pcs1_qgpio1 n note: this pinout is a top down view of the package. 2-66 mpc565/mpc566 reference manual motorola package description figure 2-15. mpc565/mpc566 ball map (black and white, page 4) vss vss vss b_eck b_miso_qgpio4 b_pcs3_j1850_t x b_mosi_qgpio5 p vss vss vss b_sck_qgpio6 b_pcs2_qgpio2 b_txd1_qgpo1 b_txd2_qgpo2 r vss vss vss a_txd1_qgpo1 a_miso_qgpio4 b_rxd2_j1850_r x a_sck_qgpio6 t a_pcs2_qgpio2 a_rxd1_qpi1 a_mosi_qgpio5 a_pcs3_qgpio3 u a_pcs0_ss_b_q gpio0 a_txd2_qgpo2 a_rxd2_qpi2 b_rxd1_qgpi1 v nvddl vflash a_pcs1_qgpio1 pullsel w vddf extclk a_cntxo kapwr y poreset_b_ a_cnrxo vssf xtal aa hreset_b irq6_b_modck2 rstconf_b_te xp extal ab sgpioc7_irqou t_b_lwp0 nvddl we_b_at1 nvddl cs3_b bi_b_sts_b vddh vdd vss qvddl sreset_b irq7_b_modck3 vsssyn ac irq4_b_at2_sg pioc4 tea_b irq2_b_cr_b_s gpioc2 we_b_at2 cs1_b tsiz0 b0epee clkout vdd vss qvddl irq5_b_sgpioc 5_modck1 xfc ad bb_b_vf2_iwp3 rd_wr_b oe_b we_b_at0 cs0_b burst_b ts_b bdip_b nc vdd vss qvddl vddsyn ae bg_b_vf0_lwp1 br_b_vf1_iwp2 irq0_b_sgpioc 0 we_b_at3 cs2_b tsiz1 ta_b epee engclk_buclk nc vdd vss qvddl af 14 15 16 17 18 19 20 21 22 23 24 25 26 note: this pinout is a top down view of the package. trst_b motorola chapter 3. central processing unit 3-1 chapter 3 central processing unit the risc processor (rcpu) used in the mpc500 family of microcontrollers integrates five independent execution units: an integer unit (iu), a load/store unit (lsu), a branch processing unit (bpu), a floating-point unit (fpu) and an integer multiplier divider (imd). the risc?s use of simple instructions with rapid execution times yields high efficiency and throughput for mpc500-based systems. most integer instructions execute in one clock cycle. instructions can complete out of order for increased performance; however, the processor makes execution appear sequential. this section provides an overview of the rcpu. for a detailed description of this processor, refer to the rcpu reference manual . the following sections describe each block and sub-block. 3.1 rcpu block diagram figure 3-1 provides a block diagram of the rcpu. 3-2 mpc565/mpc566 reference manual motorola rcpu block diagram figure 3-1. rcpu block diagram control bus fpu fpr history fpr (32 x 64) load/store floating data load/ integer store data load/ address store alu/ bfu imul/ idiv gpr history gpr (32 x 32) control regs next address generation branch unit processor instruction queue pre-fetch instruction sequencer rcpu l-data l-addr source buses (4 slots/clock) i-data i-addr write back bus 2 slots/clock motorola chapter 3. central processing unit 3-3 rcpu key features 3.2 rcpu key features major features of the rcpu include: high-performance microprocessor ? single clock-cycle execution for many instructions five independent execution units and two register files ? independent lsu for load and store operations ? bpu featuring static branch prediction ? a 32-bit integer unit (iu) ? fully ieee 754-compliant fpu for both single- and double-precision operations ? 32 general-purpose registers (gprs) for integer operands ? 32 floating-point registers (fprs) for single- or double-precision operands facilities for enhanced system performance ? atomic memory references in-system testability and debugging features high instruction and data throughput ? condition register (cr) look-ahead operations performed by bpu ? branch-folding capability during execution (zero-cycle branch execution time) ? programmable static branch prediction on unresolved conditional branches ? a pre-fetch queue that can hold up to four instructions, providing look-ahead capability ? interlocked pipelines with feed-forwarding that control data dependencies in hardware class code compression model support ? increases code density and efficient use of internal/external flash 3.3 instruction sequencer the instruction sequencer provides centralized control over data flow between execution units and register files. it implements the basic instruction pipeline, fetches instructions from the memory system, issues them to available execution units, and maintains a state history that is used to back up the machine in the event of an exception. the instruction sequencer fetches instructions from the burst buffer controller into the instruction pre-fetch queue. the bpu extracts branch instructions from the pre-fetch queue and, using branch prediction on unresolved conditional branches, allows the instruction sequencer to fetch instructions from a predicted target stream while a conditional branch is 3-4 mpc565/mpc566 reference manual motorola independent execution units evaluated. the bpu folds out branch instructions for unconditional or conditional branches unaffected by instructions in the execution stage. instructions issued beyond a predicted branch do not complete execution until the branch is resolved, preserving the programming model of sequential execution. if branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions are issued from the correct path. figure 3-2. sequencer data path 3.4 independent execution units the mpc500 architecture supports independent floating-point, integer, load/store, and branch processing execution units, making it possible to implement advanced features such as look-ahead operations. for example, since branch instructions do not depend on gprs, branches can often be resolved early, eliminating stalls caused by taken branches. instruction address generator cc unit 32 32 read write buses branch instruction buffer 32 condition evaluation instruction pre-fetch queue execution units and registers files instruction memory system motorola chapter 3. central processing unit 3-5 independent execution units table 3-1 summarizes the rcpu execution units. the following sections describe these execution units in greater detail. 3.4.1 branch processing unit (bpu) the bpu, located within the instruction sequencer, performs condition register look-ahead operations on conditional branches. the bpu looks through the instruction queue for a conditional branch instruction and attempts to resolve it early, achieving the effect of a zero-cycle branch in many cases. the bpu uses a bit in the instruction encoding to predict the direction of the conditional branch. therefore, when it encounters an unresolved conditional branch instruction, the processor pre-fetches instructions from the predicted target stream until the conditional branch is resolved. the bpu uses a calculation feature to compute branch target addresses with three special-purpose, user-accessible registers: the link register (lr), the count register (ctr), and the condition register (cr). the bpu calculates the return pointer for a subroutine, then calls and saves it into the lr. the lr also contains the branch target address for the branch conditional to link register (bclrx) instruction. the ctr contains the branch target address for the branch conditional to count register (bcctrx) instruction. the contents of the lr and ctr can be copied to or from any gpr. because the bpu uses dedicated registers rather than general-purpose or floating-point registers, execution of branch instructions is independent from execution of integer instructions. the cr bits indicate conditions that may result from the execution of relevant instructions. table 3-1. rcpu execution units unit description branch processing unit (bpu) includes the implementation of all branch instructions load/store unit (lsu) includes implementation of all load and store instructions, whether defined as part of the integer processor or the floating-point processor integer unit (iu) includes implementation of all integer instructions except load/store instructions. this module includes the gprs (including gpr history and scoreboard) and the following subunits: the imul-idiv, which includes the implementation of the integer multiply and divide instructions and the alu-bfu, which includes implementation of all integer logic, add and subtract instructions, and bit field instructions. floating-point unit (fpu) includes the fprs (including fpr history and scoreboard) and the implementation of all floating-point instructions except load and store floating-point instructions 3-6 mpc565/mpc566 reference manual motorola independent execution units 3.4.2 integer unit (iu) the iu executes all integer processor instructions (except the integer storage access instructions) implemented by the load/store unit. the iu contains the following subunits: the imul?idiv unit, which implements the integer multiply and divide instructions the arithmetic logic unit (alu)?bfu unit, which implements all integer logic, add, subtract, and bit-field instructions the iu also includes the integer exception register (xer) and the general-purpose register file. imul?idiv and alu?bfu are implemented as separate execution units. the alu?bfu unit can execute one instruction per clock cycle. imul?idiv instructions require multiple clock cycles to execute. imul?idiv is pipelined for multiply instructions, so that consecutive multiply instructions can be issued on consecutive clock cycles. divide instructions are not pipelined; an integer divide instruction preceded or followed by an integer divide or multiply instruction results in a processor-pipeline stall. however, since imul?idiv and alu?bfu are implemented as separate execution units, an integer divide instruction preceded or followed by an alu?bfu instruction does not cause a delay in the pipeline. 3.4.3 load/store unit (lsu) the load/store unit handles all data transfer between the general-purpose register file and the internal load/store bus (l-bus). the load/store unit is implemented as an independent execution unit so that stalls in the memory pipeline do not stall the master instruction pipeline (unless there is a data dependency). the unit is fully pipelined so that memory instructions of any size may be issued on back-to-back cycles. there is a 32-bit wide data path between the load/store unit and the general-purpose register file. single-word accesses can be achieved with an internal on-chip data ram, resulting in a two-clock latency. double-word accesses require two clocks, resulting in a three-clock latency. since the l-bus is 32 bits wide, double-word transfers require two bus accesses. the load/store unit performs zero-fill for byte and half-word transfers and sign extension for half-word transfers. addresses are formed by adding the source-one register operand specified by the instruction (or zero) to either a source-two register operand or to a 16-bit, immediate value embedded in the instruction. motorola chapter 3. central processing unit 3-7 levels of the mpc500 architecture 3.4.4 floating-point unit (fpu) the fpu contains a double-precision multiply array, the floating-point status and control register (fpscr), and the fprs. the multiply-add array allows the mpc565/mpc566 to efficiently implement floating-point operations such as multiply, multiply-add, and divide. the mpc565/mpc566 depends on a software envelope to fully implement the ieee floating-point specification. overflows, underflows, nans (not a number), and denormalized numbers cause floating-point assist exceptions that invoke a software routine to deliver (with hardware assistance) the correct ieee result. to accelerate time-critical operations and make them more deterministic, the mpc565/mpc566 provides a mode of operation that avoids invoking the software envelope and attempts to deliver results in hardware that are adequate for most applications, if not in strict compliance with ieee standards. in this mode, denormalized numbers, nans, and ieee invalid operations are legitimate, returning default results rather than causing floating-point assist exceptions. 3.5 levels of the mpc500 architecture the mpc500 architecture consists of three levels. adherence to the mpc500 architecture can be measured in terms of which of the following levels of the architecture are implemented: user instruction set architecture (uisa) ? defines the base user-level instruction set, user-level registers, data types, floating-point exception model, memory models for a uniprocessor environment, and programming model for a uniprocessor environment. virtual environment architecture (vea) ? describes the memory model for a multiprocessor environment, and describes other aspects of virtual environments. implementations that conform to the vea also adhere to the uisa, but may not necessarily adhere to the oea. operating environment architecture (oea) ? defines the memory-management model, supervisor-level registers, synchronization requirements, and the exception model. implementations that conform to the oea also adhere to the uisa and the vea. 3.6 rcpu programming model the mpc500 architecture defines register-to-register operations for most computational instructions. source operands for these instructions are accessed from the registers or are embedded in the instruction opcode. the three-register instruction format allows specification of a target register distinct from the two source operands. load and store instructions transfer data between memory and on-chip registers. 3-8 mpc565/mpc566 reference manual motorola rcpu programming model mpc500 processors have two levels of privilege: supervisor mode (typically used by the operating environment) and user mode (used by the application software). the programming models incorporate 32 gprs, special-purpose registers (sprs), and several miscellaneous registers. supervisor-level access is provided through the processor?s exception mechanism. that is, when an exception is taken (whether automatically, because of an error or problem that needs to be serviced, or deliberately, as in the case of a trap instruction), the processor begins operating in supervisor mode. the access level is indicated by the privilege-level (pr) bit in the machine state register (msr). figure 3-3 illustrates the user-level and supervisor-level rcpu programming models and the three levels of the mpc500 architecture. the numbers to the left of the sprs indicate the decimal number that the instruction-operand syntax uses to access the register. note that registers such as the general-purpose registers (gprs) are accessed through operands that are part of the instructions. registers can be accessed explicitly through specific instructions such as move to special-purpose register (mtspr) or move from special-purpose register (mftspr), or implicitly as part of an instruction?s execution. some registers are accessed both explicitly and implicitly. motorola chapter 3. central processing unit 3-9 rcpu programming model figure 3-3. rcpu programming model msr supervisor-level sprs user model vea supervisor model oea machine state register development support sprs condition register floating-point status and control register fpscr cr 0 31 031 0 31 gpr0 gpr1 gpr31 user-level sprs integer exception register (xer) link register (lr) count register (ctr) 0 31 0 63 031 time base lower ? read (tbl) time base upper ? read (tbu) time base facility (for reading) user model uisa fpr0 fpr1 fpr31 see table 3-2 for list of supervisor-level sprs. see table 3-3 for list of development-support sprs. 31 0 031 3-10 mpc565/mpc566 reference manual motorola rcpu programming model table 3-2 lists the mpc565/mpc566 supervisor-level registers. table 3-2. supervisor-level sprs spr number (decimal) special-purpose register 18 dae/source instruction service register (dsisr) see section 3.9.2, ?dae/source instruction service register (dsisr),? for bit descriptions. 19 data address register (dar) see section 3.9.3, ?data address register (dar),? for bit descriptions. 22 decrementer register (dec) see section 3.9.5, ?decrementer register (dec),? for bit descriptions. 26 save and restore register 0 (srr0) see section 3.9.6, ?machine status save/restore register 0 (srr0),? for bit descriptions. 27 save and restore register 1 (srr1) see section 3.9.7, ?machine status save/restore register 1 (srr1),? for bit descriptions. 80 external interrupt enable (eie) 1 see section 3.9.10.1, ?eie, eid, and nri special-purpose registers,? for bit descriptions. 81 external interrupt disable (eid) 1 see section 3.9.10.1, ?eie, eid, and nri special-purpose registers,? for bit descriptions. 82 non-recoverable interrupt (nri) 1 see section 3.9.10.1, ?eie, eid, and nri special-purpose registers,? for bit descriptions. 272 spr general 0 (sprg0) 1 see section 3.9.8, ?general sprs (sprg0?sprg3),? for bit descriptions. 273 spr general 1 (sprg1) 1 see section 3.9.8, ?general sprs (sprg0?sprg3),? for bit descriptions. 274 spr general 2 (sprg2) see section 3.9.8, ?general sprs (sprg0?sprg3),? for bit descriptions. 275 spr general 3 (sprg3) see section 3.9.8, ?general sprs (sprg0?sprg3),? for bit descriptions. 284 time base lower ? write (tbl) see table 3-14 for bit descriptions. 285 time base upper ? write (tbu) see table 3-14 for bit descriptions. 287 processor version register (pvr) see table 3-16 for bit descriptions. motorola chapter 3. central processing unit 3-11 rcpu programming model 528 impu global region attribute (mi_gra) 1 see table 4-8 for bit descriptions. 536 l2u region attribute (l2u_gra) see table 11-10 for bit descriptions. 560 bbc module configuration register (bbc_mcr) 1 see table 4-4 for bit descriptions. 568 l2u module configuration register (l2u_mcr) 1 see table 11-7 for bit descriptions. 784 l2u region base address register 0 (l2u_rba0) 1 see table 4-5 for bit descriptions. 785 impu region base address register 1 (mi_rba1) 1 see table 4-5 for bits descriptions. 786 impu region base address register 2 (mi_rba2) 1 see table 4-5 for bits descriptions. 787 impu region base address register 3 (mi_rba3) 1 see table 4-5 for bits descriptions. 816 impu region attribute register 0 (mi_ra0) 1 .see table 4-6 for bits descriptions. 817 impu region attribute register 1 (mi_ra1) 1 .see table 4-6 for bits descriptions. 818 impu region attribute register 2 (mi_ra2) 1 .see table 4-6 for bits descriptions. 819 impu region attribute register 3(mi_ra3) 1 .see table 4-6 for bits descriptions. 792 l2u region base address register 0 (l2u_rba0) 1 see table 11-8 for bit descriptions. 793 l2u region base address register 1 (l2u_rba1) 1 see table 11-8 for bit descriptions. 794 l2u region base address register 2 (l2u_rba2) 1 see table 11-8 for bit descriptions. 795 l2u region base address register 3 (l2u_rba3) 1 see table 11-8 for bit descriptions. 824 l2u region attribute register 0 (l2u_ra0) 1 see table 11-9 for bit descriptions. 825 l2u region attribute register 1 (l2u_ra1) 1 see table 11-9 for bit descriptions. 826 l2u region attribute register 2 (l2u_ra2) 1 see table 11-9 for bit descriptions. table 3-2. supervisor-level sprs (continued) spr number (decimal) special-purpose register 3-12 mpc565/mpc566 reference manual motorola rcpu programming model table 3-3 lists the mpc565/mpc566 sprs used for development support. 827 l2u region attribute register 3 (l2u_ra3) 1 see table 11-9 for bit descriptions. 1022 floating-point exception cause register (fpecr) 1 see section 3.9.10.2, ?floating-point exception cause register (fpecr),? for bit descriptions. 1 implementation-specific spr. table 3-3. development support sprs 1 spr number (decimal) special-purpose register 144 comparator a value register (cmpa) see table 22-17 for bit descriptions. 145 comparator b value register (cmpb) see table 22-17 for bit descriptions. 146 comparator c value register (cmpc) see table 22-17 for bit descriptions. 147 comparator d value register (cmpd) see table 22-17 for bit descriptions. 148 exception cause register (ecr) see table 22-18 for bit descriptions. 149 debug enable register (der) see table 22-19 for bit descriptions. 150 breakpoint counter a value and control (counta) see table 22-20 for bit descriptions. 151 breakpoint counter b value and control (countb) see table 22-21 for bit descriptions. 152 comparator e value register (cmpe) see table 22-22 for bit descriptions. 153 comparator f value register (cmpf) see table 22-22 for bit descriptions. 154 comparator g value register (cmpg) see table 22-23 for bit descriptions. 155 comparator h value register (cmph) see table 22-23 for bit descriptions. 156 l-bus support comparators control 1 (lctrl1) see table 22-26 for bit descriptions. 157 l-bus support comparators control 2 (lctrl2) see table 22-27 for bit descriptions. table 3-2. supervisor-level sprs (continued) spr number (decimal) special-purpose register motorola chapter 3. central processing unit 3-13 user instruction set architecture (uisa) register set unless otherwise noted, reserved fields in registers are ignored when written and return zero when read. an exception to this rule is xer[16:23] (see 3-14 mpc565/mpc566 reference manual motorola user instruction set architecture (uisa) register set supports the double-precision, floating-point format. every instruction that interprets the contents of an fpr as a floating-point value does so using the double-precision floating-point format. therefore, all floating-point numbers are stored in double-precision format. all floating-point arithmetic instructions operate on data located in fprs and, with the exception of the compare instructions (which update the cr), place the result into an fpr. information about the status of floating-point operations is placed into the floating-point status and control register (fpscr) and in some cases, after the completion of the operation?s writeback stage, into the cr. for information on how the cr is affected by floating-point operations, see section 3.7.4, ?condition register (cr).? 3.7.3 floating-point status and control register (fpscr) the fpscr controls the handling of floating-point exceptions and records status resulting from the floating-point operations. fpscr[0:23] are status bits. fpscr[24:31] are control bits. fpscr[0:12] and fpscr[21:23] are floating-point exception condition bits. these bits are sticky, except for the floating-point enabled exception summary (fex) and floating-point invalid operation exception summary (vx). once set, sticky bits remain set until they are cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0 instruction. table 3-4 summarizes which bits in the fpscr are sticky status bits, which are normal status bits, and which are control bits. msb 0 lsb 63 fpr0 fpr1 ... ... fpr31 reset: unchanged figure 3-5. fprs? floating-point registers table 3-4. fpscr bit categories bits type [0], [3:12], [21:23] status, sticky [1:2], [13:20] status, not sticky [24:31] control motorola chapter 3. central processing unit 3-15 user instruction set architecture (uisa) register set fex and vx are the logical ors of other fpscr bits. therefore these two bits are not listed among the fpscr bits directly affected by the various instructions. a listing of fpscr bit settings is shown in table 3-5. msb 0 123456789101112131415 fx fex vx ox ux zx xx vxsn an vxisi vxidi vxzd z vxim z vxvc fr fi fprf 0 reset: unchanged 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 fprf[1:4] 0 vxso ft vxsq rt vxcv i ve oe ue ze xe ni rn reset: unchanged figure 3-6. fpscr ? floating-point status and control register table 3-5. fpscr bit descriptions bit(s) name description 0 fx floating-point exception summary. every floating-point instruction implicitly sets fpscr[fx] if that instruction causes any of the floating-point exception bits in the fpscr to change from 0 to 1. the mcrfs instruction implicitly clears fpscr[fx] if the fpscr field containing fpscr[fx] has been copied. the mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions can set or clear fpscr[fx] explicitly. sticky bit 1 fex floating-point enabled exception summary. this bit signals the occurrence of any of the enabled exception conditions. it is the logical or of all the floating-point exception bits masked with their respective enable bits. the mcrfs instruction implicitly clears fpscr[fex] if the result of the logical or described above becomes zero. the mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear fpscr[fex] explicitly. not sticky 2 vx floating-point invalid operation exception summary. this bit signals the occurrence of any invalid operation exception. it is the logical or of all of the invalid operation exceptions. the mcrfs instruction implicitly clears fpscr[vx] if the result of the logical or described above becomes zero. the mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear fpscr[vx] explicitly. not sticky 3 ox floating-point overflow exception. sticky bit 4 ux floating-point underflow exception. sticky bit 5 zx floating-point zero divide exception. sticky bit 6 xx floating-point inexact exception. sticky bit 7 vxsnan floating-point invalid operation exception for snan. sticky bit 8 vxisi floating-point invalid operation exception for 3-16 mpc565/mpc566 reference manual motorola user instruction set architecture (uisa) register set 11 vximz floating-point invalid operation exception for motorola chapter 3. central processing unit 3-17 user instruction set architecture (uisa) register set table 3-6 illustrates the floating-point result flags that correspond to fpscr[15:19]. 3.7.4 condition register (cr) the condition register (cr) is a 32-bit register that reflects the result of certain operations and provides a mechanism for testing and branching. the bits in the cr are grouped into eight 4-bit fields: cr0 to cr7. the cr fields can be set in the following ways: specified fields of the cr can be set by an instruction (mtcrf) to move to the cr from a gpr. specified fields of the cr can be moved from one crx field to another with the mcrf instruction. 29 ni non-ieee mode bit. ? 30?31 rn floating-point rounding control. 00 round to nearest 01 round toward zero 10 round toward +infinity 11 round toward -infinity ? table 3-6. floating-point result flags in fpscr result flags (bits 15:19) c<>=? result value class 10001 quiet nan 01001 ? infinity 01000 ? normalized number 11000 ? denormalized number 10010 ? zero 00010 + zero 10100 + denormalized number 00100 + normalized number 00101 + infinity msb 0 123456789101112131415161718192021222324252627282930lsb 31 cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 reset: unchanged figure 3-7. cr ? condition register table 3-5. fpscr bit descriptions (continued) bit(s) name description 3-18 mpc565/mpc566 reference manual motorola user instruction set architecture (uisa) register set a specified field of the cr can be set by an instruction (mcrxr) to move to the cr from the xer. condition register logical instructions can be used to perform logical operations on specified bits in the condition register. cr0 can be the implicit result of an integer operation. a specified cr field can be the explicit result of an integer compare instruction. instructions are provided to test individual cr bits. 3.7.4.1 condition register cr[0] field definition in most integer instructions, when the cr is set to reflect the result of the operation (that is, when rc = 1), and for addic., andi., and andis., the first three bits of cr0 are set by an algebraic comparison of the result to zero; the fourth bit of cr0 is copied from xer[so]. for integer instructions, cr[0:3] are set to reflect the result as a signed quantity. the eq bit reflects the result as an unsigned quantity or bit string. the cr0 bits are interpreted as shown in table 3-7. if any portion of the result (the 32-bit value placed into the destination register) is undefined, the value placed in the first three bits of cr0 is undefined. 3.7.4.2 condition register cr1 field definition in all floating-point instructions when the cr is set to reflect the result of the operation (that is, when rc = 1), the cr1 field (bits 4 to 7 of the cr) is copied from fpscr[0:3] to indicate the floating-point exception status. for more information about the fpscr, see section 3.7.3, ?floating-point status and control register (fpscr).? the bit settings for the cr1 field are shown in table 3-8. table 3-7. bit settings for cr0 field of cr cr0 bit description 0 negative (lt). this bit is set when the result is negative. 1 positive (gt). this bit is set when the result is positive (and not zero). 2 zero (eq). this bit is set when the result is zero. 3 summary overflow (so). this is a copy of the final state of xer[so] at the completion of the instruction. table 3-8. bit settings for cr1 field of cr cr1 bit description 0 floating-point exception (fx). this is a copy of the final state of fpscr[fx] at the completion of the instruction. 1 floating-point enabled exception (fex).this is a copy of the final state of fpscr[fex] at the completion of the instruction. motorola chapter 3. central processing unit 3-19 user instruction set architecture (uisa) register set 3.7.4.3 condition register crn field ? compare instruction when a specified cr field is set by a compare instruction, the bits of the specified field are interpreted as shown in table 3-9. a condition register field can also be accessed by the mfcr, mcrf, and mtcrf instructions. 3.7.5 integer exception register (xer) the integer exception register (xer), spr 1, is a user-level, 32-bit register. the bit descriptions for xer, shown in table 3-10, are based on the operation of an instruction considered as a whole, not on intermediate results. for example, the result of the subtract from carrying (subfcx) instruction is specified as the sum of three values. this instruction sets bits in the xer based on the entire operation, not on an intermediate sum. 2 floating-point invalid exception (vx).this is a copy of the final state of fpscr[vx] at the completion of the instruction. 3 floating-point overflow exception (ox).this is a copy of the final state of fpscr[ox] at the completion of the instruction. table 3-9. crn field bit settings for compare instructions crn bit 1 1 here, the bit indicates the bit number in any one of the four-bit subfields, cr0?cr7 description 0 less than, floating-point less than (lt, fl). for integer compare instructions, (ra) < simm, uimm, or (rb) (algebraic comparison) or (ra) simm, uimm, or (rb) (logical comparison). for floating-point compare instructions, (fra) < (frb). 1 greater than, floating-point greater than (gt, fg). for integer compare instructions, (ra) > simm, uimm, or (rb) (algebraic comparison) or (ra) simm, uimm, or (rb) (logical comparison). for floating-point compare instructions, (fra) > (frb). 2 equal, floating-point equal (eq, fe). for integer compare instructions, (ra) = simm, uimm, or (rb). for floating-point compare instructions, (fra) = (frb). 3 summary overflow, floating-point unordered (so, fu). for integer compare instructions, this is a copy of the final state of xer[so] at the completion of the instruction. for floating-point compare instructions, one or both of (fra) and (frb) is not a number (nan). msb 0 123456789101112131415161718192021222324252627282930lsb 31 so ov ca reserved bytes reset: u uuuuu 0000 000000000000000uuuuuu u figure 3-8. xer ? integer exception register table 3-8. bit settings for cr1 field of cr (continued) cr1 bit description 3-20 mpc565/mpc566 reference manual motorola user instruction set architecture (uisa) register set in most cases, reserved fields in registers are ignored when written to and return zero when read. however, xer[16:23] are set to the value written to them and return that value when read. 3.7.6 link register (lr) the link register (lr), spr 8, supplies the branch target address for the branch conditional to link register (bclrx) instruction, and can be used to hold the logical address of the instruction that follows a branch and link instruction. note that although the two least-significant bits can accept any values written to them, they are ignored when the lr is used as an address. both conditional and unconditional branch instructions include the option of placing the effective address of the instruction after the branch instruction in the lr. this is done regardless of whether the branch is taken. 3.7.7 count register (ctr) the count register (ctr), spr 9, is used to hold a loop count that can be decremented during execution of branch instructions with an appropriately coded bo field. if the value table 3-10. integer exception register bit descriptions bit(s) name description 0 so summary overflow (so). the summary overflow bit is set whenever an instruction sets the overflow bit (ov) to indicate overflow and remains set until software clears it. it is not altered by compare instructions or other instructions that cannot overflow. 1 ov overflow (ov). the overflow bit is set to indicate that an overflow has occurred during execution of an instruction. integer and subtract instructions having oe=1 set ov if the carry out of bit 0 is not equal to the carry out of bit 1, and clear it otherwise. the ov bit is not altered by compare instructions or other instructions that cannot overflow. 2 ca carry (ca). in general, the carry bit is set to indicate that a carry out of bit 0 occurred during execution of an instruction. add carrying, subtract from carrying, add extended, and subtract from extended instructions set ca to one if there is a carry out of bit 0, and clear it otherwise. the ca bit is not altered by compare instructions or other instructions that cannot carry, except that shift right algebraic instructions set the ca bit to indicate whether any ?1? bits have been shifted out of a negative quantity. 3:24 ? reserved 25:31 bytes this field specifies the number of bytes to be transferred by a load string word indexed (lswx) or store string word indexed (stswx) instruction. msb 0 123456789101112131415161718192021222324252627282930lsb 31 branch address reset: unchanged figure 3-9. lr ? link register motorola chapter 3. central processing unit 3-21 vea register set ? time base in ctr is 0 before being decremented, it is ?1 afterward. the count register provides the branch target address for the branch conditional to count register (bcctrx) instruction. 3.8 vea register set ? time base the virtual environment architecture (vea) defines registers in addition to the uisa register set. the vea register set can be accessed by all software with either user- or supervisor-level privileges. the vea includes the time base facility (tb), a 64-bit structure that contains a 64-bit unsigned integer that is incremented periodically. the frequency at which the counter is updated is implementation-dependent. for details on the time base clock in the mpc565/mpc566, refer to section 6.8, ?time base (tb),? section 8.5, ?internal clock signals,? and section 8.11.1, ?system clock control register (sccr).? the tb consists of two 32-bit registers: time base upper (tbu), spr 268, and time base lower (tbl), spr 269. in the context of the vea, user-level applications are permitted read-only access to the tb. the oea defines supervisor-level access for writing values to the tb. different spr encodings are provided for reading and writing the time base. in 32-bit mpc500 implementations such as the rcpu, it is not possible to read the entire 64-bit time base in a single instruction. the mftb simplified mnemonic copies the lower half of the time base register (tbl) to a gpr, and the mftbu simplified mnemonic copies the upper half of the time base (tbu) to a gpr. msb 0 123456789101112131415161718192021222324252627282930lsb 31 loop count reset: unchanged figure 3-10. ctr ? count register 0313263 tbu tbl reset: unchanged figure 3-11. tb ? time base (read only)spr table 3-11. time base field definitions (read only) bits name description 0-31 tbu time base (upper). the high-order 32 bits of the time base 32-63 tbl time base (lower). the low-order 32 bits of the time base 3-22 mpc565/mpc566 reference manual motorola oea register set 3.9 oea register set the operating environment architecture (oea) includes a number of sprs and other registers that are accessible only by supervisor-level instructions. some sprs are rcpu-specific; some rcpu sprs may not be implemented in other mpc500 processors, or may not be implemented in the same way. 3.9.1 machine state register (msr) the machine state register is a 32-bit register that defines the state of the processor. when an exception occurs, the contents of the msr are loaded into srr1, and the msr is updated to reflect the exception-processing machine state. the msr can also be modified by the mtmsr, sc, and rfi instructions. it can be read by the mfmsr instruction. 11 table 3-12 shows the bit definitions for the msr. msb 0 123456789101112131415 reserved pow 0 ile reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 ee pr fp me fe0 se be fe1 0 ip ir dr rese rved dcm pen 1 ri le reset: 000u00000id1 2 000id21 & id22 2 00 1 this bit is available only on code compression-enabled options of the mpc565/mpc566. 2 reset value of these bits depends on the value of the internal data bus line during reset. default value is based on id21 and id22. figure 3-12. machine state register table 3-12. machine state register bit descriptions bit(s) name description 0:12 ? reserved 13 pow power management enable. 0 power management disabled (normal operation mode) 1 power management enabled (reduced power mode) 14 ? reserved motorola chapter 3. central processing unit 3-23 oea register set 15 ile exception little-endian mode. when an exception occurs, this bit is copied into msr[le] to select the endian mode for the context established by the exception. little-endian mode is not supported on mpc565/mpc566. this bit should be cleared to 0 at all times. 0 the processor runs in big-endian mode during exception processing. 1 the processor runs in little-endian mode during exception processing. 16 ee external interrupt enable. interrupts should only be negated while the ee bit is disabled (0). software should disable interrupts in the cpu core prior to masking or disabling any interrupt which might be currently pending at the cpu core. for external interrupts, it is recommended that the edge-triggered interrupt scheme be used. 0 the processor delays recognition of external interrupts and decrementer exception conditions. 1 the processor is enabled to take an external interrupt or the decrementer exception. 17 pr privilege level. 0 the processor can execute both user- and supervisor-level instructions. 1 the processor can only execute user-level instructions. 18 fp floating-point available . 0 the processor prevents dispatch of floating-point instructions, including floating-point loads, stores and moves. floating-point enabled program exceptions can still occur and the fprs can still be accessed. 1 the processor can execute floating-point instructions, and can take floating-point enabled exception type program exceptions. 19 me machine check enable. 0 machine check exceptions are disabled. 1 machine check exceptions are enabled. 20 fe0 floating-point exception mode 0 (see table 3-13.) 21 se single-step trace enable. 0 the processor executes instructions normally. 1 the processor generates a single-step trace exception when the next instruction executes successfully. when this bit is set, the processor dispatches instructions in strict program order. successful execution means the instruction caused no other exception. single-step tracing may not be present on all implementations. 22 be branch trace enable. 0 no trace exception occurs when a branch instruction is completed. 1 trace exception occurs when a branch instruction is completed. 23 fe1 floating-point exception mode 1 (see table 3-13). 24 ? reserved 25 ip exception prefix. the setting of this bit specifies the location of the exception vector table. 0 exception vector table starts at the physical address 0x0000 0000. 1 exception vector table starts at the physical address 0xfff0 0000. 26 ir instruction relocation. 0 instruction address translation is off; the bbc impu does not check for address permission attributes. 1 instruction address translation is on; the bbc impu checks for address permission attributes. 27 dr data relocation. 0 data address translation is off; the l2u dmpu does not check for address permission attributes. 1 data address translation is on; the l2u dmpu checks for address-permission attributes. table 3-12. machine state register bit descriptions (continued) bit(s) name description 3-24 mpc565/mpc566 reference manual motorola oea register set the floating-point exception mode bits are interpreted as shown in table 3-13. 3.9.2 dae/source instruction service register (dsisr) the dsisr, spr 18, identifies the cause of data access and alignment exceptions. 3.9.3 data address register (dar) after an alignment exception, the dar, spr 19, is set to the effective address of a load or store element. 28 ? reserved 29 dcmpe n decompression on/off. the reset value of this bit is (bbcmcr[en_comp] & bbcmcr[exc_comp]). note: this is for the mpc566 only. 0 the rcpu runs in normal operation mode. 1 the rcpu runs in compressed mode. 30 ri recoverable exception (for machine check and non-maskable breakpoint exceptions). 0 machine state is not recoverable. 1 machine state is recoverable. 31 le little-endian mode. this mode is not supported on mpc565/mpc566. this bit should be cleared to 0 at all times. 0 the processor operates in big-endian mode during normal processing. 1 the processor operates in little-endian mode during normal processing. table 3-13. floating-point exception mode bits fe[0:1] mode 00 ignore exceptions mode. floating-point exceptions do not cause the floating-point assist error handler to be invoked. 01, 10, 11 floating-point precise mode. the system floating-point assist error handler is invoked precisely at the instruction that caused the enabled exception. msb 0 123456789101112131415161718192021222324252627282930lsb 31 dsisr reset: unchanged figure 3-13. dsisr ? dae/source instruction service register table 3-12. machine state register bit descriptions (continued) bit(s) name description motorola chapter 3. central processing unit 3-25 oea register set 3.9.4 time base facility (tb) ? oea as described in section 3.8, ?vea register set ? time base,? the time base (tb) provides a 64-bit incrementing counter. whereas the vea defines user-level, read-only access to the tb, the oea defines supervisor-level, write access. writing to the tb, spr 284 and 285, is reserved for supervisor-level applications such as operating systems and bootstrap routines. the tb can be written to at the supervisor-level only. the mttbl and mttbu simplified mnemonics write the lower and upper halves of the tb, respectively. the mtspr, mttbl, and mttbu instructions treat tbl and tbu as separate 32-bit registers; setting one leaves the other unchanged. it is not possible to write the entire 64-bit time base in a single instruction. for information about reading the time base, refer to section 3.8, ?vea register set ? time base.? 3.9.5 decrementer register (dec) the decrementer register (dec), spr 22, is decrementing counter that provides a decrementer exception after a programmable delay. the dec satisfies the following requirements: remains unaffected when a gpr is loaded from the dec replaces the value in the dec with the value in the gpr when a gpr is stored in the dec msb 0 123456789101112131415161718192021222324252627282930lsb 31 data address reset: unchanged figure 3-14. dar ? data address register 0313263 tbu tbl reset: unchanged figure 3-15. tb ? time base (write only) table 3-14. time base field (write only) bit descriptions bits name description 0:31 tbu time base (upper). the high-order 32 bits of the time base 32:63 tbl time base (lower). the low-order 32 bits of the time base 3-26 mpc565/mpc566 reference manual motorola oea register set signals a decrementer exception request (unless masked) whenever bit 0 of the dec changes from zero to one. multiple dec exception requests may be received before the first exception occurs; however, any additional requests are canceled when the exception occurs for the first request signals an exception request if the dec is altered by software and the content of bit 0 is changed from zero to one stops counting and clears the register with poreset (hreset /sreset do not) the decrementer frequency is based on a subdivision of the processor clock. a bit in the system clock control register (sccr) in the siu determines the clock source of both the decrementer and the time base. for details on the decrementer and time base clock, refer to section 6.7, ?decrementer (dec),? section 8.5, ?internal clock signals,? and section 8.11.1, ?system clock control register (sccr).? the dec does not run after power-up and must be enabled by setting the tbe bit in the tbscr register, see table 6-18. power-on reset stops its counting and clears the register. a decrementer exception may be signaled to software prior to initialization. 3.9.6 machine status save/restore register 0 (srr0) the machine status save/restore register 0 (srr0), spr 26, identifies where instruction execution should resume when an rfi instruction is executed following an exception. it also holds the effective address of the instruction that follows the system call (sc) instruction. when an exception occurs, srr0 is set to point to an instruction such that all prior instructions have completed execution and no subsequent instruction has begun execution. the instruction addressed by srr0 may not have completed execution, depending on the exception type. srr0 addresses either the instruction causing the exception or the instruction immediately following. the instruction addressed can be determined from the exception type and status bits. msb 0 123456789101112131415161718192021222324252627282930lsb 31 decrementing counter reset: unchanged figure 3-16. dec ? decrementer register msb 0 123456789101112131415161718192021222324252627282930lsb 31 srr0 reset: undefined figure 3-17. srr0 ? machine status save/restore register 0 motorola chapter 3. central processing unit 3-27 oea register set 3.9.7 machine status save/restore register 1 (srr1) srr1, spr 27, saves the machine status on exceptions and restores the machine status when an rfi instruction is executed. in general, when an exception occurs, srr1[0:15] are loaded with exception-specific information, and msr[16:31] are placed into srr1[16:31]. 3.9.8 general sprs (sprg0?sprg3) sprg0?sprg3, sprs 272-275, are provided for general operating system use, such as fast-state saves and multiprocessor-implementation support. sprg0?sprg3 are shown below. uses for sprg0?sprg3 are shown in table 3-15. msb 0 123456789101112131415161718192021222324252627282930lsb 31 srr1 reset: undefined figure 3-18. srr1 ? machine status save/restore register 1 msb 0 123456789101112131415161718192021222324252627282930lsb 31 sprg0 sprg1 sprg2 sprg3 reset: unchanged figure 3-19. sprg0?sprg3 ? general special-purpose registers 0?3 table 3-15. uses of sprg0?sprg3 register description sprg0 software may load a unique physical address in this register to identify an area of memory reserved for use by the exception handler. this area must be unique for each processor in the system. sprg1 this register may be used as a scratch register by the exception handler to save the content of a gpr. that gpr then can be loaded from sprg0 and used as a base register to save other gprs to memory. sprg2 this register may be used by the operating system as needed. sprg3 this register may be used by the operating system as needed. 3-28 mpc565/mpc566 reference manual motorola oea register set 3.9.9 processor version register (pvr) the pvr is a 32-bit, read-only register that identifies the version and revision level of the mpc500 processor. the contents of the pvr can be copied to a gpr by the mfspr instruction. read access to the pvr is available in supervisor mode only; write access is not provided. 3.9.10 implementation-specific sprs the mpc565/mpc566 includes several implementation-specific sprs that are not defined by the mpc500 architecture. these registers, listed in table 3-2 and table 3-3, can be accessed by supervisor-level instructions only. 3.9.10.1 eie, eid, and nri special-purpose registers the rcpu includes three implementation-specific sprs that facilitate the software manipulation of the msr[ri] and msr[ee] bits. issuing the mtspr instruction with one of these registers as an operand causes the ri and ee bits to be set or cleared as shown in table 3-17. a read (mfspr) of any of these locations is treated as an unimplemented instruction, resulting in a software emulation exception. msb 0 123456789101112131415161718192021222324252627282930lsb 31 version revision 000000000 000010000000000010000 0 figure 3-20. pvr ? processor version register table 3-16. processor version register bit descriptions bit(s) name description 0:15 version a 16-bit number that identifies the version of the processor and of the mpc500 architecture. mpc565/mpc566 value is 0x0002. 16:31 revision a 16-bit number that distinguishes between various releases of a particular version. the mpc565/mpc566 value is 0x0020. table 3-17. eie, eid, and nri registers spr number (decimal) mnemonic msr[ee] msr[ri] 80 eie 1 1 81 eid 0 1 82 nri 0 0 motorola chapter 3. central processing unit 3-29 oea register set 3.9.10.2 floating-point exception cause register (fpecr) the fpecr, spr 1022, is a supervisor-level internal status and control register used by the floating-point assist firmware envelope. it contains four status bits that indicate whether the result of the operation is tiny and whether any of three source operands are denormalized. in addition, it contains one control bit to enable or disable sie mode. this register must not be accessed by user code. a listing of fpecr bit settings is shown in table 3-18. note software must insert a sync instruction before reading the fpecr. msb 0 123456789101112131415 sie reserved reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved dnc dnb dna tr reset: 0000000000000000 figure 3-21. fpecr ? floating-point exception cause register table 3-18. fpecr bit descriptions bit(s) name description 0 sie synchronized ignore exception mode control bit. 0 disable sie mode 1 enable sie mode [1:27] ? reserved 28 dnc source operand c denormalized status bit. 0 source operand c is not denormalized 1 source operand c is denormalized 29 dnb source operand b denormalized status bit. 0 source operand b is not denormalized 1 source operand b is denormalized 30 dna source operand a denormalized status bit . 0 source operand a is not denormalized 1 source operand a is denormalized 31 tr floating-point tiny result. 0 floating-point result is not tiny 1 floating-point result is tiny 3-30 mpc565/mpc566 reference manual motorola instruction set 3.9.10.3 additional implementation-specific registers refer to the following sections for details on additional implementation-specific registers in the mpc565/mpc566: section 4.7, ?bbc programming model? section 6.14.1.2, ?internal memory map register? section 11.8, ?l2u programming model? chapter 22, ?development support? 3.10 instruction set all mpc500 instructions are encoded as single words (32 bits) and are consistent among all instruction types. the fixed instruction length and consistent format simplify instruction pipelining and permit efficient decoding to occur in parallel with operand accesses. the mpc500 instructions are divided into the following categories: integer instructions, which include computational and logical instructions ? integer arithmetic instructions ? integer compare instructions ? integer logical instructions ? integer rotate and shift instructions floating-point instructions, which include floating-point computational instructions, as well as instructions that affect the floating-point status and control register (fpscr) ? floating-point arithmetic instructions ? floating-point multiply/add instructions ? floating-point rounding and conversion instructions ? floating-point compare instructions ? floating-point status and control instructions load/store instructions., which include integer and floating-point load and store instructions ? integer load and store instructions ? integer load and store multiple instructions ? floating-point load and store ? primitives used to construct atomic memory operations (lwarx and stwcx. instructions) motorola chapter 3. central processing unit 3-31 instruction set flow control instructions, which include branching instructions, condition register logical instructions, trap instructions, and other instructions that affect the instruction flow ? branch and trap instructions ? condition register logical instructions processor control instructions, which are used for synchronizing memory accesses. ? move to/from spr instructions ? move to/from msr ? synchronize ? instruction synchronize note this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instructions. integer instructions operate on byte, half-word, and word operands. floating-point instructions operate on single-precision (one word) and double-precision (one double word) floating-point operands. the mpc500 architecture uses instructions that are four bytes long and word-aligned. it provides for byte, half-word, and word operand loads and stores between memory and a set of 32 gprs. computational instructions do not modify memory. to use a memory operand in a computation and then modify the same or another memory location, the memory contents must be loaded into a register, modified, and then written back to the target location with distinct instructions. mpc500 processors follow the program flow when they are in the normal execution state. however, the flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous event. either kind of exception may cause one of several components of the system software to be invoked. 3.10.1 instruction set summary table 3-19 provides a summary of rcpu instructions. refer to the rcpu reference manual for a detailed description of the instruction set. table 3-19. instruction set summary mnemonic operand syntax name add (add. addo addo.) rd,ra,rb add addc (addc. addco addco.) rd,ra,rb add carrying adde (adde. addeo addeo.) rd,ra,rb add extended 3-32 mpc565/mpc566 reference manual motorola instruction set addi rd,ra,simm add immediate addic rd,ra,simm add immediate carrying addic. rd,ra,simm add immediate carrying and record addis rd,ra,simm add immediate shifted addme (addme. addmeo addmeo.) rd,ra add to minus one extended addze (addze. addzeo addzeo.) rd,ra add to zero extended and (and.) ra,rs,rb and andc (andc.) ra,rs,rb and with complement andi. ra,rs,uimm and immediate andis. ra,rs,uimm and immediate shifted b (ba bl bla) target_addr branch bc (bca bcl bcla) bo,bi,target_addr branch conditional bcctr (bcctrl) bo,bi branch conditional to count register bclr (bclrl) bo,bi branch conditional to link register cmp crfd,l,ra,rb compare cmpi crfd,l,ra,simm compare immediate cmpl crfd,l,ra,rb compare logical cmpli crfd,l,ra,uimm compare logical immediate cntlzw (cntlzw.) ra,rs count leading zeros word crand crbd,crba,crbb condition register and crandc crbd,crba, crbb condition register and with complement creqv crbd,crba, crbb condition register equivalent crnand crbd,crba,crbb condition register nand crnor crbd,crba,crbb condition register nor cror crbd,crba,crbb condition register or crorc crbd,crba, crbb condition register or with complement crxor crbd,crba,crbb condition register xor divw (divw. divwo divwo.) rd,ra,rb divide word divwu divwu. divwuo divwuo. rd,ra,rb divide word unsigned eieio ? enforce in-order execution of i/o eqv (eqv.) ra,rs,rb equivalent extsb (extsb.) ra,rs extend sign byte extsh (extsh.) ra,rs extend sign half word table 3-19. instruction set summary (continued) mnemonic operand syntax name motorola chapter 3. central processing unit 3-33 instruction set fabs (fabs.) frd,frb floating absolute value fadd (fadd.) frd,fra,frb floating add (double-precision) fadds (fadds.) frd,fra,frb floating add single fcmpo crfd,fra,frb floating compare ordered fcmpu crfd,fra,frb floating compare unordered fctiw (fctiw.) frd,frb floating convert to integer word fctiwz (fctiwz.) frd,frb floating convert to integer word with round toward zero fdiv (fdiv.) frd,fra,frb floating divide (double-precision) fdivs (fdivs.) frd,fra,frb floating divide single fmadd (fmadd.) frd,fra,frc,frb floating multiply-add (double-precision) fmadds (fmadds.) frd,fra,frc,frb floating multiply-add single fmr (fmr.) frd,frb floating move register fmsub (fmsub.) frd,fra,frc,frb floating multiply-subtract (double-precision) fmsubs (fmsubs.) frd,fra,frc,frb floating multiply-subtract single fmul (fmul.) frd,fra,frc floating multiply (double-precision) fmuls (fmuls.) frd,fra,frc floating multiply single fnabs (fnabs.) frd,frb floating negative absolute value fneg (fneg.) frd,frb floating negate fnmadd (fnmadd.) frd,fra,frc,frb floating negative multiply-add (double- precision) fnmadds (fnmadds.) frd,fra,frc,frb floating negative multiply-add single fnmsub (fnmsub.) frd,fra,frc,frb floating negative multiply-subtract (double-precision) fnmsubs (fnmsubs.) frd,fra,frc,frb floating negative multiply-subtract single frsp (frsp.) frd,frb floating round to single fsub (fsub.) frd,fra,frb floating subtract (double-precision) fsubs (fsubs.) frd,fra,frb floating subtract single isync ? instruction synchronize lbz rd,d(ra) load byte and zero lbzu rd,d(ra) load byte and zero with update lbzux rd,ra,rb load byte and zero with update indexed lbzx rd,ra,rb load byte and zero indexed lfd frd,d(ra) load floating-point double table 3-19. instruction set summary (continued) mnemonic operand syntax name 3-34 mpc565/mpc566 reference manual motorola instruction set lfdu frd,d(ra) load floating-point double with update lfdux frd,ra,rb load floating-point double with update indexed lfdx frd,ra,rb load floating-point double indexed lfs frd,d(ra) load floating-point single lfsu frd,d(ra) load floating-point single with update lfsux frd,ra,rb load floating-point single with update indexed lfsx frd,ra,rb load floating-point single indexed lha rd,d(ra) load half-word algebraic lhau rd,d(ra) load half-word algebraic with update lhaux rd,ra,rb load half-word algebraic with update indexed lhax rd,ra,rb load half-word algebraic indexed lhbrx rd,ra,rb load half-word byte-reverse indexed lhz rd,d(ra) load half-word and zero lhzu rd,d(ra) load half-word and zero with update lhzux rd,ra,rb load hal-word and zero with update indexed lhzx rd,ra,rb load half-word and zero indexed lmw rd,d(ra) load multiple word lswi rd,ra,nb load string word immediate lswx rd,ra,rb load string word indexed lwarx rd,ra,rb load word and reserve indexed lwbrx rd,ra,rb load word byte-reverse indexed lwz rd,d(ra) load word and zero lwzu rd,d(ra) load word and zero with update lwzux rd,ra,rb load word and zero with update indexed lwzx rd,ra,rb load word and zero indexed mcrf crfd,crfs move condition register field mcrfs crfd,crfs move to condition register from fpscr mcrxr crfd move to condition register from xer mfcr rd move from condition register mffs (mffs.) frd move from fpscr mfmsr rd move from machine state register mfspr rd,spr move from special purpose register mftb rd, tbr move from time base table 3-19. instruction set summary (continued) mnemonic operand syntax name motorola chapter 3. central processing unit 3-35 instruction set mtcrf crm,rs move to condition register fields mtfsb0 (mtfsb0.) crbd move to fpscr bit 0 mtfsb1 (mtfsb1.) crbd move to fpscr bit 1 mtfsf (mtfsf.) fm,frb move to fpscr fields mtfsfi (mtfsfi.) crfd,imm move to fpscr field immediate mtmsr rs move to machine state register mtspr spr,rs move to special purpose register mulhw (mulhw.) rd,ra,rb multiply high word mulhwu (mulhwu.) rd,ra,rb multiply high word unsigned mulli rd,ra,simm multiply low immediate mullw (mullw. mullwo mullwo.) rd,ra,rb multiply low nand (nand.) ra,rs,rb nand neg (neg. nego nego.) rd,ra negate nor (nor.) ra,rs,rb nor or (or.) ra,rs,rb or orc (orc.) ra,rs,rb or with complement ori ra,rs,uimm or immediate oris ra,rs,uimm or immediate shifted rfi ? return from interrupt rlwimi (rlwimi.) ra,rs,sh,mb,me rotate left word immediate then mask insert rlwinm (rlwinm.) ra,rs,sh,mb,me rotate left word immediate then and with mask rlwnm (rlwnm.) ra,rs,rb,mb,me rotate left word then and with mask sc ? system call slw (slw.) ra,rs,rb shift left word sraw (sraw.) ra,rs,rb shift right algebraic word srawi (srawi.) ra,rs,sh shift right algebraic word immediate srw (srw.) ra,rs,rb shift right word stb rs,d(ra) store byte stbu rs,d(ra) store byte with update stbux rs,ra,rb store byte with update indexed stbx rs,ra,rb store byte indexed stfd frs,d(ra) store floating-point double stfdu frs,d(ra) store floating-point double with update table 3-19. instruction set summary (continued) mnemonic operand syntax name 3-36 mpc565/mpc566 reference manual motorola instruction set stfdux frs,rb store floating-point double with update indexed stfdx frs,rb store floating-point double indexed stfiwx frs,rb store floating-point as integer word indexed stfs frs,d(ra) store floating-point single stfsu frs,d(ra) store floating-point single with update stfsux frs,rb store floating-point single with update indexed stfsx frs,r b store floating-point single indexed sth rs,d(ra) store half-word sthbrx rs,ra,rb store half-word byte-reverse indexed sthu rs,d(ra) store half-word with update sthux rs,ra,rb store half-word with update indexed sthx rs,ra,rb store half-word indexed stmw rs,d(ra) store multiple word stswi rs,ra,nb store string word immediate stswx rs,ra,rb store string word indexed stw rs,d(ra) store word stwbrx rs,ra,rb store word byte-reverse indexed stwcx. rs,ra,rb store word conditional indexed stwu rs,d(ra) store word with update stwux rs,ra,rb store word with update indexed stwx rs,ra,rb store word indexed subf (subf. subfo subfo.) rd,ra,rb subtract from subfc (subfc. subfco subfco.) rd,ra,rb subtract from carrying subfe (subfe. subfeo subfeo.) rd,ra,rb subtract from extended subfic rd,ra,simm subtract from immediate carrying subfme (subfme. subfmeo subfmeo.) rd,ra subtract from minus one extended subfze (subfze. subfzeo subfzeo.) rd,ra subtract from zero extended sync ? synchronize tw to,ra,rb trap word twi to,ra,simm trap word immediate xor (xor.) ra,rs,rb xor xori ra,rs,uimm xor immediate xoris ra,rs,uimm xor immediate shifted table 3-19. instruction set summary (continued) mnemonic operand syntax name motorola chapter 3. central processing unit 3-37 exception model note: the dot (.) suffix on a mnemonic indicates that the cr register update is enabled. the o suffix on a mnemonic indicates that the overflow bit in the xer is enabled. 3.10.2 recommended simplified mnemonics to simplify assembly language coding, a set of alternative mnemonics is provided for some frequently used operations (such as no-op, load immediate, load address, move register, and complement register). for a complete list of simplified mnemonics, see the rcpu reference manual .programs written to be portable across the various assemblers for the mpc500 architecture should not assume the existence of mnemonics not described in that manual. 3.10.3 calculating effective addresses the effective address (ea) is the 32-bit address computed by the processor when executing a memory access or branch instruction or when fetching the next sequential instruction. the mpc500 architecture supports two simple memory addressing modes: ea = (ra|0) + 16-bit offset (including offset = 0) (register indirect with immediate index) ea = (ra|0) + rb (register indirect with index) these simple addressing modes allow efficient address generation for memory accesses. calculation of the effective address for aligned transfers occurs in a single clock cycle. for a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the storage operand is considered to wrap around from the maximum effective address to effective address 0. effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. a carry from bit 0 is ignored in 32-bit implementations. 3.11 exception model the mpc500 exception mechanism allows the processor to change to supervisor state as a result of external signals, errors, or unusual conditions that arise in the execution of instructions. when exceptions occur, information about the state of the processor is saved to certain registers, and the processor begins execution at an address (exception vector) predetermined for each exception. processing of exceptions occurs in supervisor mode. although multiple exception conditions can map to a single exception vector, a more specific condition may be determined by examining a register associated with the exception ? for example, the dae/source instruction service register (dsisr). additionally, some exception conditions can be explicitly enabled or disabled by software. 3-38 mpc565/mpc566 reference manual motorola exception model 3.11.1 exception classes the mpc565/mpc566 exception classes are shown in table 3-20. 3.11.2 ordered exceptions in the mpc565/mpc566, all exceptions except for reset, debug port non-maskable interrupts, and machine check exceptions are ordered. ordered exceptions satisfy the following criteria: only one exception is reported at a time. if, for example, a single instruction encounters multiple exception conditions, those conditions are encountered sequentially. after the exception handler handles an exception, instruction execution continues until the next exception condition is encountered. when the exception is taken, no program state is lost. 3.11.3 unordered exceptions unordered exceptions may be reported at any time and are not guaranteed to preserve program state information. the processor can never recover from a reset exception. it can recover from other unordered exceptions in most cases. however, if a debug port non-maskable interrupt or machine check exception occurs during the servicing of a previous exception, the machine state information in srr0 and srr1 (and, in some cases, the dar and dsisr) may not be recoverable; the processor may be in the process of saving or restoring these registers. to determine whether the machine state is recoverable, the ri (recoverable exception) bit in srr1 can be read. during exception processing, the ri bit in the msr is copied to srr1 and then cleared. the operating system should set the ri bit in the msr at the end of each exception handler?s prologue (after saving the program state) and clear the bit at the start of each exception handler?s epilogue (before restoring the program state). then, if an unordered exception occurs during the servicing of an exception handler, the ri bit in srr1 will contain the correct value. table 3-20. mpc565/mpc566 exception classes class exception type asynchronous, unordered machine check system reset asynchronous, ordered external interrupt decrementer synchronous (ordered, precise) instruction-caused exceptions motorola chapter 3. central processing unit 3-39 exception model 3.11.4 precise exceptions in the mpc565/mpc566, all synchronous (instruction-caused) exceptions are precise. when a precise exception occurs, the processor backs the machine up to the instruction causing the exception. this ensures that the machine is in its correct architecturally-defined state. the following conditions exist at the point a precise exception occurs: 1. architecturally, no instruction following the faulting instruction in the code stream has begun execution. 2. all instructions preceding the faulting instruction appear to have completed with respect to the executing processor. 3. srr0 addresses either the instruction causing the exception or the immediately following instruction. which instruction is addressed can be determined from the exception type and the status bits. 4. depending on the type of exception, the instruction causing the exception may not have begun execution, may have partially completed, or may have completed execution. 3.11.5 exception vector table the setting of the exception prefix (ip) bit in the msr determines how exceptions are vectored. if the bit is cleared, the exception vector table begins at the physical address 0x0000 0000; if ip is set, the exception vector table begins at the physical address 0xfff0 0000. table 3-21 shows the exception vector offset of the first instruction of the exception handler routine for each exception type. note in the mpc565/mpc566, the exception table can additionally be relocated by the bbc module to internal memory and reduce the total size required by the exception table (see section 4.4, ?exception table relocation (etr).? table 3-21. exception vector offset table vector offset (hex) exception type section 00000 reserved ? 00100 system reset, nmi interrupt section 3.15.4.1, ?system reset exception and nmi (0x0100)? 00200 machine check section 3.15.4.2, ?machine check exception (0x0200)? 00300 data storage section 3.15.4.3, ?data storage exception (0x0300)? 00400 reserved instruction storage 1 00500 external interrupt section 3.15.4.5, ?external interrupt (0x0500)? 00600 alignment section 3.15.4.6, ?alignment exception (0x00600)? 3-40 mpc565/mpc566 reference manual motorola instruction timing 3.12 instruction timing the mpc565/mpc566 processor is pipelined. because the processing of an instruction is broken into a series of stages, an instruction does not require the entire resources of the processor. 00700 program section 3.15.4.7, ?program exception (0x0700)? 00800 floating-point unavailable section 3.15.4.8, ?floating-point unavailable exception (0x0800)? 00900 decrementer section 3.15.4.9, ?decrementer exception (0x0900)? 00a00 reserved ? 00b00 reserved ? 00c00 system call section 3.15.4.10, ?system call exception (0x0c00)? 00d00 trace. section 3.15.4.11, ?trace exception (0x0d00)? 00e00 floating-point assist section 3.15.4.12, ?floating-point assist exception (0x0e00)? 01000 implementation-dependent software emulation section 3.15.4.13, ?implementation-dependent software emulation exception (0x1000)? 01100 reserved ? 01200 reserved ? 01300 implementation-dependent instruction protection exception section 3.15.4.14, ?implementation-dependent instruction protection exception (0x1300)? 01400 implementation-dependent data protection error section 3.15.4.15, ?implementation-specific data protection error exception (0x1400)? 01500?01bff reserved ? 01c00 implementation-dependent data breakpoint section 3.15.4.16, ?implementation-dependent debug exceptions? 01d00 implementation-dependent instruction breakpoint section 3.15.4.16, ?implementation-dependent debug exceptions? 01e00 implementation-dependent maskable external breakpoint section 3.15.4.16, ?implementation-dependent debug exceptions? 01f00 implementation-dependent non-maskable external breakpoint section 3.15.4.16, ?implementation-dependent debug exceptions? 1 this exception will not be generated by hardware. table 3-21. exception vector offset table (continued) vector offset (hex) exception type section motorola chapter 3. central processing unit 3-41 instruction timing the instruction pipeline in the mpc565/mpc566 has four stages: 1. the dispatch stage is implemented using a distributed mechanism. the central dispatch unit broadcasts the instruction to all units. in addition, scoreboard information (regarding data dependencies) is broadcast to each execution unit. each execution unit decodes the instruction. if the instruction is not implemented, a program exception is taken. if the instruction is legal and no data dependency is found, the instruction is accepted by the appropriate execution unit, and the data found in the destination register is copied to the history buffer. if a data dependency exists, the machine is stalled until the dependency is resolved. 2. in the execute stage, each execution unit that has an executable instruction executes the instruction. (for some instructions, this occurs over multiple cycles.) 3. in the writeback stage, the execution unit writes the result to the destination register and reports to the history buffer that the instruction is completed. 4. in the retirement stage, the history buffer retires instructions in architectural order. an instruction retires from the machine if it completes execution with no exceptions and if all instructions preceding it in the instruction stream have finished execution with no exceptions. as many as six instructions can be retired in one clock. the history buffer maintains the correct architectural machine state. an exception is taken only when the instruction is ready to be retired from the machine (i.e., after all previously-issued instructions have already been retired from the machine). when an exception is taken, all instructions following the excepting instruction are canceled, (i.e., the values of the affected destination registers are restored using the values saved in the history buffer during the dispatch stage). figure 3-22 shows basic instruction pipeline timing. 3-42 mpc565/mpc566 reference manual motorola instruction timing figure 3-22. basic instruction pipeline table 3-22 indicates the latency and blockage for each type of instruction. latency refers to the interval from the time an instruction begins execution until it produces a result that is available for use by a subsequent instruction. blockage refers to the interval from the time an instruction begins execution until its execution unit is available for a subsequent instruction. note when the blockage equals the latency, it is not possible to issue another instruction to the same unit in the same cycle in which the first instruction is being written back. table 3-22. instruction latency and blockage instruction type precision latency blockage floating-point multiply-add double single 7 6 7 6 floating-point add or subtract double single 4 4 4 4 floating-point multiply double single 5 4 5 4 floating-point divide double single 17 10 17 10 integer multiply ? 2 1 or 2 1 integer divide ? 2 to 11 1 2to11 1 integer load/store ? see note 1 see note 1 i1 i2 i1 i1 i1 store i3 i2 i2 i2 fetch decode read and execute write back (to dest reg) l address drive ldata load write back branch decode branch execute i1 i1 i1 i1 load motorola chapter 3. central processing unit 3-43 user instruction set architecture (uisa) 3.13 user instruction set architecture (uisa) 3.13.1 computation modes the core of the mpc565/mpc566is a 32-bit implementation of the mpc500 architecture. any reference in the mpc500 architecture books (uisa, vea, oea) regarding 64-bit implementations are not supported by the core. all registers except the floating-point registers are 32 bits wide. 3.13.2 reserved fields reserved fields in instructions are described under the specific instruction definition sections. unless otherwise stated in the specific instruction description, fields marked ?i,? ?ii? and ?iii? in the instruction are discarded by the core decoding. thus, this type of invalid form instructions yield results of the defined instructions with the appropriate field zero. in most cases, the reserved fields in registers are ignored on write and return zeros for them on read on any control register implemented by the mpc565/mpc566. exception to this rule are bits [16:23] of the fixed-point exception cause register (xer) and the reserved bits of the machine state register (msr), which are set by the source value on write and return the value last set for it on read. 3.13.3 classes of instructions non-optional instructions are implemented by the hardware. optional instructions are executed by implementation-dependent code and any attempt to execute one of these commands causes the mpc565/mpc566 to take the implementation-dependent software emulation interrupt (offset 0x01000 of the vector table). illegal and reserved instruction class instructions are supported by implementation- dependent code and, thus, the mpc565/mpc566 hardware generates the implementation-dependent software emulation interrupt. invalid and preferred instruction forms treatment by the mpc565/mpc566 is described under the specific processor compliance sections. 3.13.4 exceptions invocation of the system software for any instruction-caused exception in the mpc565/mpc566 is precise, regardless of the type and setting. 1 refer to section 7, ?instruction timing,? in the rcpu reference manual (rcpurm/ad) for details. 3-44 mpc565/mpc566 reference manual motorola user instruction set architecture (uisa) 3.13.5 the branch processor the mpc565/mpc566 implements all the instructions defined for the branch processor in the uisa in the hardware. 3.13.6 instruction fetching the core fetches a number of instructions into its internal buffer (the instruction pre-fetch queue) prior to execution. if a program modifies the instructions it intends to execute, it should call a system library program to ensure that the modifications have been made visible to the instruction fetching mechanism prior to execution of the modified instructions. 3.13.7 branch instructions the core implements all the instructions defined for the branch processor by the uisa in the hardware. for performance of various instructions, refer to table 3-22 of this manual. 3.13.7.1 invalid branch instruction forms bits marked with z in the bo encoding definition are discarded by the mpc565/mpc566 decoding. thus, these types of invalid form instructions yield results of the defined instructions with the z-bit zero. if the decrement and test ctr option is specified for the bcctr or bcctrl instructions, the target address of the branch is the new value of the ctr. condition is evaluated correctly, including the value of the counter after decrement. 3.13.7.2 branch prediction the core uses the y bit to predict path for pre-fetch. prediction is only done for not-ready branch conditions. no prediction is done for branches to the link or count register if the target address is not ready. refer to the rcpu reference manual (conditional branch control) for more information. 3.13.8 the fixed-point processor 3.13.8.1 fixed-point instructions the core implements the following instructions: fixed-point arithmetic instructions fixed-point compare instructions fixed-point trap instructions fixed-point logical instructions motorola chapter 3. central processing unit 3-45 user instruction set architecture (uisa) fixed-point rotate and shift instructions move to/from system register instructions all instructions are defined for the fixed-point processor in the uisa in the hardware. for performance of the various instructions, refer to table 3-22. ? move to/from system register instructions. move to/from invalid special registers in which spr0 = 1 yields invocation of the privilege instruction error interrupt handler if the processor is in problem state. for a list of all implemented special registers, refer to table 3-2, and table 3-3. fixed-point arithmetic instructions. if an attempt is made to perform any of the divisions in the divw[o][.] instruction (0x80000000 -1, 3-46 mpc565/mpc566 reference manual motorola user instruction set architecture (uisa) 3.13.10.2 fixed-point load and store multiple instructions for these types of instructions, ea must be a multiple of four. if it is not, the system alignment error handler is invoked. for a lmw instruction (if ra is in the range of registers to be loaded), the instruction completes normally. ra is then loaded from the memory location as follows: ra mem(ea+(ra-rt)*4, 4) 3.13.10.3 fixed-point load string instructions load string instructions behave the same as load multiple instructions, with respect to invalid format in which ra is in the range of registers to be loaded. when ra is in range, it is updated from memory. 3.13.10.4 storage synchronization instructions for these type of instructions, ea must be a multiple of four. if it is not, the system alignment error handler is invoked. 3.13.10.5 floating-point load and store with update instructions for load and store with update instructions, if rt = 0 then the ea is written into r0. 3.13.10.6 floating-point load single instructions when the operand falls in the range of a single denormalized number, the floating-point assist interrupt handler is invoked. refer to the rcpu reference manual (floating-point assist for denormalized operands) for complete description of handling denormalized floating-point numbers. 3.13.10.7 floating-point store single instructions when the operand falls in the range of a single denormalized number, the floating-point assist interrupt handler is invoked. when the operand is zero it is converted to the correct signed zero in single-precision format. when the operand is between the range of single denormalized and double denormalized it is considered a programming error. the hardware will handle this case as if the operand was single denormalized. when the operand falls in the range of double denormalized numbers it is considered a programming error. the hardware will handle this case as if the operand was zero. motorola chapter 3. central processing unit 3-47 virtual environment architecture (vea) the following check is done on the stored operand in order to determine whether it is a denormalized single-precision operand and invoke the floating-point assist interrupt handler: (frs[1:11] 0) and (frs[1:11] 896) refer to the rcpu reference manual (floating-point assist for denormalized operands) for complete description of handling denormalized floating-point numbers. 3.13.10.8 optional instructions no optional instructions are supported. 3.14 virtual environment architecture (vea) 3.14.1 atomic update primitives both the lwarx and stwcx instructions are implemented according to the mpc500 architecture requirements. the mpc565/mpc566 does not provide support for snooping an external bus activity outside the chip. the provision is made to cancel the reservation inside the mpc565/mpc566 by using the cr_b and kr_b input pins. 3.14.2 effect of operand placement on performance the load/store unit hardware supports all of the mpc500 load/store instructions. an optimal performance is obtained for naturally aligned operands. these accesses result in optimal performance (one bus cycle) for up to four bytes in size and good performance (two bus cycles) for double precision floating-point operands. unaligned operands are supported in hardware and are broken into a series of aligned transfers. the effect of operand placement on performance is as stated in the vea, except for the case of 8-byte operands. in that case, since the mpc565/mpc566 uses a 32-bit wide data bus, the performance is good rather than optimal. 3.14.3 storage control instructions the mpc565/mpc566 does not implement cache control instructions (icbi, dcbt, dcbi, dcbf, dcbz, dcbst, and dcbtst) . 3.14.4 instruction synchronize ( isync ) instruction the isync instruction causes a reflect which waits for all prior instructions to complete and then executes the next sequential instruction. any instruction after an isync will see all effects of prior instructions. 3-48 mpc565/mpc566 reference manual motorola operating environment architecture (oea) 3.14.4.1 enforce in-order execution of i/o ( eieio ) instruction when executing an eieio instruction, the load/store unit will wait until all previous accesses have terminated before issuing cycles associated with load/store instructions following the eieio instruction. 3.14.5 timebase a description of the timebase register may be found in chapter 6, ?system configuration and protection ,? and in chapter 8, ?clocks and power control.? 3.15 operating environment architecture (oea) the mpc565/mpc566 has an internal memory space that includes memory-mapped control registers and internal memory used by various modules on the chip. this memory is part of the main memory as seen by the mpc565/mpc566 but cannot be accessed by any external system master. 3.15.1 branch processor registers 3.15.1.1 machine state register (msr) the floating-point exception mode encoding in the mpc565/mpc566 core is as follows: : the sf bit is reserved set to zero the ip bit initial state after reset is set as programmed by the reset configuration as specified by the usiu characteristics. 3.15.1.2 branch processors instructions the mpc565/mpc566 implements all the instructions defined for the branch processor in the uisa in the hardware. table 3-23. floating-point exception mode encoding mode fe0 fe1 ignore exceptions 0 0 precise 0 1 precise 1 0 precise 1 1 motorola chapter 3. central processing unit 3-49 operating environment architecture (oea) 3.15.2 fixed-point processor 3.15.2.1 special purpose registers unsupported registers ? the following registers are not supported by the mpc565/mpc566: sdr, ear, ibat0u, ibat0l, ibat1u, ibat1l, ibat2u, ibat2l, ibat3u, ibat3l, dbat0u, dbat0l, dbat1u, dbat1l, dbat2l, dbat3u, dbat3l. added registers ? for a list of added special purpose registers, refer to table 3-2, and table 3-3. 3.15.3 storage control instructions storage control instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlbsync are not implemented by the mpc565/mpc566. 3.15.4 exceptions the following paragraphs define the types of oea exceptions the exception table vector defines the offset value by exception type. refer to table 3-21. 3.15.4.1 system reset exception and nmi (0x0100) a system reset exception occurs when: any reset pin is asserted ? poreset ,hreset ,orsreset an internal reset is requested, such as from the software watchdog timer settings caused by reset as shown in table 3-24. table 3-24. settings caused by reset register setting msr ip depends on internal data bus configuration word me is cleared dcmpen is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) all other bits are cleared srr0 undefined srr1 undefined fpecr 0x0000 0000 ictrl 0x0000 0000 lctrl1 0x0000 0000 lctrl2 0x0000 0000 3-50 mpc565/mpc566 reference manual motorola operating environment architecture (oea) a non-maskable interrupt (nmi) occurs when the irq [0] is asserted and the following registers are set. execution begins at physical address 0x0100 if the hard reset configuration word ip bit is cleared to 0. execution begins at physical address 0xfff0 0100 if the hard reset configuration word ip bit is set to 1. 3.15.4.2 machine check exception (0x0200) a machine-check exception is assumed to be caused by one of the following conditions: the accessed address does not exist. a data error was detected. a storage protection violation was detected by chip-select logic. when a machine-check exception occurs, the processor does one of the following: takes a machine check exception; enters the checkstop state; or enters debug mode. counta[16:31] 0x0000 0000 countb[16:31] 0x0000 0000 table 3-25. register settings following an nmi register name bits description save/restore register 0 (srr0) all set to the effective address of the next instruction the processor executes if no interrupt conditions are present save/restore register 1 (srr1) 1:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 table 3-24. settings caused by reset (continued) register setting motorola chapter 3. central processing unit 3-51 operating environment architecture (oea) which action is taken depends on the value of the msr[me] bit, whether or not debug mode was enabled at reset, and (if debug mode is enabled) the values of the chstpe (checkstop enable) and mcie (machine check enable) bits in the debug enable register (der). table 3-26 summarizes the possibilities. when the processor is in the checkstop state, instruction processing is suspended and cannot be restarted without resetting the core. an indication is sent to the siu which may generate an automatic reset in this condition. refer to chapter 7, ?reset,? for more details. the register settings for machine check exceptions are shown in table 3-27. table 3-26. machine check exception processor actions msr[me] debug mode enable chstpe mcie action performed when exception detected 00xx enter checkstop state 10xx branch to machine-check exception handler 010x enter checkstop state 011x enter debug mode 11x0 branch to machine-check exception handler 11x1 enter debug mode table 3-27. register settings following a machine check exception register name bits description save/restore register 0 (srr0) 1 all set to the effective address of the instruction that caused the interrupt save/restore register 1 (srr1) 1 set to 1 for instruction fetch-related errors and 0 for load/store-related errors 2:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 3-52 mpc565/mpc566 reference manual motorola operating environment architecture (oea) when a machine check exception is taken, instruction execution resumes at offset 0x0200 from the base address indicated by msr[ip]. 3.15.4.3 data storage exception (0x0300) a data storage exception is never generated by the hardware. the software may branch to this location as a result of implementation-specific data storage protection error exception. 3.15.4.4 instruction storage exception (0x0400) an instruction storage interrupt is never generated by the hardware. the software may branch to this location as a result of an implementation-specific instruction storage protection error exception. 3.15.4.5 external interrupt (0x0500) the external interrupt exception is taken on assertion of the internal irq line to the rcpu. theinterruptmaybecausedbytheassertionofanexternalirq pin, by a usiu timer, or by an external chip peripheral. refer to section 6.4, ?enhanced interrupt controller,? for more information on the interrupt controller. the interrupt may be delayed by other higher priority exceptions or if the msr[ee] bit is cleared when the exception occurs. msr[ee] is automatically cleared by hardware to disable external interrupts when any exception is taken. upon detecting an external interrupt, the processor assigns it to the instruction at the head of the history buffer (after retiring all instructions that are ready to retire). the register settings for the external interrupt exception are shown in table 3-28. data/storage interrupt status register (dsisr) 2 0:14 cleared to 0 15:16 set to bits [29:30] of the instruction if x-form and to 0b00 if d-form 17 set to bit 25 of the instruction if x-form and to bit 5 if d-form 18:21 set to bits [21:24] of the instruction if x-form and to bits [1:4] if d-form 22:31 set to bits [6:15] of the instruction data address register (dar) 2 all set to the effective address of the data access that caused the interrupt 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. 2 dsisr and dar registers are only updated when the machine check exception is caused by a data access violation. table 3-27. register settings following a machine check exception (continued) register name bits description motorola chapter 3. central processing unit 3-53 operating environment architecture (oea) the enhanced interrupt controller mode is available for interrupt-driven applications on mpc565/mpc566. it allows the single external interrupt exception vector 0x500 to be split into up to 48 different vectors corresponding to 48 interrupt sources in order to speed up interrupt processing. it also supports low priority source masking feature in hardware to handle nested interrupts more easily. see section 6.4, ?enhanced interrupt controller,? and chapter 4, ?burst buffer controller 2 module.? when an external interrupt is taken, instruction execution resumes at offset 0x00500 from the physical base address indicated by msr[ip]. 3.15.4.6 alignment exception (0x00600) the following conditions cause an alignment exception: the operand of a floating-point load or store instruction is not word-aligned. the operand of a load or store multiple instruction is not word-aligned. the operand of lwarx or stwcx. is not word-aligned. alignment exceptions use the srr0 and srr1 to save the machine state and the dsisr to determine the source of the exception. the register settings for alignment exceptions are shown in table 3-29. table 3-28. register settings following external interrupt register bits setting description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. all set to the effective address of the instruction that the processor would have attempted to execute next if no interrupt conditions were present. save/restore register 1 (srr1) [0:15] cleared to 0 [16:31] loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other clearedto0 3-54 mpc565/mpc566 reference manual motorola operating environment architecture (oea) table 3-29. register settings for alignment exception register bits setting description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. set to the effective address of the instruction that caused the exception. save/restore register 1 (srr1) [0:15] cleared to 0 [16:31] loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 data/storage interrupt status register (dsisr) [0:11] cleared to 0 [12:13] cleared to 0 14 cleared to 0 [15:16] for instructions that use register indirect with index addressing, set to bits [29:30] of the instruction. for instructions that use register indirect with immediate index addressing, cleared. 17 for instructions that use register indirect with index addressing, set to bit 25 of the instruction. for instructions that use register indirect with immediate index addressing, set to bit 5 of the instruction. [18:21] for instructions that use register indirect with index addressing, set to bits [21:24] of the instruction. for instructions that use register indirect with immediate index addressing, set to bits [1:4] of the instruction. [22:26] set to bits [6:10] (source or destination) of the instruction. [27:31] set to bits [11:15] of the instruction (ra). set to either bits [11:15] of the instruction or to any register number not in the range of registers loaded by a valid form instruction, for lmw, lswi, and lswx instructions. otherwise undefined. motorola chapter 3. central processing unit 3-55 operating environment architecture (oea) note for load or store instructions that use register indirect with index addressing, the dsisr can be set to the same value that would have resulted if the corresponding instruction uses register indirect with immediate index addressing had caused the exception. similarly, for load or store instructions that use register indirect with immediate index addressing, dsisr can hold a value that would have resulted from an instruction that uses register indirect with index addressing. (if there is no corresponding instruction, no alternative value can be specified.) when an alignment exception is taken, instruction execution resumes at offset 0x00600 from the physical base address indicated by msr[ip]. 3.15.4.7 program exception (0x0700) a program exception occurs when no higher priority exception exists and one or more of the following exception conditions, which correspond to bit settings in srr1, occur during execution of an instruction: system floating-point enabled exception ? a system floating-point enabled exception is generated when the following condition is met as a result of a move to fpscr instruction, move to msr (mtmsr) instruction, or return from interrupt (rfi) instruction: (msr[fe0] | msr[fe1]) & fpscr[fex] = 1. notice that in the rcpu implementation of the mpc500 architecture, a program interrupt is not generated by a floating-point arithmetic instruction that results in the condition shown above; a floating-point assist exception is generated instead. privileged instruction ? a privileged instruction type program exception is generated by any of the following conditions: ? the execution of a privileged instruction (mfmsr, mtmsr, or rfi) is attempted and the processor is operating at the user privilege level (msr[pr] = 1). ? the execution of mtspr or mfspr where spr0 = 1 in the instruction encoding (indicating a supervisor-access register) and msr[pr] = 1 (indicating the processor is operating at the user privilege level), provided the spr instruction field encoding represents either: ? a valid internal-to-the-processor special-purpose register; or ? an external-to-the-processor special-purpose register (either valid or invalid). trap ? a trap type program exception is generated when any of the conditions specified in a trap instruction is met. 3-56 mpc565/mpc566 reference manual motorola operating environment architecture (oea) notice that, in contrast to some other mpc500 processors, the rcpu generates a software emulation exception, rather than a program exception, when an attempt is made to execute any unimplemented instruction. this includes all illegal instructions and optional instructions not implemented in the rcpu. the register settings for program exceptions are shown in table 3-30. when a program exception is taken, instruction execution resumes at offset 0x0700 from the physical base address indicated by msr[ip]. 3.15.4.8 floating-point unavailable exception (0x0800) a floating-point unavailable exception occurs when no higher priority exception exists, an attempt is made to execute a floating-point instruction (including floating-point load, store, and move instructions), and the floating-point available bit in the msr is disabled, (msr[fp] = 0). table 3-30. register settings following program exception register bits setting description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. all contains the effective address of the excepting instruction save/restore register 1 (srr1) 2 2 only one of bits 11, 13, and 14 can be set. [0:10] cleared to 0 11 set for a floating-point enabled program exception; otherwise cleared. 12 cleared to 0. 13 set for a privileged instruction program exception; otherwise cleared. 14 set for a trap program exception; otherwise cleared. 15 cleared to 0 if srr0 contains the address of the instruction causing the exception, and set if srr0 contains the address of a subsequent instruction. [16:31] loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri]. machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 motorola chapter 3. central processing unit 3-57 operating environment architecture (oea) 3.15.4.9 decrementer exception (0x0900) a decrementer exception occurs when no higher priority exception exists, the decrementer register has completed decrementing, and msr[ee] = 1. the decrementer exception request is canceled when the exception is handled. the decrementer register counts down, causing an exception (unless masked) when passing through zero. the decrementer implementation meets the following requirements: loading a gpr from the decrementer does not affect the decrementer. storing a gpr value to the decrementer replaces the value in the decrementer with the value in the gpr. whenever bit 0 of the decrementer changes from zero to one, an exception request is signaled. if multiple decrementer exception requests are received before the first can be reported, only one exception is reported. the occurrence of a decrementer exception cancels the request. if the decrementer is altered by software and if bit 0 is changed from zero to one, an interrupt request is signaled. the register settings for the decrementer exception are shown in table 3-32. table 3-31. register settings following a floating-point unavailable exception register bits setting description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. all set to the effective address of the instruction that caused the exception. save/restore register 1 (srr1) [0:15] cleared to 0 [16:31] loaded from msr[16:31] machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 3-58 mpc565/mpc566 reference manual motorola operating environment architecture (oea) when a decrementer exception is taken, instruction execution resumes at offset 0x0900 from the physical base address indicated by msr[ip]. 3.15.4.10 system call exception (0x0c00) a system call exception occurs when a system call instruction is executed. the effective address of the instruction following the sc instruction is placed into srr0. msr[16:31] are placed into srr1[16:31], and srr1[0:15] are set to undefined values. then a system call exception is generated. the system call instruction is context synchronizing. that is, when a system call exception occurs, instruction dispatch is halted and the following synchronization is performed: 1. the exception mechanism waits for all instructions in execution to complete to a point where they report all exceptions they will cause. 2. the processor ensures that all instructions in execution complete in the context in which they began execution. 3. instructions dispatched after the exception is processed are fetched and executed in the context established by the exception mechanism. register settings are shown in table 3-33. table 3-32. register settings following a decrementer exception register bits setting description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. all set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present. save/restore register 1 (srr1) [0:15] cleared to 0 [16:31] loaded from msr[16:31] machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 motorola chapter 3. central processing unit 3-59 operating environment architecture (oea) when a system call exception is taken, instruction execution resumes at offset 0x00c00 from the physical base address indicated by msr[ip]. 3.15.4.11 trace exception (0x0d00) a trace interrupt occurs if msr[se] = 1 and any instruction except rfi is successfully completed or msr[be]= 1 and a branch is completed. notice that the trace interrupt does not occur after an instruction that caused an interrupt (for instance, sc). monitor/debugger software must change the vectors of other possible interrupt addresses to single-step such instructions. if this is unacceptable, other debug features can be used. refer to chapter 22, ?development support,? for more information. see table 3-34 for trace-exception register settings. table 3-33. register settings following a system call exception register setting description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. all set to the effective address of the instruction following the system call instruction save/restore register 1 (srr1) [0:15] undefined [16:31] loaded from msr[16:31] machine state register (msr) ip no change me no change le set to value of ile bit prior to the exception dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 table 3-34. register settings following a trace exception register name bits description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. all set to the effective address of the instruction following the executed instruction save/restore register 1 (srr1) 1:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 3-60 mpc565/mpc566 reference manual motorola operating environment architecture (oea) execution resumes at offset 0x0d00 from the base address indicated by msr[ip]. 3.15.4.12 floating-point assist exception (0x0e00) a floating point assist exception occurs in the following cases: when the following conditions are true: ? a floating-point enabled exception condition is detected; ? the corresponding floating-point enable bit in the fpscr (floating point status and control register) is set (exception enabled); and ? msr[fe0] | msr[fe1] = 1 these conditions are summarized in the following equation: (msr[fe0] | msr[fe1]) &fpscr[fex] = 1 notethatwhen((msr[fe0]|msr[fe1])&fpscr[fex])issetasaresultofmoveto fpscr, move to msr or rfi, a program exception is generated, rather than a floating-point assist exception. when a tiny result is detected and the floating point underflow exception is disabled (fpscr[ue] = 0) the register settings for floating-point assist exceptions are shown in table 3-35. when a floating-point exception is taken, instruction execution resumes at offset 0x0e00 from the base address indicated by msr[ip]. table 3-35. register settings following floating-point assist exceptions register name bits description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. all set to the effective address of the instruction that caused the interrupt save/restore register 1 (srr1) 1:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 motorola chapter 3. central processing unit 3-61 operating environment architecture (oea) 3.15.4.13 implementation-dependent software emulation exception (0x1000) an implementation-dependent software emulation exception occurs in the following instances: when executing any non-implemented instruction. this includes all illegal and unimplemented optional instructions and all floating-point instructions. when executing a mtspr or mfspr instruction that specifies an un-implemented internal-to-the-processor spr, regardless of the value of bit 0 of the spr. when executing a mtspr or mfspr that specifies an un-implemented external-to-the-processor register and spr0 = 0 or msr[pr] = 0 (no program interrupt condition). see table 3-36 for software emulation exception register settings. execution resumes at offset 0x01000 from the base address indicated by msr[ip]. 3.15.4.14 implementation-dependent instruction protection exception (0x1300) the implementation-specific instruction storage protection error interrupt occurs in the following cases: the fetch access violates storage protection and msr[ir] = 1. the fetch access is to guarded storage and msr[ir] = 1. table 3-36. register settings following a software emulation exception register name bits description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. all set to the effective address of the instruction that caused the interrupt save/restore register 1 (srr1) 1:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri]. machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 3-62 mpc565/mpc566 reference manual motorola operating environment architecture (oea) the register settings for instruction protection exceptions are shown in table 3-37. execution resumes at offset 0x1300 from the base address indicated by msr[ip]. 3.15.4.15 implementation-specific data protection error exception (0x1400) the implementation-specific data protection error exception occurs in the following case: the data access violates the storage protection and msr[dr]=1. see chapter 11, ?l-bus to u-bus interface (l2u).? see table 3-38 for data-protection-error exception register settings. table 3-37. register settings following an instruction protection exception register name bits description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. all set to the effective address of the instruction that caused the exception save/restore register 1 (srr1) 0:2 cleared to 0 3 set to 1 if the fetch access was to a guarded storage when msr[ir] = 1, otherwise clear to 0 4 set to 1 if the storage access is not permitted by the protection mechanism (impu in bbc) and msr[ir] = 1; otherwise clear to 0 5:15 cleared to 0 16:31 loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ir] machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 motorola chapter 3. central processing unit 3-63 operating environment architecture (oea) when a data protection error exception is taken, instruction execution resumes at offset 0x1400 from the base address indicated by msr[ip]. 3.15.4.16 implementation-dependent debug exceptions implementation-dependent debug exceptions occur in the following cases: when there is an internal breakpoint match (for more details, refer to chapter 22, ?development support.? when a peripheral breakpoint request is asserted to the mpc565/mpc566 core. when the development port request is asserted to the mpc565/mpc566 core. refer to chapter 22, ?development support,? for details on how to generate the development port-interrupt request. see table 3-39 for debug-exception register settings. table 3-38. register settings following a data protection error exception register name bits description save/restore register 0 (srr0) 1 1 if the exception occurs during a data access in ?decompression on? mode, the srr0 register will contain the address of the load/store instruction in compressed format. if the exception occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain an indeterminate value. all set to the effective address of the instruction that caused the exception save/restore register 1 (srr1) 0:15 cleared to 0 other loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ri] machine state register (msr) ip no change me no change le bit is copied from ile dcmpen this bit is set according to (bbcmcr[en_comp] & bbcmcr[exc_comp]) other cleared to 0 data/storage interrupt status register (dsisr) 0:3 cleared to 0 4 set to 1 if the storage access is not permitted by the protection mechanism. otherwise cleared to 0 5 cleared to 0 6 set to 1 for a store operation and cleared to 0 for a load operation 7:31 cleared to 0 data address register (dar) all set to the effective address of the data access that caused the exception 3-64 mpc565/mpc566 reference manual motorola operating environment architecture (oea) for l-bus breakpoint instances, these registers are set to: execution resumes at offset from the base address indicated by msr[ip] as follows: 0x01c00 ? for data breakpoint match 0x01d00 ? for instruction breakpoint match 0x01e00 ? for development port maskable request or a peripheral breakpoint 0x01f00 ? for development port non-maskable request table 3-39. register settings following a debug exception register name bits description save/restore register 0 (srr0) 1 1 if an error occurs during an instruction fetch in ?decompression on? mode, the srr0 register will contain the instruction address in compressed format. all for i-breakpoints, set to the effective address of the instruction that caused the interrupt. for l-breakpoint, set to the effective address of the instruction following the instruction that caused the interrupt. for development port maskable request or a peripheral breakpoint, set to the effective address of the instruction that the processor would have executed next if no interrupt conditions were present. if the development port request is asserted at reset, the value of srr0 is undefined. save/restore register 1 (srr1) 1:4 cleared to 0 10:15 cleared to 0 other loaded from bits [16:31] of msr. in the current implementation, bit 30 of the srr1 is never cleared, except by loading a zero value from msr[ ri] . if the development port request is asserted at reset, the value of srr1 is undefined. machine state register (msr) ip no change me no change le bit is copied from ile other cleared to 0 table 3-40. register settings for l-bus breakpoint instances register name bits description bar set to the effective address of the data access as computed by the instruction that caused the interrupt dar and dsisr do not change motorola chapter 3. central processing unit 3-65 operating environment architecture (oea) 3.15.5 partially executed instructions in general, the architecture permits instructions to be partially executed when an alignment or data storage interrupt occurs. in the core, instructions are not executed at all if an alignment interrupt condition is detected and data storage interrupt is never generated by the hardware. in the mpc565/mpc566, the instruction can be partially executed only in the case of the load/store instructions that cause multiple accesses to the memory subsystem. these instructions are: multiple/string instructions unaligned load/store instructions in the last case, the store instruction can be partially completed if one of the accesses (except the first one) causes the data storage protection error. the implementation-specific data storage protection interrupt is taken in this case. for the update forms, the update register (ra) is not altered. 3.15.6 timer facilities descriptions of the timebase and decrementer registers can be found in chapter 6, ?system configuration and protection ,? and in chapter 8, ?clocks and power control.? 3.15.7 optional facilities and instructions any other oea optional facilities and instructions (except those that are discussed here) are not implemented by the mpc565/mpc566hardware. attempting to execute any of these instructions causes an implementation dependent software emulation interrupt to be taken. 3-66 mpc565/mpc566 reference manual motorola operating environment architecture (oea) motorola chapter 4. burst buffer controller 2 module 4-1 chapter 4 burst buffer controller 2 module the burst buffer controller module (bbc) consists of three main functional parts: the bus interface unit (biu), the instruction memory protection unit (impu) and the instruction code decompressor unit (icdu). see figure 4-1. the bbc master biu interfaces between the rcpu instruction port and an internal u-bus and can support burstable and non-burstable accesses on the u-bus. the impu allows the instruction memory to be divided into four regions with different protection attributes. the impu compares the attributes of the rcpu memory access request with the attributes of the appropriate region. if the access is allowed, the proper signals are sent to the biu. if the memory region is protected, an interrupt is sent to the rcpu and the master biu cancels u-bus access. the impu is able to relocate the rcpu exception vectors. the impu always maps the exception vectors into the internal memory space of the mpc565/mpc566. this feature is important for a multi-mpc565/mpc566 system, where, although the internal memories of some of controllers are not shifted to be on the lower four mbytes, they can still have their own internal exception vector tables with the same exception addresses issued by their rcpu cores. the impu also supports an mpc565/mpc566-enhanced interrupt controller by extending an exception vector?s relocation mechanism to translate the rcpu external interrupt exception vector separately and splitting it in up to 48 different vectors, corresponding to the code generated by the interrupt controller. see also section 6.4.4, ?enhanced interrupt controller.? for the mpc566, icdu is responsible for on-line (previously compressed) instruction code decompression in the ?decompression on? mode note the code compression features of the mpc566 are different than the code compression of the mpc556. the icdu contains a four-kbyte ram (decram). decram is used for decompressor vocabulary table storage when compression is enabled or as general-purpose memory on u-bus when compression is disabled. 4-2 mpc565/mpc566 reference manual motorola the bbc includes a special branch target buffer (btb) to improve the mpc565/mpc566 performance mode by holding and supplying previously accessed or decompressed instructions to the rcpu core. the btb can be enabled in either decompression on or off mode. figure 4-1. bbc module block diagram impu registers u-bus slave machine address buffer to addresses impu decomp. ram 2kbytes decompressor control logic icdu btb rcpu core (sequencer) data buffer 1x32 address & data buffers control pipelined & burstable access control u-bus master machine biu bbc u-bus u-bus controls l/u interface siu interface 32 u-bus data compress/ uncompress data compression address sequencer address pi_btb_ addr 30 32 32 32 32 motorola chapter 4. burst buffer controller 2 module 4-3 key features 4.1 key features 4.1.1 biu key features supports pipelined and burstable accesses to internal and external memories supports the de-coupled interface with the rcpu instruction unit parked master on the u-bus, resulting with zero clock delays for rcpu fetch accesses to the u-bus full utilization of the u-bus pipeline for fetch accesses tight interface with the l2u module, taking advantage of full u-bus bandwidth and back-to-back accesses avoiding undesirable bubbles supports program trace and show cycles supports a special attribute for debug port fetch accesses. programming is done using the mpc500?s mtspr/mfspr instructions to/from implementation-specific special-purpose registers. 4.1.2 impu key features there are four regions in which the base address and size can be programmed available region sizes are: 2 kbytes, 8 kbytes, 16 kbytes, 32 kbytes, 64 kbytes, 128 kbytes, 256 kbytes, 512 kbytes, 1 mbyte, 2 mbytes, 4 mbytes, 8 mbytes, 16 mbytes....4 gbytes overlap between regions is allowed each of the four regions supports the following attributes: ? user/supervisor ? guard attribute (causes an interrupt in case of speculative fetch attempt) ? compressed/non-compressed can be enabled or disabled by software global region entry declares the default access attributes for all memory areas not covered by the four regions: the rcpu gets the instruction storage protection exception generated upon: ? an access violation of protection attributes ? a fetch from a guarded region the rcpu msr[ir] bit controls impu protection programming is done using the mpc500?s mtspr/mfspr instructions to/from implementation specific special-purpose registers. compressed/non-compressed region with an enable/disable option 4-4 mpc565/mpc566 reference manual motorola key features exception table relocation: the impu supplies relocation addresses of all the exceptions within the internal memory space external interrupt vector splitting to reduce the external interrupt latency a special reset exception vector for ?decompression on? mode 4.1.3 icdu key features (mpc566 only) instruction code on-line decompression based on an ?instruction class? algorithm. no need for address translation between compressed and non-compressed address spaces ? icdu provides the ?next instruction address? to the rcpu instruction decompression takes one clock mostly code decompression is pipelined: ? no performance penalty during sequential program flow execution ? minimal performance penalty due to change of program flow execution two operation modes are available: ?decompression on? and ?decompression off?. switches between compressed and non-compressed user application software is possible. 4.1.3.1 decram key features four kbytes ram for decompression vocabulary tables two clock read/write accesses when used as a u-bus general-purpose ram four clock load/store accesses from the l-bus byte, half-word (16-bit) or word (32-bit) read/write accesses and fetches special access protection functions low power standby operation for data retention 4.1.4 branch target buffer key features consists of eight ?branch target entries? (bte). each entry contains: ? a 32-bit register that stores the target of historical cof (address) ? four ram entries, 38 bits each, which hold up to four valid instruction opcodes (32 bits). the six extra bits are used by icdu in ?decompression on? mode. ? a 32-bit register which stores the values used to calculate the address following the last valid instruction. fifo removal policy management is implemented for the eight btes software-controlled btb enable/disable and invalidate user transparent ? no user management is required motorola chapter 4. burst buffer controller 2 module 4-5 class-based compression model main principles 4.2 class-based compression model main principles this section is valid for the mpc566 only. 4.2.1 compression model features (mpc566 only) implemented for mpc500 architecture up to 50% code size reduction no need for address translation tables no changes in the cpu architecture compression is done off-line by a special ?compressor? tool, using instruction class-based algorithms optimized for the mpc500 instruction set decompression is done at run-time by special hardware optimized for cache-less systems: ? highly effective in system solutions for a low-cache hit ratio environment and for systems with fast embedded program memory ? deterministic program execution ? no performance penalty during sequential program flow execution ? minimal performance penalty due to change of program flow execution switches between compressed and non-compressed user application sections is possible. (a compressed subroutine can call a non-compressed one and be called from non-compressed portions of the user application) adaptive vocabularies, generated for a particular application slight changes in the core and existing risc development tools ? compilers, simulators, manually coded libraries compressed address space is up to one gbyte branch displacement from its target: ? conditional branch displacement is up to four kbytes ? unconditional branch displacement is up to four mbytes note branch displacement is hardware limited. the compiler can enlarge the branch scope by creating branch chains. 4.2.2 model limitations (mpc566 only) no address arithmetic is allowed, because the address map changes during compression and no software tool can identify address arithmetic structures in the code. 4-6 mpc565/mpc566 reference manual motorola class-based compression model main principles 4.2.3 instruction class-based compression algorithm (mpc566 only) the code compression algorithm is based on creating optimal vocabularies of frequently appearing mpc500 risc instructions or instruction halves and replacing these instructions with pointers to the vocabularies. the system contains several sets of vocabularies for different groups of instructions. these groups are referred to as classes. every instruction belongs to exactly one class. compression of the instructions in a class may be in one of the following modes. refer to figure 4-2. 1. compression of the whole instruction into one vocabulary pointer 2. compression of each half of the instruction into a different vocabulary 3. compression of one of the instruction?s halves into a vocabulary pointer and bypass of the other half. bypass is the placing of the field?s non-compressed data in the compressed code. after compression is defined, the non-compressed data field is defined in the class. 4. bypass of the whole instruction. no compression is permitted figure 4-2. instruction compression alternatives (mpc566 only) a 4-bit class identifier is added to the beginning of each compressed instruction in order to enable class identification during decompression. compressed and bypass field lengths may vary. uncompressed instruction compressed instruction 1. 2. 3. 4. legend uncompressed or bypassed code compressed code class identifier or motorola chapter 4. burst buffer controller 2 module 4-7 class-based compression model main principles the compressed instruction is guaranteed to be of an even length of bits. thus, four bits are needed to find the starting location of the instruction inside a memory word. the instruction address in ?decompression on? mode consists of a 28-bit word address (one gbyte of address space) and a 4-bit instruction pointer (ip). see figure 4-3. figure 4-3. compressed address format (mpc566 only) 4.2.4 class code compression algorithm rules (mpc566 only) compressed instruction length may vary between 6 and 36 bits and is even. a compressed instruction can begin at any even location in a memory word. an instruction source may be compressed as a single 32-bit segment or as two independent 16-bit segments. possible partitions of an instruction for compression are: ? one 32- bit bypass segment ? one 32-bit compressed segment ? one 16-bit compressed segment and one 16-bit bypass segment ? two 16-bit compressed segments a bypass field is always the second field of the two possible. length of a bypass field can be zero, 10, 15, 16 or 32 bits. the class prefix in a compressed instruction is 4 bits long. the vocabulary table pointer of each field may be 2 to 9 bits long. compressed instruction adddress memory layout base address 27 31 ip 2*ip bits ? compressed instruction x x+4 x+8 x+c 4-8 mpc565/mpc566 reference manual motorola class-based compression model main principles vocabulary table pointers are reversed in the code. this means the pointer?s lsb will be the first bit. in a class with a single segment of full compression, data is fetched from both memories. every vocabulary table in the decram is 16 bytes (8 entries) aligned (3 lsbs zeroed). 4.2.5 bypass field compression rules (mpc566 only) the bypass field can be either a full bypass, (i.e., the whole segment from the un-compressed instruction appears as is in the compressed instruction), or it can be represented in one of several compression encoding formats. these formats are hard-wired in the decompression module. 4.2.5.1 branch right segment compression #1 for the mpc566, a 15-bit bypass is used to indicate that the aa bit of a branch instruction should be inserted with a value of zero. the decompression process is performed as shown in figure 4-4. figure 4-4. branch right segment compression #1 this bypass is coded by a value of ?13? in the tp2len field of dccr register. 4.2.5.2 branch right segment compression #2 also created for branch instructions on the mpc566, a bypass of 10 bits indicates that the aa bit should be inserted with a value of zero and that the 5-bit word offset should be extended to 10 bits. the decompression process is performed as shown in figure 4-5. 15-bit compressed decompressed 0 13 14 16 29 30 right segment 31 0 lk bypass field motorola chapter 4. burst buffer controller 2 module 4-9 class-based compression model main principles : figure 4-5. branch right segment compression #2 this bypass is coded by a value of ?12? in the tp2len field of dccr register. 4.2.5.3 right segment zero length compression bypass this mpc566 bypass type indicates that no bypass data exists in the compressed instruction. the bypassed segment is16 zero bits. this bypass is coded by a value of ?11? in the tp2len field of dccr register. 4.2.6 instruction classes structures and programming (mpc566 only) the four possible compression layouts of an instruction and their attributes are listed in this section. see section 4.7.2.6, ?decompressor class configuration registers (dccr0-15) (mpc566 only),? for the instruction classes attributes and more programming details. 4.2.6.1 global bypass this mpc566 instruction is not compressed at all. figure 4-6. global bypass instruction layout 10-bit compressed bypass field decompressed 0 8 9 16 29 30 right segment 31 0 4 5 wor d offset 1 ip lk 26 25 22 21 32-bit bypass data 0000 32-bit segment ? to be bypassed uncompressed instruction compressed instruction msb 4-10 mpc565/mpc566 reference manual motorola class-based compression model main principles this class does not have a configuration register. its prefix is hard-wired to ?0000? and no other attributes are needed. 4.2.6.2 single segment full compression ? class_1 this mpc566 instruction is compressed into a single segment. the vocabulary table pointer points to an offset in tables of all rams (decrams). . figure 4-7. class_1 instruction layout the definition of the class includes: tp1 length=2-9 tp2 length=0 tp1 base address, tp2 base address = the two tables? base addresses for ram #1 and ram #2, respectively. as,ds=0 data brought from ram#1 is the 16 msbs of the decompressed instruction and data brought from ram#2 is the 16 lsbs of the decompressed instruction. 4.2.6.3 twin segment full compression ? class_2 this mpc566 instruction is divided into two segments. each segment is compressed and mapped into a different vocabulary. the vocabularies reside in different rams. proper programming can swap the vocabularies? locations. 32-bit segment ? to be compressed 2-to 9-bit tp1 4-bit class uncompressed instruction compressed instruction msb motorola chapter 4. burst buffer controller 2 module 4-11 class-based compression model main principles figure 4-8. class_2 instruction layout the definition of the class includes: tp1 length=2-9 tp2 length=2-9 as=0 for alternative #1: ? tp1 base address = base address of segment #1 vocabulary in ram #1 ? tp2 base address = base address of segment #2 vocabulary in ram #2 ?ds=0 for alternative #2: ? tp1 base address = base address of segment #2 vocabulary in ram #1 ? tp2 base address = base address of segment #1 vocabulary in ram #2 ?ds=1 alternatives #1 and #2 are referred to as class_2a and class_2b respectively. 4.2.6.4 left segment compression and right segment bypass ? class_3 for the mpc566, the instruction is divided into two segments. the left segment is compressed and mapped into a vocabulary. the vocabulary location is programmable. the right segment is either fully bypassed by a 16-bit field or by a shorter field which is decompressed according to fixed rules. 16-bit segment #1 ? to be compressed 2- to 9-bit tp1 for segment #1 4-bit class uncompressed instruction compressed instruction 16-bit segment #2 ? to be compressed msb alternative #1 2- to 9-bit tp2 for segment #2 2- to 9-bit tp1 for segment #2 4-bit class alternative #2 2- to 9-bit tp2 for segment #1 4-12 mpc565/mpc566 reference manual motorola class-based compression model main principles . figure 4-9. class_3 instruction layout the definition of the class includes tp1 length=2-9 tp2 length=11, 12, 13 or 14 indicating a 0, 10, 15 or 16 bit bypass, respectively. tp1 base address = base address of segment #1 vocabulary in ram #1, if it exists there. tp2 base address = base address of segment #1 vocabulary in ram #2, if it exists there. ds=0 as=0 or 1 directing access to the vocabulary in ram #1 or ram #2, respectively. when the vocabulary is located in ram #1, the class will be referred to as class_3a and when the vocabulary is located in ram #2, the class will be referred to as class_3b. 4.2.6.5 left segment bypass and right segment compression ? class_4 this mpc566 instruction is divided into two segments. the left segment is either fully bypassed by a 16-bit field or by a shorter field which is decompressed according to fixed rules. the right segment is compressed and mapped into a vocabulary. the vocabulary location is programmable. the compressed fields must be swapped in the compressed instruction order to follow the rule that bypass appears only in the second field of compressed instruction. 16-bit segment #1 ? to be compressed 2- to 9-bit tp1 for segment #1 4-bit class uncompressed instruction compressed instruction 16-bit segment #2 ? to be bypassed msb 0-, 10-, 15- or 16-bit bypass for segment #2 motorola chapter 4. burst buffer controller 2 module 4-13 class-based compression model main principles . figure 4-10. class_4 instruction layout the definition of the class includes: tp1 length=2-9 tp2 length=11, 12, 13 or 14 indicating a 0, 10, 15 or 16 bit bypass, respectively. tp1 base address = base address of segment #1 vocabulary in ram #1, if it exists there tp2 base address = base address of segment #1 vocabulary in ram #2, if it exists there ds=1 as=0 or 1 directing access to the vocabulary in ram #1 or ram #2, respectively. when the vocabulary is located in ram #1, the class is referred to as class_4b and when the vocabulary is located in ram #2, the class is referred to as class_4a. 4.2.7 instruction layout programming summary (mpc566 only) table 4-11 summarizes the programming for all possible compressed instruction layouts. the un-compressed instruction of two half-words are referred as h1 & h2. the compressed instruction can be built out of: (1) x1 field ? representing a vocabulary pointer for encoding of either h1 or h1+h2; (2) x2 field ? representing a vocabulary pointer for encoding of h2; and (3) bp ? representing a bypass field. vocabularies v1 and v2 refer to the 16 msbits and 16 lsbits of the uncompressed instruction, respectively. 4.2.8 compression process (mpc566 only) the compression process is implemented by the following steps. see figure 4-11. user code compilation/linking 16-bit segment #1 ? to be bypassed 2- to 9-bit tp1 for segment #2 4-bit class uncompressed instruction compressed instruction 16-bit segment #2 ? to be compressed msb 0-, 10-, 15- or 16-bit bypass for segment #1 4-14 mpc565/mpc566 reference manual motorola class-based compression model main principles vocabulary and class generation user application code compression by a software compression tool the vocabulary and class configurations are generated by profiling the static code, based on the instruction class algorithm. the code compression can be done by using either default or specific application vocabularies, generated at the previous step. in case of default vocabularies, the generation step can be omitted, but compression efficiency is reduced. the compression tool replaces regular powerpc instruction with a compressed representation that contains fewer data bits. the tool also updates offset fields in direct branch instructions to include compressed format offset (four bits of ip and word offset). thus, maximum branch offsets in ?decompression on? mode are reduced. the rcpu uses the word offset for direct branch target address computation. the rcpu provides the ip portion of the branch offset field to the decompression unit as it is represented in the branch instruction. figure 4-11. code compression process compiler/ program executable compressor linker to ol vocabulary generator generator classes classes non-compressed program executable compressed vocabulary vocabulary generation tool motorola chapter 4. burst buffer controller 2 module 4-15 class-based compression model main principles 4.2.9 decompression (mpc566 only) the instruction code is stored in the memory in the compressed format the vocabularies are stored in a dedicated icdu ram (decram) the class configuration is stored in a dedicated icdu register (dccr) the decompression is done on-line by the dedicated decompressor unit decompression flow is as follows: (see figure 4-12) ? rcpu provides to the bbc a 2-bit aligned cof 1 address ? the icdu: converts the cof address to a word-aligned physical address to access the memory fetches the compressed instruction code data from the memory, decompresses it and delivers non-compressed instruction code, together with the bit-aligned next instruction address, to the rcpu. figure 4-12. code decompression process 4.2.10 compression environment initialization (mpc566 only) in order to commence the execution of the compressed code, the decram and the class information (in the dccr registers) should be programmed. the data to be programmed is 1 cof = change of flow compressed memory instructions de vocabulary compressor mpc500 embedded cpu bit-aligned cof noncompressed instruction code address cof word aligned physical address compressed instruction compressed space ?next instruction? address code classes (dccr) registers icdu 4-16 mpc565/mpc566 reference manual motorola class-based compression model main principles supplied by the compressor tool and the vocabulary generator. there are two initialization scenarios: 1. wake up in ?decompression off? mode ? if the chip wakes up with decompression disabled, the initialization routine can be executed at any time before entering ?decompression on? mode. after the compression environment is initialized, the operational mode would be changed to ?decompression on?. 2. wake up in ?decompression on? mode ? if the chip wakes up in ?decompression on? mode, it has to perform compressed instructions without the vocabularies and class parameters. thus, all instructions executed until the end of the initialization routine will be compressed in the global bypass format. perform the routine as close as possible to the wake up. 4.2.11 compression/non-compression mode switch (mpc566 only) the mpc566 allows the option to switch between compressed and non-compressed code on the fly. there are two ways to switch between the modes, as shown in section 4.2.11.1, ?compression definition for exception handlers,? and section 4.2.11.2, ?running mixed code.? 4.2.11.1 compression definition for exception handlers the mpc566 can wake up upon reset with all the exception handlers defined to be compressed (or not), so when any exception occurs or completes, the hardware switches to the appropriate mode without software intervention. 4.2.11.2 running mixed code if the compression mode is enabled on the mpc566, the software can switch between compressed and non-compressed code by setting (or clearing) the compression mode bit in the rcpu msr register. this is done by setting/clearing bit [29] in the rcpu srr1 register (srr1 gets loaded into the msr register when the rfi instruction is executed and bit [29] is the dcmpen bit of the msr). the next step is to load srr0 with a target address in compressed/non-compressed format and then executing an rfi instruction. figure 4-13 shows a suggested routine to execute the switch in both directions (must be run in supervisor mode when rcpu msr[pr] bit is cleared). # r30 contains destination address in appropriate format .set turn_on_compression_bit_mask, 4 .set turn_off_compression_bit_mask, 0xfffb mfmsr r31 # to go to compressed code motorola chapter 4. burst buffer controller 2 module 4-17 operation modes ori r31,r31,turn_on_compression_bit_mask #or alternative to go to uncompressed code: andi. r31,r31,turn_off_compression_bit_mask mtspr nri,r0 # disable external interrupts mtspr srr1,r31 mtspr srr0,r30 # destination address load rfi # branch and modify msr figure 4-13. suggested routine for operation mode switches warning when bbcmcr[en_comp] (bit 21) is set, modification of msr[dcmpen] (bit 29) by mtmsr instruction is strictly forbidden. it may cause the machine to hang until reset. 4.3 operation modes 4.3.1 instruction fetch (mpc566 only) the bbc provides two instruction fetch modes: ?decompression off? and ?decompression on?. the operational modes are defined by rcpu msr[dcmpen] bit. if the bit is set, the mode is ?decompression on?. otherwise, it is in ?decompression off?. 4.3.1.1 ?decompression off? mode in this mode, the mpc566?s biu module transfers fetch accesses from the rcpu to the u-bus. when a new access is issued by the rcpu, it is transferred in parallel to both the impu and the biu. the impu compares the address of the access to its region programming. the biu checks if the access can be immediately transferred to the u-bus, otherwise it requests the u-bus for the next clock. for the mpc566, the biu may be programmed for burstable or non-burstable access. if the biu is programmed for burstable access, the u-bus address phase transaction is accompanied by the burst request attribute. if burstable access is allowed by the u-bus slave, the biu continues current access as burstable, otherwise current access is executed as a single access. if any protection violation is detected by the impu, the current u-bus access is aborted by the biu and an exception is signaled to the rcpu. show cycle, program trace and debug port access attributes accompanying the rcpu access are forwarded by the biu along with the u-bus access. 4-18 mpc565/mpc566 reference manual motorola operation modes 4.3.1.2 ?decompression on? mode in this mode, the mpc566?s rcpu sends the two-bit aligned change of flow address to the bbc. the biu transfers the word portion of the address to the u-bus. the bbc continues to pre-fetch the data from the consequent memory addresses regardless of whether the rcpu requests them in order to supply data to the icdu. in the mpc566, the data coming from the instruction memory is not provided directly to the rcpu, but loaded into the icdu for decompression. decompressed instruction code together with ?next instruction address? are provided to the rcpu whenever it requires another instruction fetch. all addresses issued by the biu to the u-bus are transferred in parallel to the impu. the impu compares the address of the access to its region programming. if any protection violation is detected by the impu, the current u-bus access is aborted by the biu and an exception is signaled to the rcpu. show cycle and program trace access attributes accompanying the cof rcpu access only are forwarded by the biu along with the u-bus access. additional information about the ip of the compressed instruction address is provided on the u-bus data bus. refer to section 4.3.1.3, ?show cycles in ?decompression on? mode,? for more details. in this mode the mpc566?s icdu decram is used as a decompressor vocabulary storage and may not be used as a general purpose ram. 4.3.1.3 show cycles in ?decompression on? mode in the mpc566?s ?decompression on? mode, the instruction address consists of an instruction base address and four bits of the instruction bit pointer. in order to provide the capability to show full instruction address, including instruction bit pointer on the external bus, show cycle information is presented not only on the address bus, but also on some bits of the data bus: addr[0:29] ? show the value of the base address of compressed instruction (word pointer into the memory) data[0] ? shows in which mode the mpc566 is operating 0 = ?decompression off? mode 1 = ?decompression on? mode data[1:4] ? represent an instruction bit pointer within the word. note the bbcmcr[decomp_sc_en] bit determines if the data portion (data[0:4]) of the instruction show cycle is driven or not, regardless of decompression mode (bbcmcr[en_comp] bit) motorola chapter 4. burst buffer controller 2 module 4-19 operation modes if the bbcmcr[decomp_sc_en] bit is set, the show cycle may be delayed by one clock by the usiu. this happens if the show cycle occurs after an external device read cycle. 4.3.2 burst operation of the bbc the bbc may initiate and handle burst accesses on the u-bus. the bbcmcr[be] bit determines whether the bbc operates burst cycles or not. burst requests are enabled when the be bit is set. the bbc handles non-wrap-around bursts with up to 4 data beats on the internal u-bus. refer to section 4.7.2.1, ?bbc module configuration register bbcmcr.? note the burst operation in the mpc565/mpc566 is useful if a user system implements burstable memory devices on the external bus. otherwise the mode will cause performance degradation in the mpc565/mpc566. when the rcpu runs in serialized mode it is recommended that bursts be disabled by the bbc to speed up mpc565/mpc566 operation. burst operation in ?decompression on? and ?debug? modes are disabled regardless of bbcmcr[be] bit setting. the bbc burst should be turned off if the usiu burst feature is enabled. 4.3.3 access violation detection instruction memory protection is assigned on a regional basis. default operation of impu is done on a global region. the impu has control registers which contain the following information: region protection on/off, region base address, size and access permissions. protection logic is activated only if the rcpu msr[ir] bit is set. during each fetch request from the rcpu core to instruction memory, the address is compared to a value in the region base address of enabled regions. any address matching the specific region within its appropriate size as defined in the region attribute register sets a match indication. when more than one match indication occurs, the effective region is the region with the highest priority. priority is determined by region number. the lowest region number has the highest priority and the global region has lowest priority. when no match happens, the effective region is the global region. 4-20 mpc565/mpc566 reference manual motorola operation modes the region attribute registers contain the region protection fields: pp, g, and cmpr .the protection fields are compared to address attributes issued by the rcpu. if the access is permitted, the address is passed to the biu and further to the u-bus. whenever the impu detects access violation, the following actions are taken: 1. the request forwarded to the biu is canceled 2. the rcpu is informed that the requested address caused an access violation by exception request. however, if the required address contains a show cycle attribute, the biu delivers the access onto the u-bus to obtain program tracking. the exception vector (address) that the rcpu issues for this exception has a 0x1300 offset in the mpc500 exception vector table. the access violation status is provided in the rcpu srr1 special purpose register. the encoding of the status bits is as follows: srr1 [1] = 0 srr1 [3] = guarded storage srr1 [4] = protected storage or compression violation srr1 [10] = 0 only one bit is set at a time. 4.3.4 slave operation the bbc is operating as a u-bus slave when the impu registers, decompressor ram (decram) or icdu registers are accessed from the u-bus. the impu register programming is done using mpc500 mtspr/mfspr instructions. the icdu configuration registers (dccrs) (see table 4-10) and decram are mapped into the chip memory space and accessed by mpc500 load/store instructions. dccr and decram accesses may be disabled by bbcmcr[dcae] bit. refer to section 4.7.2.1, ?bbc module configuration register bbcmcr.? 4.3.5 reset behavior upon soft reset, the bbc switches to an idle state and all pending u-bus accesses are ignored, the icdu internal queue is flushed and the impu switches to a disabled state where all memory space is accessible for both user and supervisor. hard reset sets some of the fields and bits in the bbc configuration registers to their default reset state. some bits in bbcmcr register get their values from the reset configuration word. all the registers are reset using hreset .sreset alone has no effect on them. motorola chapter 4. burst buffer controller 2 module 4-21 exception table relocation (etr) note because hreset resets the en_comp bit and the exc_comp bit but sreset does not, there may be different behavior between hreset and sreset when both en_comp and exc_comp are set. special care must be taken to ensure operation in a known mode whenever reset occurs. the reset states of these bits are determined by reset configuration words. the location of the reset vector is dependent on the value of the msr[ip] bit in the rcpu. if msr[ip] is set, the exception table relocation feature can be used. see section 4.4.2, ?etr operation.? 4.3.6 debug operation mode when the mpc565/mpc566 rcpu core is in debug mode, the bbc initiates non-burstable access to the debug port and icdu is bypassed, (i.e., instructions transmitted to the debug port must be non-compressed regardless of operational mode). 4.4 exception table relocation (etr) 4.4.1 etr overview the bbc is able to relocate the exception addresses of the rcpu. the relocation feature always maps the exception addresses into the internal memory space of the mpc565/mpc566. see figure 4-14. this feature is important in multi-mpc565/mpc566 systems, where, although the memory map in some was shifted to not be on the lower 4 mbytes, their rcpu cores can still access their exception handlers in their internal flash in spite of several rcpus issuing the same exception addresses. the relocation also saves wasted space between the exception table entries in the case where each exception entry contained only a branch instruction to the exception routine, which is located elsewhere. the exception vector table may be programmed to be located in four places in the mpc565/mpc566 internal memory space. the exception table relocation is supported in both ?decompression on? and ?decompression off? operation modes. the reset routine vector is relocated differently in ?decompression on? and in ?decompression off? modes. this feature may be used by a software code compression tool to guarantee that a vocabulary table initialization routine is always executed before application code is running. 4-22 mpc565/mpc566 reference manual motorola exception table relocation (etr) figure 4-14. exception table entries mapping 4.4.2 etr operation the exception vectors are 0x100 bytes apart from each other, starting at address 0x0000 0100 or 0xfff0 0100, depending on the value of msr[ip] bit in the rcpu. if the exception table relocation is disabled by the etre bit in the bbcmcr register, the bbc transfers the exception fetch address to the u-bus of the mpc565/mpc566 with no interference. in this case, normal powerpc exception addressing is implemented. if the exception table relocation is enabled, the bbc translates the exception vector into the exception relocation address. at that location, a branch instruction with absolute addressing (ba) must be placed. each instruction branches to the required exception routine. these branch instructions should be successive in that region of the memory. that way, a table of branch instructions is implemented. executing the branch instruction causes the core to branch twice until it gets to the exception routine. each exception relocation table entry occupies two words to support ?decompression on? mode, where a branch instruction can be more than 32 bits long. 100 200 300 400 500 600 700 1f00 exception table exception pointer by core internal memory structure branch to... branch to... branch to... branch to ... branch to... branch to... branch to... branch to... branch to... branch to... branch to... branch to... free memory space 0 branch to... branch to... 1ffc 1ffc 0 8 10 decompression on n y b8 motorola chapter 4. burst buffer controller 2 module 4-23 exception table relocation (etr) note the eight kbytes allocated for the original powerpc exception table can be almost fully utilized. this is possible if the mpc565/mpc566 system memory is not mapped to the exception address space, (i.e., the addresses 0xfff0_0000 to 0xfff0_1fff are not used). in such case, these eight kbytes can fully be utilized by the compiler, except for the lower 64 words (256 bytes) which are dedicated for the branch instructions. if the rcpu, while executing an exception, issues any address between two successive exception entries (e.g., 0xfff0_0104), then the operation of the mpc565/mpc566 is not guaranteed if the etr is enabled. in order to activate the exception table relocation feature, the following steps are required: 1. set the rcpu msr[ip] bit 2. set the bbcmcr[etre] bit. see section 4.7.2.1, ?bbc module configuration register bbcmcr,? for programming details. 3. program the bbcmcr[oerc] bits to determine the exception branch table location in the memory, according the description in table 4-2. the etr feature can be activated from reset, by setting corresponding bits in the reset configuration word. . table 4-1. exception addresses mapping name of exception original address issues by core mapped address by exception table relocation logic system reset 0xfff0_0100 compression disabled compression enabled page_offset 1 +0x08 page_offset 1 +0x0b8 machine check 0xfff0 0200 page_offset+0x010 data storage 0xfff0 0300 page_offset+0x018 alignment 0xfff0 0600 page_offset+0x028 external interrupt 2 0xfff0 0500 page_offset+0x030 program 0xfff0 0700 page_offset+0x038 floating point unavailable 0xfff0 0800 page_offset+0x040 decrementer 0xfff0 0900 page_offset+0x048 system call 0xfff0 0c00 page_offset+0x060 trace 0xfff0 0d00 page_offset+0x068 floating point assist 0xfff0 0e00 page_offset+0x070 4-24 mpc565/mpc566 reference manual motorola exception table relocation (etr) 4.4.3 enhanced external interrupt relocation (eeir) the bbc also supports the enhanced external interrupt model of the mpc565/mpc566 which allows the removal of the interrupt requesting a source detection stage from the interrupt routine. when the rcpu receives an external interrupt, it provides the information to its mpc500 external interrupt vector. the bbc logic detects this address and replaces it with another address corresponding to the module which initiated the interrupt. see figure 4-15. precise information about the interrupt source module is provided by the interrupt controller of the usiu. implementation dependent software emulation 0xfff0 1000 page_offset+0x080 implementation dependent instruction storage protection error 0xfff0 1300 page_offset+0x098 implementation dependent data storage protection error 0xfff0 1400 page_offset+0x0a0 implementation dependent data breakpoint 0xfff0 1c00 page_offset+0x0e0 implementation dependent instruction breakpoint 0x0fff 1d00 page_offset+0x0e8 implementation dependent maskable external breakpoint 0xfff0 1e00 page_offset+0x0f0 non-maskable external breakpoint 0xfff0 1f00 page_offset+0x0f8 1 refer to table 4-2. 2 0x500 is remapped if the eeir feature is enabled. see section 4.4.3, ?enhanced external interrupt relocation (eeir).? table 4-2. exception relocation page offset bbcmcr(oerc[0:1]) page offset comments 00 0x0+isboffset 1 1 isb offset is equal 4m * isb (0x400000 * isb), where isb is value of bit field in usiu immr register. 0 0 1 0x10000+isboffset 64kbytes 2 2 this offset is different from the mpc555. 1 0 0x8 0000 + isb offset 512 kbytes 1 1 0x3f e000 + isb offset l-bus (calram) address table 4-1. exception addresses mapping (continued) name of exception original address issues by core mapped address by exception table relocation logic motorola chapter 4. burst buffer controller 2 module 4-25 exception table relocation (etr) the external interrupt relocation table should start at the physical address defined in the external interrupt relocation table base address register. see section 4.7.2.5, ?external interrupt relocation table base address register ? eibadr.? each table entry must contain a branch absolute (ba) instruction to the first instruction of an interrupt service routine. each table entry occupies two words (eight bytes) to support ?decompression on? mode, where a branch instruction can be more than 32 bits long. the memory space allocated for the external interrupt relocation table is up to two kbytes. if part of the external interrupt relocation table entries is not used, it may be utilized for another purpose as either instruction code space or data space. in order to activate the external interrupt relocation feature, the following steps are required: 1. program the eibadr register to the external interrupt branch table base address. see section 4.7.2.5, ?external interrupt relocation table base address register ? eibadr.? 2. set the msr[ip] bit 3. set the bbcmcr[eir] bit. see section 4.7.2.1, ?bbc module configuration register bbcmcr,? for programming details. 4. set siumcr[eic] bit. see section 6.4.4, ?enhanced interrupt controller.? note if both the enhanced external interrupt relocation and exception table relocation functions are activated simultaneously, the final external interrupt vector is defined by eeir mechanism. when the eeir function is activated, any branch instruction execution with the 0xfff0_0500 target address may cause unpredictable program execution. 4-26 mpc565/mpc566 reference manual motorola decompressor ram (decram) functionality figure 4-15. external interrupt vectors splitting 4.5 decompressor ram (decram) functionality decompressor ram (decram) is a part of the icdu. it occupies a 4-kbyte physical ram array block. it is mapped both in the icdu internal address space and in the chip memory address space. it is a single port memory and may not be accessed simultaneously from the icdu and u-bus. interrupt vector external interrupt handlers table interrupt pointer by core internal memory structure main code here 0x500 translated vectors external interrupt vector relocator branch absolute to handler branch absolute to handler branch absolute to handler branch absolute to handler branch absolute to handler external relocation table base address 000 interrupt (eibadr) can start interrupt code from interrupt controller offset motorola chapter 4. burst buffer controller 2 module 4-27 decompressor ram (decram) functionality figure 4-16. decram interfaces block diagram 4.5.1 vocabulary table storage operation (mpc566 only) the mpc566 uses decram for decompressor vocabulary tables (vt1 and vt2) storage in ?decompression on? mode. the icdu utilizes decram as four separately accessed 2-kbyte ram arrays (16 bits wide) which are accessed via internal icdu buses. the vts should be loaded before the decompression process starts. in order to allow decompression, the decram must be disabled for the u-bus accesses after vts and decompressor class configuration registers (dccrs) are initialized. vocabulary table (vt1) (1 kbyte) decram array vocabulary table (vt2) (1 kbyte) array u-bus address u-bus data slave biu vt1 address vt2 address vt1 data vt2 data icdu control logic icdu 4-28 mpc565/mpc566 reference manual motorola decompressor ram (decram) functionality 4.5.2 general-purpose memory operation in the case of ?decompression off? mode, the decram can serve as a two-clock access general-purpose ram for u-bus instruction fetches or four-clock access for read/write data operations. the base address of the decram is 0x2 f8000. see figure 4-18. the proper access rights to the decram array may be defined by programming the r, d, and s bits of the bbcmcr register: read/write or read only instruction/data or data only supervisor/user or supervisor only external access mode of the ram is activated by the bbcmcr[dcae] bit setting (see section 4.7.2.1, ?bbc module configuration register bbcmcr).? in this mode the decram can be accessed from the u-bus and cannot be accessed by the icdu logic. in this mode: the decram supports word, half-word and byte operations. the decram is emulated to be 32 bits wide. for example: a load access from offset 0 in the decram will deliver the concatenation of the first word in each of the decram banks when ram 1 contains the 16 lsb of the word and ram 2 contains the 16 msb. load accesses at any width are supplied with 32 bits of valid data. the decram communicates with the u-bus pipeline but does not support pipelined accesses to itself. if a store operation is second in the u-bus pipe, the store is carried out immediately and the u-bus acknowledgment is performed when the previous transaction in the pipe completes. burst access is not supported. 4.5.2.1 memory protection violations the decram module does not acknowledge u-bus accesses that violate the configuration defined in the bbcmcr . this causes the machine check exception for the internal rcpu or an error condition for the mpc565/mpc566 external master. 4.5.2.2 decram standby operation mode the bus interface and decram control logic are powered by v dd . the memory array(s) is supplied by a separate power pin (vddsram3). if main power is shut off, vddsram may subsequently be lowered for purposes of low voltage data retention. when the decram array is powered by the vddsram3 pin, access to the ram array is blocked. the application software may use vsrmcr[lvdrs] bit value to determine if motorola chapter 4. burst buffer controller 2 module 4-29 branch target buffer the content of decram is valid (see section 8.11.4, ?vddsram control register (vsrmcr)? for details). 4.6 branch target buffer the burst buffer controller contains a branch target buffer (btb) to reduce the impact of branches on performance. following is a summary of the btb features: software controlled btb enable/disable, lock/unlock and invalidate user transparent ? no user management required the btb compensates for the branch hit and branch miss prediction impact on the system performance. it consists of eight branch target entries (bte). refer to figure 4-17. all entries are managed as a fully associative cache. each entry contains a tag and several data buffers related to this tag 4.6.1 btb operation when the rcpu generates a change of flow (cof) address for instruction fetch, the btb control logic compares it to the tag values currently stored in the tag register file where following events can happen: bte miss ? the target address and instruction code data will be stored in one of the bte entries defined by its control logic. up to four instructions and their corresponding addresses subsequent to the cof target instruction may be saved in each bte entry. the number of valid instructions currently stored in the bte entry is written into the vdc field of the current bte entry. the valid flag is set at the end of this process. the entry to be replaced upon miss is chosen based on fifo replacement method. thus the btb can support up to eight different branch target addresses in a program loop. bte hit ? when the target address of a branch matches one of the valid bte entries or the bcme entry, two activities take place in parallel: the btb supplies all the valid instructions in the matched entry to the rcpu. ? the icdu (which is flushed due to the cof) starts to prefetch instructions (and decompresses them in compressed mode) from the address following the last instruction which is stored in the matched btb entry. it will supply these instructions to the rcpu after all the stored instructions in the matched btb entry were delivered. in case of a btb hit, the impact of instruction decompression latency is eliminated as well as a latency of instruction storage memory device. 4-30 mpc565/mpc566 reference manual motorola branch target buffer . figure 4-17. btb block diagram 4.6.1.1 btb invalidation write access to any bbc special purpose register invalidates all btb entries. 4.6.1.2 btb enabling/disabling the bte operation may be enabled/disabled by programming the btee bit in the bbcmcr register. data buffers data buffers data buffers tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v tag register/comparator next address vdc v 32-bit compressed instruction address hit hit hit hit hit hit hit hit btb hit bte tag register file bte memory array data buffers data buffers data buffers data buffers data buffers motorola chapter 4. burst buffer controller 2 module 4-31 bbc programming model 4.6.1.3 btb inhibit regions the btb operation may be inhibited regarding some memory regions. the btb caching is inhibited for a region if the btbinh bit set in the region attribute register (or global region attribute register). see section 4.7.2.3, ?region attribute registers mi_ra[0:3],? and section 4.7.2.4, ?global region attribute register mi_gra? for details. 4.7 bbc programming model 4.7.1 address map the bbc consists of three separately addressable sections within the internal chip address space. 1. bbc and impu control registers. these are mapped in the spr registers area and may be programmed by using the mpc500?s mtspr/mfspr instructions. 2. decompressor vocabulary ram (decram). decram array occupies the four-kbyte physical memory (eight kbytes mpc565/mpc566 address space is allocated for decram). 3. decompressor class configuration registers (dccr) block. it consists of 15 decompression class configuration registers. these registers are available for word wide read/write accesses through u-bus. the registers occupy a 64-byte physical block (eight-kbyte chip address space is allocated for the register block). figure 4-18. mpc565/mpc566 memory map 0x2f 8fff 0x2f 9fff 0x2f 9000 0x2f a000 0x2f 8000 0x2f a03f reserved dccr0 ? dccr15 decram 4kbytes 4-32 mpc565/mpc566 reference manual motorola bbc programming model 4.7.1.1 bbc special purpose registers (sprs) all the above registers may be accessed in the supervisor mode only. an exception is internally generated by the rcpu if there is an attempt to access them in user mode. an external master receives a transfer error acknowledge when attempting to access a register in user mode. 4.7.1.2 decram and dccr block the decram occupies addresses from 0x2f 8000 to 0x2f 8fff. the dccr block occupies addresses from 0x2f a000 to 0x2f a03f. the address for non-implemented memory blocks is not acknowledged, and causes an error condition. table 4-3. bbc sprs spr number (decimal) address for external master access (hex) register name 528 0x2100 impu global region attribute register (mi_gra). see table 4-8 for bits descriptions. 529 0x2300 external interrupt relocation table base address register (eibadr). see table 4-9 for bits descriptions. 560 0x2110 bbc module configuration register (bbcmcr). see table 4-4 for bits descriptions 784 0x2180 impu region base address register 0 (mi_rba0). see table 4-5 for bits descriptions. 785 0x2380 impu region base address register 1 (mi_rba1). see table 4-5 for bits descriptions. 786 0x2580 impu region base address register 2 (mi_rba2). see table 4-5 for bits descriptions. 787 0x2780 impu region base address register 3 (mi_rba3). see table 4-5 for bits descriptions. 816 0x2190 impu region attribute register 0 (mi_ra0). see table 4-6 for bits descriptions. 817 0x2390 impu region attribute register 1 (mi_ra1). see table 4-6 for bits descriptions. 818 0x2590 impu region attribute register 2 (mi_ra2). see table 4-6 for bits descriptions. 819 0x2790 impu region attribute register 3 (mi_ra3). see table 4-6 for bits descriptions. motorola chapter 4. burst buffer controller 2 module 4-33 bbc programming model 4.7.2 bbc register descriptions 4.7.2.1 bbc module configuration register bbcmcr , msb 0 12 3 4 5 6 7 89101112131415 r d s test reserved hreset 000 0 0 0 0 0 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved be etre eir en_ comp 1 1 mpc566 only. exc_ comp 2 decomp _sc_en 2 oerc[0:1] btee reserved dcae tst hreset 0 0 0 id 2 (19) 2 id ? gets value of corresponding bit of reset configuration word 0 id(21) id(22) id(21) id(24:25) 0 0 0 0 0 0 figure 4-19. bbcmcr ? bbc module configuration register spr 560 table 4-4. bbcmcr bbc module configuration register bit descriptions bit(s) name description 0 r read only ? for any attempt to write to the decram array while r is set, is terminated with an error. this causes a machine check exception for rcpu. 0 decram array is readable and writable. 1 decram array is read only. 1 d data only ? the decram array may be used for instructions and data or for data storage only. any attempt to load instructions from the decram array, while d is set, is terminated with an error this causes a machine check exception for the rcpu. 0 decram array holds data and/or instruction. 1 decram array holds data only. 2 s supervisor only. when the bit set (s = 1), only a supervisor program may access the decram. if a supervisor program is accessing the array, normal read/write operation will occur. if a user program is attempting to access the array, the access will be terminated with an error this causes a machine check exception for the rcpu. if s = 0, the ram array is placed in unrestricted space and access by both supervisor and user programs is allowed. 3:7 test these bits can be set in factory test mode only. the user should treat these bits as reserved and always write as zeros. 8:17 ? reserved 18 be burst enable 0 burst access is disabled. 1 burst access is enabled. 4-34 mpc565/mpc566 reference manual motorola bbc programming model 19 etre exception table relocation enable 0 exception table relocation is off: bbc does not map exception addresses. 1 exception table relocation is on: bbc maps exception addresses to a table holding branch instructions two memory words apart from each other. the reset value is taken from the reset configuration word bit #19. 20 eir enhanced external interrupt relocation enable? this bit activates the external interrupt relocation table mechanism. this bit is independent from the value of etre bit, but if eir and etre are enabled, the mapping of external interrupt will be via eir. 0 eir function is disabled. 1 eir function is active. 21 en_ comp 1 enable compression ? this bit enables the operation of the mpc566 in ?compression on? mode. the default state is disabled. 0 ?decompression on? mode is disabled. the mpc565/mpc566 operates only in ?decompression off? mode. 1 ?decompression on? mode is enabled. the mpc566 may operate with both ?decompression on? and ?decompression off? modes. the bit value is determined by reset configuration word, bit #21. 22 exc_ comp 1 exception compression ? this bit determines the operation of the mpc565/mpc566 with exceptions. if this bit is set, the mpc566 assumes that the all exception routine codes are compressed; otherwise it is assumed that all exception routine codes are not compressed. the reset value is determined by reset configuration word bit #22. 0 the mpc565/mpc566 assumes that exception routines are noncompressed 1 the mpc566 assumes that all exception routines are compressed. this bit has effects only when the en_comp bit is set. 23 decomp_ sc_en 1 decompression show cycle enable ? this bit determines the way the mpc565/mpc566 executes instruction show cycles. the reset value is determined by configuration word bit #21. for further details regarding show cycles execution in ?decompression on? mode see section 4.3.1.2, ??decompression on? mode.? 0 decompression show cycles do not include the bit pointer. 1 decompression show cycles include the bit pointer information on the data bus. 24:25 oerc[0:1] other exceptions relocation control ? these bits have effect only if etre was enabled; see details in section 4.4.2, ?etr operation.? 00: offset 0 01: offset 64 kbytes 10: offset 512 kbytes 11: offset to 0x003fe000 (sram start address) the reset value is determined by reset configuration word bits #24, #25 26 btee branch target entries enable ? this bit enables branch target entries of btb operation 0 bte operation is disable 1 bte operation is enable. 27:29 ? reserved. note: bit 27 was bcmee and should be written as 0. table 4-4. bbcmcr bbc module configuration register bit descriptions (continued) bit(s) name description motorola chapter 4. burst buffer controller 2 module 4-35 bbc programming model note when writing to the bbcmcr register, the following instruction after mtspr bbcmcr, rx should be isync, to make sure that the programmed value will come into effect before any further action. 4.7.2.2 region base address registers mi_rba[0:3] the following registers contain 32 bits and define the starting address of the protected regions. there is one register for each of four regions. , 30 dcae decompressor configuration access enable ? this bit enables decram and dccr registers access from the u-bus master (i.e., rcpu, external master). 0 decram and dccr registers are locked. 1 decram allows accesses from the u-bus only. dcae bit should be set before vocabulary tables are loaded via the u-bus. 31 tst reserved for bbc test operations. 1 this bit is available on the mpc566 only. msb 0 123456789101112131415 ra hreset uuuuuuuuuuuuuuuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 ra reserved hreset uuuu0 0 0000000000 figure 4-20. mi_rba0 ? region base address register spr 784 mi_rba1 spr 785 mi_rba2 spr 786 mi_rba3 spr 787 table 4-4. bbcmcr bbc module configuration register bit descriptions (continued) bit(s) name description 4-36 mpc565/mpc566 reference manual motorola bbc programming model note when the mpc566 operates in ?decompression on? mode, a minimum of four unused words must be left after the last instruction in any region. 4.7.2.3 region attribute registers mi_ra[0:3] the following registers define protection attributes and size for four memory regions. , table 4-5. mi_rba[0:3] registers bit descriptions bit(s) name description 0:19 ra region base address. the ra field provides the base address of the region. the region base address should start on the memory block boundary for the corresponding region size, specified in the region attribute register mi_ra. 20:31 ? reserved msb 0 123456789101112131415 rs hreset uuuuuuuuuuuuuuuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 rs pp reserved g cmpr? btbi nh reserved hreset uuuuuu0 0 0uuuu0 0 0 figure 4-21. mi_ra0 ? region attribute register spr 816 mi_ra1spr 817 mi_ra2spr 818 mi_ra3spr 819 table 4-6. mi_ra[0:3] registers bit descriptions bit(s) name description 0:19 rs region size. for byte size by region, see table 4-7. 20:21 pp 1 protection bits: 00: supervisor ? no access, user ? no access. 01: supervisor ? fetch, user ? no access. 1x: supervisor ? fetch, user ? fetch. 22:24 ? reserved motorola chapter 4. burst buffer controller 2 module 4-37 bbc programming model 25 g guard attribute for region 0 speculative fetch is not prohibited from region. region is not guarded. 1 speculative fetch is prohibited from guarded region. an exception will occur under such attempt. 26:27 cmpr 2 compressed region. x0 the region in not restricted 01 region is considered a non-compressed code region access to the region is allowed only in ?decompression off? mode 11 region is considered a compressed code region. access to the region is allowed only in ?decompression on? mode 28 btbinh 2 btb inhibit region 0 btb operation is not prohibited for current memory region 1 btb operation is prohibited for current memory region. 29:31 ? reserved 1 g and pp attributes perform similar protection activities on a region. the more protective attribute will be implied on the region if the attributes programming oppose each other. 2 this bit is available only on the mpc566. table 4-7. region size programming possible values rs field value (binary) size 0000_0000_0000_0000_0000 4 kbytes 0000_0000_0000_0000_0001 8 kbytes 0000_0000_0000_0000_0011 16 kbytes 0000_0000_0000_0000_0111 32 kbytes 0000_0000_0000_0000_1111 64 kbytes 0000_0000_0000_0001_1111 128 kbytes 0000_0000_0000_0011_1111 256 kbytes 0000_0000_0000_0111_1111 512 kbytes 0000_0000_0000_1111_1111 1 mbyte 0000_0000_0001_1111_1111 2 mbytes 0000_0000_0011_1111_1111 4 mbytes 0000_0000_0111_1111_1111 8 mbytes 0000_0000_1111_1111_1111 16 mbytes 0000_0001_1111_1111_1111 32 mbytes 0000_0011_1111_1111_1111 64 mbytes 0000_0111_1111_1111_1111 128 mbytes 0000_1111_1111_1111_1111 256 mbytes 0001_1111_1111_1111_1111 512 mbytes table 4-6. mi_ra[0:3] registers bit descriptions (continued) bit(s) name description 4-38 mpc565/mpc566 reference manual motorola bbc programming model 4.7.2.4 global region attribute register mi_gra mi_gra register defines protection attributes for memory region, not covered by mi_rb0-3/mi_rba0-3 registers. it also contains protection regions 0-3 enable bits. , 0011_1111_1111_1111_1111 1 gbyte 0111_1111_1111_1111_1111 2 gbytes 1111_1111_1111_1111_1111 4 gbytes msb 0 123456789101112131415 enr 0 enr1 enr2 enr3 reserved hreset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved pp reserved g cmpr btbi nh reserved hreset 0000000000000000 figure 4-22. mi_gra ? global region attribute register spr 528 table 4-8. mi_gra global region attribute register bits description bit(s) name description 0 enr0 enable impu region 0 0region0isoff. 1region0ison. 1 enr1 enable impu region 1 0region1isoff. 1region1ison. 2 enr2 enable impu region 2 0region2isoff. 1region2ison. 3 enr3 enable impu region 3 0region3isoff. 1region3ison. 4:19 ? reserved table 4-7. region size programming possible values rs field value (binary) size motorola chapter 4. burst buffer controller 2 module 4-39 bbc programming model note the mi_gra register should be programmed to enable fetch access (pp and g bits) before rcpu msr[ir] bit set. 4.7.2.5 external interrupt relocation table base address register ? eibadr , 20:21 pp protection bits 00 supervisor ? no access, user ? no access. 01 supervisor ? fetch, user ? no access. 1x supervisor ? fetch, user ? fetch. 22:24 ? reserved 25 g guard attribute for region 0 fetch is not prohibited from region. region is not guarded. 1 fetch is prohibited from guarded region. an exception will occur under such attempt. 26:27 cmpr 1 compressed region. x0 the region in not restricted 01 region is considered a non-compressed code region access to the region is allowed only in ?decompression off? mode 11 region is considered a compressed code region.access to the region is allowed only in ?decompression on? mode 28 btbinh 1 btb inhibit region 0 btb operation is not prohibited for current memory region 1 btb operation is prohibited for current memory region. 29:31 ? reserved 1 this bit is available only on the mpc566. msb 0 123456789101112131415 base address hreset uuuuuuuuuuuuuuuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 base address reserved hreset u u u u 0 0 0 0 0 0 0 0 0 0 0 0 figure 4-23. eibadr ? external interrupt relocation table base address register spr 529 table 4-8. mi_gra global region attribute register bits description (continued) bit(s) name description 4-40 mpc565/mpc566 reference manual motorola bbc programming model 4.7.2.6 decompressor class configuration registers (dccr0-15) (mpc566 only) the dccr fields are programmed to achieve maximum flexibility in the vocabulary tables placement into the two decram banks under constraints, implied by hardware, which are: a bypass field must always be in the second field of the compressed instruction when fetching 32 bits of de-compressed instruction from the decram, each 16 bits will be read from different ram banks. the dccr registers should be programmed with data supplied by the code compression tool, in order to be correlated with the compressed code. table 4-9. eibadr external interrupt relocation table base address register bit descriptions bit(s) name description 0:20 ba external interrupt relocation table base address bits [0:20] 21:31 ? reserved. eibadr must be set on a 4k page boundary. motorola chapter 4. burst buffer controller 2 module 4-41 bbc programming model , 1. dccr0 register is hard coded for the ?bypass decompressor class?. write accesses do not affect this register; the dccr0 register will always return 0x0000 0000 when read. msb 0 123456789101112131415 tp1len tp2len tp1ba tp2ba hreset uuuuuuuuuuuuuuu u 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 tp2ba as ds reserved hreset u u u u 0 u u u 0 0 0 0 0 0 0 0 figure 4-24. dccr0 1 ? decompressor class configuration registers 0x2f a000 dccr10x2f a004 dccr20x2f a008 dccr30x2f a00c dccr40x2f a010 dccr50x2f a014 dccr60x2f a018 dccr70x2f a01c dccr80x2f a020 dccr90x2f a024 dccr100x2f a028 dccr110x2f a02c dccr120x2f a030 dccr130x2f a034 dccr140x2f a038 dccr150x2f a03c 4-42 mpc565/mpc566 reference manual motorola bbc programming model table 4-10. dccr0-dccr15 decompressor class configuration registers bit descriptions (mpc566 only) bit(s) name description 0:3 tp1len length and type of table pointer 1 ? this field?s value defines the length of the field that contains a pointer to the first vocabulary table allocated for the class. 0x0 empty field 0x1 reserved 0x2 tp1 length is 2 bits 0x3 tp1 length is 3 bits 0x4 tp1 length is 4 bits 0x5 tp1 length is 5 bits 0x6 tp1 length is 6 bits 0x7 tp1 length is 7 bits 0x8 tp1 length is 8 bits 0x9 tp1 length is 9 bits 0xa to 0xfreserved 4:7 tp2len length and type of table pointer 2 ? this field?s value defines the length of the field that contains either a pointer to the second vocabulary table allocated for the class or a bypass field. 0x0 empty field 0x1 reserved 0x2 tp2 length is 2 bits 0x3 tp2 length is 3 bits 0x4 tp2 length is 4 bits 0x5 tp2 length is 5 bits 0x6 tp2 length is 6 bits 0x7 tp2 length is 7 bits 0x8 tp2 length is 8 bits 0x9 tp2 length is 9 bits 0xa reserved 0xb reserved 0xc tp2 field is a 10 bits compact bypass field 0xd tp2 field is a 15 bits compact bypass field 0xe tp2 field is a 16 bits bypass field 0xf reserved. 8:14 tp1ba base address for vocabulary table in ram bank 1 ? this field specifies the base page address of the class? vocabulary table that resides in ram bank 1. 15:21 tp2ba base address for vocabulary table in ram bank 2 ? this field specifies the base page address of the class? vocabulary table that resides in ram bank 2. 22 as address swap specification 0 address swap operation will not be performed for the class. 1 address swap operation will be performed for the class for further details concerning as operation refer to table 4-11. 23 ds data swap specification 0 data swap operation will not be performed for the class. 1 data swap operation will be performed for the class. for further details concerning ds operation refer to table 4-11. 24:31 ? reserved motorola chapter 4. burst buffer controller 2 module 4-43 bbc programming model table 4-11. instruction layout encoding (mpc566 only) configuration configu ration code tp1 points to ram # tp2 points to ram # tp1ba points to tp2ba points to as ds compressed instruction layout ram # vocab. ram # vocab. single segment full compression class 1 1and2? 1v12v2??x1 1 1 x1,x2 - pointers to vocabularies twin segments full compression class 2a 1 2 1v12v2?0x1x2 twin segments full compression with swapped vocabularies (vocabulary in ram #2 for msb segment) class 2b v2 v1 1 x2 x1 left segment compression, right segment bypassed, vocabulary in ram #1 class 3a 1 bypass 1 v1 ? ? 0 0 x1 bp 2 2 bp - the bypassed data left segment compression, right segment bypassed, vocabulary in ram #2 class 3b 2??2v11x1bp left segment bypassed, right segment compression, vocabulary in ram #1 class 4b 1 1 v2 ? ? 0 1 x2 bp left segment bypassed, right segment compression, vocabulary in ram #2 class 4a 2??2v21x2bp 4-44 mpc565/mpc566 reference manual motorola bbc programming model motorola chapter 5. unified system interface unit (usiu) 5-1 chapter 5 unified system interface unit (usiu) the unified system interface unit (usiu) of the mpc565/mpc566 consists of several functional modules that control system start-up, system initialization and operation, system protection, and the external system bus. the mpc565/mpc566 usiu functions include the following: system configuration and protection enhanced interrupt controller system reset monitoring and generation clock synthesizer power management external bus interface (ebi) memory controller supports four memory banks debug support 5.1 usiu module overview the system configuration and protection features control the overall system configuration and provides various monitors and timers, including the bus monitor, software watchdog timer, periodic interrupt timer, ppc decrementer, time base, and real-time clock. the interrupt controller supports up to eight external interrupts, eight levels for all internal usiu interrupt sources and 32 levels for internal peripheral modules on the imb bus. it has an enhanced mode of operation, which simplifies the mpc565/mpc566 interrupt structure and speeds up interrupt processing. the usiu provides several pinout configurations that allow up to 64 general-purpose i/o, external 32-bit port that supports internal and external masters, and various debug functions. refer to chapter 6, ?system configuration and protection ? for details. the usiu supports the internal flash censorship mechanism. any attempt to operate the mpc565/mpc566 from the external world, while the internal flash is in censorship mode, locks the internal flash. the flash is blocked after following events: booting from external memory; 5-2 mpc565/mpc566 reference manual motorola usiu module overview external master access into the mpc565/mpc566; debug port/readi accesses are performed. the clock synthesizer generates the clock signals used by the usiu as well as the other modules and external devices. this circuitry can generate the system clock from a 4-mhz or 20-mhz crystal. the usiu supports various low-power modes. each one supplies a different range of power consumption, functionality and wake-up time. refer to chapter 8, ?clocks and power control,? for details. the ebi handles the transfer of information between the internal busses and the memory or peripherals in the external address space. the mpc565/mpc566 is designed to allow external bus masters to request and obtain mastership of the system bus, and if required access the on-chip memory and registers. refer to chapter 9, ?external bus interface,? for details. the memory controller module provides glueless interface to many types of memory devices and peripherals. it supports up to four memory banks. refer to chapter 10, ?memory controller,? for details. figure 5-1 shows the usiu block diagram. motorola chapter 5. unified system interface unit (usiu) 5-3 usiu module overview figure 5-1. block diagram 5.1.1 address map table 5-1 is an address map of the siu registers. where not otherwise noted, registers are 32 bits wide. the address shown for each register is relative to the base address of the mpc565/mpc566 internal memory map. the internal memory block can reside in one of eight possible four-mbyte memory spaces. see figure 1-3 for details. table 5-1. address map address register 0x2f c000 siu module configuration register (siumcr) see table 6-7 for bit descriptions. 0x2f c004 system protection control register (sypcr) see table 6-15 for bit descriptions. 0x2f c008 reserved 0x2f c00e 1 software service register (swsr) see table 6-16 for bit descriptions. 0x2f c010 interrupt pending register (sipend). memory control lines memory controller e-bus u-bus slave clocks & reset u-bus sgpio interface interface software watchdog bus monitor periodic interrupt timer and decrementer real-time clock debug pin multiplexing interrupt controller address data e-bus interface 5-4 mpc565/mpc566 reference manual motorola usiu module overview 0x2f c014 interrupt mask register (simask) see section 6.14.2.4, ?siu interrupt mask register,? for bit descriptions. 0x2f c018 interrupt edge level mask (siel) see section 6.14.2.7, ?siu interrupt edge level register (siel),? for bit descriptions. 0x2f c01c interrupt vector (sivec) see section 6.14.2.8, ?siu interrupt vector register,? for bit descriptions. 0x2f c020 transfer error status register (tesr) see table 6-17 for bit descriptions. 0x2f c024 usiu general-purpose i/o data register (sgpiodt1) see table 6-23 for bit descriptions. 0x2f c028 usiu general-purpose i/o data register 2 (sgpiodt2) see table 6-24 for bit descriptions. 0x2f c02c usiu general-purpose i/o control register (sgpiocr) see table 6-25 for bit descriptions. 0x2f c030 external master mode control register (emcr) see table 6-13 for bit descriptions. 0x2f c038 pads module configuration register 2 (pdmcr2) see table 2-4 for bit descriptions. 0x2f c03c pads module configuration register (pdmcr) see table 2-3 for bit descriptions. 0x2f c040 interrupt pend2 register (sipend2) see section 6.14.2.2, ?siu interrupt pending register 2,? for bit descriptions. 0x2f c044 interrupt pend3 register (sipend3) see section 6.14.2.3, ?siu interrupt pending register 3,? for bit descriptions. 0x2f c048 interrupt mask2 register (simask2) see section 6.14.2.5, ?siu interrupt mask register 2,? for details. 0x2f c04c interrupt mask3 register (simask3) see section 6.14.2.6, ?siu interrupt mask register 3,? for details. 0x2f c050 interrupt in-service2 register (sisr2) see section 6.14.2.9, ?interrupt in-service registers,? for details. 0x2f c054 interrupt in-service3 register (sisr3) see section 6.14.2.9, ?interrupt in-service registers,? for details. 0x2f c0fc?0x2f c0ff reserved memory controller registers 0x2f c100 base register 0 (br0) see table 10-8 for bit descriptions. 0x2f c104 option register 0 (or0) see table 10-10 for bit descriptions. 0x2f c108 base register 1 (br1) see table 10-8 for bit descriptions. table 5-1. address map (continued) address register motorola chapter 5. unified system interface unit (usiu) 5-5 usiu module overview 0x2f c10c option register 1 (or1) see table 10-10 for bit descriptions. 0x2f c110 base register 2 (br2) see table 10-8 for bit descriptions. 0x2f c114 option register 2 (or2) see table 10-10 for bit descriptions. 0x2f c118 base register 3 (br3) see table 10-8 for bit descriptions. 0x2f c11c option register 3 (or3) see table 10-10 for bit descriptions. 0x2f c120?0x2f c13c reserved 0x2f c140 dual-mapping base register (dmbr) see table 10-11 for bit descriptions. 0x2f c144 dual-mapping option register (dmor) see table 10-12 for bit descriptions. 0x2f c148?0x2f c174 reserved 0x2f c178 1 memory status (mstat) see table 10-7 for bit descriptions. 0x2f c17a?0x2f c1fc reserved system integration timers 0x2f c200 time base status and control (tbscr) see table 6-18 for bit descriptions. 0x2f c204 time base reference 0 (tbref0) see section 6.14.4.3, ?time base reference registers,? for bit descriptions. 0x2f c208 time base reference 1 (tbref1) see section 6.14.4.3, ?time base reference registers,? for bit descriptions. 0x2f c20c?0x2f c21c reserved 0x2f c220 real-time clock status and control (rtcsc) see table 6-19 for bit descriptions. 0x2f c224 real-time clock (rtc) see section 6.14.4.6, ?real-time clock register (rtc),? for bit descriptions. 0x2f c228 real-time alarm seconds (rtsec) ? reserved 0x2f c22c real-time alarm (rtcal) see section 6.14.4.7, ?real-time clock alarm register (rtcal),? for bit descriptions. 0x2f c230?0x2f c23c reserved 0x2f c240 pit status and control (piscr) see table 6-20 for bit descriptions. 0x2f c244 pit count (pitc) see table 6-21 for bit descriptions. table 5-1. address map (continued) address register 5-6 mpc565/mpc566 reference manual motorola usiu module overview 0x2f c248 pit register (pitr) see table 6-22 for bit descriptions. 0x2f c24c?0x2f c27c reserved clocks and reset 0x2f c280 system clock control register (sccr) see table 8-9 for bit descriptions. 0x2f c284 pll low-power and reset control register (plprcr) see table 8-11 for bit descriptions. 0x2f c288 1 reset status register (rsr) see table 7-3 for bit descriptions. 0x2f c28c 1 change of lock interrupt register (colir) see table 8-12 for bit descriptions. 0x2f c290 1 vddsram1 control register (vsrcr) see table 8-13 for bit descriptions. 0x2f c294?0x2f c2fc reserved system integration timer keys 0x2f c300 time base status and control key (tbscrk) see table 8-8 for bit descriptions. 0x2f c304 time base reference 0 key (tbref0k) see table 8-8 for bit descriptions. 0x2f c308 time base reference 1 key (tbref1k) see table 8-8 for bit descriptions. 0x2f c30c time base and decrementor key (tbk) see table 8-8 for bit descriptions. 0x2f c310?0x2f c31c reserved 0x2f c320 real-time clock status and control key (rtcsck) see table 8-8 for bit descriptions. 0x2f c324 real-time clock key (rtck) see table 8-8 for bit descriptions. 0x2f c328 real-time alarm seconds key (rtseck) see table 8-8 for bit descriptions. 0x2f c32c real-time alarm key (rtcalk) see table 8-8 for bit descriptions. 0x2f c330?0x2f c33c reserved 0x2f c340 pit status and control key (piscrik) see table 8-8 for bit descriptions. 0x2f c344 pit count key (pitck) see table 8-8 for bit descriptions. 0x2f c348?0x2f c37c reserved table 5-1. address map (continued) address register motorola chapter 5. unified system interface unit (usiu) 5-7 usiu module overview 5.1.2 usiu special-purpose registers table 5-2 lists the mpc565/mpc566 special purpose registers (spr). these registers reside in an alternate internal memory space that can only be accessed with the mtspr and mfspr instructions, or from an external master (refer to section 6.2, ?external master modes,? for details). all registers are 32 bits wide. note rcpu special purpose registers can not be accessed by external master. only spr?s in the usiu can be accessed by an external master. clocks and reset keys 0x2f c380 system clock control key (sccrk) see table 8-8 for bit descriptions. 0x2f c384 pll low-power and reset control register key (plprcrk) see table 8-8 for bit descriptions. 0x2f c388 reset status register key (rsrk) see table 8-8 for bit descriptions. 0x2f c38c?0x2f c3fc reserved 1 16-bit register. table 5-2. usiu special-purpose registers internal address[0:31] register decimal address spr[5:9]:spr[0:4] 1 1 bits [0:17] and [28:31] are all 0. 0x2c00 decrementer (dec). see section 3.9.5, ?decrementer register (dec),? for more information. 22 0x1880 time base ? read (tb). see table 3-11 for bit descriptions 268 0x1a80 time base upper ? read (tbu). see section 6.14.4.2, ?time base sprs,? for bit descriptions 269 0x3880 time base ? write (tb). see table 3-14 for bit descriptions 284 0x3a80 time base upper ? write (tbu). see section 6.14.4.2, ?time base sprs,? for bit descriptions 285 0x3d30 internal memory mapping register (immr). see table 6-12 for bit descriptions. 638 table 5-1. address map (continued) address register 5-8 mpc565/mpc566 reference manual motorola usiu module overview table 5-3 shows the mpc565/mpc566 address format for special purpose registers access. for an external master, accessing an mpc500 spr, address bits [0:17] and [28:31] are compared to zeros to confirm that an spr access is valid. see section 6.2.1, ?operation in external master modes,? for more details. table 5-3. mpc565/mpc566 address format for spr access from external bus 0:17 18:27 28:31 0..0 spr[5:9],spr[0:4] 0000 motorola chapter 6. system configuration and protection 6-1 chapter 6 system configuration and protection the mpc565/mpc566 incorporates many system functions that normally must be provided in external circuits. in addition, it is designed to provide maximum system safeguards again hardware and/or software faults. the system configuration and protection sub-module provides the following features: system configuration?the usiu allows the configuration of the system according to the particular requirements. the functions include control of show cycle operation, pin multiplexing, and internal memory map location. system configuration also includes a register containing part and mask number constants to identify the part in software. interrupt controller?the interrupt controller receives interrupt requests from a number of internal and external sources and directs them on a single interrupt-request line to the rcpu. general-purpose i/o?the usiu provides 64 pins for general-purpose i/o. the sgpio pins are multiplexed with the address and data pins. external master modes support?external master modes are special modes of operation that allow an alternate master on the external bus to access the internal modules for debugging and backup purposes. bus monitor?the siu provides a bus monitor to watch internal to external accesses. it monitors the transfer acknowledge (ta) response time for internal to external transfers. a transfer error acknowledge (tea ) is asserted if the ta response limit is exceeded. this function can be disabled. software watchdog timer (swt)?the swt asserts a reset or non-maskable interrupt, as selected by the system protection control register (sypcr), if the software fails to service the swt for a designated period of time (e.g., because the software is trapped in a loop or lost). after a system reset, this function is enabled with a maximum time-out period and asserts a system reset if the time-out is reached. the swt can be disabled or its time-out period can be changed in the sypcr. once the sypcr is written, it cannot be written again until a system reset. periodic interrupt timer (pit)?the siu provides a timer to generate periodic interrupts for use with a real-time operating system or the application software. the 6-2 mpc565/mpc566 reference manual motorola pit provides a period from 1 s to 4 seconds with a four-mhz crystal or 200 ns to 0.8 ms with a 20-mhz crystal. the pit function can be disabled. time base counter (tb)?the tb is a 64-bit counter defined by the mpc565/mpc566 architecture to provide a time base reference for the operating system or application software. the tb has four independent reference registers which can generate a maskable interrupt when the time-base counter reaches the value programmed in one of the four reference registers. the associated bit in the tb status register will be set for the reference register which generated the interrupt. decrementer (dec)?the dec is a 32-bit decrementing counter defined by the mpc565/mpc566 architecture to provide a decrementer interrupt. this binary counter is clocked by the same frequency as the time base (also defined by the mpc565/mpc566 architecture). the period for the dec when driven by a 4-mhz oscillator is 4295 seconds, which is approximately 71.6 minutes. real-time clock (rtc)?the rtc is used to provide time-of-day information to the operating system or application software. it is composed of a 45-bit counter and an alarm register. a maskable interrupt is generated when the counter reaches the value programmed in the alarm register. the rtc is clocked by the same clock as the pit. freeze support?the siu allows control of whether the swt, pit, tb, dec and rtc should continue to run during the freeze mode. figure 6-1 shows a block diagram of the system configuration and protection logic. motorola chapter 6. system configuration and protection 6-3 system configuration figure 6-1. system configuration and protection logic 6.1 system configuration the siu allows the configuration of the system according to the particular requirements. the functions include control of show cycle operation, pin multiplexing, and internal memory map location. system configuration also includes a register containing part and mask number constants to identify the part in software. system configuration registers include the siu module configuration register (siumcr), and the internal memory mapping register (immr). refer to section 6.14, ?system configuration and protection registers,? for register diagrams and bit descriptions. interrupt controller bus monitor periodic interrupt timer software watchdog timer decrementer time base counter real-time clock clock tea signal interrupt interrupt or system reset interrupt interrupt module configuration decrementer exception mpc565/mpc566 mpc565/mpc566 6-4 mpc565/mpc566 reference manual motorola system configuration 6.1.1 usiu pin multiplexing some of the functions defined in the various sections of the usiu (external bus interface, memory controller, and general-purpose i/o) share pins. table 6-1 summarizes how the pin functions of these multiplexed pins are assigned. . 6.1.2 memory mapping the mpc565/mpc566 internal memory space can be assigned to one of eight locations. the internal memory map is organized as a single four-mbyte block. the user can assign this block to one of eight locations by programming the isb field in the internal memory mapping register (immr). the eight possible locations are the first eight 4-mbyte memory blocks starting with address 0x0000 0000. (refer to figure 6-2.) table 6-1. usiu pin multiplexing control pin name multiplexing controlled by: irq [0]/sgpioc[0] irq [1]/rsv/ sgpioc[1] irq [2]/cr /sgpioc[2]/mts irq [3]/kr /retry/ sgpioc[3] irq[ 4]/at[2]/sgpioc[4] irq [5]/sgpioc[5]/modck[1] irq [6]/modck[2] irq [7]/modck[3] at power-on reset: modck[1:3] otherwise: programmed in siumcr sgpioc[6]/frz/ptr sgpioc[7]/irqout /lwp[0] bg /vf[0]/lwp[1] br/vf[1]/iwp[2] bb /vf[2]/iwp[3] iwp[0:1]/vfls[0:1] bi /sts we [0:3]/be [0:3]/at[0:3] tdi/dsdi/mdi[0] tck/dsck/mcki tdo/dsdo/mdo[0] programmed in siumcr and hard reset configuration data[0:31]/sgpiod[0:31] addr[8:31]/sgpioa[8:31] programmed in siumcr rstconf /texp at power-on reset: rstconf otherwise: programmed in siumcr motorola chapter 6. system configuration and protection 6-5 system configuration figure 6-2. mpc565/mpc566 memory map 6.1.3 arbitration support two bits in the siumcr control usiu bus arbitration. the external arbitration (earb) bit determines whether arbitration is performed internally or externally. if earb is cleared (internal arbitration), the external arbitration request priority (earp) bit determines the priority of an external master?s arbitration request. the operation of the internal arbiter is described in section 9.5.7.4, ?internal bus arbiter.? 0x0000 0000 0x003f ffff 0x0040 0000 0x007f ffff 0x0080 0000 0x00bf ffff 0x00c0 0000 0x00ff ffff 0x0100 0000 0x013f ffff 0x0140 0000 0x017f ffff 0x0180 0000 0x01bf ffff 0x01c0 0000 0x01ff ffff 0xffff ffff internal 4-mbyte memory block (resides in one of eight locations) 6-6 mpc565/mpc566 reference manual motorola external master modes 6.2 external master modes external master modes are special modes of operation that allow an alternative master on the external bus to access the internal modules for debugging and backup purposes. they provide access to the internal buses (u-bus and l-bus) and to the intermodule bus (imb3). there are two external master modes. peripheral mode (enabled by setting prpm in the emcr register) uses a special slave mechanism which shuts down the rcpu and an alternative master on the external bus can perform accesses to any internal bus slave. slave mode (enabled by setting slvm and clearing prpm in the emcr register) enables an external master to access any internal bus slave while the rcpu is fully operational. both modes can be enabled and disabled by software. in addition, peripheral mode can be selected from reset. the internal bus is not capable of providing priority between internal rcpu accesses and external master accesses. if the bandwidth of external master accesses is large, it is recommended that the system forces gaps between external master accesses in order to avoid suspension of internal rcpu activity. the mpc565/mpc566 does not support burst accesses from an external master; only single accesses of 8, 16, or 32 bits can be performed. the mpc565/mpc566 asserts burst inhibit (bi ) on any attempt to initiate a burst access to internal memory. the mpc565/mpc566 provides memory controller services for external master accesses (single and burst) to external memories. see chapter 10, ?memory controller,? for details. 6.2.1 operation in external master modes the external master modes are controlled by the emcr register, which contains the internal bus attributes. the default attributes in the emcr allow an external master to configure the emcr with the required attributes and access internal registers. the external master must be granted external bus ownership in order to initiate the external master access. the siu compares the address on the external bus to the allocated internal address space. if the address is within the internal space, the access is performed with the internal bus. the internal address space is determined according to the isb bit field of the immr register (see section 6.14.1.2, ?internal memory map register,? for details). the external master access is terminated by the ta , tea or retry signal on the external bus. a deadlock situation might occur if an internal-to-external access is attempted on the internal bus while an external master access is initiated on the external bus. in this case, the siu will assert the retry on the external bus in order to relinquish and retry the external access until the internal access is completed. the internal bus will deny other internal accesses for the next eight clocks in order to complete the pending accesses and prevent additional internal accesses from being initiated on the internal bus. the siu will also mask internal accesses to support consecutive external accesses if the delay between the external motorola chapter 6. system configuration and protection 6-7 external master modes accesses is less than four clocks. the external master access and retry timings are described in section 9.5.12, ?bus operation in external master modes.? the external master may access the internal mpc565/mpc566 special registers that are located outside the rcpu. in order to access one of these mpc565/mpc566 registers, program the emcr to mpc565/mpc566 special register access (cont = 1 and supu = 0 in emcr). next, access the register by providing the address according to the mpc565/mpc566 address map. only the first external master access that follows emcr setting will be assigned to the special register map; any subsequent accesses will be directed to the normal address map. this is done in order to enable access to the emcr again after the required mpc565/mpc566 special register access. peripheral mode does not require external bus arbitration between the external master and the internal rcpu, since the internal rcpu is disabled. the br and bb signals should be connected to ground, and the internal bus arbitration should be selected in order to prevent the ?slave? mpc565/mpc566 from occupying the external bus. internal bus arbitration is selected by clearing the earb bit in the siumcr (see section 6.14.1.1, ?siu module configuration register (siumcr)?). 6.2.2 address decoding for external accesses during an external master access, the usiu compares the external address with the internal address block to determine if mpc565/mpc566 operation is required. since only 24 of the 32 internal address bits are available on the external bus, the usiu assigns zeros to the most significant address bits (addr[0:7]). the address compare sequence can be summarized as follows: normal external access. if the cont bit in emcr is cleared, the address is compared to the internal address map. refer to section 6.14.1.3, ?external master control register (emcr)?. mpc565/mpc566 special register external access. if the cont bit in emcr is set by the previous external master access, the address is compared to the mpc565/mpc566 special address range. see section 5.1.2, ?usiu special-purpose registers,? for a list of the sprs in the usiu. memory controller external access. if the first two comparisons do not match, the internal memory controller determines whether the address matches an address assigned to one of the regions. if it finds a match, the memory controller generates the appropriate chip select and attribute accordingly when trying to fetch an mpc565/mpc566 special register from an external master, the address might be aliased to one of the external devices on the external bus. if this device is selected by the mpc565/mpc566 internal memory controller, this aliasing does not occur since the chip select is disabled. if the device has its own address decoding or is being selected by external logic, this case is resolved. 6-8 mpc565/mpc566 reference manual motorola usiu general-purpose i/o 6.3 usiu general-purpose i/o the usiu provides 64 general-purpose i/o (sgpio) pins (see table 6-2). the sgpio pins are multiplexed with the address and data pins. in single-chip mode, where communicating with external devices is not required, all 64 sgpio pins can be used. in multiple-chip mode, only eight sgpio pins are available. another configuration allows the use of the address bus for instruction show cycles while the data bus is dedicated to sgpio functionality. the functionality of these pins is assigned by the single-chip (sc) bit in the siumcr. (see section 6.14.1.1, ?siu module configuration register (siumcr).?) sgpio pins are grouped as follows: six groups of eight pins each, whose direction is set uniformly for the whole group 16 single pins whose direction is set separately for each pin table 6-2 describes the sgpio signals, and all available configurations. the sgpio registers are described in section 6.14.5, ?general-purpose i/o registers.? figure 6-3 illustrates the functionality of the sgpio. table 6-2. sgpio configuration sgpio group name individual pin control direction control available when sc = 00 (32-bit port size mode) available when sc = 01 (16-bit port size mode) available when sc = 10 (single-chip mode with trace) available when sc = 11 (single-chip mode) sgpiod[0:7] gddr0 x x sgpiod[8:15] gddr1 x x sgpiod[16:23] gddr2 x x x sgpiod[24:31] x sddrd[23:31] x x x sgpioc[0:7] 1 1 sgpioc[0:7] is selected according to gpc and mlrc fields in siumcr. see section 6.14.1.1, ?siu module configuration register (siumcr).? x sddrc[0:7] sgpioa[8:15] gddr3 x sgpioa[16:23] gddr4 x sgpioa[24:31] gddr5 x motorola chapter 6. system configuration and protection 6-9 enhanced interrupt controller figure 6-3. sgpio cell 6.4 enhanced interrupt controller 6.4.1 key features significant interrupt latency reduction from that of the mpc555. simplified interrupt structure up to 48 different interrupt requests splitting of single external interrupt vector into up to 48 vectors, one for each source automatic lower priority requests masking full backward compatibility with mpc555/mpc556 (enhanced mode is software programmable.) 6.4.2 interrupt configuration an overview of the mpc565/mpc566 interrupt structure is shown in figure 6-4. the interrupt controller receives interrupts from usiu internal sources, such as pit, rtc, from the uimb module (which has its own interrupt controller) or from the imb3 bus (directly from imb modules) and from external pins irq [0:7]. bus read oe internal write clock sgpio pad write read 6-10 mpc565/mpc566 reference manual motorola enhanced interrupt controller figure 6-4. mpc565/mpc566 interrupt structure if programmed to generate an interrupt, the swt and external pin irq[ 0] always generate an nmi, non-maskable interrupt to the rcpu. level 2 level 7 level 6 level5 level 4 level 3 level 1 level 0 irq [0:7] ireq to rcpu nmi gen usiu imb swt i0 regular interrupt controller selector edge det interrupt i7 i6 i5 i4 i3 i2 i1 i0 8 levels timers, change of lock enhanced interrupt controller u-bus int levelsi[0:7] imb3 ilbs[0:1] imbirq sequencer offset in branch table 6 48 16 mux sivec nmi to rcpu wake up from low-power mode siumcr eicen irqout [eicen, lpmasken] dec dec_irq to rcpu lpmasken to bbc/impu level[0:6] level[7] uimb imb_irq [0:6] imb_irq [0:6] levels[0:7] motorola chapter 6. system configuration and protection 6-11 enhanced interrupt controller note the rcpu takes the system reset exception when an nmi is asserted, the external interrupt exception for any other asserted interrupt request, and the decrementer exception when the decrementer msb changes from 0 to 1. decrementer interrupt request is not a part of the interrupt controller. each one of the external pins irq [1:7] has its own dedicated assigned priority level. irq[ 0] is also mapped, but it should be used only as a status bit indicating that irq[ 0] was asserted and generated nmi interrupt. there are eight additional interrupt priority levels. each one of the siu internal interrupt sources, or any of the peripheral module interrupt sources can be assigned by software to any one of the eight interrupt priority levels. thus, a very flexible interrupt scheme is implemented. the interrupt request signal generated by the interrupt controller is driven to the rpcu core and to the irqout pin (optionally). this pin may be used in peripheral mode, when the rcpu is disabled, and the internal modules are accessed externally. the imb interrupts are controlled by the uimb. the imb provides 32 interrupt levels, and any interrupt source could be configured to any imb interrupt level. the uimb contains a 32-bit register that holds the imb interrupt requests, and maps them to the usiu eight interrupt levels. note if one interrupt level was configured to more than one interrupt source, the software should read the uipend register in the uimb module, and the particular status bits in order to identify which interrupt was asserted. the interrupt controller may be programmed to operate in two modes?a regular mode and an enhanced mode. 6.4.3 regular interrupt controller operation (mpc555/mpc556 compatible mode) in regular operation mode (default setting) the interrupt controller receives interrupt requests from internal sources, such as timers, pll lock detector, imb modules and from external pins irq [0:7]. all the internal interrupt sources may be programmed to drive one or more of eight u-bus interrupt level lines while the rcpu, upon receiving an interrupt request, has to read the usiu and uimb status register in order to determine the interrupt source. the sivec register contains an 8-bit code representing the unmasked interrupt request which has the highest priority level. the priority between all interrupt sources for the regular interrupt controller operation is shown in table 6-3. 6-12 mpc565/mpc566 reference manual motorola enhanced interrupt controller each interrupt request from external lines and from usiu internal interrupt sources in the case of its assertion will set a corresponding bit in sipend register. the individual sipend bits may be masked by clearing an appropriate bit in simask register. 6.4.4 enhanced interrupt controller 6.4.4.1 general operation the enhanced interrupt controller operation may be turned on by setting the eicen control bit in siumcr register. in this mode the 32 imb interrupt levels will be latched by usiu using eight imb interrupt lines and two lines of ilbs via time multiplexing scheme defined by the uimb module. in addition to the imb interrupt sources the external interrupts and timer interrupts are available in the same way as in the regular scheme. in this mode, the uimb module does not drive u-bus interrupt level lines. each interrupt request will set a corresponding bit in sipend2 or sipend3 registers. sipend2 an sipend3 may be masked by clearing an appropriate bit in simask2 or simask3 registers. table 6-3. priority of interrupt sources?regular operation number priority level interrupt source description offset in branch table (hex) sivec interrupt code 1 1 this is the value in the 8 most significant bits of the sivec register (sivec[25:31]). 0 highest ext_irq [0] 0x0000 00000000 1 ? level 0 0x0008 00000100 2 ? ext_irq [1] 0x0010 00001000 3 ? level 1 0x0018 00001100 4 ? ext_irq [2] 0x0020 00010000 5 ? level 2 0x0028 00010100 6 ? ext_irq [3] 0x0030 00011000 7 ? level 3 0x0038 00011100 8 ? ext_irq [4] 0x0040 00100000 9 ? level 4 0x0048 00100100 10 ? ext_irq [5] 0x0050 00101000 11 ? level 5 0x0058 00101100 12 ? ext_irq [6] 0x0060 00110000 13 ? level 6 0x0068 00110100 14 ? ext_irq [7] 0x0070 00111000 15 lowest level 7 0x0078 00111100 motorola chapter 6. system configuration and protection 6-13 enhanced interrupt controller the priority logic is provided in order to determine the highest unmasked interrupt request, and interrupt code is generated in the sivec register. see table 6-4. table 6-4. priority of interrupt sources?enhanced operation 1 number priority level interrupt source description offset in branch table (hex) 2 sivec interrupt code 3 0 highest ext_irq [0] 0x0000 00000000 1 ? level 0 0x0008 00000100 2 ? imb_irq 0 0x0010 00001000 3 ? imb_irq 1 0x0018 00001100 4 ? imb_irq 2 0x0020 00010000 5 ? imb_irq 3 0x0028 00010100 6 ? ext_irq [1] 0x0030 00011000 7 ? level 1 0x0038 00011100 8 ? imb_irq 4 0x0040 00100000 9 ? imb_irq 5 0x0048 00100100 10 ? imb_irq 6 0x0050 00101000 11 ? imb_irq 7 0x0058 00101100 12 ? ext_irq [2] 0x0060 00110000 13 ? level 2 0x0068 00110100 14 ? imb_irq 8 0x0070 00111000 15 ? imb_irq 9 0x0078 00111100 16 ? imb_irq 10 0x0080 01000000 17 ? imb_irq 11 0x0088 01000100 18 ? ext_irq [3] 0x0090 01001000 19 ? level 3 0x0098 01001100 20 ? imb_irq 12 0x00a0 01010000 21 ? imb_irq 13 0x00a8 01010100 22 ? imb_irq 14 0x00b0 01011000 23 ? imb_irq 15 0x00b8 01011100 24 ? ext_irq [4] 0x00c0 01100000 25 ? level 4 0x00c8 01100100 26 ? imb_irq 16 0x00d0 01101000 27 ? imb_irq 17 0x00d8 01101100 28 ? imb_irq 18 0x00e0 01110000 29 ? imb_irq 19 0x00e8 01110100 30 ? ext_irq [5] 0x00f0 01111000 6-14 mpc565/mpc566 reference manual motorola enhanced interrupt controller the value of the sivec register is supplied internally to the bbc module and can be used as an offset to the branch table start address for the external interrupt relocation feature. thus a fast way to a specific interrupt source routine is provided without software overhead. the bbcmcr (see section 4.7.2.1, ?bbc module configuration register bbcmcr?) and eibadr (see section 4.7.2.5, ?external interrupt relocation table base address register ? eibadr?) registers must be programmed to enable this feature in the bbc. additionally, the sipend2 and sipend3 registers contain the information about all the interrupt requests that are asserted at a given time, so that software can always read them. note when the enhanced interrupt controller is enabled the sipend and simask registers are not used. 31 ? level 5 0x00f8 01111100 32 ? imb_irq 20 0x0100 10000000 33 ? imb_irq 21 0x0108 10000100 34 ? imb_irq 22 0x0110 10001000 35 ? imb_irq 23 0x0118 10001100 36 ? ext_irq [6] 0x0120 10010000 37 ? level 6 0x0128 10010100 38 ? imb_irq 24 0x0130 10011000 39 ? imb_irq 25 0x0138 10011100 40 ? imb_irq 26 0x0140 10100000 41 ? imb_irq 27 0x0148 10100100 42 ? ext_irq [7] 0x0150 10101000 43 ? level 7 0x0158 10101100 44 ? imb_irq 28 0x0160 10110000 45 ? imb_irq 29 0x0168 10110100 46 ? imb_irq 30 0x0170 10111000 47 lowest imb_irq 31 0x0178 10111100 1 the bbcmcr[eir] bit must be set to use this enhanced interrupt feature. 2 this offset is added to the table base address from the eibdr register. 3 this is the value in the 8 most significant bits of the sivec register. table 6-4. priority of interrupt sources?enhanced operation 1 (continued) number priority level interrupt source description offset in branch table (hex) 2 sivec interrupt code 3 motorola chapter 6. system configuration and protection 6-15 enhanced interrupt controller 6.4.4.2 lower priority request masking this feature (if enabled) simplifies the masking of lower priority interrupt requests when a request of certain priority is in service in applications that require interrupt nesting. the highest (pending) request is also masked by itself. the masking is accomplished in the following way. upon asserting an interrupt request the bbc generates an acknowledge signal to notify the interrupt controller that the request and the branch table offset have been latched. the interrupt controller then sets a bit in the sisr register (interrupt in-service register), according to the asserted request. all other requests whose priority is lower than or equal to the one that is currently in-service, become masked. the mask remains set until the sisr bit is cleared by software (by the interrupt handler routine), writing a ?1? value to the corresponding bit. the lower priority request masking diagram is presented in figure 6-5. the lower priority request masking feature is disabled by hreset and it may be enabled by setting the lpmask_en bit in the siumcr register. note in regular mode of the interrupt controller the lower priority request masking feature is not possible. the feature must be activated only together with exception table relocation in the bbc module. figure 6-5. lower priority request masking?one bit diagram enable control bit from bit i - 1 to b i t i + 1 set reset by software sipend [i] simask [i] to rcpu sisr[i] generation (or between all the bits) to sivec generation impu acknowledge (lpmask_en) reset external interrupt request 6-16 mpc565/mpc566 reference manual motorola enhanced interrupt controller 6.4.4.3 backward compatibility with mpc555/mpc556 the enhanced interrupt controller is a feature that may be enabled according to a user?s application using the eicen control bit in siumcr register, which can be set and cleared at any time by software. if the bit is cleared, the default interrupt controller operation is available, as described in section 6.4.3, ?regular interrupt controller operation (mpc555/mpc556 compatible mode)?. the regular operation is fully compatible with the interrupt controller already implemented in mpc555/mpc556. figure 6-6 illustrates the interrupt controller functionality in the mpc565/mpc566. motorola chapter 6. system configuration and protection 6-17 enhanced interrupt controller figure 6-6. mpc565/mpc566 interrupt controller block diagram sipend siel s i v e c priority encoder 8 interrupt vector (6 from 48) (enables branch to the highest priority interrupt routine) sipend2 sipend3 simask2 simask3 interrupt request (to rcpu and irqout pad) ubus int levels[0:7] (offset to branch table ? to bbc) imb irq sequencer 32 8 imb_irq[0:7] ilbs[0:1] simask synchronizer external irq 8 wake up from low-power mode mux enhanced interrupt. controller enabled sisr2 sisr3 from imb 5 5 48 16 0 1 6-18 mpc565/mpc566 reference manual motorola interrupt overhead estimation for enhanced interrupt controller mode 6.5 interrupt overhead estimation for enhanced interrupt controller mode the interrupt overhead consists of two main parts: storage of general and special purpose registers recognition of the interrupt source the interrupt overhead can lead to large latency, and decrease the overall system performance. the overhead of register saving time can be reduced by improving the operating system. the number of registers that should be saved can be reduced if each interrupt event has its own interrupt vector. this solution solves the interrupt source recognition overhead. table 6-5 below illustrates the improvements. only registers required for the recognition routine are considered to be saved in the calculations below. recognition of module internal events/channels is out of the scope of the calculations. see also the typical interrupt handler flowchart in figure 6-7. table 6-5. interrupt latency estimation for three typical cases mpc555/mpc556 architecture without using sivec mpc565/mpc566 architecture using sivec mpc565/mpc566 architecture using enhanced interrupt controller features operation details interrupt propagation from request module to rcpu ? 8clocks storeofsomegprand spr?10 clocks read sipend?4 clocks read simask?4 clocks sipend data processing ? 20 clocks (find first set, access to lut in the flash, branches) read uipend?4 clocks uipend data processing?20 clocks (find first set, access to lut in the flash, branches) interrupt propagation from request module to rcpu ? 8clocks store of some gpr and spr ?10 clocks read sivec?4 clocks branch to routine?10 clocks read uipend?4 clocks uipend data processing ? 20 clocks (find first set, access to lut in the flash, branches) interrupt propagation from request module to rcpu ? 6clocks storeofsomegprand spr?10 clocks only one branch is executed to reach the interrupt handler routine of the device requesting interrupt servicing?2 clocks notes: if there is a need to enable nesting of interrupts during source recognition procedure, at least 30 clocks should be added to the interrupt latency estimation to use this feature in compressed mode some undetermined latency is added to make a branch to compressed address of the routine. this latency is dependant on how the user code is implemented. ? total: at least 70-80 clocks at least 50-60 clocks 20 clocks motorola chapter 6. system configuration and protection 6-19 interrupt overhead estimation for enhanced interrupt controller mode note compiler and bus collision overhead are not included in the calculations. . figure 6-7. typical interrupt handler routine start saving the cpu context masking lower priority requests clearing interrupt source clearing mask rfi clearing in-service bit legend: flow with lower priority masking enabled restoring the cpu context flow without lower priority masking enabled disabling interrupt handler body enabling interrupt 6-20 mpc565/mpc566 reference manual motorola hardware bus monitor 6.6 hardware bus monitor the bus monitor ensures that each bus cycle is terminated within a reasonable period of time. the usiu provides a bus monitor option to monitor internal to external bus accesses on the external bus. the monitor counts from transfer start to transfer acknowledge and from transfer acknowledge to transfer acknowledge within bursts. if the monitor times out, transfer error acknowledge (tea ) is asserted internally. the bus monitor timing bit in the system protection control register (sypcr) defines the bus monitor time-out period. the programmability of the time-out allows for variation in system peripheral response time. the timing mechanism is clocked by the system clock divided by eight. the maximum value is 2040 system clock cycles. the bus monitor enable (bme) bit in the sypcr enables or disables the bus monitor. the bus monitor is always enabled when freeze is asserted or when a debug mode request is pending, regardless of the state of this bit. 6.7 decrementer (dec) the decrementer (dec) is a 32-bit decrementing counter defined by the mpc565/mpc566 architecture to provide a decrementer interrupt. this binary counter is clocked by the same frequency as the time base (also defined by the mpc565/mpc566 architecture). the operation of the time base and decrementer are therefore coherent. the dec is clocked by the tmbclk clock. the decrementer period is computed as follows: the state of the dec is not affected by any resets and should be initialized by software. the dec runs continuously after power-up once the time base is enabled by setting the tbe bit of the tbscr (see table 6-18) (unless the clock module is programmed to turn off the clock). the decrementer continues counting while reset is asserted. reading from the decrementer has no effect on the counter value. writing to the decrementer replaces the value in the decrementer with the value in the gpr. whenever bit 0 (the msb) of the decrementer changes from zero to one, a decrementer exception occurs. if software alters the decrementer such that the content of bit 0 is changed to a value of 1, a decrementer exception occurs. a decrementer exception causes a decrementer interrupt request to be pending in the rcpu. when the decrementer exception is taken, the decrementer interrupt request is automatically cleared. table 6-6 illustrates some of the periods available for the decrementer, assuming a 4-mhz or 20-mhz crystal, and tbs = 0 which selects tmbclk division to 4. tdec = 2 32 ftmbclk motorola chapter 6. system configuration and protection 6-21 time base (tb) note time base must be enabled to use the decrementer. see section 6.14.4.4, ?time base control and status register,? for more information. refer to section 3.9.5, ?decrementer register (dec),? for more information. 6.8 time base (tb) the time base (tb) is a 64-bit free-running binary counter defined by the mpc565/mpc566 architecture. the tb has two independent reference registers which can generate a maskable interrupt when the time base counter reaches the value programmed in one of the two reference registers. the period of the tb depends on the driving frequency. the tb is clocked by the tmbclk clock. the period for the tb is: the state of tb is not affected by any resets and should be initialized by software. reads and writes of the tb are restricted to special instructions. separate special-purpose registers are defined in the mpc565/mpc566 architecture for reading and writing the tb. for the mpc565/mpc566 implementation, it is not possible to read or write the entire tb in a single instruction. therefore, the mttb and mftb instructions are used to move the lower half of the time base (tbl) while the mttbu and mftbu instructions are used to move the upper half (tbu). two reference registers are associated with the time base: tbref0 and tbref1. a maskable interrupt is generated when the tb count reaches to the value programmed in one table 6-6. decrementer time-out periods count value time-out @ 4 mhz time-out @ 20 mhz 01.0s0.2s 910s2.0s 99 100 s 20 s 999 1.0 ms 200 s 9999 10.0 ms 2 ms 999999 1.0 s 200 ms 9999999 10.0 s 2.0 s 99999999 100.0 s 20 s 999999999 1000 s 200 s (hex) ffffffff 4295 s 859 s t tb 2 64 f tmbclk ----------------------------- - = 6-22 mpc565/mpc566 reference manual motorola real-time clock (rtc) of the two reference registers. two status bits in the time base control and status register (tbscr) indicate which one of the two reference registers generated the interrupt. refer to section 6.14.4, ?system timer registers,? for diagrams and bit descriptions of tb registers. refer to section 3.9.4, ?time base facility (tb) ? oea,? and to the rcpu reference manual for additional information. 6.9 real-time clock (rtc) the rtc is a 32-bit counter and pre-divider used to provide a time-of-day indication to the operating system and application software as show in figure 6-8. it is clocked by the pitrtclk clock. the counter is not affected by reset and operates in all low-power modes. it is initialized by software. the rtc can be programmed to generate a maskable interrupt when the time value matches the value programmed in its associated alarm register. it can also be programmed to generate an interrupt once a second. a control and status register is used to enable or disable the different functions and to report the interrupt source. note pitrtclk can be divided by 4 or 256. see table 8-1 for default settings. figure 6-8. rtc block diagram 6.10 periodic interrupt timer (pit) the periodic interrupt timer consists of a 16-bit counter clocked by the pitrtclk clock signal supplied by the clock module as shown in figure 6-9. the 16-bit counter counts down to zero when loaded with a value from the pitc register. after the timer reaches zero, the ps bit is set and an interrupt is generated if the pie bit is a logic one. the software service routine should read the ps bit and then write a zero to pitrtclk freeze divide 32-bit register (rtcal) sec alarm = clock disable divide mux 4-mhz/20-mhz crystal interrupt interrupt by 78125 by 15625 clock rtsec 32-bit counter (rtc) motorola chapter 6. system configuration and protection 6-23 software watchdog timer (swt) terminate the interrupt request. at the next input clock edge, the value in the pitc is loaded into the counter, and the process starts over again. when a new value is written into the pitc, the periodic timer is updated, the divider is reset, and the counter begins counting. if the ps bit is not cleared, an interrupt request is generated. the request remains pending until ps is cleared. if the ps bit is set again prior to being cleared, the interrupt remains pending until ps is cleared. any write to the pitc stops the current countdown, and the count resumes with the new value in pitc. if the piscr[pte] bit is not set, the pit is unable to count and retains the old count value. reads of the pit have no effect on the counter value. figure 6-9. pit block diagram the timeout period is calculated as: solving this equation using a 4-mhz external clock and a pre-divider of 256 gives: this gives a range from 64 microseconds, with a pitc of 0x0000, to 4.19 seconds, with a pitc of 0xffff. when a 20-mhz crystal is used with a pre-divider of 256, the range is between 12.8 microseconds to 0.84 seconds. 6.11 software watchdog timer (swt) the software watchdog timer (swt) prevents system lockout in case the software becomes trapped in loops with no controlled exit. the swt is enabled after system reset to cause a system reset if it times out. it. the swt requires a special service sequence to be executed on a periodic basis. if this periodic servicing action does not occur, the swt times out and clock 16-bit pitc pitrtclk ps (piscr) pie (piscr) pit pte disable clock modulus counter interrupt pitf (piscr) (piscr) (piscr) pit period pitc 1 + f pitrtclk ---------------------------------- - pitc 1 + externalclock 4or256 ---------------------------------------- - ?? 6-24 mpc565/mpc566 reference manual motorola software watchdog timer (swt) issues a reset or a non-maskable interrupt (nmi), depending on the value of the swri bit in the sypcr register. the swt can be disabled by clearing the swe bit in the sypcr. once the sypcr is written by software, the state of the swe bit cannot be changed. the swt service sequence consists of the following two steps: 1. write 0x556c to the software service register (swsr) 2. write 0xaa39 to the swsr the service sequence clears the watchdog timer and the timing process begins again. if any value other than 0x556c or 0xaa39 is written to the swsr, the entire sequence must start over. although the writes must occur in the correct order prior to time-out, any number of instructions may be executed between the writes. this allows interrupts and exceptions to occur, if necessary, between the two writes. figure 6-10. swt state diagram although most software disciplines support the watchdog concept, different systems require different time-out periods. for this reason, the software watchdog provides a selectable range for the time-out period. in figure 6-11, the range is determined by the value swtc field. the value held in the swtc field is then loaded into a 16-bit decrementer clocked by the system clock. an additional divide by 2048 prescaler is used if necessary. the decrementer begins counting when loaded with a value from the software watchdog timing count field (swtc). after the timer reaches 0x0, a software watchdog expiration request is issued to the reset or nmi control logic. 0x556c/don?t reload reset 0xaa39/reload state 0 waiting for 0x556c state 1 waiting for 0xaa39 not0xaa39/don?treload not 0x556c/don?t reload not 0x556c/don?t reload motorola chapter 6. system configuration and protection 6-25 freeze operation upon reset, the value in the swtc is set to the maximum value and is again loaded into the software watchdog register (swr), starting the process over. when a new value is loaded into the swtc, the software watchdog timer is not updated until the servicing sequence is written to the swsr. if the swe is loaded with the value zero, the modulus counter does not count (i.e. swtc is disabled). figure 6-11. swt block diagram 6.12 freeze operation when the freeze line is asserted, the clocks to the software watchdog, the periodic interrupt timer, the real-time clock, the time base counter, and the decrementer can be disabled. this is controlled by the associated bits in the control register of each timer. if programmed to stop during freeze assertion, the counters maintain their values while freeze is asserted. the bus monitor remains enabled regardless of this signal. 6.13 low power stop operation when the processor is set in a low-power mode (doze, sleep, or deep-sleep), the software watchdog timer is frozen. it remains frozen and maintains its count value until the processor exits this state and resumes executing instructions. the periodic interrupt timer, decrementer, and time base are not affected by these low-power modes. they continue to run at their respective frequencies. these timers are capable of generating an interrupt to bring the mcu out of these low-power modes. disable clock freeze swr/decrementer time-out 16-bit swtc swe service logic reload rollover = 0 reset swsr mux 2048 system swp clock divide by or nmi (sypcr) (sypcr) 6-26 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14 system configuration and protection registers this section provides diagrams and bit descriptions of the system configuration and protection registers. 6.14.1 system configuration registers system configuration registers include the siumcr, the immr and the emcr registers. 6.14.1.1 siu module configuration register (siumcr) the siumcr contains bits which configure various features in the siu module. the register contents are shown below. warning all siumcr fields which are controlled by the reset configuration word should not be changed by software while the corresponding functions are active. msb 0 1 2 3 4567 8 9 10 11 12131415 earb earp reserved dshw dbgc reser ved 1 atwc gpc dlk hreset: id(0) 2 0 0 0 0000 0 id(9:10) 3 id(11) 4 id(12) 5 00 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 rese rved sc rctx mlrc reserved mtsc nos how eicen lpmask _en reserved hreset: 0id(17:18) 6 0000000000000 1 dbpc in mask set k85h. 2 the hreset value is a reset configuration word value, extracted from the internal data bus id(0) line. 3 the hreset value is a reset configuration word value, extracted from the internal data bus id(9:10) lines. 4 the hreset value is a reset configuration word value, extracted from the internal data bus id(11) line. 5 the hreset value is a reset configuration word value, extracted from the internal data bus id(12) line. 6 the hreset value is a reset configuration word value, extracted from the internal data bus id(17:18) lines. figure 6-12. siumcr?siu module configuration register 0x2f c000 motorola chapter 6. system configuration and protection 6-27 system configuration and protection registers table 6-7. siumcr bit descriptions bit(s) name description 0 earb external arbitration 0 internal arbitration is performed 1 external arbitration is assumed 1:3 earp external arbitration request priority. this field defines the priority of an external master?s arbitration request. this field is valid when earb is cleared. refer to section 9.5.7.4, ?internal bus arbiter,? for details. 4:7 ? reserved 8 dshw data show cycles. this bit selects the show cycle mode to be applied to u-bus data cycles (data cycles to imb modules and flash eeprom). this field is locked by the dlk bit. note that instruction show cycles are programmed in the ictrl and l-bus data show cycles are programmed in the l2umcr. 0 disable show cycles for all internal data cycles 1 show address and data of all internal data cycles 9:10 dbgc debug pins configuration. refer to table 6-8. 11 dbpc reserved. 1 12 atwc address write type enable configuration. this bit configures the pins to function as byte write enables or address types for debugging purposes. 0we [0:3]/be [0:3]/at[0:3] functions as we [0:3]/be [0:3] 2 1we [0:3]/be [0:3]/at[0:3] functions as at[0:3] 13:14 gpc this bit configures the pins as shown in table 6-9 . 15 dlk debug register lock 0 normal operation 1 siumcr is locked and can be written only in test mode or when the internal freeze signal is asserted. 16 ? reserved 17:18 sc single-chip select. this field configures the functionality of the address and data buses. changing the sc field while external accesses are performed is not supported. refer to table 6-10. 19 rctx reset configuration/timer expired. during reset the rstconf/texp pin functions as rstconf. after reset the pin can be configured to function as texp, the timer expired signal that supports the low-power modes. 0 rstconf/texp functions as rstconf 1 rstconf/texp functions as texp 20:21 mlrc multi-level reservation control. this field selects between the functionality of the reservation logic and irq pins, refer to table 6-11. 22:23 ? reserved 24 mtsc memory transfer start control. 0irq[ 2]/cr/ sgpioc[2]/mts functions according to the mlrc bits setting 1irq[ 2]/cr/ sgpioc[2]/mts functions as mts 25 noshow instruction show cycles disabled?if the noshow bit is set (1), then all instruction show cycles are not transmitted to the external bus. 26 eicen enhanced interrupt controller enable. 0 enhanced interrupt controller operates in regular mode (compatible with mpc555/mpc556) 1 enhanced interrupt controller is enabled 6-28 mpc565/mpc566 reference manual motorola system configuration and protection registers 27 lpmask _en low priority request masking enable. 0 lower priority interrupt request masking is disabled 1 lower priority interrupt request masking is enabled 28:31 ? reserved 1 dbpc on mask set k85h. 0 = dsck, dsdi, dsdo selected. 1 = tck, tdi, tdo selected. 2 we /be is selected per memory region by webs in the appropriate br register in the memory controller. table 6-8. debug pins configuration dbgc pin function iwp[0:1]/vfls[0:1] bi /sts bg /vf[0]/lwp[1] br /vf[1]/iwp[2] bb /vf[2]/iwp[3] 00 vfls[0:1] bi bg br bb 01 iwp[0:1] sts bg br bb 10 vfls[0:1] sts vf[0] vf[1] vf[2] 11 iwp[0:1] sts lwp[1] iwp[2] iwp[3] table 6-9. general pins configuration gpc pin function frz/ptr/sgpioc[6] irqout /lwp[0]/sgpioc[7] 00 ptr lwp[0] 01 sgpioc[6] sgpioc[7] 10 frz lwp[0] 11 frz irqout table 6-10. single-chip select field pin configuration sc pin function data[0:15]/ sgpiod[0:15] data[16:31] sgpiod[16:31] addr[8:31]/ sgpioa[8:31] 00 (multiple chip, 32-bit port size) data[0:15] data[16:31] addr[8:31] 01 (multiple chip, 16-bit port size data[0:15] spgiod[16:31] addr[8:31] 10 (single-chip with address show cycles for debugging) spgiod[0:15] spgiod[16:31] addr[8:31] 11 (single-chip) spgiod[0:15] spgiod[16:31] spgioa[8:31] table 6-7. siumcr bit descriptions (continued) bit(s) name description motorola chapter 6. system configuration and protection 6-29 system configuration and protection registers 6.14.1.2 internal memory map register the internal memory map register (immr) is a register located within the mpc565/mpc566 special register space. the immr contains identification of a specific device as well as the base for the internal memory map. based on the value read from this register, software can deduce availability and location of any on-chip system resources. this register can be read by the mfspr instruction. the isb field can be written by the mtspr instruction. the partnum and masknum fields are mask programmed and cannot be changed. table 6-11. multi-level reservation control pin configuration mlrc pin function irq[ 0]/ sgpioc[0]/ mdo[4] irq[ 1]/rsv / sgpioc[1] irq[ 2]/cr/ sgpioc[2]/mts irq3 /kr / retry /sgpioc[3] irq4 /at[2]/ sgpioc[4] irq[ 5]/ sgpioc[5]/modck[1] 1 1 operates as modck[1] during reset. 00 irq [0] irq[1] irq [2] 2 2 this is true if mtsc is reset to 0. otherwise, irq[ 2]/cr/ sgpioc[2]/mts will function as mts . irq [3] irq [4] irq [5]/modck [1] 01 irq [0] rsv cr 2 kr /retry at[2] irq [5]/ modck[1] 10 sgpioc0 sgpioc[1] sgpioc[2] 2 sgpioc[3] sgpioc[4] sgpioc[5]/modck[1] 11 irq [0] irq [1] sgpioc[2] 2 kr /retry at[2] sgpioc[5]/modck[1] msb 0 123456789101112131415 partnum masknum reset: 00110011 read-onlyfixedvalue 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved flen reserved rese rved reserved isb 0 reset: 0000id20 1 00id23 1 0000 id[28:30]* 0 1 the reset value is a reset configuration word value extracted from the indicated bits of the internal data bus. refer to section 7.5.2, ?hard reset configuration word.? figure 6-13. immr?internal memory mapping register spr 638 6-30 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14.1.3 external master control register (emcr) the external master control register selects the external master modes and determines the internal bus attributes for external-to-internal accesses. table 6-12. immr bit descriptions bit(s) name description 0:7 partnum this read-only field is mask programmed with a code corresponding to the part number of the part on which the siu is located. it is intended to help factory test and user code which is sensitive to part changes. this changes when the part number changes. for example, it would change if any new module is added, if the size of any memory module is changed. it would not change if the part is changed to fix a bug in an existing module. the mpc565/mpc566 chip has an id of 0x33. 8:15 masknum this read-only field is mask programmed with a code corresponding to the mask number of the part. it is intended to help factory test and user code which is sensitive to part changes. 16:19 ? reserved 20 flen flash enable is a read-write bit. the default state of flen is negated, meaning that the boot is performed from external memory. this bit can be set at reset by the reset configuration word. 0 on-chip flash memory is disabled, and all internal cycles to the allocated flash address space are mapped to external memory 1 on-chip flash memory is enabled 21:22 ? reserved 23 ? reserved. this bit should be programmed to 0 at all times. 24:27 ? reserved 28:30 isb this read-write field defines the base address of the internal memory space. the initial value of this field can be configured at reset to one of eight addresses, and then can be changed to any value by software. internal base addresses are as follows: 000 0x0000 0000 001 0x0040 0000 010 0x0080 0000 011 0x00c0 0000 100 0x0100 0000 101 0x0140 0000 110 0x0180 0000 111 0x01c0 0000 31 ? reserved motorola chapter 6. system configuration and protection 6-31 system configuration and protection registers msb 0 123456789101112131415 reserved reset: 0 000000000 0 000 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 prpm slvm 0 size supu inst reserved resv cont 0 trac sizen reserved reset: id16 1 000101001 1 011 00 1 the reset value is a reset configuration word value, extracted from the indicated internal data bus line. refer to section 7.5.2, ?hard reset configuration word.? figure 6-14. emcr?external master control register 0x2f c030 table 6-13. emcr bit descriptions bit(s) name description 0:15 ? reserved 16 prpm peripheral mode. in this mode, the internal rcpu core is shut off and an alternative master on the external bus can access any internal slave module. the reset value of this bit is determined by the reset configuration word bit 16. the bit can also be written by software. 0 normal operation 1 peripheral mode operation 17 slvm slave mode (valid only if prpm = 0). in this mode, an alternative master on the external bus can access any internal slave module while the internal rcpu core is fully operational. if prpm is set, the value of slvm is a ?don?t care.? 0 normal operation 1slavemode 18 ? reserved 19:20 size size attribute. if sizen = 1, the size bits controls the internal bus attributes as follows: 00 double word (8 bytes) 01 word (4 bytes) 10 half word (2 bytes) 11 byte 21 supu supervisor/user attribute. supu controls the supervisor/user attribute as follows: 0 supervisor mode access permitted to all registers 1 user access permitted to registers designated ?user access? 22 inst instruction attribute. inst controls the internal bus instruction attribute as follows: 0 instruction fetch 1 operand or non-cpu access 23:24 ? reserved 25 resv reservation attribute. resv controls the internal bus reservation attribute as follows: 0 storage reservation cycle 1 not a reservation 6-32 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14.2 siu interrupt controller registers the siu interrupt controller contains the following registers: sipend, sipend2 and sipend3 (interrupt pending registers), simask, simask2 and simask3 (interrupt mask registers), siel, sivec, sisr2 and sisr3. the sipend and simask registers are used when the interrupt controller is configured for regular, mpc555/mpc556 compatible, operation. sipend2, sipend3, simask2, simask3, sisr2 and sisr3 registers are used only when the interrupt controller is operating in enhanced interrupt mode. sipend, sipend2 and sipend3 are 32-bit registers. each bit in the register corresponds to an interrupt request. the bits associated with internal exceptions indicate, if set, that an interrupt service is requested. these bits reflect the status of the internal requesting device, and will be cleared when the appropriate actions are initiated by software in the device itself. writing to these bits has no effect. the bits associated with the irq pins have a different behavior depending on the sensitivity defined for them in the siel register. when the irq is defined as a ?level? interrupt the corresponding bit behaves in a manner similar to the bits associated with internal interrupt sources, (i.e., it reflects the status of the irq pin). this bit can not be changed by software, it will be cleared when the external signal is negated. when the irq is defined as an ?edge? interrupt, if the corresponding bit is set, it indicates that a falling edge was detected on the line. the bit must be reset by software by writing a ?1? to it. the following acronym definitions apply to the various bits implemented in the siu interrupt controller registers. 26 cont control attribute. cont drives the internal bus control bit attribute as follows: 0 access to mpc565/mpc566 control register, or control cycle access 1 access to global address map 27 ? reserved 28 trac trace attribute. trac controls the internal bus program trace attribute as follows: 0 program trace 1 not program trace 29 sizen external size enable control bit. sizen determines how the internal bus size attribute is driven: 0 drive size from external bus signals tsize[0:1] 1 drive size from size0, size1 in emcr 30:31 ? reserved table 6-13. emcr bit descriptions (continued) bit(s) name description motorola chapter 6. system configuration and protection 6-33 system configuration and protection registers 6.14.2.1 siu interrupt pending register 6.14.2.2 siu interrupt pending register 2 table 6-14. siu interrupt controller ? bit acronym definitions name description irqn interrupt n request lvln interrupt level n imbirqn intermodule bus interrupt n request irmn interrupt n mask lvmn interrupt level n mask edn falling edge detect, interrupt n wmn wakeup mask, interrupt n msb 0 123456789101112131415 irq0 lvl0 irq1 lvl1 irq2 lvl2 irq3 lvl3 irq4 lvl4 irq5 lvl5 irq6 lvl6 irq7 lvl7 sreset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved sreset: 0000000000000000 figure 6-15. sipend?siu interrupt pending register 0x2f c010 msb 0 1234 5 6 789101112131415 irq0 lvl0 imb irq0 imb irq1 imb irq2 imb irq3 irq1 lvl1 imb irq4 imb irq5 imb irq6 imb irq7 irq2 lvl2 imb irq8 imb irq9 sreset: 0 0 00 0 0 0 0 000 0 0 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 imb irq10 imb irq11 irq3 lvl3 imb irq12 imb irq13 imb irq14 imb irq15 irq4 lvl4 imb irq16 imb irq17 imb irq18 imb irq19 irq5 lvl5 sreset: 0 0 00 0 0 0 0 000 0 0 0 00 figure 6-16. sipend2?siu interrupt pending register 2 0x2f c040 6-34 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14.2.3 siu interrupt pending register 3 6.14.2.4 siu interrupt mask register simask is a 32-bit read/write register. each bit in the register corresponds to an interrupt request bit in the sipend register. simask2 is a 32-bit read/write register. each bit in the register corresponds to an interrupt request bit in the sipend2 register. simask3 is a 32-bit read/write register. each bit in the register corresponds to an interrupt request bit in the sipend3 register. when the bit is set, it enables the generation of an interrupt request to the rcpu. simask, simask2, simask3 are updated by software and cleared upon reset. it is the responsibility of the software to determine which of the interrupt sources are enabled at a given time. note to mask interrupt sources, first set the core?s status register interrupt mask level to that of the source being masked in simask. then, the simask bit can be masked. msb 0 123456789101112131415 imb irq20 imb irq21 imb irq22 imb irq23 irq6 lvl6 imb irq24 imb irq25 imb irq26 imb irq27 irq7 lvl7 imb irq28 imb irq29 imb irq30 imb irq31 sreset: 0 0 0 0 000 0 0 0 00 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved sreset: 0 0 0 0 000 0 0 0 00 0 0 0 0 figure 6-17. sipend3?siu interrupt pending register3 0x2f c044 motorola chapter 6. system configuration and protection 6-35 system configuration and protection registers 6.14.2.5 siu interrupt mask register 2 msb 0 123456789101112131415 irm0 1 lvm0 irm1 lvm1 irm2 lvm2 irm3 lvm3 irm4 lvm4 irm5 lvm5 irm6 lvm6 irm7 lvm7 sreset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved sreset: 0000000000000000 1 irq [0] of the sipend register is not affected by the setting or clearing of the irm0 bit of the simask register. irq [0] is a non-maskable interrupt figure 6-18. simask?siu interrupt mask register 0x2f c014 msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 irq0 1 lvl0 imb irq0 imb irq1 imb irq2 imb irq3 irq1 lvl1 imb irq4 imb irq5 imb irq6 imb irq7 irq2 lvl2 imb irq8 imb irq9 sreset: 0 0 00 0 0 0 0 00 0 0 0 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 imb irq10 imb irq11 irq3 lvl3 imb irq12 imb irq13 imb irq14 imb irq15 irq4 lvl4 imb irq16 imb irq17 imb irq18 imb irq19 irq5 lvl5 sreset: 0 0 00 0 0 0 0 00 0 0 0 0 00 1 irq [0] of the sipend register is not affected by the setting or clearing of the irm0 bit of the simask register. irq [0] is a non-maskable interrupt figure 6-19. simask2?siu interrupt mask register2 0x2f c048 6-36 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14.2.6 siu interrupt mask register 3 6.14.2.7 siu interrupt edge level register (siel) the siel is a 32-bit read/write register. each pair of bits corresponds to an external interrupt request. the edx bit, if set, specifies that a falling edge in the corresponding irq line will be detected as an interrupt request. when the edx bit is 0, a low logical level in the irq line will be detected as an interrupt request. the wmx (wake-up mask) bit, if set, indicates that an interrupt request detection in the corresponding line causes the mpc565/mpc566 to exit low-power mode. 6.14.2.8 siu interrupt vector register the sivec is a 32-bit read-only register that contains an 8-bit code representing the unmasked interrupt source of the highest priority level. the sivec can be read as either a byte, half word, or word. when read as a byte, a branch table can be used in which each entry contains one instruction (branch). when read as a half-word, each entry can contain msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 imb irq20 imb irq21 imb irq22 imb irq23 irq6 lvl6 imb irq24 imb irq25 imb irq26 imb irq27 irq7 lvl7 imb irq28 imb irq29 imb irq30 imb irq31 sreset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved sreset: 0000000000000000 figure 6-20. simask3?siu interrupt mask register3 0x2f c04c msb 0 123456789101112131415 ed0 wm0 ed1 wm1 ed2 wm2 ed3 wm3 ed4 wm4 ed5 wm5 ed6 wm6 ed7 wm7 reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved reset: 0000000000000000 figure 6-21. siel?siu interrupt edge level register 0x2f c018 motorola chapter 6. system configuration and protection 6-37 system configuration and protection registers a full routine of up to 256 instructions. the interrupt code is defined such that its two least significant bits are 0, thus allowing indexing into the table. the two possible ways of the code usage are shown on figure 6-23. msb 0 123456789101112131415 interrupt code reserved reset: 0011110000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved reset: 0000000000000000 figure 6-22. sivec?siu interrupt vector register 0x2f c01c 6-38 mpc565/mpc566 reference manual motorola system configuration and protection registers figure 6-23. example of sivec register usage for interrupt table handling 6.14.2.9 interrupt in-service registers sisr2, sisr3 are 32-bit read/write registers. each bit in the register corresponds to an interrupt request. a bit is set if: there is a pending interrupt request (sipend2/3), that is not masked by (simask2/3), and the bbc/impu acknowledges interrupt request and latches sivec value. once a bit is set, all requests with lower or equal priority become masked (i.e. they will not generate any interrupt request to the rcpu) until the bit is cleared. a bit is cleared by writing a ?1? to it. writing zero has no effect. intr: save state r3 <- @sivec r4<--baseofbranchtable lbzrx, r3 (0)# load as byte addrx,rx,r4 mtspr ctr, rx bctr intr: save state r3 <- @sivec r4<--baseofbranchtable lhzrx, r3 (0) # load as half addrx,rx,r4 mtspr ctr, rx bctr base b routine1 b routine2 b routine3 b routine4 base + n base + 4 base + 8 base + c base +10 base 1st instruction of routine1 1st instruction of routine2 1st instruction of routine3 1st instruction of routine4 base + n base + 400 base + 800 base + c00 base +1000 motorola chapter 6. system configuration and protection 6-39 system configuration and protection registers 6.14.3 system protection registers 6.14.3.1 system protection control register (sypcr) the system protection control register (sypcr) controls the system monitors, the software watchdog period, and the bus monitor timing. this register can be read at any time, but can be written only once after system reset. msb 0 123456789101112131415 irq0 lvl0 imb irq0 imb irq1 imb irq2 imb irq3 irq1 lvl1 imb irq4 imb irq5 imb irq6 imb irq7 irq2 lvl2 imb irq8 imb irq9 sreset: 0 000 0 0 0 0 000 00 000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 imb irq10 imb irq11 irq3 lvl4 imb irq12 imb irq13 imb irq14 imb irq15 irq4 lvl4 imb irq16 imb irq17 imb irq18 imb irq19 irq5 lvl5 sreset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 6-24. sisr2?interrupt in-service register 2 0x2f c050 msb 0 12 3456 7 8 9101112131415 imb irq20 imb irq21 imb irq22 imb irq23 irq6 lvl6 imb irq24 imb irq25 imb irq26 imb irq27 irq7 lvl7 imb irq28 imb irq29 imb irq30 imb irq31 sreset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved sreset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 6-25. sisr3?interrupt in-service register 3 0x2f c054 6-40 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14.3.2 software service register (swsr) the swsr is the location to which the swt servicing sequence is written. to prevent swt time-out, a 0x556c followed by 0xaa39 should be written to this register. the swsr can be written at any time but returns all zeros when read. msb 0 123456789101112131415 swtc reset: 1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 bmt bme reserved swf swe swri swp reset: 1111111100000111 figure 6-26. sypcr?system protection control register 0x2f c004 table 6-15. sypcr bit descriptions bit(s) name description 0:15 swtc software watchdog timer count. this field contains the count value of the software watchdog timer. 16:23 bmt bus monitor timing. this field specifies the time-out period, in eight-system-clock resolution, of the bus monitor. 24 bme bus monitor enable 0 disable bus monitor 1 enable bus monitor 25:27 ? reserved 28 swf software watchdog freeze 0 software watchdog continues to run while freeze is asserted 1 software watchdog stops while freeze is asserted 29 swe software watchdog enable. software should clear this bit after a system reset to disable the software watchdog timer. 0 watchdog is disabled 1 watchdog is enabled 30 swri software watchdog reset/interrupt select 0 software watchdog time-out causes a non-maskable interrupt to the rcpu 1 software watchdog time-out causes a system reset 31 swp software watchdog prescale 0 software watchdog timer is not prescaled 1 software watchdog timer is prescaled by 2048 motorola chapter 6. system configuration and protection 6-41 system configuration and protection registers 6.14.3.3 transfer error status register (tesr) the transfer error status register contains a bit for each exception source generated by a transfer error. a bit set to logic 1 indicates what type of transfer error exception occurred since the last time the bits were cleared by reset or by the normal software status bit-clearing mechanism. note these bits may be set due to canceled speculative accesses which do not cause an interrupt. the register has two identical sets of bit fields; one is associated with instruction transfers and the other with data transfers. msb 0 1234567891011121314lsb 15 swsr reset: 0000000000000000 figure 6-27. swsr?software service register 0x2f c00e table 6-16. swsr bit descriptions bit(s) name description 0:15 swsr swt servicing sequence is written to this register. to prevent swt time-out, a 0x556c followed by 0xaa39 should be written to this register. the swsr can be written at any time but returns all zeros when read. msb 0 123456789101112131415 reserved reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved iext ibmt reserved dext dbm reserved reset: 0000000000000000 figure 6-28. tesr?transfer error status register 0x2f c020 6-42 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14.4 system timer registers the following sections describe registers associated with the system timers. these facilities are powered by the kapwr and can preserve their value when the main power supply is off. refer to section 8.2.3, ?pre-divider,? for details on the required actions needed in order to guarantee this data retention. 6.14.4.1 decrementer register the 32-bit decrementer register is defined by the powerpc architecture. the values stored in this register are used by a down counter to cause decrementer exceptions. the decrementer causes an exception whenever bit zero changes from a logic zero to a logic one. a read of this register always returns the current count value from the down counter. contents of this register can be read or written to by the mfspr or the mtspr instruction. the decrementer register is reset by poreset .hreset and sreset do not affect this register. the decrementer is powered by standby power and can continue to count when standby power is applied. decrementer counts down the time base clock and the counting is enabled by tbe bit in tbcsr register section 6.14.4.4, ?time base control and status register.? table 6-17. tesr bit descriptions bit(s) name description 0:17 ? reserved 18 iext instruction external transfer error acknowledge. this bit is set if the cycle was terminated by an externally generated tea signal when an instruction fetch was initiated. 19 ibmt instruction transfer monitor time out. this bit is set if the cycle was terminated by a bus monitor time-out when an instruction fetch was initiated. 20:25 ? reserved 26 dext data external transfer error acknowledge. this bit is set if the cycle was terminated by an externally generated tea signal when a data load or store is requested by an internal master. 27 dbm data transfer monitor time out. this bit is set if the cycle was terminated by a bus monitor time-out when a data load or store is requested by an internal master. 28:31 ? reserved motorola chapter 6. system configuration and protection 6-43 system configuration and protection registers refer to section 3.9.5, ?decrementer register (dec)? for more information on this register. 6.14.4.2 time base sprs the tb is a 64-bit register containing a 64-bit integer that is incremented periodically. there is no automatic initialization of the tb; the system software must perform this initialization. the contents of the register may be written by the mttbl or the mttbu instructions, see section 3.9.4, ?time base facility (tb) ? oea.? refer to section 3.8, ?vea register set ? time base? and section 3.9.4, ?time base facility (tb) ? oea? for more information on reading and writing the tbu and tbl registers. 6.14.4.3 time base reference registers two reference registers (tbref0 and tbref1) are associated with the lower part of the time base (tbl). each is a 32-bit read/write register. upon a match between the contents of tbl and the reference register, a maskable interrupt is generated. msb 0 lsb 31 decrementing counter poreset 00000000000000000000000000000000 hreset/sreset: unchanged figure 6-29. dec?decrementer register spr 22 msb 0 31 32 lsb 63 tbu tbl reset: unchanged figure 6-30. tb?time base (reading) spr 268, 269 msb 0 31 32 lsb 63 tbu tbl reset: unchanged figure 6-31. tb?time base (writing) spr 284, 285 6-44 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14.4.4 time base control and status register the tbscr is 16-bit read/write register. it controls the tb, decrementer count enable, and interrupt generation and is used for reporting the source of the interrupts. the register can be read anytime. a status bit is cleared by writing a one to it. (writing a zero has no effect.) more than one bit can be cleared at a time. msb 0 lsb 31 tbref0 reset: figure 6-32. tbref0?time base reference register 0 0x2f c204 msb 0 lsb 31 tbref1 reset: figure 6-33. tbref1?time base reference register 1 0x2f c208 msb 0 123456789101112 1314lsb 15 tbirq refa refb reserved refae refbe tbf tbe poreset: 000000000000 0 0 00 figure 6-34. tbscr?time base control and status register 0x2f c200 table 6-18. tbscr bit descriptions bit(s) name description 0:7 tbirq time base interrupt request. these bits determine the interrupt priority level of the time base. refer to section 6.4, ?enhanced interrupt controller? for interrupt level encoding. 8 refa reference a (tbref0) interrupt status. 0 no match detected 1 tbref0 value matches value in tbl 9 refb reference b (tbref1) interrupt status. 0 no match detected 1 tbref1 value matches value in tbl 10:11 ? reserved 12 refae reference a (tbref0) interrupt enable. if this bit is set, the time base generates an interrupt when the refa bit is set. 13 refbe reference b (tbref1) interrupt enable. if this bit is set, the time base generates an interrupt when the refb bit is set. motorola chapter 6. system configuration and protection 6-45 system configuration and protection registers 6.14.4.5 real-time clock status and control register the rtcsc is used to enable the different rtc functions and to report the source of the interrupts. the register can be read anytime. a status bit is cleared by writing a one to it. (writing a zero does not affect a status bit?s value.) more than one status bit can be cleared at a time. this register is locked after reset. unlocking is accomplished by writing 0x55ccaa33 to its associated key register. see section 8.8.3.2, ?keep-alive power registers lock mechanism.? 14 tbf time base freeze. if this bit is set, the time base and decrementer stop while freeze is asserted. 15 tbe time base enable 0 time base and decrementer are disabled 1 time base and decrementer are enabled msb 0 1234567891011121314lsb 15 rtcirq sec alr rese rved 4m sie ale rtf rte reset: 00000000000?000? figure 6-35. rtcsc?real-time clock status and control register 0x2f c220 table 6-19. rtcsc bit descriptions bit(s) name description 0:7 rtcirq real-time clock interrupt request. thee bits determine the interrupt priority level of the rtc. refer to section 6.4, ?enhanced interrupt controller? for interrupt level encoding. 8 sec once per second interrupt. this status bit is set every second. it should be cleared by the software. 9 alr alarm interrupt. this status bit is set when the value of the rtc equals the value programmed in the alarm register. 10 ? reserved 11 4m real-time clock source 0 rtc assumes that it is driven by 20 mhz to generate the seconds pulse. 1 rtcassumesthatitisdrivenby4mhz 12 sie second interrupt enable. if this bit is set, the rtc generates an interrupt when the sec bit is set. 13 ale alarm interrupt enable. if this bit is set, the rtc generates an interrupt when the alr bit is set. 14 rtf real-time clock freeze. if this bit is set, the rtc stops while freeze is asserted. 15 rte real-time clock enable 0 rtc is disabled 1 rtc is enabled table 6-18. tbscr bit descriptions (continued) bit(s) name description 6-46 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14.4.6 real-time clock register (rtc) the real-time clock register is a 32-bit read write register. it contains the current value of the real-time clock. a write to the rtc resets the seconds timer to zero. this register is locked after reset. unlocking is accomplished by writing 0x55ccaa33 to its associated key register. see section 8.8.3.2, ?keep-alive power registers lock mechanism.? 6.14.4.7 real-time clock alarm register (rtcal) the rtcal is a 32-bit read/write register. when the value of the rtc is equal to the value programmed in the alarm register, a maskable interrupt is generated. the alarm interrupt will be generated as soon as there is a match between the alarm field and the corresponding bits in the rtc. the resolution of the alarm is 1 second. this register is locked after reset. unlocking is accomplished by writing 0x55ccaa33 to its associated key register. see section 8.8.3.2, ?keep-alive power registers lock mechanism.? 6.14.4.8 periodic interrupt status and control register (piscr) the piscr contains the interrupt request level and the interrupt status bit. it also contains the controls for the 16-bits to be loaded into a modulus counter. this register can be read or written at any time. msb 0 lsb 31 rtc reset: unchanged figure 6-36. rtc ?real-time clock register 0x2f c224 msb 0 lsb 31 alarm reset: unchanged figure 6-37. rtcal?real-time clock alarm register 0x2f c22c msb 0 1234567891011121314lsb 15 pirq ps reserved pie pitf pte hreset: 0000000000000000 figure 6-38. piscr?periodic interrupt status and control register 0x2f c240 motorola chapter 6. system configuration and protection 6-47 system configuration and protection registers 6.14.4.9 periodic interrupt timer count register (pitc) the pitc register contains the 16-bits to be loaded in a modulus counter. this register is readable and writable at any time. 6.14.4.10 periodic interrupt timer register (pitr) the periodic interrupt register is a read-only register that shows the current value in the periodic interrupt down counter. read or writing this register does not affect the register. table 6-20. piscr bit descriptions bit(s) name description 0:7 pirq periodic interrupt request. these bits determine the interrupt priority level of the pit. refer to section 6.4, ?enhanced interrupt controller? for interrupt level encoding. 8 ps periodic interrupt status. this bit is set if the pit issues an interrupt. the pit issues an interrupt after the modulus counter counts to zero. ps can be negated by writing a one to it. a write of zero has no affect. 9:12 ? reserved 13 pie periodic interrupt enable. if this bit is set, the time base generates an interrupt when the ps bit is set. 14 pitf pit freeze. if this bit is set, the pit stops while freeze is asserted. 15 pte periodic timer enable 0 pit stops counting and maintains current value 1 pit continues to decrement msb 0 123456789101112131415 pitc reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved reset: 0000000000000000 figure 6-39. pitc?periodic interrupt timer count 0x2f c244 table 6-21. pitc bit descriptions bit(s) name description 0:15 pitc periodic interrupt timing count. this field contains the 16-bit value to be loaded into the modulus counter that is loaded into the periodic timer. this register is readable and writable at any time. 16:31 ? reserved 6-48 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14.5 general-purpose i/o registers 6.14.5.1 sgpio data register 1 (sgpiodt1) msb 0 123456789101112131415 pit reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved reset: 0000000000000000 figure 6-40. pitr?periodic interrupt timer register 0x2f c248 table 6-22. pit bit descriptions bit(s) name description 0:15 pit periodic interrupt timing count?this field contains the current count remaining for the periodic timer. writes have no effect on this field. 16:31 ? reserved msb 0 123456789101112131415 sgpiod[0:7] sgpiod[8:15] reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 sgpiod[16:23] sgpiod[24:31] reset: 0000000000000000 figure 6-41. sgpiodt1?sgpio data register 1 0x2f c024 motorola chapter 6. system configuration and protection 6-49 system configuration and protection registers 6.14.5.2 sgpio data register 2 (sgpiodt2) table 6-23. sgpiodt1 bit descriptions bit(s) name description 0:7 sgpiod[0:7] siu general-purpose i/o group d[0:7]. this 8-bit register controls the data of general-purpose i/o pins sgpiod[0:7]. the direction (input or output) of this group of pins is controlled by the gddr0 bit in the sgpio control register. 8:15 sgpiod[8:15] siu general-purpose i/o group d[8:15]. this 8-bit register controls the data of general-purpose i/o pins sgpiod[8:15]. the direction (input or output) of this group of pins is controlled by the gddr1 bit in the sgpio control register. 16:23 sgpiod[16:23] siu general-purpose i/o group d[16:23]. this 8-bit register controls the data of the general-purpose i/o pins sgpiod[16:23]. the direction (input or output) of this group of pins is controlled by the gddr2 bit in the sgpio control register 24:31 sgpiod[24:31] siu general-purpose i/o group d[24:31]. this 8-bit register controls the data of the general-purpose i/o pins sgpiod[24:31]. the direction of sgpiod[24:31] is controlled by eight dedicated direction control signals sddrd[24:31]. each pin in this group can be configured separately as general-purpose input or output. msb 0 123456789101112131415 sgpioc[0:7] sgpioa[8:15] reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 sgpioa[16:23] sgpioa[24:31] reset: 0000000000000000 figure 6-42. sgpiodt2?sgpio data register 2 0x2f c028 table 6-24. sgpiodt2 bit descriptions bit(s) name description 0:7 sgpioc[0:7] siu general-purpose i/o group c[0:7]. this 8-bit register controls the data of the general-purpose i/o pins sgpioc[0:7]. the direction of sgpioc[0:7] is controlled by 8 dedicated direction control signals sddrc[0:7] in the sgpio control register. each pin in this group can be configured separately as general-purpose input or output. 8:15 sgpioa[8:15] siu general-purpose i/o group a[8:15]. this 8-bit register controls the data of the general-purpose i/o pins sgpioa[8:15]. the gddr3 bit in the sgpio control register configures these pins as a group as general-purpose input or output. 6-50 mpc565/mpc566 reference manual motorola system configuration and protection registers 6.14.5.3 sgpio control register (sgpiocr) table 6-26 describes the bit values for data direction control. 16:23 sgpioa [16:23] siu general-purpose i/o group a[16:23]. this 8-bit register controls the data of the general-purpose i/o pins sgpioa[16:23]. the gddr4 bit in the sgpio control register configures these pins as a group as general-purpose input or output. 24:31 sgpioa [24:31] siu general-purpose i/o group a[24:31]. this 8-bit register controls the data of the general-purpose i/o pins sgpioa[24:31]. the gddr5 bit in the sgpio control register configures these pins as a group as general-purpose input or output. msb 0 123456789101112131415 sddrc[0:7] reserved reset: 0 0 0 0 0 0 0 0 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 gddr0 gddr1 gddr2 gddr3 gddr4 gddr5 reserved sddrd[24:31] reset: 0 0 0 0 0 0 0 0 00000000 figure 6-43. sgpiocr?sgpio control register 0x2f c02c table 6-25. sgpiocr bit descriptions bit(s) name description 0:7 sddrc[0:7] sgpio data direction for sgpioc[0:7]. each sddr bit zero to seven controls the direction of the corresponding sgpioc pin zero to seven 8:15 ? reserved 16 gddr0 group data direction for sgpiod[0:7] 17 gddr1 group data direction for sgpiod[8:15] 18 gddr2 group data direction for sgpiod[16:23] 19 gddr3 group data direction for sgpioa[8:15] 20 gddr4 group data direction for sgpioa[16:23] 21 gddr5 group data direction for sgpioa[24:31] 22:23 ? reserved 24:31 sddrd [24:31] sgpio data direction for sgpiod[24:31]. each sddrd bit 24:31 controls the direction of the corresponding sgpiod pin [24:31]. table 6-24. sgpiodt2 bit descriptions (continued) bit(s) name description motorola chapter 6. system configuration and protection 6-51 system configuration and protection registers table 6-26. data direction control sddr/gddr operation 0 sgpio configured as input 1 sgpio configured as output 6-52 mpc565/mpc566 reference manual motorola system configuration and protection registers motorola chapter 7. reset 7-1 chapter 7 reset this section describes the mpc565/mpc566 reset sources, operation, control, and status. 7.1 reset operation the mpc565/mpc566 has several inputs to the reset logic which include the following: power-on reset external hard reset pin (hreset ) external soft reset pin (sreset ) lossofplllock on-chip clock switch software watchdog reset checkstop reset debug port hard reset debug port soft reset jtag reset all of these reset sources are fed into the reset controller. the control logic determines the cause of the reset, synchronizes it, and resets the appropriate logic modules, depending on the source of the reset. the memory controller, system protection logic, interrupt controller, and parallel i/o pins are initialized only on hard reset. external soft reset initializes internal logic while maintaining system configuration. the reset status register (rsr) reflects the most recent source to cause a reset. 7.1.1 power-on reset the power-on reset pin, poreset , is an active low input. in a system with power-down low-power mode, this pin should be activated only as a result of a voltage failure in the kapwr pin. after detecting the assertion of poreset , the mpc565/mpc566 enters the power-on reset state. during this state the modck[1:3] signals determine the oscillator 7-2 mpc565/mpc566 reference manual motorola reset operation frequency, pll multiplication factor, and the pitrtclk and tmbclk clock sources. in addition, the mpc565/mpc566 asserts the sreset and hreset pins. the poreset pin should be asserted for a minimum time of 100,000 cycles of clock oscillator after a valid level has been reached on the kapwr supply. after detecting the assertion of poreset , the mpc565/mpc566 remains in the power-on reset state until the last of the following two events occurs: the internal pll enters the lock state and the system clock is active. the poreset pin is negated. if the mpc565/mpc566 is in single-chip mode and limp mode is enabled, the internal pll is not required to be locked before the chip exits power-on reset. after exiting the power-on reset state, the mcu continues to drive the hreset and sreset pins for 512 system clock cycles. when the timer expires (after 512 cycles), the configuration is sampled from data bus pins, if required (see section 7.5.1, ?hard reset configuration?) and the mcu stops driving the hreset and sreset pins. in addition, the internal modck[1:3] values are sampled at the rising edge of poreset. the poreset pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. the internal poreset signal asserts only if the poreset pin asserts for more than 100 ns. 7.1.2 hard reset hreset (hard reset) is an active low, bidirectional i/o pin. the mpc565/mpc566 can detect an external assertion of hreset only if it occurs while the mcu is not asserting hreset . when the mpc565/mpc566 detects assertion of the external hreset pin or a cause to assert the internal hreset line, is detected the chip starts to drive the hreset and sreset for 512 cycles. when the timer expires (after 512 cycles) the configuration is sampled from data pins (refer to section 7.5.1, ?hard reset configuration?) and the chip stops driving the hreset and sreset pins. an external pull-up resistor should drive the hreset and sreset pins high. after detecting the negation of hreset or sreset ,the mcu waits 16 clock cycles before testing the presence of an external hard or soft reset. the hreset pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. the internal hreset will be asserted only if hreset is asserted for more than 100 ns. the hreset is an open collector type pin. motorola chapter 7. reset 7-3 reset operation 7.1.3 soft reset sreset (soft reset) is an active low, bidirectional i/o pin. the mpc565/mpc566 can only detect an external assertion of sreset if it occurs while the mpc565/mpc566 is not asserting sreset . when the mpc565/mpc566 detects the assertion of external sreset or a cause to assert the internal sreset line, the chip starts to drive the sreset for 512 cycles. when the timer expires (after 512 cycles) the debug port configuration is sampled from the dsdi and dsck pins and the chip stops driving the sreset pin. an external pull-up resistor should drive the sreset pin high. after the mpc565/mpc566 detects the negation of sreset , it waits 16 clock cycles before testing the presence of an external soft reset. 7.1.4 loss of pll lock if the pll detects a loss of lock, erroneous external bus operation will occur if synchronous external devices use the mpc565/mpc566 input clock. erroneous operation could also occur if devices with a pll use the mpc565/mpc566 clkout signal. this source of reset can be optionally asserted if the lolre bit in the pll, low-power, and reset control register (plprcr) is set. the enabled pll loss of lock event generates an internal hard reset sequence. refer to chapter 8, ?clocks and power control,? for more information on loss of pll lock. 7.1.5 on-chip clock switch if the system clock is switched to the backup clock or switched from backup clock to another clock source an internal hard reset sequence is generated. refer to chapter 8, ?clocks and power control.? 7.1.6 software watchdog reset when the mpc565/mpc566 software watchdog counts to zero, a software watchdog reset is asserted. the enabled software watchdog event generates an internal hard reset sequence. 7.1.7 checkstop reset when the rcpu enters a checkstop state, and the checkstop reset is enabled (the csr bit in the plprcr is set), a checkstop reset is asserted. the enabled checkstop event generates an internal hard reset sequence. refer to the rcpu reference manual for more information. 7-4 mpc565/mpc566 reference manual motorola reset actions summary 7.1.8 debug port hard reset when the development port receives a hard reset request from the development tool, an internal hard reset sequence is generated, see chapter 8, ?clocks and power control.? in this case the development tool must reconfigure the debug port. refer to chapter 22, ?development support,? for more information. 7.1.9 debug port soft reset when the development port receives a soft reset request from the development tool, an internal soft reset sequence is generated, see chapter 8, ?clocks and power control.? in this case the development tool must reconfigure the debug port. refer to chapter 22, ?development support,? for more information. 7.1.10 jtag reset when the jtag logic asserts the jtag soft reset signal, an internal soft reset sequence is generated, see chapter 8, ?clocks and power control.? refer to chapter 24, ?ieee 1149.1-compliant interface (jtag),? for more information. 7.2 reset actions summary table 7-1 summarizes the action taken for each reset. table 7-1. reset action taken for each reset cause reset source reset logic and pll states reset system configuration reset clock module reset hreset pin driven debug port configuration other internal logic reset sreset pin driven power-on reset yes yes yes yes yes yes yes hard reset sources external hard reset loss of lock on-chip clock switch illegal low-power mode software watchdog checkstop debug port hard reset no yes yes yes yes yes yes soft reset sources external soft reset debug port soft reset jtag reset no no no no yes yes yes motorola chapter 7. reset 7-5 data coherency during reset 7.3 data coherency during reset the mpc565/mpc566 supports data coherency and avoids data corruption while in reset. if a cycle is to be executed when detecting any sreset or hreset source, then the cycle will either complete or will not start before generating the corresponding reset control signal. there are reset sources, however, when the mpc565/mpc566 generates an internal reset due to special internal situation where this protection is not supported. see section 7.4, ?reset status register.? in the case of large operand size (32 or 16 bits) transaction to a smaller port size, the cycle is split into two 16-bit or four 8-bit cycles. in this case, data coherency is assured and data will not be corrupted. in the case where the core executes an unaligned load/store cycle which is broken down into multiple cycles, data coherency is not assured between these cycles (i.e., data could be corrupted). a contention on the data pins may occur while asserting external reset (ext_reset )if the data coherency mechanism is required, and thus enables a cycle to complete, while external hardware drives the data for the configuration word. see table 7-2 for a description of the required ext_reset line source in a system. 7.4 reset status register all of the reset sources are fed into the reset controller. the 16-bit reset status register (rsr) reflects the most recent source, or sources, of reset. (simultaneous reset requests can cause more than one bit to be set at the same time.) this register contains one bit for each reset source. a bit set to logic one indicates the type of reset that occurred. once set, individual bits in the rsr remain set until software clears them. bits in the rsr can be cleared by writing a one to the bit. a write of zero has no effect on the bit. the register can be read at all times. the reset status register receives its default reset values during power-on reset. the rsr is powered by the kapwr pin. table 7-2. reset configuration word and data corruption/coherency reset driven reset to use for data coherency (ext_reset ) comments hreset sreset sreset hreset hreset & sreset hreset || sreset provided only one of them is driven into the mpc565/mpc566 at a time 7-6 mpc565/mpc566 reference manual motorola reset status register msb lsb 0123456789101112131415 ehrs esrs llrs swr s csrs dbh rs dbsr s jtrs occ s ilbc gpo r ghr st gsr st reserved reset: 0000000000111000 figure 7-1. rsr ? reset status register0x2f c288 table 7-3. reset status register bit descriptions bit(s) name description 0ehrs 1 external hard reset status 0 no external hard reset has occurred 1 an external hard reset has occurred 1 esrs 1 external soft reset status 0 no external soft reset has occurred 1 an external soft reset has occurred 2 llrs loss of lock reset status 0 no enabled loss-of-lock reset has occurred 1 an enabled loss-of-lock reset has occurred 3 swrs software watchdog reset status 0 no software watchdog reset has occurred 1 a software watchdog reset has occurred 4 csrs checkstop reset status 0 no enabled checkstop reset has occurred 1 an enabled checkstop reset has occurred 5 dbhrs debug port hard reset status 0 no debug port hard reset request has occurred 1 a debug port hard reset request has occurred 6 dbsrs debug port soft reset status 0 no debug port soft reset request has occurred 1 a debug port soft reset request has occurred 7 jtrs jtag reset status 0 no jtag reset has occurred 1 a jtag reset has occurred 8 occs on-chip clock switch 0 no on-chip clock switch reset has occurred 1 an on-chip clock switch reset has occurred 9 ilbc illegal bit change. this bit is set when the mpc565/mpc566 changes any of the following bits when they are locked: lpm[0:1], locked by the lpml bit mf[0:11], locked by the mfpdl bit divf[0:4], locked by the mfpdl bit 10 gpor glitch detected on poreset pin. this bit is set when the poreset pin is asserted for more than 20ns 0 no glitch was detected on the poreset pin 1 a glitch was detected on the poreset pin motorola chapter 7. reset 7-7 reset configuration 7.5 reset configuration 7.5.1 hard reset configuration when a hard reset event occurs, the mpc565/mpc566 reconfigures its hardware system as well as the development port configuration. the logical value of the bits that determine its initial mode of operation, are sampled from the following: the external data bus pins data[0:31] an internal default constant (0x0000 0000) an internal nvm register value (uc3fcfig) if at the sampling time rstconf is asserted, then the configuration is sampled from the data bus. if rstconf is negated and a valid nvm value exists (uc3fcfig bit hc =0), then the configuration is sampled from the nvm register in the uc3f module. if rstconf is negated and no valid nvm value exists (uc3fcfig bit hc =1), then the configuration word is sampled from the internal default. hc will be ?1? if the internal flash is erased. table 7-4 summarizes the reset configuration options. if the prds control bit in the pdmcr register is set and hreset and rstconf are asserted, the mpc565/mpc566 pulls the data bus low with a weak resistor. the user can 11 ghrst glitch detected on hreset pin. this bit is set when the hreset pin is asserted for more than 20ns 0 no glitch was detected on the hreset pin 1 a glitch was detected on the hreset pin 12 gsrst glitch detected on sreset pin. if the sreset pin is asserted for more than 20ns the ghrst bit will be set. if an internal or external sreset is generated the sreset pinisassertedand the gsrst bit will be set. the gsrst bit remains set until software clears it. the gsrst bit can be negated by writing a one to gsrst. a write of zero has no effect on this bit. 0 no glitch was detected on sreset pin 1 a glitch was detected on sreset pin . 13:15 ? reserved 1 in the usiu rsr, if both ehrs and esrs are set, the reset source is internal. the ehrs and esrs bits in rsr register are set for any internal reset source in addition to external hreset and external sreset events. if both internal and external indicator bits are set, then the reset source is internal. table 7-4. reset configuration options rstconf has configuration (hc) internal configuration word 0 x data[0:31] pins 1 0 nvm flash eeprom register (uc3fcfig) 1 1 internal data word default (0x0000 0000) table 7-3. reset status register bit descriptions (continued) bit(s) name description 7-8 mpc565/mpc566 reference manual motorola reset configuration overwrite this default by driving the appropriate bit high. see figure 7-2 for the basic reset configuration scheme. figure 7-2. reset configuration basic scheme during the assertion of the poreset input signal, the chip assumes the default reset configuration. this assumed configuration changes if the input signal rstconf is asserted when the poreset is negated or the clkout starts to oscillate. to ensure that stable data is sampled, the hardware configuration is sampled every eight clock cycles on the rising edge of clkout with a double buffer. the setup time required for the data bus is approximately 15 cycles (defined as tsup in the following figures) and the maximum rise time of hreset should be less than six clock cycles. in systems where an external reset configuration word and the texp output function are both required, rstconf should be asserted until sreset is negated. figure 7-3 to figure 7-6 provide sample reset configuration timings. int_reset d x (data line) mux flash 32 32 32 data coherency has configuration hc oe ext_reset (see table 7-2) hreset /sreset rstconf config. word mpc565/mpc566 motorola chapter 7. reset 7-9 reset configuration note timing diagrams in the following figures are not to scale. figure 7-3. reset configuration sampling scheme for ?short? poreset assertion, limp mode disabled clkout poreset hreset rstconf internal poreset default rstconf controlled ts u p internal data[0:31] >10,000 clocks 7-10 mpc565/mpc566 reference manual motorola reset configuration figure 7-4. reset configuration timing for ?short? poreset assertion, limp mode enabled figure 7-5. reset configuration timing for ?long? poreset assertion, limp mode disabled clkout poreset hreset rstconf internal poreset default rstconf controlled tsu p internal data(0:31) (backup clock) clkout poreset hreset rstconf internal poreset default rstconf controlled ts u p internal data[0:31] pll lock motorola chapter 7. reset 7-11 reset configuration figure 7-6. reset configuration sampling timing requirements clkout hreset rstconf data 12345678910111213141516 maximum time of reset recognition reset configuration word tsup = minimum setup time of reset recognition = 15 clocks sample data configuration sample data configuration (maximum rise time - up to 6 clocks) internal reset 7-12 mpc565/mpc566 reference manual motorola reset configuration 7.5.2 hard reset configuration word following is the hard reset configuration word that is sampled from the internal data bus, data_sgpiod(0:31) on the negation of hreset . if the external reset config word is selected (rstconf = 0), the internal data bus will reflect the state of external data bus. if the internal reset config word is selected and neither of the flash reset config words are enabled (hc = 1), the internal data bus is internally driven with all zeros. the reset configuration word is not a register in the memory map. most of the bits in the configuration are located in registers in the siu. refer to table 7-5 for a detailed description of each control bit. 1. reserved on mask set k13y (rev. a) and later. this was dbpc on mask set k85h. 2. available only on the mpc566. msb 01234 5 6 789101112131415 earb ip bdrv bdis bps[0:1] reserved dbgc[0:1] reser ved 1 atw c ebdf[0:1] reser ved reset 00000 0 0 000000000 lsb 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prp m sc etre flen en_ comp 2 exc_ comp 2 rese rved oerc reserved isb dme reset 00000 0 0 000000000 figure 7-7. rcw? reset configuration word table 7-5. rcw bit descriptions bit(s) name description 0 earb external arbitration ? refer to section 9.5.7, ?arbitration phase,? for a detailed description of bus arbitration. the default value is that internal arbitration hardware is used. 0 internal arbitration is performed 1 external arbitration is assumed 1 ip initial interrupt prefix ? this bit defines the initial value of the msr ip immediately after reset. the msr ip bit defines the interrupt table location. if ip is zero then the msr ip initial value is zero, if the ip is one, then the msr ip initial value is one. default value is zero. see table 3-12 for more information. 0 msr[ip] = 0 after reset 1 msr[ip] = 1 after reset 2 bdrv bus pins drive strength ? this bit determines the bus pins (address, data and control) driving capability to be either full or reduced drive. the bus default drive strength is full; upon default, it also effects the clkout drive strength to be full. see table 6-7 for more information. bdrv controls the default state of com[1] in the siumcr. 0fulldrive 1 reduced drive motorola chapter 7. reset 7-13 reset configuration 3 bdis boot disable ? if the bdis bit is set, then memory controller is not activated after reset. if it is cleared then the memory controller bank 0 is active immediately after reset such that it matches any addresses. if a write to the or0 register occurs after reset this bit definition is ignored. the default value is that the memory controller is enabled to control the boot with the cs[ 0] pin. see section 10.7, ?global (boot) chip-select operation,? for more information. 0 memory controller bank 0 is active and matches all addresses immediately after reset 1 memory controller is not activated after reset. 4:5 bps boot port size ? this field defines the port size of the boot device on reset (br0[ps]). if a write to the or0 register occurs after reset this field definition is ignored. see table 10-5 and table 10-8 for more information. 00 32-bit port (default) 01 8-bit port 10 16-bit port 11 reserved 6:8 ? reserved. these bits must not be high in the reset configuration word. 9:10 dbgc[0:1] debug pins configuration ? see section 6.14.1.1, ?siu module configuration register (siumcr),? for this field definition. the default value is that these pins function as: vfls[0:1], bi , br ,bg and bb .seetable6-8. 11 ? reserved. 1 12 atwc address type write enable configuration ? the default value is that these pins function as we pins. 0we [0:3]/be [0:3]/at[0:3] functions as we [0:3]/be [0:3] 1we [0:3]/be [0:3]/at[0:3] functions as at[0:3] see table 6-7. 13:14 ebdf external bus division factor ? this field defines the initial value of the external bus frequency. the default value is that clkout frequency is equal to that of the internal clock (no division). see ta bl e 8 - 9 . 15 ? reserved. this bit must be 0 in the reset configuration word. 16 prpm peripheral mode enable ? this bit determines if the chip is in peripheral mode. a detailed description is in table 6-13 the default value is no peripheral mode enabled. 17:18 sc single chip select ? this field defines the mode of the mpc565/mpc566. 00 extended chip, 32 bits data 01 extended chip, 16 bits data 10 single chip and show cycles (address) 11 single chip see table 6-10. 19 etre exception table relocation enable ? this field defines whether the exception table relocation feature in the bbc is enabled or disabled; the default state for this field is disabled. for more details, see table 4-4. 20 flen flash enable ? this field determines whether the on-chip flash memory is enabled or disabled out of reset. the default state is disabled, which means that by default, the boot is from external memory. refer to table 6-12 for more details. 0 flash disabled ? boot is from external memory 1 flash enabled 21 en_ comp 2 enable compression ? this bit enables the operation of the mpc565/mpc566 with compressed code. the default state is disabled. see table 4-4. table 7-5. rcw bit descriptions (continued) bit(s) name description 7-14 mpc565/mpc566 reference manual motorola reset configuration 7.5.3 soft reset configuration when a soft reset event occurs, the mpc565/mpc566 reconfigures the development port. refer to chapter 22, ?development support,? for details. 22 exc_ comp 2 exception compression ? this bit determines the operation of the mpc565/mpc566 with exceptions. if this bit is set, than the mpc565/mpc566 assumes that all the exception routines are in compressed code. the default indicates the exceptions are all non-compressed. see ta bl e 4 - 4 . 23 ? reserved. this bit must not be high in the reset configuration word. 24:25 oerc other exceptions relocation control ? these bits effect only if etre was enabled. relocation offset: 00 offset 0 01 offset 64 kb 10 offset 512 kb 11 offset to 0x003 fe000 (sram start address) see table 4-2. 26:27 ? reserved 28:30 isb internal space base select ? this field defines the initial value of the isb field in the immr register. a detailed description is in table 6-12. the default state is that the internal memory map is mapped to start at address 0x0000_0000 hex. this bit must not be high in the reset configuration word. 31 dme dual mapping enable ? this bit determines whether dual mapping of the internal flash is enabled. for a detailed description refer to table 10-11. the default state is that dual mapping is disabled. 0 dual mapping disabled 1 dual mapping enabled 1 this bit was dbpc on mask set k85h. it is reserved on all later mask sets. see table 6-7. 2 available only on the mpc566. table 7-5. rcw bit descriptions (continued) bit(s) name description motorola chapter 8. clocks and power control 8-1 chapter 8 clocks and power control the main timing reference for the mpc565/mpc566 can monitor any of the following: an external crystal with a frequency of 4 or 20 mhz an external frequency source with a frequency of 4 mhz an external frequency source at the system frequency the system operating frequency is generated through a programmable phase-locked loop, the system pll (spll). the spll runs at twice the system speed. the spll is programmable in integer multiples of the input frequency to generate the internal (vco/2) operating frequency. a pre-divider before the spll enables the division of the high frequency crystal oscillator. the internal operating spll frequency should be at least 30 mhz. it can be divided by a power-of-two divider to generate the system operating frequencies. in addition to the system clock, the clocks submodule provides the following: tmbclk to the time base (tb) and decrementer (dec) pitrtclk to the periodic interrupt timer (pit) and ppc real-time clock (rtc) note the ppc rtc is separate from the mios14 real-time clock sub-module. see section 17.14, ?real-time clock submodule (mrtcsm)?. the oscillator, tb, dec, rtc, and the pit are powered from the keep alive power supply (kapwr) pin. this allows the counters to continue to count (increment/decrement) at the oscillator frequency even when the main power to the mcu is off. while the power is off, the pit may be used to signal the power supply ic to enable power to the system at specific intervals. this is the power-down wake-up feature. when the chip is not in power-down low-power mode, the kapwr is powered to the same voltage value as the voltage of the i/o buffers and logic. the mpc565/mpc566 clock module consists of the main crystal oscillator, the spll, the low-power divider, the clock generator, the system low-power control block, and the limp mode control block. the clock module receives control bits from the system clock control 8-2 mpc565/mpc566 reference manual motorola register (sccr), change of lock interrupt register (colir), the pll low-power and reset-control register (plprcr), and the pll. figure 8-1 is a functional block diagram of the clock unit. figure 8-1. clock unit block diagram 2:1 spll clock gclk1 / gclk2 gclk1c / gclk2c vcoout clkout 3:1 mux system low-power control xfc tmbclk tmbclk lock vddsyn drivers driver main clock xtal extal 3:1 mux rtc / pit clock and driver oscillator mux tbclk (/4 or /16) modck[1:3] pitrtclk extclk 2:1 mux low power dividers (1/2n) /4 or /256 gclk2 back_up clock detector oscillator loss engclk vsssyn drivers system clock system clock to rcpu and bbc motorola chapter 8. clocks and power control 8-3 system clock sources 8.1 system clock sources the system clock can be provided by the main system oscillator, an external clock input, or the backup clock (buclk) on-chip ring oscillator, see. the main system oscillator uses either a 4-mhz or 20-mhz crystal to generate the pll reference clock. when the main system oscillator output is the timing reference to the system pll, skew elimination between the xtal/extal pins and clkout is not guaranteed. there is also an on-chip crystal feedback resistor on the mpc565/mpc566; however, space should be reserved for an off-chip resistor to allow for future configurations. figure 8-2 illustrates the main system oscillator crystal configuration. the external clock input (extclk pin) can receive a clock signal from an external source. the clock frequency must be in the range of 3-5 mhz or, for 1:1 mode, at the system frequency of at least 15 mhz. when the external clock input is the timing reference to the system pll, the skew between the extclk pin and the clkout is less than 1ns. the backup clock on-chip ring oscillator allows the mpc565/mpc566 to function with a less precise clock. when operating from the backup clock, the mpc565/mpc566 is in limp mode. this enables the system to continue minimum functionality until the system is fixed. the buclk frequency is approximately 11 mhz for the mpc565/mpc566 (see appendix e, ?electrical characteristics? for the complete frequency range). for normal operation, at least one clock source (extclk or main system oscillator) must be active. a configuration with both clock sources active is possible as well. at this configuration extclk provides the system clock and main system oscillator provides the pitrtclk. the input of an unused timing reference (extclk or extal) must be grounded. figure 8-2. main system oscillator crystal configuration 8.2 system pll the pll allows the processor to operate at a high internal clock frequency using a low frequency clock input, a feature which offers two benefits. lower frequency clock input reduces the overall electromagnetic interference generated by the system, and the ability to oscillate at different frequencies reduces cost by eliminating the need to add an additional oscillator to a system. extal xtal cl cl 1mw 1 1. resistor is not currently required on the board but space should be available for its addition in the future. 8-4 mpc565/mpc566 reference manual motorola system pll the pll can perform the following functions: frequency multiplication skew elimination frequency division 8.2.1 frequency multiplication the pll can multiply the input frequency by any integer between one and 4096. the multiplication factor depends on the value of the mf[0:11] bits in the plprcr register. while any integer value from one to 4096 can be programmed, the resulting vco output frequency must be at least 15 mhz. the multiplication factor is set to a predetermined value during power-on reset as defined in table 8-1. 8.2.2 skew elimination the pll is capable of eliminating the skew between the external clock entering the chip (extclk) and both the internal clock phases and the clkout pin, making it useful for tight synchronous timings. skew elimination is active only when the pll is enabled and programmed with a multiplication factor of one or two (mf = 0 or 1). the timing reference to the system pll is the external clock input (extclk pin). 8.2.3 pre-divider a pre-divider before the phase comparator enables additional system clock resolution when the crystal oscillator frequency is 20 mhz. the division factor is determined by the divf[0:4] bits in the plprcr. 8.2.4 pll block diagram as shown in figure 8-3, the reference signal, oscclk, goes to the phase comparator. the phase comparator controls the direction (up or down) that the charge pump drives the voltage across the external filter capacitor (xfc). the direction depends on whether the feedback signal phase lags or leads the reference signal. the output of the charge pump drives the vco. the output frequency of the vco is divided down and fed back to the phase comparator for comparison with the reference signal, oscclk. the mf values, zero to 4095, are mapped to multiplication factors of one to 4096. note that when the pll is operating in 1:1 mode (refer to table 8-1), the multiplication factor is one (mf = 0). the pll output frequency is twice the maximum system frequency. this double frequency is needed to generate gclk1 and gclk2 clocks. on power-up, with a 4-mhz or 20-mhz crystal and the default mf settings, vcoout will be 40 mhz and the system clock will be 20 mhz. the equation for vcoout is shown below: motorola chapter 8. clocks and power control 8-5 system pll note when operating with the backup clock, the system clock (and clkout) is one-half of the ring oscillator frequency, (i.e., the system clock is approximately 7 mhz). the time base and pit clocks will be twice the system clock frequency. the pll maximum lock time is determined by the input clock to the phase detector. the pll locks within 500 input clock cycles. note upon initial system power up and after kapwr is lost, an external circuit must assert power on reset (poreset ). if limp mode will be enabled during power-on reset, poreset must be asserted for at least 100,000 cycles of input pll clock after a valid level has been reached on the kapwr supply. if limp mode will be disabled, poreset should be asserted for approximately 3 s after a valid level has been reached on the kapwr supply. whenever power-on reset is asserted, the mf bits are set according to table 8-1, and the division factor high frequency (dfnh) and division factor low frequency (dfnl) bits in sccr are set to the value of 0 ( 1 for dfnh and 2 for dfnl). figure 8-3. system pll block diagram vcoout = oscclk divf + 1 x(mf+1)x2 vddsyn / vsssyn phase comparator multiplication factor mf[0:11] xfc oscclk up down vcoout feedback clock delay charge pump vco division factor divf[0:4] 8-6 mpc565/mpc566 reference manual motorola system clock during pll loss of lock 8.2.5 pll pins the following pins are dedicated to the pll operation: vddsyn ? drain voltage. this is the v dd dedicated to the analog pll circuits. the voltage should be well-regulated and the pin should be provided with an extremely low impedance path to the v dd power rail. vddsyn should be bypassed to vsssyn by a 0.1 f capacitor located as close as possible to the chip package. vsssyn ? source voltage. this is the v ss dedicated to the analog pll circuits. the pin should be provided with an extremely low impedance path to ground. vsssyn should be bypassed to vddsyn by a 0.1 f capacitor located as close as possible to the chip package. xfc ? external filter capacitor. xfc connects to the off-chip capacitor for the pll filter. one terminal of the capacitor is connected to xfc, and the other terminal is connected to vddsyn. ? the off-chip capacitor must have the following values (preliminary): ? 0 < mf + 1 < 4(1130 x (mf + 1) ? 80) pf ?mf+1 42100 x (mf + 1) pf note: where mf = the value stored on mf[0:11]. this is one less than the desired frequency multiplication. 8.3 system clock during pll loss of lock at reset, until the spll is locked, the spll output clock is disabled. during normal operation (once the pll has locked), either the oscillator or an external clock source is generating the system clock. in this case, if loss of lock is detected and the lolre (loss of lock reset enable) bit in the plprcr is cleared, the system clock source continues to function as the pll?s output clock. the usiu timers can operate with the input clock to the pll, so that these timers are not affected by the pll loss of lock. software can use these timers to measure the loss-of-lock period. if the timer reaches the user-preset software criterion, the mpc565/mpc566 can switch to the backup clock by setting the switch to backup clock (stbuc) bit in the sccr, provided the limp mode enable (lme) bit in the sccr is set. if loss of lock is detected during normal operation, assertion of hreset (for example, if lolre is set) disables the pll output clock until the lock condition is met. during hard reset, the stbuc bit is set as long as the pll lock condition is not met and clears when the pll is locked. if stbuc and lme are both set, the system clock switches to the backup clock (buclk), and the chip operates in limp mode until stbuc is cleared. every change in the lock status of the pll can generate a maskable interrupt. motorola chapter 8. clocks and power control 8-7 low-power divider note when the vco is the system clock source, chip operation is unpredictable while the pll is unlocked. note further that a switch to the backup clock is possible only if the lme bit in the sccr is set. 8.4 low-power divider the output of the pll is sent to a low-power divider block. (in limp mode the buclk is sent to a low-power divider block.) this block generates all other clocks in normal operation, but has the ability to divide the output frequency of the vco before it generates the general system clocks sent to the rest of the mpc565/mpc566. the pll vcoout is always divided by at least two. the purpose of the low-power divider block is to allow reduction and restoration of the operating frequencies of different sections of the mpc565/mpc566 without losing the pll lock. using the low-power divider block, full chip operation can still be obtained, but at a lower frequency. this is called gear mode. the selection and speed of gear mode can be changed at any time, with changes occurring immediately. the low-power divider block is controlled in the system clock control register (sccr). the default state of the low-power divider is to divide all clocks by one. thus, for a 40-mhz system, the general system clocks are each 40 mhz. whenever power-on reset is asserted, the mf bits are set according to table 8-1, and the division factor high frequency (dfnh) and division factor low frequency (dfnl) bits in sccr are set to the value of 0 ( 1for dfnh and 2 for dfnl). 8.5 internal clock signals the internal clocks generated by the clocks module are shown in figure 8-4. the clocks module also generates the clkout and engclk external clock signals. the pll synchronizes these signals to each other. the pitrtclk frequency and source are specified by the rtdiv and rtsel bits in the sccr. when the backup clock is functioning as the system clock, the backup clock is automatically selected as the time base clock source and is twice the mpc565/mpc566 system clock. 8-8 mpc565/mpc566 reference manual motorola internal clock signals figure 8-4. mpc565/mpc566 clocks note that gclk1_50, gclk2_50, and clkout can have a lower frequency than gclk1 and gclk2. this is to enable the external bus operation at lower frequencies (controlled by ebdf in the sccr). gclk2_50 always rises simultaneously with gclk2. when dfnh = 0, gclk2_50 has a 50% duty cycle. with other values of dfnh or dfnl, the duty cycle is less than 50%. refer to figure 8-7. gclk1_50 rises simultaneously with gclk1. when the mpc565/mpc566 is not in gear mode, the falling edge of gclk1_50 occurs in the middle of the high phase of gclk2_50. ebdf determines the division factor between gclk1/gclk2 and gclk1_50/gclk2_50. during power-on reset, the mocck1, modck2, and modck3 pins determine the clock source for the pll and the clock drivers. these pins are latched on the positive edge of gclk1 gclk2 gclk1_50 gclk2_50 clkout t1 t2 t3 t4 gclk1_50 gclk2_50 (ebdf = 00) (ebdf = 00) (ebdf = 01) (ebdf = 01) clkout (ebdf = 00) (ebdf = 01) motorola chapter 8. clocks and power control 8-9 internal clock signals poreset . their values must be stable as long as this line is asserted. the configuration modes are shown in table 8-1. modck1 specifies the input source to the spll (main system oscillator or extclk). modck1, modck2, and modck3 together determine the multiplication factor at reset and the functionality of limp mode. if the configuration of pitrtclk and tmbclk and the spll multiplication factor is to remain unchanged in power-down low-power mode, the modck signals should not be sampled at wake-up from this mode. in this case the poreset pinshouldremainnegated and hreset should be asserted during the power supply wake-up stage. when modck1 is cleared, the output of the main oscillator is selected as the input to the spll. when modck1 is asserted, the external clock input (extclk pin) is selected as the input to the spll. in all cases, the system clock frequency (freq gclk2 ) can be reduced by the dfnh[0:2] bits in the sccr. note that freq gclk2(max) occurs when the dfnh bits are cleared. the tbs bit in the sccr selects the time base clock to be either the spll input clock or gclk2. when the backup clock is functioning as the system clock, the backup clock is automatically selected as the time base clock source. the pitrtclk frequency and source are specified by the rtdiv and rtsel bits in the sccr. when the backup clock is functioning as the system clock, the backup clock is automatically selected as the time base clock source. when the poreset pin is negated (driven to a high value), the modck1, modck2, and modck3 values are not affected. they remain the same as they were defined during the most recent power-on reset. table 8-1 shows the clock configuration modes during power-on reset (poreset asserted). note the modck[1:3] are shared functions with irq[5:7]. if irq[5:7] are used as interrupts, the interrupt source should be removed during poreset to insure the modck pins are in the correct state on the rising edge of poreset . table 8-1. reset clocks source configuration modck[1:3] 1 default values after poreset spll options lme rtsel mf + 1 pitclk di- vision tmbclk division 000 0 0 1 4 4 used for testing purposes. 001 0 0 1 256 16 normal operation, pll enabled. main timing reference is crystal osc (20 mhz). limp mode disabled. 8-10 mpc565/mpc566 reference manual motorola internal clock signals note the reset value of the pll pre-divider is one. the values of the pitrtclk clock division and tmbclk clock division can be changed by software. the rtdiv bit value in the sccr register defines the division of pitrtclk. all possible combinations of the tmbclk divisions are listed in table 8-2. 8.5.1 general system clocks the general system clocks (gclk1c, gclk2c, gclk1, gclk2, gclk1_50, and gclk2_50) are the basic clock supplied to all modules and sub-modules on the mpc565/mpc566. gclk1c and gclk2c are supplied to the rcpu and to the bbc. gclk1c and gclk2c are stopped when the chip enters the doze-low power mode. gclk1 and gclk2 are supplied to the siu and the clock module. the external bus clock 010 1 0 5 256 4 normal operation, pll enabled. main timing reference is crystal osc (4 mhz). limp mode enabled. 011 1 0 1 256 16 normal operation, pll enabled. main timing reference is crystal osc (20 mhz). limp mode enabled. 100 101 01 1 256 16 normal operation, pll enabled. 1:1 mode main timing reference is extclk pin (>15mhz) limp mode disabled. 110 0 1 5 256 4 normal operation, pll enabled. main timing reference is extclk (3-5 mhz). limp mode disabled. 111 1 1 1 256 16 normal operation, pll enabled. 1:1 mode main timing reference is extclk pin (>15mhz) limp mode enabled. 1 indicates modck pins value during power-on reset table 8-2. tmbclk divisions sccr[tbs] mf + 1 tmbclk division 1?16 01,216 0>24 table 8-1. reset clocks source configuration (continued) modck[1:3] 1 default values after poreset spll options lme rtsel mf + 1 pitclk di- vision tmbclk division motorola chapter 8. clocks and power control 8-11 internal clock signals gclk2_50 is the same as clkout. the general system clock defaults to vco/2 = 20 mhz (assuming a 20-mhz system frequency) with default power-on reset mf values. the general system clock frequency can be switched between different values. the highest operational frequency can be achieved when the system clock frequency is determined by dfnh (csrc bit in the plprcr is cleared) and dfnh = 0 (division by one). the general system clock can be operated at a low frequency (gear mode) or a high frequency. the dfnl bits in sccr define the low frequency. the dfnh bits in sccr define the high frequency. the frequency of the general system clock can be changed dynamically with the system clock control register (sccr), as shown in figure 8-5. figure 8-5. general system clocks select the frequency of the general system clock can be changed ?on the fly? by software. the user may simply cause the general system clock to switch to its low frequency. however, in some applications, there is a need for a high frequency during certain periods. interrupt routines, for example, may require more performance than the low frequency operation provides, but must consume less power than in maximum frequency operation. the mpc565/mpc566 provides a method to automatically switch between low and high frequency operation whenever one of the following conditions exists: there is a pending interrupt from the interrupt controller. this option is maskable by the prqen bit in the sccr. the (pow) bit in the msr is clear in normal operation. this option is maskable by the prqen bit in the sccr. when neither of these conditions exists and the csrc bit in plprcr is set, the general system clock switches automatically back to the low frequency. abrupt changes in the divide ratio can cause linear changes in the operating currents of the mpc565/mpc566. insure that the proper power supply filtering is available to handle this change instantaneously. when the general system clock is divided, its duty cycle is changed. one phase remains the same (for example, 12.5 ns @ 40 mhz) while the other becomes longer. dfnh divider dfnl divider vco/2 (e.g., 40 mhz) dfnh normal low power general system clock dfnl o o o o 8-12 mpc565/mpc566 reference manual motorola internal clock signals note clkout does not have a 50% duty cycle when the general system clock is divided. the clkout wave form is the same as that of gclk2_50. figure 8-6. divided system clocks timing diagram the system clocks gclk1 and gclk2 frequency is: therefore, the complete equation for determining the system clock frequency is: the clocks gclk1_50 and gclk2_50 frequency is: figure 8-7 shows the timing of usiu clocks when dfnh = 1 or dfnl = 0. gclk1 divide by 1 gclk2 divide by 1 gclk1 divide by 2 gclk2 divide by 2 gclk1 divide by 4 gclk2 divide by 4 freq sys freqsysmax 2 dfnh () or 2 dfnl 1 + () ------------------------------------------------------ = where freqsysmax = vcoout/2 system frequency= oscclk divf + 1 x (mf + 1) (2 dfnh or 2 dfnl + 1 ) 2 2 x freq 50 freqsysmax 2 dfnh () or 2 dfnl 1 + () ------------------------------------------------------ 1 ebdf 1 + ------------------------- = motorola chapter 8. clocks and power control 8-13 internal clock signals figure 8-7. clocks timing for dfnh = 1 (or dfnl = 0) 8.5.2 clock out (clkout) clkout has the same frequency as the general system clock (gclk2_50). unlike the main system clock gclk1/gclk2 however, clkout (and gclk2_50) represents the external bus clock, and thus will be one-half of the main system clock if the external bus is running at half speed (ebdf = 0b01). the clkout frequency defaults to vco/2. clkout can drive full, half, or quarter strength; it can also be disabled. the drive strength is controlled in the system clock and reset-control register (sccr) by the com[0:1] and cqds bits. (see section 8.11.1, ?system clock control register (sccr)?). disabling or decreasing the strength of clkout can reduce power consumption, noise, and electromagnetic interference on the printed circuit board. when the pll is acquiring lock, the clkout signal is disabled and remains in the low state (provided that bucs = 0). 8.5.3 engineering clock (engclk) engclk is an output clock with a 50% duty cycle. its frequency defaults to vco/128, which is 1/64 of the main system frequency. engclk frequency can be programmed to the main system frequency divided by a factor from one to 64, as controlled by the engdiv[0:5] bits in the sccr. engclk can drive full- or half-strength, or it can also be disabled (remaining in the high state). the drive strength is controlled by the eeclk[0:1] gclk1 gclk2 gclk1_50 gclk2_50 clkout gclk1_50 gclk2_50 (ebdf = 00) (ebdf = 00) (ebdf = 01) (ebdf = 01) clkout (ebdf = 00) (ebdf = 01) 8-14 mpc565/mpc566 reference manual motorola clock source switching bits in the sccr. disabling engclk can reduce power consumption, noise, and electromagnetic interference on the printed circuit board. note the full strength engclk setting selects a 5-v driver, while the half strength selection is a 2.6-v driver. when the pll is acquiring lock, the engclk signal is disabled and remains in the low state (provided that bucs = 0). note skew elimination between clkout and engclk is not guaranteed. 8.6 clock source switching for limp mode support, clock source switching is supported. if for any reason the clock source for the chip is not functioning, the option is to switch the system clock to the backup clock ring oscillator, buclk. this circuit consists of a loss-of-clock detector, which sets the locs status bit and locss sticky bit in the plprcr. if the lme bit in the sccr is set, whenever locs is asserted, the clock logic switches the system clock automatically to buclk and asserts hard reset to the chip. switching the system clock to buclk is also possible by software setting the stbuc bit in sccr. switching from limp mode to normal system operation is accomplished by clearing stbuc and locss bits. this operation also asserts hard reset to the chip. at hreset assertion, if the pll output clock is not valid, the buclk will be selected until software clears locss bit in sccr. at hreset assertion, if the pll output clock is valid, the system will switch to oscillator/external clock. if during hreset the pll loses lock or the clock frequency becomes slower than the required value, the system will switch to the buclk. after hreset negation the pll lock condition does not effect the system clock source selection. if the lme bit is clear, the switch to the backup clock is disabled and assertion of stbuc bit is ignored. if the chip is in limp mode, clearing the lme bit switches the system to normal operation and asserts hard reset to the chip. figure 8-8 describes the clock switching control logic. table 8-3 summarizes the status and control for each state. motorola chapter 8. clocks and power control 8-15 clock source switching figure 8-8. clock source switching flow chart note buclk_enable = (stbuc | loc) & lme lock indicates loss of lock status bit (locs) for all cases and loss of clock sticky bit (locss) when state 3 is active. when buclk_enable is changed, the chip asserts hreset to switch the system clock to buclk or pll. hreset_b = 1 bucl k _ e nable = 1 assert hreset_b buclk-enable = 1 &hreset_b=0 lme = 1 poreset_b = 0 1,buclk 2,buclk 5, osc poreset_b = 1 lme = 1 3,buclk 4, osc 6,bulck poreset_b = 0 hresert_b = 0 hreset_b = 1 bu c lk _ en a b l e = 1 h r e s e t_b = 1 b u c l k _ e n a b l e = 0 h r e s e t _ b = 1 else hreset_b = 0 locs lme = 0 buclk_enable = 0 &hreset_b=0 else buclk_enable=0 &hreset_b=0 buclk_enable = 1 &hreset_b=0 else 8-16 mpc565/mpc566 reference manual motorola low-power modes at poreset negation, if the pll is not locked, the loss-of-clock sticky bit (locss) is asserted, and the chip should operate with buclk. the switching from state three to state four is accomplished by clearing the stbuc and locss bits. if the switching is done when the pll is not locked, the system clock will not oscillate until lock condition is met. the default value of the lme bit is determined by modck[1:3] during assertion of the poreset line. the configuration modes are shown in table 8-1. 8.7 low-power modes the lpm and other bits in the plprcr are encoded to provide one normal operating mode and four low-power modes. in normal and doze modes the system can be in high state with frequency defined by the dfnh bits, or in the low state with frequency defined by the dfnl bits. the normal-high operating mode is the state out of reset. this is also the state of the bits after the low-power mode exit signal arrives. there are four low-power modes: doze mode sleep mode deep-sleep mode power-down mode 8.7.1 entering a low-power mode low-power modes are enabled by setting the pow bit in the msr and clearing the lpml (low-power mode lock) bit in the sccr. once enabled, a low-power mode is entered by table 8-3. status of clock source state poreset hreset lme locs (status) locss (sticky) stbuc bucs chip clock source 1 0 0 1 0 0 0 1 buclk 2 1 0 1 0/1 0 0 1 buclk 3 1 1 at least one of the two bits, locss or bucs, must be asserted (one) in this state. 111x 2 2 x = don?t care. 0/1 0/1 1 buclk 41 00/10x 2 00oscillator 51 10/10x 2 00oscillator 6 1 0 1 0/1 1 0/1 1 buclk motorola chapter 8. clocks and power control 8-17 low-power modes setting the lpm bits to the appropriate value. this can be done only in one of the normal modes. the user cannot change the lpm or csrc bits when the mcu is in doze mode. table 8-6 summarizes the control bit settings for the different clock power modes. 8.7.2 power mode descriptions table 8-5 describes the clock frequency and chip functionality for each power mode. table 8-4. power mode control bit settings power mode lpm[0:1] csrc texps normal-high 00 0 x normal-low (?gear?) 00 1 x doze-high 01 0 x doze-low 01 1 x sleep 10 x x deep-sleep 11 x 1 power-down 11 x 0 table 8-5. power mode descriptions operation mode spll clocks functionality power pins that need to be powered-up normal-high active full frequency 2 dfnh full functions not in use are shut off all on normal-low (?gear?) active full frequency 2 dfnl+1 all on doze-high active full frequency 2 dfnh enabled: rtc, pit, tb and dec, memory controller disabled: extended core (rcpu, bbc, fpu) kapwr, vddsyn, vdd, qvddl, nvddl, vddsram, vddrtc doze-low active full frequency 2 dfnl+1 kapwr, vddsyn, vdd, qvddl, nvddl, vddsram, vddrtc sleep active not active enabled: rtc, pit, tb and dec kapwr, vddsyn, vddsram, vddrtc 1 1 vddrtc can optionally be powered off if not required. deep-sleep not active not active kapwr, vddsram, vddrtc 1 power-down not active not active kapwr, vddsram, vddrtc 1 vddsram not active not active sram data retention vddsram, vddrtc 1 8-18 mpc565/mpc566 reference manual motorola low-power modes 8.7.3 exiting from low-power modes exiting from low-power modes occurs through an asynchronous interrupt or a synchronous interrupt generated by the memory controller. any enabled asynchronous interrupt clears the lpm bits but does not change the plprcr[csrc] bit. the return to normal-high mode from normal-low, doze-high, low, and sleep mode is accomplished with the asynchronous interrupt. the sources of the asynchronous interrupt are: asynchronous wake-up interrupt from the interrupt controller rtc, pit, or time base interrupts (if enabled) decrementer exception the system responds quickly to asynchronous interrupts. the wake-up time from normal-low, doze-high, doze-low, and sleep mode caused by an asynchronous interrupt or a decrementer exception is only three to four clock cycles of maximum system frequency. in 40-mhz systems, this wake-up requires 75 to 100 ns. the asynchronous wake-up interrupt from the interrupt controller is level sensitive one. it will therefore be negated only after the reset of interrupt cause in the interrupt controller. the timers? (rtc, pit, time base, or decrementer) interrupts indications set status bits in the plprcr (tmist). the clock module considers this interrupt to be pending asynchronous interrupt as long as the tmist is set. the tmist status bit should be cleared before entering any low-power mode. table 8-7 summarizes wake-up operation for each of the low-power modes. table 8-6. power mode wake-up operation operation mode wake-up method return time from wake-up event to normal-high normal-low (?gear?) software or interrupt asynchronous interrupts: 3-4 maximum system cycles synchronous interrupts: 3-4 actual system cycles doze-high interrupt doze-low interrupt sleep interrupt 3-4 maximum system clocks deep-sleep interrupt < 500 oscillator cycles 125 s ? 4 mhz 25 s ? 20 mhz power-down interrupt < 500 oscillator cycles + power supply wake-up v ddsram external power-on sequence motorola chapter 8. clocks and power control 8-19 low-power modes 8.7.3.1 exiting from normal-low mode in normal mode (as well as doze mode), if the plprcr[csrc] bit is set, the system toggles between low frequency (defined by plprcr[dfnl]) and high frequency (defined by plprcr[dfnh]. the system switches from normal-low mode to normal-high mode if either of the following conditions is met: an interrupt is pending from the interrupt controller; or the msr[pow] bit is cleared (power management is disabled). when neither of these conditions are met, the plprcr[csrc] bit is set, and the asynchronous interrupt status bits are reset, the system returns to normal-low mode. 8.7.3.2 exiting from doze mode the system changes from doze mode to normal-high mode whenever an interrupt is pending from the interrupt controller. 8.7.3.3 exiting from deep-sleep mode the system switches from deep-sleep mode to normal-high mode if any of the following conditions is met: an interrupt is pending from the interrupt controller an interrupt is requested by the rtc, pit, or time base a decrementer exception in deep-sleep mode the pll is disabled. the wake-up time from this mode is up to 500 pll input frequency clocks. in one-to-one mode the wake-up time may be up to 100 pll input frequency clocks. for a pll input frequency of four mhz, the wake-up time is less than 125 s. 8.7.3.4 exiting from power-down mode exit from power-down mode is accomplished through hard reset. external logic should assert hreset in response to the texps bit being set and texp pin being asserted. the texps bit is set by an enabled rtc, pit, time base, or decrementer interrupt. the hard reset should be asserted for no longer than the time it takes for the power supply to wake-up in addition to the pll lock time. when the texps bit is cleared (and the texp signal is negated), assertion of hard reset sets the bit, causes the pin to be asserted, and causes an exit from power-down low-power mode. refer to section 8.8.3, ?keep-alive power? for more information. 8-20 mpc565/mpc566 reference manual motorola low-power modes 8.7.3.5 low-power modes flow figure 8-9 shows the flow among the different power modes. 1 software is active only in normal-high/low modes. 2 texps receives the zero value by writing one. writing of zero has no effect on texps. 3 the switch from normal-high to normal-low is enable only if the conditions to asynchronous interrupt are cleared. figure 8-9. mpc565/mpc566 low-power modes flow diagram normal high mode lpm = 00 csrc = 0/1 normal-low lpm = 00, csrc = 1 doze-low lpm = 01, csrc = 1 doze-high lpm = 01, csrc = 0/1 sleep mode lpm = 10, csrc = 0 deep-sleep mode lpm = 11, csrc = 0, power-down mode lpm = 11, csrc = 0, (msrpow+interrupt)+csrc ((msrpow+interrupt))*csrc 3 interrupt software 1 software 1 software 1 software 1 software 1 async. wake-up or interrupt wake-up: frequency clocks wake-up: 3 - 4 sysfreq clocks 500 input software 1 rtc/pit/tb/dec interrupt hard reset asynchronous wake-up: 3 - 4 sys interrupts clocks texps = 1 texps = 0 2 software 1 rtc/pit/tb/dec freqmax followed by external hard reset motorola chapter 8. clocks and power control 8-21 basic power structure 8.8 basic power structure 8.8.1 general power supply definitions kapwr and vss power the following clock unit modules: oscillator, pitrtclk and tmbclk generation logic, timebase, decrementer, rtc, pit, system clock control register (sccr), low-power and reset-control register (plprcr), and reset status register (rsr). all other circuits are powered by the normal supply pins, vdd, qvddl, nvddl, vddf, vddsyn, vddrtc, vflash, vddh and vss. the power supply for each block is listed in table 8-7. the following are the relations between different power supplies: vdd = qvddl = nvddl = vddsyn = vddf = 2.6 v 0.1 v kapwr = vdd 0.2 v (during normal operation) vddrtc = vddl 0.2 v (during normal operation) vddsram[1,2,3] = vdd 0.3 v (during normal operation) vddh = vdda = vflash = 5.0 5% vddsram[1,2,3] 1.4 v (during standby operation) kapwr = 2.6 0.1 v (during standby operation) vddrtc = 2.6 0.1 v (during standby operation) table 8-7. power supplies circuit power supply clkout spll (digital), system low-power control internal logic clock drivers nvddl/qvddl spll (analog) vddsyn main oscillator reset machine limp mode mechanism register control sccr, pllrcr and rsr ppc rtc, pit, tb, and dec kapwr calram_a (32 kbytes) vddsram1/vdd 1 1 keep-alive power is supplied by vddsramx, but run current is provided through vdd calram_b (4 kbytes) vddsram2/vdd 1 dptram (ab and c), decram vddsram3/vdd 1 mios rtcsm vddrtc 8-22 mpc565/mpc566 reference manual motorola basic power structure note the power supply inputs vdd, qvddl, nvddl, vddsyn, and vddf should all be connected to the same 2.6-v power supply. the power supplies vddsram1, vddsram2, vddsram3, vddrtc, and kapwr can, in any combination, be connected to a 2.6-v standby power supply. standby power pins that are not connected to the standby power supply, should be connected to the same power supply as vdd. additionally, the standby power supply for vddsram1, vddsram2, and vddsram3 only can be connected to a supply as low as 1.4 v. the power supply inputs vddh and vflash should be connected to the same 5.0-v supply. vdda can be isolated from vddh, but should be the same approximate voltage. 8.8.2 chip power structure the mpc565/mpc566 provides a wide range of possibilities for power supply connections. figure 8-10 illustrates the different power supply sources for each of the basic units on the chip. 8.8.2.1 nvddl this supplies the final output stage of the 2.6-v pad output drivers. 8.8.2.2 qvddl this supplies all pad logic and pre-driver circuitry, except for the final output stage of the 2.6-v pad output drivers. 8.8.2.3 vdd vdd powers the internal logic of the mpc565/mpc566, nominally 2.6 v. 8.8.2.4 vddsyn, vsssyn the charge pump and the vco of the spll are fed by a separate 2.6-v power supply (vddsyn) in order to improve noise immunity and achieve a high stability in its output frequency. vsssyn provides an isolated ground reference for the pll. 8.8.2.5 kapwr the oscillator, time base counter, decrementer, periodic interrupt timer and the real-time clock are fed by the kapwr rail. this allows the external power supply unit to disconnect motorola chapter 8. clocks and power control 8-23 basic power structure all other sub-units of the mcu in low-power deep-sleep mode. the texp pin (fed by the same rail) can be used by the external power supply unit to switch between sources. the irq [6:7]/modck[2:3], irq5 /modck1, xtal, extal, ext-clk, poreset , hreset ,sreset , and rstconf /texp input pins are powered by kapwr. circuits, including pull-up resisters, driving these inputs should be powered by kapwr. 8.8.2.6 vdda, vssa vdda supplies power to the analog subsystems of the qadca and qadcb modules; it is nominally 5.0 v. vdda is the ground reference for the analog subsystems. 8.8.2.7 vflash vflash supplies the uc3f normal operating voltage. it is nominally 5.0 v. 8.8.2.8 vddf, vssf vddf provides internal core voltage to the uc3f flash module; it should be a nominal 2.6 v. vssf provides an isolated ground for the uc3f flash module. 8.8.2.9 vddh vddh provides power for the 5-v i/o operations. it is a nominal 5.0 v. 8.8.2.10 vddsram1 this is the 2.6-v voltage supply input for the keep-alive section of the calram_a(32k) module. this pin supplies only keep-alive power to the calram_a(32k) module. this supply can be between 1.4 and 2.7 v. run current is supplied by normal vdd. 8.8.2.11 vddsram2 this is the 2.6-v voltage supply input for the calram_b (4k) module. this supply can be between 1.4 and 2.7 v. this pin supplies keep-alive power only to the calram_b(4k) module. run current is supplied by normal vdd. 8.8.2.12 vddsram3 this is the 2.6-v voltage supply input for the arrays in the dptram_ab (6k), dptram_c (4k), and decram modules. this pin supplies keep-alive voltage to the dptram arrays and the decram. run current is supplied by the normal vdd. 8-24 mpc565/mpc566 reference manual motorola basic power structure 8.8.2.13 vddrtc vddrtc supplies power to the mios real-time clock submodule and its 32.768-khz oscillator. the rtc can be kept running when all of the other power supplies are turned off. 8.8.2.14 vss vss provides the ground reference for the mpc565/mpc566. figure 8-10. basic power supply configuration 8.8.3 keep-alive power 8.8.3.1 keep-alive power configuration figure 8-11 illustrates an example of a switching scheme for an optimized low-power system. sw1 and sw2 can be unified in only one switch if vddsyn and vdd/nvddl/qvddl are supplied by the same source. clock control pll pit, rtc, tb, and dec internal logic nvddl i/o vdd vddsyn kapwr texp oscillator, sram vddsram1 vdd vddh flash vflash vddf qvddl dptram decram vddsram3 vddsram2 sram mios rtc vddrtc qadc vdda vssa vdd motorola chapter 8. clocks and power control 8-25 basic power structure figure 8-11. external power supply scheme the mpc565/mpc566 asserts the texp signal, if enabled, when the rtc or tb time value matches the value programmed in the associated alarm register or when the pit or dec value reaches zero. the texp signal is negated when the texps status bit is written to one. the kapwr power supply feeds the main crystal oscillator (oscm). the condition for the main crystal oscillator stability is that the power supply value changes slowly. the maximum slope must be less than 5 mv per oscillation cycle ( > 200-300/freq oscm ). 8.8.3.2 keep-alive power registers lock mechanism the usiu timer, clocks, reset, power, decrementer, and time base registers are powered by the kapwr supply. when the main power supply is disconnected after power-down mode is entered, the value stored in any of these registers is preserved. if power-down mode is not entered before power disconnect, there is a chance of data loss in these registers. to minimize the possibility of data loss, the mpc565/mpc566 includes a key mechanism that ensures data retention as long as a register is locked. while a register is locked, writes to this register are ignored. each of the registers in the kapwr region have a key that can be in one of two states: open or locked. at power-on reset the following keys are locked: rtc, rtsec, rtcal, and main power backup vddsyn 2.6 v vdd kapwr supply switch logic texp 2.6-v sw1 sw2 power supply vddsram 1.4 v < power supply vddsram[1,2,3] o o o o mpc565/mpc566 vddrtc vddsram <2.7 v 8-26 mpc565/mpc566 reference manual motorola basic power structure rtcsc. all other registers are unlocked. each key has an address associated with it in the internal memory map. a write of 0x55ccaa33 to the associated key register changes the key to the open state. a write of any other data to this location changes the key to the locked state. the key registers are write-only. a read of the key register has undefined side effects and may be interpreted as a write that locks the associated register. table 8-8 lists the registers powered by kapwr and the associated key registers. table 8-8. kapwr registers and key registers kapwr register associated key register address or spr number register address register 0x2f c200 time base status and control (tbscr) see table 6-18 for bit descriptions. 0x2f c300 time base status and control key (tbscrk) 0x2f c204 time base reference 0 (tbref0) see section 6.14.4.3, ?time base reference registers? for bit descriptions. 0x2f c304 time base reference 0 key (tbref0k) 0x2f c208 time base reference 1 (tbref1) see section 6.14.4.3, ?time base reference registers for bit descriptions. 0x2f c308 time base reference 1 key (tbref1k) 0x2f c220 real time clock status and control (rtcsc) see table 6-19 for bit descriptions. 0x2f c320 real time clock status and control key (rtcsck) 0x2f c224 real time clock (rtc) see section 6.14.4.6, ?real-time clock register (rtc)? for bit descriptions. 0x2f c324 real time clock key (rtck) 0x2f c228 real time alarm seconds (rtsec) reserved 0x2f c328 real time alarm seconds key (rtseck) 0x2f c22c real time alarm (rtcal) see section 6.14.4.7, ?real-time clock alarm register (rtcal)? for bit descriptions. 0x2f c32c real time alarm key (rtcalk) 0x2f c240 pit status and control (piscr) see table 6-20 for bit descriptions. 0x2f c340 pit status and control key (piscrk) 0x2f c244 pit count (pitc) see table 6-21 for bit descriptions. 0x2f c344 pit count key (pitck) 0x2f c280 system clock control register (sccr) see table 8-9 for bit descriptions. 0x2f c380 system clock control key (sccrk) 0x2f c284 pll low-power and reset-control register (plprcr) see table 8-11 for bit descriptions. 0x2f c384 pll low-power and reset-control register key (plprcrk) 0x2f c288 reset status register (rsr) see table 7-3 for bit descriptions. 0x2f c388 reset status register key (rsrk) motorola chapter 8. clocks and power control 8-27 vddsram supply failure detection figure 8-12 illustrates the process of locking or unlocking a register powered by kapwr. figure 8-12. keep-alive register key state diagram 8.9 vddsram supply failure detection a special circuit for vddsram supply failure detection is provided. in the case of supply failure detection, the dedicated sticky bits lvsrs in the vsrmcr register are asserted. software can read or clear these bits. the user should enable the detector and then clear these bits. if any of the lvsr bits are read as one, then a power failure of vddsram has occurred. the circuit is capable of detecting supply failure below a voltage level to be determined. also, enable/disable control bit for the vddsram detector may be used to disconnect the circuit and save the detector power consumption. note at temperatures above room ambient (25c), the vddsram low voltage detect circuit may not always indicate that the vddsram voltage has dropped below the minimum data retention level for the sram. use an external mechanism to determine when the voltage supplied to the vddsram pin(s) is below the minimum data retention voltage. spr 22 decrementer see section 3.9.5, ?decrementer register (dec)? for bit descriptions. 0x2f c30c time base and decrementer key (tbk) spr 268, 269, 284, 285, time base see table 3-11 and table 3-14 for bit descriptions. table 8-8. kapwr registers and key registers (continued) kapwr register associated key register address or spr number register address register open locked write to the key 0x55ccaa33 writetothekeyothervalue power on reset (valid for rtc, rtsec, rtcal and rtcsc) (valid for other registers) power-on reset 8-28 mpc565/mpc566 reference manual motorola power-up/down sequencing 8.10 power-up/down sequencing figure 8-13 and figure 8-14 detail the power-up sequencing for mpc565/mpc566 during normal operation. note that for each of the conditions detailing the voltage relationships the absolute bounds of the minimum and maximum voltage supply cannot be violated; that is, the value of vddl cannot fall below 2.5 v or exceed 2.7 v, and the value of vddh cannot fall below 4.75 v or exceed 5.25 v for normal operation. power consumption during power up sequencing can not be specified prior to evaluation and characterization of production silicon. the goal is to keep the power consumption during power up sequencing below the operating power consumption. during the power down sequence poreset needs to be asserted while vdd, nvddl, and qvddl are at a voltage greater than or equal to 2.5 v. below this voltage the power supply chip can be turned off. if the turn-off voltage of the power supply chip is greater than 0.74 v for the 2.6-v supply and greater than 0.8 v for the 5-v supply, then the circuitry inside the mpc565/mpc566 will act as a load to the respective supply and will discharge the supply line down to these values. since the 2.6-v logic represents a larger load to the supply chip, the 2.6-v supply line will decay faster than the 5-v supply line. figure 8-13. no standby, no kapwr, all system power-on/off power on power off operating see note 1. see note 2. vddh vdd, nvvl, qvddl kaprr vddsram vdda, vrh vddsyn vflash (5 v) poreset hreset motorola chapter 8. clocks and power control 8-29 power-up/down sequencing figure 8-14. standby and kapwr, other power-on/off note the following notes apply to figure 8-13 and figure 8-14 above. for more detailed information on power sequencing see section e.8, ?power-up/down sequencing.? 1 vddh 8-30 mpc565/mpc566 reference manual motorola clocks unit programming model 8.11 clocks unit programming model 8.11.1 system clock control register (sccr) the spll has a 32-bit control register, sccr, which is powered by keep-alive power. note com[1] bit default value is determined during by bdrv reset configuration bit; see section 7.5.2, ?hard reset configuration word. msb 0 1 2 3 4 56 7 8 9 10 11 12131415 dbct com dcslr mfpdl lpml tbs rtdiv stbuc cqds prqen rtsel bucs ebdf[0:1] lme poreset: 10id(2) 1 00001101eq2 2 0 id[13:14] 2 eq3 3 hreset: u0id(2) 1 u u u u u u u 1 u u id[13:14] 1 u 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 eeclk[0:1] engdiv[0:5] rese rved dfnl[0:2] rese rved dfnh[0:2] poreset: 001 1 1 11 1 0 0 0 0 0 000 hreset: uuu u u uuu 0 0 0 0 0 0 0 0 1 the hard reset value is a reset configuration word value, extracted from the indicated internal data bus lines. refer to section 7.5.2, ?hard reset configuration word.? 2 eq2 = modck1 3 eq3 = (modck1 & modck2 & modck3 ) | (modck1 & modck2 & modck3) | (modck1 & modck2 & modck3). see table 8-1. u = unaffected by reset figure 8-15. sccr ? system clock and reset control register 0x2f c280 motorola chapter 8. clocks and power control 8-31 clocks unit programming model table 8-9. sccr bit descriptions bit(s) name description 0 dbct disable backup clock for timers. the dbct bit controls the timers clock source while the chip is in limp mode. if dbct is set, the timers clock (tmblck, rtclk) source will not be the backup clock, even if the system clock source is the backup clock ring oscillator. the real-time clock source will be extal or extclk according to rtsel bit (see description in bit 11 below), and the time base clocks source will be determined according to tbs bit and modck1. 0 if the chip is in limp mode, the timer clock source is the backup (limp) clock 1 the timer clock source is either the external clock or the crystal (depending on the current clock mode selected) 1:2 com clock output mode ? the com and cqds bits control the output buffer strength of the clkout and external bus pins. when both com bits are set the clkout pin is held in the high (1) state and external bus pins are driven at reduced drive. these bits can be dynamically changed without generating spikes on the clkout and external bus pins. if clkout pin is not connected to external circuits, set both bits (disabling clkout) to minimize noise and power dissipation. the default value for com[1] is determined by the bdrv bit in the reset configuration word. see table 7-5. for clkout control see table 8-10. 3 dcslr disable clock switching at loss of lock during reset. when dcslr is clear and limp mode is enabled, the chip will switch automatically to the backup clock if the pll losses lock during hreset . when dcslr is asserted, a pll loss-of-lock event does not cause clock switching. if hreset is asserted and dcslr is set, the chip will not negate hreset until the pll acquires lock. 0 enable clock switching if the pll loses lock during reset 1 disable clock switching if the pll loses lock during reset 4 mfpdl mf and pre-divider lock. setting this control bit disables writes to the mf and divf bits. this helps prevent runaway software from changing the vco frequency and causing the spll to lose lock. in addition, to protect against hardware interference, a hardware reset will be asserted if these fields are changed while lpml is asserted. this bit is writable once after power-on reset. 0 mf and divf fields are writable 1 mf and divf fields are locked 5 lpml lpm lock. setting this control bit disables writes to the lpm and csrc control bits. in addition, for added protection, a hardware reset is asserted if any mode is entered other than normal-high mode. this protects against runaway software causing the mcu to enter low-power modes. (the msr[pow] bit provides additional protection). lpml is writable once after power-on reset. 0 lpm and csrc bits are writable 1 lpm and csrc bits are locked and hard reset will occur if the mcu is not in normal-high mode 6 tbs time base source. note that when the chip is operating in limp mode (bucs = 1), tbs is ignored, and the backup clock is the time base clock source. 0 source is oscclk divided by either 4 or 16 1 source is system clock divided by 16 7 rtdiv rtc (and pit) clock divider. at power-on reset this bit is cleared if modck[1:3] are all low; otherwise the bit is set. 0 rtc and pit clock divided by 4 1 rtc and pit clock divided by 256 8 stbuc switch to backup clock control. when software sets this bit, the system clock is switched to the on-chip backup clock ring oscillator, and the chip undergoes a hard reset. the stbuc bit is ignored if lme is cleared. 0 do not switch to the backup clock ring oscillator 1 switch to backup clock ring oscillator 8-32 mpc565/mpc566 reference manual motorola clocks unit programming model 9 cqds clock quarter drive strength ? the com and cqds bits control the output buffer strength of the clkout, see table 8-10. 10 prqen power management request enable 0 remains in the lower frequency (defined by dfnl) even if the power management bit in the msr is reset (normal operational mode) or if there is a pending interrupt from the interrupt controller 1 switches to high frequency (defined by dfnh) when the power management bit in the msr is reset (normal operational mode) or there is a pending interrupt from the interrupt controller 11 rtsel rtc circuit input source select. at power-on reset rtsel receives the value of the modck1 signal. refer to table 8-1. note that if the chip is operating in limp mode (bucs = 0), the rtsel bit is ignored, and the backup clock is the clock source for the rt and pit clocks 0 oscm clock is selected as input to rtc and pit 1 extclk clock is selected as the rtc and pit clock source 12 bucs backup clock status. this status bit indicates the current system clock source. when loss of clock is detected and the lme bit is set, the clock source is the backup clock and this bit is set. when the stbuc bit and lme bit are set, the system switches to the backup clock and bucs is set. 0 system clock is not the backup clock 1 system clock is the backup clock 13:14 ebdf[0:1] external bus division factor. these bits define the frequency division factor between (gclk1 and gclk2) and (gclk1_50 and gclk2_50). clkout is similar to gclk2_50. the gclk2_50 and gckl1_50 are used by the external bus interface and memory controller in order to interface to the external system. the ebdf bits are initialized during hard reset using the hard reset configuration mechanism. 00 clkout is gckl2 divided by 1 01 clkout is gckl2 divided by 2 1x reserved 15 lme limp mode enable. when lme is set, the loss-of-clock monitor is enabled and any detection of loss of clock will switch the system clock automatically to backup clock. it is also possible to switch to the backup clock by setting the stbuc bit. if lme is cleared, the option of using limp mode is disabled. the loss of clock detector is not active, and any write to stbuc is ignored. the lme bit is writable once, by software, after power-on reset, when the system clock is not backup clock (bucs = 0). during power-on reset, the value of lme is determined by the modck[1:3] bits. (refer to ta bl e 8 - 1 .) 0 limp mode disabled 1 limp mode enabled 16:17 eeclk[0:1] enable engineering clock. this field controls the output buffer voltage of the engclk pin. when both bits are set the engclk pin is held in the high state. these bits can be dynamically changed without generating spikes on the engclk pin. if engclk is not connected to external circuits, set both bits (disabling engclk) to minimize noise and power dissipation. for measurement purposes the backup clock (buclk) can be driven externally on the engclk pin. 00 engineering clock enabled, 2.6 v output buffer 01 engineering clock enabled, 5 v output buffer 10 buclk is the output on the engclk 2.6 v output buffer 11 engineering clock disabled table 8-9. sccr bit descriptions (continued) bit(s) name description motorola chapter 8. clocks and power control 8-33 clocks unit programming model 18:23 engdiv[0:5] engineering clock division factor. these bits define the frequency division factor between vco/2 and engclk. division factor can be from 1 (engdiv = 000000) to 64 (engdiv = 111111). these bits can be read and written at any time. they are not affected by hard reset but are cleared during power-on reset. note: if the engineering clock division factor is not a power of two, synchronization between the system and engclk is not guaranteed. 24 ? reserved 25:27 dfnl[0:2] division factor low frequency. the user can load these bits with the desired divide value and the csrc bit to change the frequency. changing the value of these bits does not result in a loss of lock condition. these bits are cleared by power-on or hard reset. refer to section 8.5.1, ?general system clocks? and figure 8-5 for details on using these bits. 000 divide by 2 001 divide by 4 010 divide by 8 011 divide by 16 100 divide by 32 101 divide by 64 110 reserved 111 divide by 256 28 ? reserved 29:31 dfnh division factor high frequency. these bits determine the general system clock frequency during normal mode. changing the value of these bits does not result in a loss of lock condition. these bits are cleared by power-on or hard reset. the user can load these bits at any time to change the general system clock rate. note that the gclks generated by this division factor are not 50% duty cycle (i.e. clkout). 000 divide by 1 001 divide by 2 010 divide by 4 011 divide by 8 100 divide by 16 101 divide by 32 110 divide by 64 111 reserved table 8-10. com and cqds bits functionality com[0:1] cqds function 00 x clock output enabled full-strength output buffer, bus pins full drive 01 0 clock output enabled half-strength output buffer, bus pins reduced drive 01 1 clock output enabled quarter-strength output buffer, bus pins reduced drive 10 x clock output disabled, bus pins full drive 11 x clock output disabled, bus pins reduced drive table 8-9. sccr bit descriptions (continued) bit(s) name description 8-34 mpc565/mpc566 reference manual motorola clocks unit programming model 8.11.2 pll, low-power, and reset-control register (plprcr) the pll, low-power, and reset-control register (plprcr) is a 32-bit register powered by the keep-alive power supply. msb 0 123456789101112131415 mf res erv ed locs locss spls poreset: 0or4 0 0 0 0 hreset: u u u uuuuuuuuuuu uu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 splss texps texp_ inv tmist res erv ed csrc lpm csr lolre res erv ed divf poreset: 0 1 0 00000000000 00 hreset: u1u0u000uu uuuuu u = unaffected by reset figure 8-16. plprcr ? pll, low-power, and reset-control register0x2f c284 table 8-11. plprcr bit descriptions bit(s) name description 0:11 mf multiplication factor bits. the output of the vco is divided to generate the feedback signal to the phase comparator. the mf bits control the value of the divider in the spll feedback loop. the phase comparator determines the phase shift between the feedback signal and the reference clock. this difference results in either an increase or decrease in the vco output frequency. the mf bits can be read and written at any time. however, this field can be write-protected by setting the mf and pre-divider lock (mfpdl) bit in the sccr. changing the mf bits causes the spll to lose lock. also, the mf field should not be modified when entering or exiting from low power mode (lpm change), or when back-up clock is active. the normal reset value for the dfnh bits is zero (divide by 1). when the pll is operating in one-to-one mode, the multiplication factor is set to x1 (mf = 0). 12 ? reserved motorola chapter 8. clocks and power control 8-35 clocks unit programming model 13 locs loss of clock status. when the oscillator or external clock source is not at the minimum frequency, the loss-of-clock circuit asserts the locs bit. this bit is cleared when the oscillator or external clock source is functioning normally. this bit is reset only on power-on reset. writes to this bit have no effect. 0 no loss of oscillator is currently detected 1 loss of oscillator is currently detected 14 locss loss of clock sticky. if, after negation of poreset , the loss-of-clock circuit detects that the oscillator or external clock source is not at a minimum frequency, the locss bit is set. locss remains set until software clears it by writing a one to it. a write of zero has no effect on this bit. the reset value is determined during hard reset. the stbuc bit will be set provided the pll lock condition is not met when hreset is asserted, and cleared if the pll is locked when hreset is asserted. 0 no loss of oscillator has been detected 1 loss of oscillator has been detected 15 spls system pll lock status bit 0 spll is currently not locked 1 spll is currently locked 16 splss spll lock status sticky bit. an out-of-lock sets the splss bit. the bit remains set until software clears it by writing a one to it. a write of zero has no effect on this bit. the bit is cleared at power-on reset. this bit is not affected due to a software initiated loss-of-lock (mf change and entering deep-sleep or power-down mode). the splss bit is not affected by hard reset. 0 spll has remained in lock 1 spll has gone out of lock at least once (not due to software-initiated loss of lock) 17 texps timer expired status bit. this bit controls whether the chip negates the texp pin in deep-sleep mode, thus enabling external circuitry to switch off the vdd (power-down mode). when lpm = 11, csrc = 0, and texps is high, the texp pin remains asserted. when lpm = 11, csrc = 0, and texps is low, the texps pin is negated. to enable automatic wake-up texps is asserted when one of the following occurs: thepitisexpired the real-time clock alarm is set the time base clock alarm is set the decrementer exception occurs the bit remains set until software clears it by writing a one to it. a write of zero has no effect on this bit. texps is set by power-on or hard reset. 0 texp is negated in deep-sleep mode 1 texp pin remains asserted always 18 texp_invp timer expired pin inversed polarity ? the tex_invp bit controls whether the polarity of the texp pin will be active high (normal default) or active low. 0 the texp pin is active high 1 the texp pin is active low 19 tmist timers interrupt status.tmist is set when an interrupt from the rtc, pit, tb or dec occurs. the tmist bit is cleared by writing a one to it. writing a zero has no effect on this bit. the system clock frequency remains at its high frequency value (defined by dfnh) if the tmist bit is set, even if the csrc bit in the plprcr is set (dfnl enabled) and conditions to switch to normal-low mode do not exist. this bit is cleared during power-on or hard reset. 0 no timer expired event was detected 1 a timer expire event was detected 20 ? reserved table 8-11. plprcr bit descriptions (continued) bit(s) name description 8-36 mpc565/mpc566 reference manual motorola clocks unit programming model 8.11.3 change of lock interrupt register (colir) the colir is 16-bit read/write register. it controls the change of lock interrupt generation, and is used for reporting a loss of lock interrupt source. it contains the interrupt request level and the interrupt status bit. this register is readable and writable at any time. a status bit is cleared by writing a one (writing a zero does not affect a status bit?s value). the colir is memory mapped into the mpc565/mpc566 usiu register map. 21 csrc clock source. this bit is cleared at hard reset. 0 general system clock is determined by the dfnh value 1 general system clock is determined by the dfnl value 22:23 lpm low-power mode select. these bits are encoded to provide one normal operating mode and four low-power modes. in normal and doze modes, the system can be in high state (frequency determined by the dfnh bits) or low state (frequency defined by the dfnl bits). the lpm field can be write-protected by setting the lpm and csrc lock (lpml) bit in the sccr refer to table 8-4 and table 8-5. 24 csr checkstop reset enable. if this bit is set, then an automatic reset is generated when the rcpu signals that it has entered checkstop mode, unless debug mode was enabled at reset. if the bit is clear and debug mode is not enabled, then the usiu will not do anything upon receiving the checkstop signal from the rcpu. if debug mode is enabled, then the part enters debug mode upon entering checkstop mode. in this case, the rcpu will not assert the checkstop signal to the reset circuitry. this bit is writable once after soft reset. 0 no reset will occur when checkstop is asserted 1 reset will occur when checkstop is asserted 25 lolre loss of lock reset enable 0 loss of lock does not cause hreset assertion 1 loss of lock causes hreset assertion note: if limp mode is enabled, use the colir feature instead of setting the lolre bit. see section 8.11.3, ?change of lock interrupt register (colir).? 26 ? reserved 27:31 divf the divf bits control the value of the pre-divider in the spll circuit. the divf bits can be read and written at any time. however, the divf field can be write-protected by setting the mf and pre-divider lock (mfpdl) bit in the sccr. changing the divf bits causes the spll to lose lock. msb 0 1234567 8 91011121314lsb 15 colirq colis rese rved colie reserved reset: 00000000 0 0uuuuuu u = unaffected by reset figure 8-17. colir ? change of lock interrupt register 0x2f c28c table 8-11. plprcr bit descriptions (continued) bit(s) name description motorola chapter 8. clocks and power control 8-37 clocks unit programming model 8.11.4 vddsram control register (vsrmcr) this register contains control bits for enabling or disabling the vddsram supply detection circuit. there are also four bits that indicate the failure detection. all four bits have the same function and are required to improve the detection capability in extreme cases. table 8-12. colir bit descriptions bit(s) name description 0:7 colirq change of lock interrupt request level. these bits determine the interrupt priority level of the change of lock. to specify certain level, the appropriate one of these bits should be set. 8 colis if set (?one?), the bit indicates that a change in the pll lock status was detected. the pll was locked and lost lock, or the pll was unlocked and got locked. the bit should be cleared by writing a one. 9?reserved 10 colie change of lock interrupt enable. if colie bit is asserted, an interrupt will be generated when the colis bit is asserted. 0 change of lock interrupt disable 1 change of lock interrupt enable 10:15 ? reserved msb 0 1234 5 6 7891011121314lsb 15 0 lvsrs vsrde lvdrs reserved hreset: uuuu 0 u u = unaffected by reset figure 8-18. vsrmcr ? vddsram control register0x2f c290 table 8-13. vsrmcr bit descriptions bit(s) name description 0?reserved 1:4 lvsrs loss of vddsram1 sticky. these status bits indicate whether a vddsram1 supply failure occurred. in addition, when the power is turned on for the first time, vddsram1 rises and these bits are set. the lvsrs bits are cleared by writing them to ones. a write of zero has no effect on these bits. 0 no vddsram1 supply failure was detected 1 vddsram1 supply failure was detected 5 vsrde vddsram1 detector disable. 0 vddsram1 detection circuit is enabled 1 vddsram1 detection circuit is disabled 8-38 mpc565/mpc566 reference manual motorola clocks unit programming model 6 lvdrs loss of vddsram1 for decram sticky ? the status bit, dedicated especially for the bbc decram, which indicates if there was vddsram1 supply failure. when the power is turned on for the first time, vddsram1 rises also and the bits will be asserted. the lvdecram bit can be cleared by writing ones to lvdecram. a write of zero has no effect on this bit. the bit may be used by application software, to decide if there is need to load decompression vocabularies during reset routine. 0 vddsram1 supply failure was not detected 1 vddsram1 supply failure was detected note: the lvdrs bit is provided as a convenience for indicating that the decram has lost power. it requires that the vddsram1 and vddsram3 pins are connected to the same power supply. it actually only monitors the vddsram1 supply. 7:15 ? reserved table 8-13. vsrmcr bit descriptions (continued) bit(s) name description motorola chapter 9. external bus interface 9-1 chapter 9 external bus interface the mpc565/mpc566 external bus is a synchronous, burstable bus. signals driven on this bus must adhere to the setup and hold time relative to the bus clock?s rising edge. the bus has the ability to support multiple masters. the mpc565/mpc566 external bus interface architecture supports byte, half-word, and word operands allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles controlled by the size outputs (tsiz0, tsiz1). for accesses to 16- and 8-bit ports, the slave must be controlled by the memory controller. 9.1 features the external bus interface features are listed below. 32-bit address bus with transfer size indication (only 24 available on pins) 32-bit data bus bus arbitration logic on-chip with external master support chip-select and wait state generation to support peripheral or static memory devices through the memory controller supports various memory (sram, eeprom) types: synchronous and asynchronous, burstable and non-burstable supports non-wrap bursts with up to four data beats flash rom programming support implements the powerpc architecture easy to interface to slave devices bus is synchronous (all signals are referenced to rising edge of bus clock) bus can operate at the same frequency as the internal rcpu core of mpc565/mpc566 or half the frequency. 9.2 bus transfer signals the bus transfers information between the mpc565/mpc566 and external memory of a peripheral device. external devices can accept or provide 8, 16, and 32 data bits in parallel 9-2 mpc565/mpc566 reference manual motorola bus control signals and must follow the handshake protocol described in this section. the maximum number of bits accepted or provided during a bus transfer is defined as the port width. the mpc565/mpc566 has non-multiplexed address and data buses. control signals indicate the beginning and type of the cycle, as well as the address space and size of the transfer. the selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. a strobe signal for the address lines indicates the validity of the address. the mpc565/mpc566 bus is synchronous with a synchronous support. the bus and control input signals must be timed to setup and hold times relative to the rising edge of the clock. bus cycles can be completed in two clock cycles. for all inputs, the mpc565/mpc566 latches the level of the input during a sample window around the rising edge of the clock signal. this window is illustrated in figure 9-1, where t su and t ho are the input setup and hold times, respectively. to ensure that an input signal is recognized on a specific rising edge of the clock, that input must be stable during the sample window. if an input makes a transition during the window time period, the level recognized by the mpc565/mpc566 is not predictable; however, the mpc565/mpc566 always resolves the latched level to either a logic high or low before using it. in addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section. figure 9-1. input sample window 9.3 bus control signals the mpc565/mpc566 initiates a bus cycle by driving the address, size, address type, cycle type, and read/write outputs. at the beginning of a bus cycle, tsiz[0:1] are driven with the address type signals. tsiz0 and tsiz1 indicate the number of bytes remaining to be clock signal t ho t su sample window motorola chapter 9. external bus interface 9-3 bus control signals transferred during an operand cycle (consisting of one or more bus cycles). these signals are valid at the rising edge of the clock in which the transfer start (ts ) signal is asserted. the read/write (rd/wr ) signal determines the direction of the transfer during a bus cycle. driven at the beginning of a bus cycle, rd/wr is valid at the rising edge of the clock in which ts is asserted. the logic level of rd/wr only changes when a write cycle is preceded by a read cycle or vice versa. the signal may remain low for consecutive write cycles. figure 9-2. mpc565/mpc566 bus signals addr[8:31] rd/wr burst tsiz[0:1] at[0:3] sts (bi) ts bi (sts ) kr data[0:31] ta tea bdip br bg bb cr 32 1 1 2 4 1 1 1 1 1 32 1 1 1 1 1 1 address and transfer attributes transfer start arbitration data transfer ter m in at i o n reservation protocol cycle rsv 1 ptr 1 retry 1 9-4 mpc565/mpc566 reference manual motorola bus interface signal descriptions 9.4 bus interface signal descriptions table 9-1 describes each signal in the bus interface unit. more detailed descriptions can be found in subsequent subsections. the buses are described in big endian manner, which means that bit 0 is the most significant bit in a bus. . msb 0 lsb 31 table 9-1. mpc565/mpc566 siu signals signal name pins active i/o description address and transfer attributes addr[0:31] address bus 24 [8:31] high o specifies the physical address of the bus transaction. i driven by an external bus master when it owns the external bus. an input for testing purposes only. rd/wr read/write 1 high o driven by the mpc565/mpc566 along with the address when it owns the external bus. driven high indicates that a read access is in progress. driven low indicates that a write access is in progress. i driven by an external master when it owns the external bus. driven high indicates that a read access is in progress. driven low indicates that a write access is in progress. burst burst transfer 1 low o driven by the mpc565/mpc566 along with the address when it owns the external bus. driven low indicates that a burst transfer is in progress. driven high indicates that the current transfer is not a burst. i driven by an external master when it owns the external bus. driven low indicates that a burst transfer is in progress. driven high indicates that the current transfer is not a burst. the mpc565/mpc566 does not support burst accesses to internal slaves. tsiz[0:1] transfer size 2 high o driven by the mpc565/mpc566 along with the address when it owns the external bus. specifies the data transfer size for the transaction. i driven by an external master when it owns the external bus. specifies the data transfer size for the transaction. at[0:3] address type 3 high o driven by the mpc565/mpc566 along with the address when it owns the external bus. indicates additional type on the current transaction. i only for testing purposes. motorola chapter 9. external bus interface 9-5 bus interface signal descriptions rsv reservation transfer 1 low o driven by the mpc565/mpc566 along with the address when it owns the external bus. indicates additional information about the address on the current transaction. i only for testing purposes. ptr program trace 1 high o driven by the mpc565/mpc566 along with the address when it owns the external bus. indicates additional information about the address on the current transaction. i only for testing purposes. bdip burst data in progress 1 low o driven by the mpc565/mpc566 when it owns the external bus. it is part of the burst protocol. when bdip is asserted, the second beat in front of the current one is requested by the master. this signal is negated prior to the end of a burst to terminate the burst data phase early. i driven by an external master when it owns the external bus. when bdip is asserted, the second beat in front of the current one is requested by the master. this signal is negated prior to the end of a burst to terminate the burst data phase early. the mpc565/mpc566 does not support burst accesses to internal slaves. transfer start ts transfer start 1 low o driven by the mpc565/mpc566 when it owns the external bus. indicates the start of a transaction on the external bus. i driven by an external master when it owns the external bus. it indicates the start of a transaction on the external bus or (in show cycle mode) signals the beginning of an internal transaction. sts special transfer start 1 low o driven by the mpc565/mpc566 when it owns the external bus. indicates the start of a transaction on the external bus or signals the beginning of an internal transaction in show cycle mode. reservation protocol cr cancel reservation 1 low i each mpc500 cpu has its own cr signal. assertion of cr instructs the bus master to clear its reservation; some other master has touched its reserved space. this is a pulsed signal. kr kill reservation 1 low i incaseofabuscycleinitiatedbyastwcxinstruction issued by the rcpu to a non-local bus on which the storage reservation has been lost, this signal is used by the non-local bus interface to back-off the cycle. refer to section 9.5.10, ?storage reservation? for details. table 9-1. mpc565/mpc566 siu signals (continued) signal name pins active i/o description 9-6 mpc565/mpc566 reference manual motorola bus interface signal descriptions data data[0:31] data bus 32 high the data bus has the following byte lane assignments: data byte byte lane data[8:15] 0 data[8:15] 1 data[16:23] 2 data[24:31] 3 o driven by the mpc565/mpc566 when it owns the external bus and it initiated a write transaction to a slave device. for single beat transactions, the byte lanes not selected for the transfer by addr[30:31] and tsiz[0:1] do not supply valid data. in addition, the mpc565/mpc566 drives the data[0:31] when an external master owns the external bus and initiated a read transaction to an internal slave module. i driven by the slave in a read transaction. for single beat transactions, the mpc565/mpc566 does not sample byte lanes that are not selected for the transfer by addr[30:31] and tsiz[0:1]. in addition, an external master that owns the bus and initiated a write transaction to an internal slave module drives data[0:31]. transfer cycle termination ta transfer acknowledge 1 low i driven by the slave device to which the current transaction was addressed. indicates that the slave has received the data on the write cycle or returned data on the read cycle. if the transaction is a burst, ta should be asserted for each one of the transaction beats. o driven by the mpc565/mpc566 when the slave device is controlled by the on-chip memory controller or when an external master initiated a transaction to an internal slave module. tea transfer error acknowledge 1 low i driven by the slave device to which the current transaction was addressed. indicates that an error condition has occurred during the bus cycle. o driven by the mpc565/mpc566 when the internal bus monitor detected an erroneous bus condition, or when an external master initiated a transaction to an internal slave module and an internal error was detected. table 9-1. mpc565/mpc566 siu signals (continued) signal name pins active i/o description motorola chapter 9. external bus interface 9-7 bus interface signal descriptions bi burst inhibit 1 low i driven by the slave device to which the current transaction was addressed. indicates that the current slave does not support burst mode. o driven by the mpc565/mpc566 when the slave device is controlled by the on-chip memory controller. the mpc565/mpc566 also asserts bi for any external master burst access to internal mpc565/mpc566 memory space. arbitration br bus request 1 low i when the internal arbiter is enabled, br assertion indicates that an external master is requesting the bus. o driven by the mpc565/mpc566 when the internal arbiter is disabled and the chip is not parked. bg bus grant 1 low o when the internal arbiter is enabled, the mpc565/mpc566 asserts this signal to indicate that an external master may assume ownership of the bus and begin a bus transaction. the bg signal should be qualified by the master requesting the bus in order to ensure it is the bus owner: qualified bus grant = bg &~bb i when the internal arbiter is disabled, bg is sampled and properly qualified by the mpc565/mpc566 when an external bus transaction is to be executed by the chip. bb bus busy 1 low o when the internal arbiter is enabled, the mpc565/mpc566 asserts this signal to indicate that it is the current owner of the bus. when the internal arbiter is disabled, the mpc565/mpc566 asserts this signal after the external arbiter has granted the ownership of the bus to the chip and it is ready to start the transaction. i when the internal arbiter is enabled, the mpc565/mpc566 samples this signal to get indication of when the external master ended its bus tenure (bb negated). when the internal arbiter is disabled, the bb is sampledtoproperlyqualifythebg line when an external bus transaction is to be executed by the chip. retry 1 low i in the case of regular transaction, this signal is driven by the slave device to indicate that the mpc565/mpc566 must relinquish the ownership of thebusandretrythecycle. o when an external master owns the bus and the internal mpc565/mpc566 bus initiates access to the external bus at the same time, this signal is used to cause the external master to relinquish the bus for one clock to solve the contention. table 9-1. mpc565/mpc566 siu signals (continued) signal name pins active i/o description 9-8 mpc565/mpc566 reference manual motorola bus operations 9.5 bus operations this section provides a functional description of the system bus, the signals that control it, and the bus cycles provided for data transfer operations. it also describes the error conditions, bus arbitration, and reset operation. the mpc565/mpc566 generates a system clock output (clkout). this output sets the frequency of operation for the bus interface directly. internally, the mpc565/mpc566 uses a phase-lock loop (pll) circuit to generate a master clock for all of the mpc565/mpc566 circuitry (including the bus interface) which is phase-locked to the clkout output signal. all signals for the mpc565/mpc566 bus interface are specified with respect to the rising edge of the external clkout and are guaranteed to be sampled as inputs or changed as outputs with respect to that edge. since the same clock edge is referenced for driving or sampling the bus signals, the possibility of clock skew could exist between various modules in a system due to routing or the use of multiple clock lines. it is the responsibility of the system to handle any such clock skew problems that could occur. 9.5.1 basic transfer protocol the basic transfer protocol defines the sequence of actions that must occur on the mpc565/mpc566 bus to perform a complete bus transaction. a simplified scheme of the basic transfer protocol is illustrated in figure 9-3. figure 9-3. basic transfer protocol the basic transfer protocol provides for an arbitration phase and an address and data transfer phase. the address phase specifies the address for the transaction and the transfer attributes that describe the transaction. the data phase performs the transfer of data (if any is to be transferred). the data phase may transfer a single beat of data (four bytes or less) for nonburst operations, a 4-beat burst of data (4 x 4 bytes), an 8-beat burst of data (8 x 2 bytes) or a 16-beat burst of data (16 x 1 bytes). 9.5.2 single beat transfer during the data transfer phase, the data is transferred from master to slave (in write cycles) or from slave to master (on read cycles). during a write cycle, the master drives the data as soon as it can, but never earlier than the cycle following the address transfer phase. the master has to take into consideration the ?one dead clock cycle? switching between drivers to avoid electrical contentions. the arbitration address transfer data transfer termination motorola chapter 9. external bus interface 9-9 bus operations master can stop driving the data bus as soon as it samples the ta line asserted on the rising edge of the clkout. during a read cycle, the master accepts the data bus contents as valid at the rising edge of the clkout in which the ta signal is sampled/asserted. 9.5.2.1 single beat read flow the basic read cycle begins with bus arbitration, followed by the address transfer, then the data transfer. the handshakes illustrated in the following flow and timing figures (figure 9-4, figure 9-5, and figure 9-6) are applicable to the fixed transaction protocol. figure 9-4. basic flow diagram of a single beat read cycle 3. assert bus busy (bb ) if no other master is driving bus 4. assert transfer start (ts ) 5. drive address and attributes 1. receive address 2. return data 3. assert transfer acknowledge (ta ) 1. receive data slave master 2. receive bus grant (bg ) from arbiter 1. request bus (br ) 9-10 mpc565/mpc566 reference manual motorola bus operations figure 9-5. single beat read cycle ? basic timing ? zero wait states clkout addr[0:31] ts br bg bb data ta rd/wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is valid burst ,bdip tsiz[0:1] o o o o o motorola chapter 9. external bus interface 9-11 bus operations figure 9-6. single beat read cycle ? basic timing ? one wait state 9.5.2.2 single beat write flow the basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer. the handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed transaction protocol. clkout addr[0:31] ts br bg bb data ta rd/wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is valid burst ,bdip tsiz[0:1] wait state o o o o 9-12 mpc565/mpc566 reference manual motorola bus operations figure 9-7. basic flow diagram of a single beat write cycle master slave 1. request bus (br ) 2. receive bus grant (bg )fromarbiter 3. assert bus busy (bb ) if no other master is driving bus 4. assert transfer start (ts ) 5. drive address and attributes 1. drive data 1. assert transfer acknowledge (ta ) 1. interrupt data driving motorola chapter 9. external bus interface 9-13 bus operations figure 9-8. single beat basic write cycle timing ? zero wait states clkout addr[0:31] ts br bg bb data ta rd/wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is sampled by slave burst ,bdip tsiz[0:1] o o o o o 9-14 mpc565/mpc566 reference manual motorola bus operations figure 9-9. single beat basic write cycle timing ? one wait state 9.5.2.3 single beat flow with small port size the general case of single beat transfers assumes that the external memory has a 32-bit port size. the mpc565/mpc566 provides an effective mechanism for interfacing with 16-bit and 8-bit port size memories, allowing transfers to these devices when they are controlled by the internal memory controller. in this case, the mpc565/mpc566 attempts to initiate a transfer as in the normal case. if the bus interface receives a small port size (16 or 8 bits) indication before the transfer acknowledge to the first beat (through the internal memory controller), the mcu initiates successive transactions until the completion of the data transfer. note that all the transactions initiated to complete the data transfer are considered to be part of an atomic clkout addr[0:31] ts br bg bb data ta rd/wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is sampled burst ,bdip tsiz[0:1] wait state o o o o o motorola chapter 9. external bus interface 9-15 bus operations transaction, so the mcu does not allow other unrelated master accesses or bus arbitration to intervene between the transfers. if any of the transactions except the first is re-tried during an access to a small port, then a machine-check exception is generated to the rcpu. 1. for an illustration of device connections on the data bus, see figure 9-23. figure 9-10. single beat 32-bit data write cycle timing ? 16-bit port size 9.5.3 data bus pre-discharge mode pre-discharge mode is provided for applications that use 3.3-v/5-v external memories while the mpc565/mpc566 data bus pads are optimized to 2.6-v memories, and cannot tolerate more than 3.1 v. when connecting 3.3-v devices to the ebus, and performing clkout addr[0:1] ts br bg bb data 1 ta rd/wr burst ,bdip tsiz[0:1] 00 10 addr addr + 2 abcdefgh efghefgh sts 9-16 mpc565/mpc566 reference manual motorola bus operations read and write operations, this mode should be invoked in order to avoid long term reliability issues of the data pads. when pdmcr2[predis_en] bit is set, the mpc565/mpc566 will discharge the bus during the address phase of any write cycle prior to the data phase. the data bus will be discharged from up to 5 v to a level which is suitable to the low voltage drivers. in most cases, the orx[ehtr] bit of the relevant memory bank, should be set along with the predis_en bit in order to reserve sufficient time for the memory to tri-state the bus before the bus discharge is initiated. ehtr has a slight performance reduction impact since it adds a clock gap between some read and write cycles. note ehtr also adds one idle clock for two consecutive read cycles from different memory banks. 9.5.3.1 operating conditions pre-discharge mode should be enabled in the following cases: when external devices can charge the data bus to a higher voltage level than 3.1 volts when one of the following occurs: ? the mpc565/mpc566 uses write accesses to any external memory ? data show cycles are enabled ? instruction show cycles are enabled in code compression mode (mpc566 only) note in the case of code compression program tracking (3rd case above), the predis_en bit should only be set when program tracking is not required since pre-discharge mode overwrites the compression show cycles data. the user should not set predis_en bit when program tracking is required on development system, and set predis_en bit on the production version. ehtr can always be set to keep the same system performance during development, and production phases. 9.5.3.2 initialization sequence systems that require pre-discharge operation should include the following steps: execute boot sequence motorola chapter 9. external bus interface 9-17 bus operations set ehtr bit in all relevant memory banks during the memory controller initialization phase (configure orx, and brx) if it is required to extend the time between read cycles, and pre-discharge phase of write cycles. set predis_en in pdmcr2 register start to write data to external devices refer to section section 2.3, ?pad module configuration register (pdmcr2)?, and section 10.9.4, ?memory controller option registers (or[0] ? or[3])? for more informationonpredis_en,andehtrconfigurationbits. figure 9-11. read cycle followed by write cycle when pre-discharge mode is enabled, and ehtr bit is set 9.5.4 burst transfer the mpc565/mpc566 uses non-wrapping burst transfers to access operands of up to 32 bytes (eight words). a non-wrapping burst access stops accessing the external device when the word address is modulo four/eight. burst configuration is determined by the value of clkout data ta rd/wr pre-discharge address ts read cycle write cycle write data oe read data ehtr provides 1 clock gap to tri-state data bus to low voltage 9-18 mpc565/mpc566 reference manual motorola bus operations burst_en in the siumcr register. see chapter 5, ?unified system interface unit (usiu)? for further details. the mpc565/mpc566 begins the access by supplying a starting address that points to one of the words in the array and requires the memory to sequentially drive or sample each word on the data bus. the selected slave device must internally increment addr[28] and addr[29] (and addr[30]in the case of a 16-bit port slave device, and also addr[31] in the case of an 8-bit port slave device) of the supplied address for each transfer, causing the address to reach a four/eight word boundary, and then stop. the address and transfer attributes supplied by the mpc565/mpc566 remain stable during the transfers. the selected device terminates each transfer by driving or sampling the word on the data bus and asserting ta . the mpc565/mpc566 also supports burst-inhibited transfers for slave devices that are unable to support bursting. for this type of bus cycle, the selected slave device supplies or samples the first word the mpc565/mpc566 points to and asserts the burst-inhibit signal with ta for the first transfer of the burst access. the mpc565/mpc566 responds by terminating the burst and accessing the remainder of the 16-byte block. these remaining accesses use up to three read/write bus cycles (each one for a word) in the case of a 32-bit port width slave, up to seven read/write bus cycles in the case of a 16-bit port width slave, or up to fifteen read/write bus cycles in the case of a 8-bit port width slave. the general case of burst transfers assumes that the external memory has a 32-bit port size. the mpc565/mpc566 provides an effective mechanism for interfacing with 16-bit and 8-bit port size memories, allowing bursts transfers to these devices when they are controlled by the internal memory controller. in this case, the mpc565/mpc566 attempts to initiate a burst transfer as in the normal case. if the memory controller signals to the bus interface that the external device has a small port size (8 or 16 bits), and if the burst is accepted, the bus interface completes a burst of 16 or 8 beats respectively for four words. eight words requires 32 or 16 beats. each beat of the burst transfers only one or two bytes effectively. note that this burst of 8 or 16 beats is considered an atomic transaction, so the mpc565/mpc566 does not allow other unrelated master accesses or bus arbitration to intervene between the transfers. 9.5.5 burst mechanism in addition to the standard bus signals, the mpc565/mpc566 burst mechanism uses the following signals: the burst signal indicates that the cycle is a burst cycle. the burst data in progress (bdip ) signal indicates the duration of the burst data. the burst inhibit (bi ) signal indicates whether the slave is burstable. at the start of the burst transfer, the master drives the address, the address attributes, and the burst signal to indicate that a burst transfer is being initiated, and asserts ts .ifthe motorola chapter 9. external bus interface 9-19 bus operations slave is burstable, it negates the burst-inhibit (bi ) signal. if the slave cannot burst, it asserts bi . for additional details, refer to section 10.2.5, ?burst support.? during the data phase of a burst-write cycle, the master drives the data. it also asserts bdip if it intends to drive the data beat following the current data beat. when the slave has received the data, it asserts ta to indicate to the master that it is ready for the next data transfer. the master again drives the next data and asserts or negates the bdip signal. if the master does not intend to drive another data beat following the current one, it negates bdip to indicate to the slave that the next data beat transfer is the last data of the burst-write transfer. bdip has two basic timings: normal and late (see figure 9-14 and figure 9-15). in the late timing mode, assertion of bdip is delayed by the number of wait states in the first data beat. this implies that for zero-wait-state cycles, bdip assertion time is identical in normal and late modes. cycles with late bdip generation can occur only during cycles for which the memory controller generates ta internally. refer to chapter 10, ?memory controller? for more information. in the mpc565/mpc566, no internal master initiates write bursts. the mpc565/mpc566 is designed to perform this kind of transaction in order to support an external master that is using the memory controller services. refer to section 10.8, ?memory controller external master support.? during the data phase of a burst-read cycle, the master receives data from the addressed slave. if the master needs more than one data beat, it asserts bdip . upon receiving the second-to-last data beat, the master negates bdip . the slave stops driving new data after it receives the negation of the bdip signal at the rising edge of the clock. burst inputs (reads) in the mpc565/mpc566 are used only for instruction cycles. data load cycles are not supported. figures 9-12 through 9-21 are examples of various burst cycles, including illustrations of burst-read and burst-write cycles for both the 16- and 32-bit port sizes. 9-20 mpc565/mpc566 reference manual motorola bus operations figure 9-12. basic flow diagram of a burst-read cycle master slave 1. request bus (br ) 2. receive bus grant (bg ) from arbiter 3. assert bus busy (bb ) if no other master is driving 4. assert transfer start (ts ) 5. drive address and attributes receive address return data assert transfer acknowledge (ta ) receive data 6. drive burst asserted assert bdip bdip asserted yes return data assert transfer acknowledge (ta ) receive data bdip asserted yes return data assert transfer acknowledge (ta ) receive data bdip asserted yes return data assert transfer acknowledge (ta ) receive data bdip asserted yes negate burst data in progress (bdip ) no drive last data &assertta no drive last data &assertta no drive last data &assertta no drive last data &assertta addr[28:29] mod 4 =? assert bdip assert bdip =2 =1 =3 =0 =4 motorola chapter 9. external bus interface 9-21 bus operations figure 9-13. burst-read cycle ? 32-bit port size ? zero wait state clkout addr[0:31] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip data data data data is valid is valid is valid is valid last beat expects another data 00 addr[28:31] = 0000 o o o o o o oo no data expected 9-22 mpc565/mpc566 reference manual motorola bus operations figure 9-14. burst-read cycle ? 32-bit port size ? one wait state clkout addr[0:31] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip data data data data is valid is valid is valid is valid last beat expects another data 00 wait state addr[28:31] = 0000 normal late o o o o o o o o no data expected motorola chapter 9. external bus interface 9-23 bus operations figure 9-15. burst-read cycle ? 32-bit port size ? wait states between beats clkout addr[0:31] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip data data data data is valid is valid is valid is valid last beat expects another data 00 wait state addr[28:31] = 0000 normal or late o o o o o o o o no data expected 9-24 mpc565/mpc566 reference manual motorola bus operations figure 9-16. burst-read cycle ? 16-bit port size clkout addr[0:31] ts br bg bb data[0:15] ta rd/wr burst tsiz[0:1] bdip 00 addr[28:31] = 0000 motorola chapter 9. external bus interface 9-25 bus operations figure 9-17. basic flow diagram of a burst-write cycle external master slave 1. request bus (br ) 2. receive bus grant (bg ) from arbiter 3. assert bus busy (bb ) if no other master is driving 4. assert transfer start (ts ) 5. drive address and attributes receive address sample data assert transfer acknowledge (ta ) drive data 6. drive burst asserted assert bdip bdip asserted yes sample data assert transfer acknowledge (ta ) drive data bdip asserted yes sample data assert transfer acknowledge (ta ) drive data bdip asserted yes sample data assert transfer acknowledge (ta ) stop driving data bdip asserted yes negate burst data in progress (bdip ) no don?t sample next data no don?t sample next data no don?t sample next data no don?t sample next data addr[28:29] mod 4 =? assert bdip assert bdip =2 =1 =3 =0 drive data 7. mts asserted (from mpc565/mpc566 9-26 mpc565/mpc566 reference manual motorola bus operations 1 from external master figure 9-18. burst-write cycle, 32-bit port size, zero wait states (only for external master memory controller service support) addr[0:31] mts br 1 bg 1 bb 1 rd/wr 1 burst 1 tsiz[0:1] bdip 1 data data data data is sampled is sampled is sampled is sampled last beat will drive another data addr[28:29] = 00 o o o o o o o o clkout data ta 00 ts 1 no data expected motorola chapter 9. external bus interface 9-27 bus operations 1 burst and bdip will be asserted for one cycle if the rcpu core requests a burst, but the usiu splits it into a sequence of normal cycles. figure 9-19. burst-inhibit read cycle, 32-bit port size (emulated burst) clkout addr[0:27] ts br bg bb data ta rd/wr burst 1 tsiz[0:1] bdip 1 00 bi addr[28:29] addr[30:31] 0 12 3 9-28 mpc565/mpc566 reference manual motorola bus operations figure 9-20. non-wrap burst with three beats clkout addr(0:29) ts br bg bb data ta rd/wr burst tsiz[0:1] bdip 00 bi addr[30:31] n (n modulo 4 = 1) expects another data o o motorola chapter 9. external bus interface 9-29 bus operations figure 9-21. non-wrap burst with one data beat clkout addr[0:29] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip data is sampled first and last beat 00 addr[30:31] 00 n (n modulo 4 = 3) is never asserted o 9-30 mpc565/mpc566 reference manual motorola bus operations 9.5.6 alignment and packaging of transfers the mpc565/mpc566 external bus requires natural address alignment: byte accesses allow any address alignment half-word accesses require address bit 31 to equal zero word accesses require address bits 30 ? 31 to equal zero burst accesses require address bits 30 ? 31 to equal zero the mpc565/mpc566 performs operand transfers through its 32-bit data port. if the transfer is controlled by the internal memory controller, the mpc565/mpc566 can support 8- and 16-bit data port sizes. the bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. a 32-bit port resides on data[0:31], a 16-bit port must reside on data[0:15], and an 8-bit port must reside on data[0:7]. the mpc565/mpc566 always tries to transfer the maximum amount of data on all bus cycles. for a word operation, it always assumes that the port is 32 bits wide when beginning the bus cycle. infigure 9-22, figure 9-23 table 9-2, and table 9-3, the following conventions are used: op0 is the most-significant byte of a word operand and op3 is the least-significant byte. the two bytes of a half-word operand are either op0 (most-significant) and op1 or op2 (most-significant) and op3, depending on the address of the access. the single byte of a byte-length operand is op0, op1, op2, or op3, depending on the address of the access. figure 9-22. internal operand representation figure 9-23 illustrates the device connections on the data bus. op0 op1 op2 031 word half-word byte op0 op1 op2 op3 op0 op1 op2 op3 op3 motorola chapter 9. external bus interface 9-31 bus operations figure 9-23. interface to different port size devices table 9-2 lists the bytes required on the data bus for read cycles. note: ??? denotes a byte not required during that read cycle. table 9-2. data bus requirements for read cycles transfer size tsize [0:1] address 32-bit port size 16-bit port size 8-bit port size addr [30:31] data [0:7] data [8:15] data [16:23] data [24:31] data [0:7] data [8:15] data [0:7] byte 01 00 op0 ? ? ? op0 ? op0 01 01 ?op1 ? ? ?op1op1 01 10 ? ? op2 ? op2 ? op2 01 11 ? ? ? op3 ? op3 op3 half-word 10 00 op0 op1 ? ? op0 op1 op0 10 10 ? ? op2 op3 op2 op3 op2 word 00 00 op0 op1 op2 op3 op0 op1 op0 031 32-bit port size op0 op1 op2 op3 op0 op1 op2 op3 op0 op1 op2 op3 op0 op1 op2 op3 16-bit port size 8-bit port size data[0:7] data[8:15] data[16:23] data[24:31] interface output register 9-32 mpc565/mpc566 reference manual motorola bus operations table 9-3 lists the patterns of the data transfer for write cycles when the mpc565/mpc566 initiates an access. note: ??? denotes a byte not driven during that write cycle. 9.5.7 arbitration phase the external bus design provides for a single bus master at any one time, either the mpc565/mpc566 or an external device. one or more of the external devices on the bus can have the capability of becoming bus master for the external bus. bus arbitration may be handled either by an external central bus arbiter or by the internal on-chip arbiter. in the latter case, the system is optimized for one external bus master besides the mpc565/mpc566. the arbitration configuration (external or internal) is set at system reset. each bus master must have bus request (br ), bus grant (bg ), and bus busy (bb ) signals. the device that needs the bus asserts br . the device then waits for the arbiter to assert bg . in addition, the new master must look at bb to ensure that no other master is driving the bus before it can assert bb to assume ownership of the bus. any time the arbiter has taken the bus grant away from the master and the master wants to execute a new cycle, the master must re-arbitrate before a new cycle can be executed. the mpc565/mpc566, however, guarantees data coherency for access to a small port size and for decomposed bursts. this means that the mpc565/mpc566 will not release the bus before the completion of the transactions that are considered atomic. figure 9-24 describes the basic protocol for bus arbitration. table 9-3. data bus contents for write cycles transfer size tsize[0:1] address external data bus pattern addr [30:31] data [0:7] data [8:15] data [16:23] data [24:31] byte 01 00 op0 ? ? ? 01 01 op1 op1 ? ? 01 10 op2 ? op2 ? 01 11 op3 op3 ? op3 half-word 10 00 op0 op1 ? ? 10 10 op2 op3 op2 op3 word 00 00 op0 op1 op2 op3 motorola chapter 9. external bus interface 9-33 bus operations figure 9-24. bus arbitration flowchart 9.5.7.1 bus request the potential bus master asserts br to request bus mastership. br should be negated as soon as the bus is granted, the bus is not busy, and the new master can drive the bus. if more requests are pending, the master can keep asserting its bus request as long as needed. when configured for external central arbitration, the mpc565/mpc566 drives this signal when it requires bus mastership. when the internal on-chip arbiter is used, this signal is an input to the internal arbiter and should be driven by the external bus master. 9.5.7.2 bus grant the arbiter asserts bg to indicate that the bus is granted to the requesting device. this signal can be negated following the negation of br or kept asserted for the current master to park the bus. when configured for external central arbitration, bg is an input signal to the mpc565/mpc566 from the external arbiter. when the internal on-chip arbiter is used, this signal is an output from the internal arbiter to the external bus master. requesting device arbiter request the bus 1. assert br terminate arbitration 1. negate bg (or keep asserted to park 1. wait for bb to be negated. 3. negate br bus master operate as bus master 1. perform data transfer release bus mastership 1. negate bb acknowledge bus mastership 2. assert bb to become next master grant bus arbitration 1. assert bg 9-34 mpc565/mpc566 reference manual motorola bus operations 9.5.7.3 bus busy bb assertion indicates that the current bus master is using the bus. new masters should not begin transfer until this signal is negated. the bus owner should not relinquish or negate this signal until the transfer is complete. to avoid contention on the bb line, the master should three-state this signal when it gets a logical one value. this requires the connection of an external pull-up resistor to ensure that a master that acquires the bus is able to recognize the bb line negated, regardless of how many cycles have passed since the previous master relinquished the bus. refer to figure 9-25. figure 9-25. master signals basic connection external bus slave 2 master ts bb mpc565/mpc566 motorola chapter 9. external bus interface 9-35 bus operations figure 9-26. bus arbitration timing diagram 9.5.7.4 internal bus arbiter the mpc565/mpc566 can be configured at system reset to use the internal bus arbiter. in this case, the mpc565/mpc566 will be parked on the bus. the parking feature allows the mpc565/mpc566 to skip the bus request phase, and if bb is negated, assert bb and initiate the transaction without waiting for bg from the arbiter. the priority of the external device relative to the internal mpc565/mpc566 bus masters is programmed in the siu module configuration register. if the external device requests the bus and the mpc565/mpc566 does not require it, or if the external device has higher priority than the current internal bus master, the mpc565/mpc566 grants the bus to the external device. table 9-4 describes the priority mechanism used by the internal arbiter. clkout br0 bg1 addr bg0 br1 master 0 ?turns on? and drives signals master 0 negates bb and ?turns off? (three-state controls) bb ts ta master 1 ?turns on? and drives signals &attributes 9-36 mpc565/mpc566 reference manual motorola bus operations figure 9-27 illustrates the internal finite-state machine that implements the arbiter protocol. table 9-4. priority between internal and external masters over external bus 1 1 external master will be granted external bus ownership if earp is greater than the internal access priority. type direction priority parked access 2 2 parked access is instruction or data access from the rcpu which is initiated on the internal bus without requesting it first in order to improve performance. internal motorola chapter 9. external bus interface 9-37 bus operations figure 9-27. internal bus arbitration state machine 9.5.8 address transfer phase signals address transfer phase signals include the following: transfer start address bus transfer attributes idle bg =1 bb =t.s external bg =0 external master br = 0 external master release bus bg =1 bb =t.s bb = t.s bb =0 bg =1 bb =0 bb = 1 bb =1,br = 1 br =0 requests bus br =1 external device with higher priority than the current internal bus master requests the bus internal master with higher priority than the external device requires the bus mcu needs no longer the bus needs the bus still needs the bus wait owner owner bus mpc565/mpc566 mpc565/mpc566 mpc565/mpc566 mpc565/mpc566 mpc565/mpc566 9-38 mpc565/mpc566 reference manual motorola bus operations transfer attributes signals include rd/wr ,burst , tsiz[0:1], at[0:3], sts ,andbdip . with the exception of the bdip , these signals are available at the same time as the address bus. 9.5.8.1 transfer start this signal (ts ) indicates the beginning of a transaction on the bus addressing a slave device. this signal should be asserted by a master only after the ownership of the bus was granted by the arbitration protocol. this signal is asserted for the first cycle of the transaction only and is negated in successive clock cycles until the end of the transaction. the master should three-state this signal when it relinquishes the bus to avoid contention between two or more masters in this line. this situation indicates that an external pull-up resistor should be connected to the ts signal to avoid having a slave recognize this signal as asserted when no master drives it. refer to figure 9-25. 9.5.8.2 address bus the address bus consists of 32 bits, with addr0 the most significant bit and addr31 the least significant bit. only 24 bits (addr[8:31]) are available external to the mpc565. the bus is byte-addressable, so each address can address one or more bytes. the address and its attributes are driven on the bus with the transfer start signal and kept valid until the bus master receives the transfer acknowledge signal from the slave. to distinguish the individual byte, the slave device must observe the tsiz signals. 9.5.8.3 read/write a high value on the rd/wr line indicates a read access. a low value indicates a write access. 9.5.8.4 burst indicator burst is driven by the bus master at the beginning of the bus cycle along with the address to indicate that the transfer is a burst transfer. the mpc565/mpc566 supports a non-wrapping, 8-beat maximum (with 32-bit port), critical word first burst type. the maximum burst size is 32 bytes. for a 16-bit port, the burst includes 16 beats. for an 8-bit port, the burst includes 32 beats at most. note eight- and 16-bit ports must be controlled by the memory controller. the actual size of the burst is determined by the address of the starting word of the burst. refer to table 9-5 and table 9-6. motorola chapter 9. external bus interface 9-39 bus operations 9.5.8.5 transfer size the transfer size signals (tsiz[0:1]) indicate the size of the requested data transfer. during each transfer, the tsiz signals indicate how many bytes are remaining to be transferred by the transaction. the tsiz signals can be used with burst and addr[30:31] to determine which byte lanes of the data bus are involved in the transfer. for non-burst transfers, the tsiz signals specify the number of bytes starting from the byte location addressed by addr[30:31]. in burst transfers, the value of tsiz is always 00. 9.5.8.6 address types the address type (at[0:3]), program trace (ptr ), and reservation transfer (rsv ) signals are outputs that indicate one of 16 address types. these types are designated as either a normal or alternate master cycle, user or supervisor, and instruction or data type. the address type signals are valid at the rising edge of the clock in which the special transfer start (sts ) signal is asserted. a special use of the ptr and rsv signals is for the reservation protocol described in section 9.5.10, ?storage reservation.? refer to section 9.5.14, ?show cycle transactions? for information on show cycles. table 9-7 summarizes the pins used to define the address type. table 9-8 lists all the definitions achieved by combining these pins. table 9-5. burst length and order starting address addr[28:29] burst order (assuming 32-bit port size) burst length in words (beats) burst length in bytes comments 00 word 0 9-40 mpc565/mpc566 reference manual motorola bus operations table 9-7. address type pins pin function sts 0 special transfer 1 normal transfer ts 0 start of transfer 1notransfer at[0] must equal zero on mpc565/mpc566 at[1] 0 supervisor mode 1usermode at[2] 0 instruction 1data at[3] reservation/program trace ptr 0 program trace 1 no program trace rsv 0 reservation data 1 no reservation motorola chapter 9. external bus interface 9-41 bus operations : 9.5.8.7 burst data in progress this signal is sent from the master to the slave to indicate that there is a data beat following the current data beat. the master uses this signal to give the slave advance warning of the remaining data in the burst. bdip can also be used to terminate the burst cycle early. refer to section 9.5.4, ?burst transfer? and section 9.5.5, ?burst mechanism? for more information. refer to section 10.9.3, ?memory controller base registers (br[0] ? br[3])? for memory controller bdip options. table 9-8. address types definition sts ts at[0] at[1] at[2] at[3] ptr rsv address space definitions 1xxxxx11notransfer 00 1 1 cases in which both ts and sts are asserted indicate normal cycles with the show cycle attribute. 000001rcpu,normalinstruction,programtrace,supervisormode 1 1 1 rcpu, normal instruction, supervisor mode 1 0 1 0 rcpu, reservation data, supervisor mode 1 1 1 rcpu, normal data, supervisor mode 1 0 0 0 1 rcpu, normal instruction, program trace, user mode 1 1 1 rcpu, normal instruction, user mode 1 0 1 0 rcpu, reservation data, user mode 1 1 1 rcpu, normal data, user mode 1???11reserved 1000001rcpu,showcycleaddressinstruction,programtrace, supervisor mode 1 1 1 rcpu, show cycle address instruction, supervisor mode 1 0 1 0 rcpu, reservation show cycle data, supervisor mode 1 1 1 rcpu, show cycle data, supervisor mode 1 0 0 0 1 rcpu, show cycle address instruction, program trace, user mode 1 1 1 rcpu, show cycle address instruction, user mode 1 0 1 0 rcpu, reservation show cycle data, user mode 1 1 1 rcpu, show cycle data, user mode 1???11reserved 9-42 mpc565/mpc566 reference manual motorola bus operations 9.5.9 termination signals the ebi uses three termination signals: transfer acknowledge (ta ) burst inhibit (bi ) transfer error acknowledge (tea ) 9.5.9.1 transfer acknowledge transfer acknowledge (ta ) indicates normal completion of the bus transfer. during a burst cycle, the slave asserts this signal with every data beat returned or accepted. 9.5.9.2 burst inhibit a slave sends the bi signal to the master to indicate that the addressed device does not have burst capability. if this signal is asserted, the master must transfer in multiple cycles and increment the address for the slave to complete the burst transfer. for a system that does not use the burst mode at all, this signal can be tied low permanently. refer to section 10.9.3, ?memory controller base registers (br[0] ? br[3])? for bi options. 9.5.9.3 transfer error acknowledge the tea signal terminates a bus cycle under one or more bus error conditions. the current bus cycle must be aborted. this signal overrides any other cycle termination signals, such as transfer acknowledge. 9.5.9.4 termination signals protocol the transfer protocol was defined to avoid electrical contention on lines that can be driven by various sources. to this end, a slave must not drive signals associated with the data transfer until the address phase is completed and it recognizes the address as its own. the slave must disconnect from signals immediately after it has acknowledged the cycle and no later than the termination of the next address phase cycle. this means that the termination signals must be connected to power through a pull-up resistor to avoid the situation in which a master samples an undefined value in any of these signals when no real slave is addressed. refer to figure 9-28 and figure 9-29. motorola chapter 9. external bus interface 9-43 bus operations figure 9-28. termination signals protocol basic connection figure 9-29. termination signals protocol timing diagram external bus mcu slave 2 slave 1 acknowledge signals ta tea clkout addr[0:31] ts ta ,bi ,tea rd/wr tsiz[0:1] slave 1 slave 2 slave 1 allowedtodrive acknowledge signals slave 1 negates acknowledge signals and turns off slave 2 allowed to drive acknowledge signals slave 2 negates acknowledge signals and turns off data 9-44 mpc565/mpc566 reference manual motorola bus operations 9.5.10 storage reservation reservation occurs when a master loads data from memory. the memory location must not be overwritten until the master finishes processing the data and writing the results back to the reserved location. the mpc565/mpc566 storage reservation protocol supports a multi-level bus structure. for each local bus, storage reservation is handled by the local reservation logic. the protocol tries to optimize reservation cancellation such that an mpc500 processor is notified of storage reservation loss on a remote bus only when it has issued a conditional storeword (stwcx) cycle to that address. that is, the reservation loss indication comes as part of the stwcx cycle. this method avoids the need to have very fast storage reservation loss indication signals routed from every remote bus to every mpc500 master. the storage reservation protocol makes the following assumptions: each processor has, at most, one reservation flag lwarx sets the reservation flag lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and again sets the reservation flag stwcx by the same processor clears the reservation flag store by the same processor does not clear the reservation flag some other processor (or other mechanism) store to the same address as an existing reservation clears the reservation flag in case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage the reservation protocol for a single-level (local) bus is illustrated in figure 9-30. the protocol assumes that an external logic on the bus carries out the following functions: snoops accesses to all local bus slaves holds one reservation for each local master capable of storage reservations sets the reservation when that master issues a load and reserve request clears the reservation when some other master issues a store to the reservation address motorola chapter 9. external bus interface 9-45 bus operations figure 9-30. reservation on local bus the mpc565/mpc566 samples the cr line at the rising edge of clkout. when this signal is asserted, the reservation flag is reset (negated). the external bus interface (ebi) samples the logical value of the reservation flag prior to externally starting a bus cycle initiated by the rcpu stwcx instruction. if the reservation flag is set, the ebi begins with the bus cycle. if the reservation flag is reset, no bus cycle is initiated externally, and this situation is reported to the rcpu. the reservation protocol for a multi-level (local) bus is illustrated in figure 9-31. the system describes the situation in which the reserved location is sited in the remote bus. s r reservation logic external bus interface lwarx q enable external stwcx access cr external bus master bus addr[0:29] cr clkout at[0:3], rsv, r/w, ts mpc565/mpc566 9-46 mpc565/mpc566 reference manual motorola bus operations figure 9-31. reservation on multilevel bus hierarchy in this case, the bus interface block implements a reservation flag for the local bus master. the reservation flag is set by the bus interface when a load with reservation is issued by the local bus master and the reservation address is located on the remote bus. the flag is reset (negated) when an alternative master on the remote bus accesses the same location in a write cycle. if the mpc565/mpc566 begins a memory cycle to the previously reserved address (located in the remote bus) as a result of an stwcx instruction, the following two cases can occur: s r buses interface external bus interface q kr external bus (local bus) at[0:3], rsv, r/w, ts addr[0:29] remote bus a master in the remote bus write to the reserved location local master accesses with to remove bus address lwarx mpc565/mpc566 motorola chapter 9. external bus interface 9-47 bus operations if the reservation flag is set, the buses interface acknowledges the cycle in a normal way if the reservation flag is reset, the bus interface should assert the kr . however, the bus interface should not perform the remote bus write-access or abort it if the remote bus supports aborted cycles. in this case the failure of the stwcx instruction is reported to the rcpu. 9.5.11 bus exception control cycles the mpc565/mpc566 bus architecture requires assertion of ta from an external device to signal that the bus cycle is complete. ta is not asserted in the following cases: the external device does not respond various other application-dependent errors occur external circuitry can provide tea when no device responds by asserting ta within an appropriate period of time after the mpc565/mpc566 initiates the bus cycle (it can be the internal bus monitor). this allows the cycle to terminate and the processor to enter exception-processing for the error condition (each one of the internal masters causes an internal interrupt under this situation). to properly control termination of a bus cycle for a bus error, tea must be asserted at the same time or before ta is asserted. tea should be negated before the second rising edge after it was sampled as asserted to avoid the detection of an error for the next initiated bus cycle. tea is an open drain pin that allows the ?wired-or? of any different sources of error generation. 9.5.11.1 retrying a bus cycle when an external device asserts the retry signal during a bus cycle, the mpc565/mpc566 enters a sequence in which it terminates the current transaction, relinquishes the ownership of the bus, and retries the cycle using the same address, address attributes, and data (in the case of a write cycle). figure 9-32 illustrates the behavior of the mpc565/mpc566 when the retry signal is detected as a termination of a transfer. as seen in this figure, in the case when the internal arbiter is enabled, the mpc565/mpc566 negates bb and asserts bg in the clock cycle following the retry detection. this allows any external master to gain bus ownership. in the next clock cycle, a normal arbitration procedure occurs again. as shown in the figure, the external master did not use the bus, so the mpc565/mpc566 initiates a new transfer with the same address and attributes as before. in figure 9-33, the same situation is shown except that the mpc565/mpc566 is working with an external arbiter. in this case, in the clock cycle after the retry signal is detected asserted, br is negated together with bb . one clock cycle later, the normal arbitration procedure occurs again. 9-48 mpc565/mpc566 reference manual motorola bus operations figure 9-32. retry transfer timing ? internal arbiter clkout addr[0:31] ts br bg (output) bb data ta rd/wr burst tsiz[0:1] retry (input) addr addr allow external master to gain the bus o motorola chapter 9. external bus interface 9-49 bus operations figure 9-33. retry transfer timing ? external arbiter when the mpc565/mpc566 initiates a burst access, the bus interface recognizes the retry assertion as a retry termination only if it detects it before the first data beat was acknowledged by the slave device. when the retry signal is asserted as a termination signal on any data beat of the access after the first (being the first data beat acknowledged by a normal ta assertion), the mpc565/mpc566 recognizes retry as a transfer error acknowledge. clkout addr[0:31] ts br (output) bg bb data ta rd/wr burst tsiz[0:1] retry (input) addr addr allow external master to gain the bus o 9-50 mpc565/mpc566 reference manual motorola bus operations figure 9-34. retry on burst cycle if a burst access is acknowledged on its first beat with a normal ta but with the bi signal asserted, the following single-beat transfers initiated by the mpc565/mpc566 to complete the 16-byte transfer recognizes the retry signal assertion as a transfer error acknowledge. in the case in which a small port size causes the mpc565/mpc566 to break a bus transaction into several small transactions, terminating any transaction with retry causes a transfer error acknowledge. see section 9.5.2.3, ?single beat flow with small port size.? clkout addr[0:31] ts br bg (output) bb data ta rd/wr burst tsiz[0:1] retry addr addr allow external master to gain the bus bi if asserted will cause transfer error o motorola chapter 9. external bus interface 9-51 bus operations 9.5.11.2 termination signals protocol summary table 9-9 summarizes how the mpc565/mpc566 recognizes the termination signals provided by the slave device that is addressed by the initiated transfer. 9.5.12 bus operation in external master modes when an external master takes ownership of the external bus and the mpc565/mpc566 is programmed for external master mode operation, the external master can access the internal space of the mpc565/mpc566 (see section 6.2, ?external master modes?). in external master mode, the external master owns the bus, and the direction of most of the bus signals is inverted, relative to its direction when the mpc565/mpc566 owns the bus. the external master gets ownership of the bus and asserts ts in order to initiate an external master access. the access is directed to the internal bus only if the input address matches the internal address space. the access is terminated with one of the followings outputs: ta , tea , or retry . if the access completes successfully, the mpc565/mpc566 asserts ta , and the external master can proceed with another external master access or relinquish the bus. if an address or data error is detected internally, the mpc565/mpc566 asserts tea for one clock. tea should be negated before the second rising edge after it is sampled asserted in order to avoid the detection of an error for the next bus cycle initiated. tea is an open drain pin, and the negation timing depends on the attached pull-up. the mpc565/mpc566 asserts the retry signal for one clock in order to retry the external master access. if the address of the external access does not match the internal memory space, the internal memory controller can provide the chip-select and control signals for accesses that belong to one of the memory controller regions. this feature is explained in chapter 10, ?memory controller.? figure 9-35 and figure 9-36 illustrate the basic flow of read and write external master accesses. table 9-9. termination signals protocol tea ta retry action asserted x x transfer error termination negated asserted x normal transfer termination negated negated asserted retry transfer termination 9-52 mpc565/mpc566 reference manual motorola bus operations figure 9-35. basic flow of an external master read access external master 1. request bus (br ) 2. receives bus grant (bg ) from arbiter 3. asserts bus busy (bb ) if no other master is driving 4. assert transfer start (ts ) 1. receives address 1. returns data 1. asserts transfer acknowledge (ta ) 1. receives data address in internal memory map no yes asserts csx if in range memory controller mpc565/mpc566 5. drives address and attributes motorola chapter 9. external bus interface 9-53 bus operations figure 9-36. basic flow of an external master write access figure 9-37, figure 9-38 and figure 9-39 describe read and write cycles from an external master accessing internal space in the mpc565/mpc566. note the minimum number of wait states for such access is two clocks. the accesses in these figures are valid for both peripheral mode and slave mode. external master 1. asserts transfer acknowledge ( ta ) address in internal memory map no yes asserts csx if in range memory controller 1. drives data 1. receives address 1. receives data mpc565/mpc566 1. request bus (br ) 2. receives bus grant (bg ) from arbiter 3. asserts bus busy (bb ) if no other master is driving 4. assert transfer start (ts ) 5. drives address and attributes 9-54 mpc565/mpc566 reference manual motorola bus operations figure 9-37. peripheral mode: external master reads from mpc565/mpc566 ? two wait states clkout addr[0:31] ts (input) br (input) bg bb data ta (output) rd/wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is valid burst tsiz[0:1] minimum 2 wait states bdip use the internal arbiter o o o o o motorola chapter 9. external bus interface 9-55 bus operations figure 9-38. peripheral mode: external master writes to mpc565/mpc566 ? two wait states 9.5.13 contention resolution on external bus when the mpc565/mpc566 is in slave mode, external master access to the mpc565/mpc566 internal bus can be terminated with relinquish and retry in order to allow a pending internal-to-external access to be executed. the retry signal functions as an clkout addr[0:31] ts (input) br (input) bg bb data ta (output) rd/wr receive bus grant and bus busy negated assert bb , drive address and assert ts data is sampled burst tsiz[0:1] minimum 2 wait states bdip use the internal arbiter o o o o o 9-56 mpc565/mpc566 reference manual motorola bus operations output that signals the external master to release the bus ownership and retry the access after one clock. figure 9-39 describes the flow of an external master retried access. figure 9-40 shows the timing when an external access is retried and a pending internal-to-external access follows. motorola chapter 9. external bus interface 9-57 bus operations figure 9-39. flow of retry of external master read access external master 1. request bus (br ) 2. receives bus grant (bg ) from arbiter 3. asserts bus busy (bb ) if no other master is driving 4. assert transfer start (ts ) 5. drives address and attributes 1. receives address 1. returns data 1. asserts transfer acknowledge (ta ) 1. receives data address in internal memory map no yes asserts csx if in range memory controller 1. assert retry 1. release bus request (br ) for one clock and request bus (br )again 2. wait until bus busy negated (no other master is driving) 4. assert transfer start (ts ) 5. drives address and attributes 3. assert bus busy (bb ) mpc565/mpc566 9-58 mpc565/mpc566 reference manual motorola bus operations note: the delay for the internal to external cycle may be one clock or greater. figure 9-40. retry of external master access (internal arbiter) 9.5.14 show cycle transactions show cycles are representations of rcpu accesses of the to mpc565/mpc566 internal devices. these accesses are driven externally for emulation, visibility, and debugging purposes. a show cycle can have one address phase and one data phase, or just an address phase in the case of instruction show cycles. the cycle can be a write or a read access. the data for both the read and write accesses should be driven by the bus master. (this is different from normal bus read and write accesses.) the address and data of the show cycle clkout addr[0:31] ts br bg (output) bb data ta rd/wr burst tsiz[0:1] retry (output) addr (ext)ernal addr (internal) allow internal access to gain the bus o motorola chapter 9. external bus interface 9-59 bus operations must each be valid on the bus for one clock. the data phase must not require a transfer acknowledge to terminate the bus show cycle. show cycles are activated by properly setting the siumcr register bits. refer to section 6.14.1.1, ?siu module configuration register (siumcr).? construction visibility is controlled by the isct_ser bits in the ictrl register. refer to table 22-21. data visibility is controlled by the lshow bits of the l2u_mcr register. refer to table 11-7. in a burst show cycle only the first data beat is shown externally. refer to table 9-8 for show cycle transaction encodings. instruction show cycle bus transactions have the following characteristics (see figure 9-41): one clock cycle address phase only (in ?decompression on? mode part of ?compressed? address is driven on data lines together with address lines. external bus interface adds one clock delay between a read cycle and such show cycle. sts assertion only (no ta assertion) the ?compressed? address is driven on the external bus in following manner: addr[0:29] = the word ?base? address; data[0] = operating mode: ? 0 = decompression off mode; ? 1 = decompression on mode; data[1:4] = ?bit? pointer see chapter 4, ?burst buffer controller 2 module? for more details about decompression mode. 9-60 mpc565/mpc566 reference manual motorola bus operations i figure 9-41. instruction show cycle transaction both read and write data show cycles have the following characteristics: (see figure 9-42) two clock cycle duration address valid for two clock cycles data is valid only in the second clock cycle sts signal only is asserted (no ta or ts ) clkout addr[0:31] ptr bb (three-state) ta rd/wr burst tsiz[0:1] addr1 addr2 sts ts ?normal? non-show cycle bus transaction instruction show cycle bus transaction ?compressed? address on data lines data motorola chapter 9. external bus interface 9-61 bus operations figure 9-42. data show cycle transaction clkout addr[0:31] br (in) bg (out) bb data ta rd/wr burst tsiz[0:1] addr1 addr2 sts ts data1 data2 read data show cycle bus transaction write data show cycle bus transaction 9-62 mpc565/mpc566 reference manual motorola bus operations motorola chapter 10. memory controller 10-1 chapter 10 memory controller the memory controller generates interface signals to support a glueless interface to external memory and peripheral devices. it supports four regions, each with its own programmed attributes. the four regions are controlled by four chip-select pins. read and write strobes are also provided. the memory controller operates in parallel with the external bus interface to support external cycles. when an access to one of the memory regions is initiated, the memory controller takes ownership of the external signals and controls the access until its termination. refer to figure 10-1. figure 10-1. memory controller function within the usiu internal bus ebi bus memory controller u-bus interface external bus interface memory controller addr[0:31] data[0:31] control bus we[0:3]/be[0:3] oe cs[0:3] bus 10-2 mpc565/mpc566 reference manual motorola overview 10.1 overview the memory controller provides a glueless interface to external eprom, static ram (sram), flash (eeprom), and other peripherals. the general-purpose chip-selects are available on lines cs [0] through cs [3]. cs [0] also functions as the global (boot) chip-select for accessing the boot flash eeprom. the chip select allows zero to 30 wait states. figure 10-2 is a block diagram of the mpc565/mpc566 memory controller. figure 10-2. memory controller block diagram most memory controller features are common to all four banks. (for features unique to the cs [0] bank, refer to section 10.7, ?global (boot) chip-select operation.") a full 32-bit address decode for each memory bank is possible with 17 bits having address masking. the internal addresses [0:16], at[0:2] attributes wait state counter expired load cs [0:3] we /be [0:3] oe base register option register dual mapping base register (dmbr) dual mapping option register (dmor) base register 3 (br3) option register 3 (or3) 0(or0) 1(or1) 2(or2) 0(br0) 1(br1) 2(br2) region match logic general-purpose chip-select machine (gpcm) motorola chapter 10. memory controller 10-3 overview full 32-bit decode is available, even if all 32 address bits are not mpc565/mpc566 pins connected to the external device. each memory bank includes a variable block size of 32 kbytes, 64 kbytes and up to four gbytes. each memory bank can be selected for read-only or read/write operation. the access to a memory bank can be restricted to certain address type codes for system protection. the address type comparison occurs with a mask option as well. from 0 to 30 wait states can be programmed with ta generation. four write-enable and byte-enable signals (we /be [0:3]) are available for each byte that is written to memory. an output enable (oe ) signal is provided to eliminate external glue logic. a memory transfer start (mts ) strobe permits one master on a bus to access external memory through the chip selects on another. the memory controller functionality allows mpc565/mpc566-based systems to be built with little or no glue logic. a minimal system using no glue logic is shown in figure 10-3. in this example cs [0] is used for a 16-bit boot eprom and cs [1] is used for a 32-bit sram. the we /be [0:3] signals are used both to program the eprom and to enable write access to various bytes in the ram. figure 10-3. mpc565/mpc566 simple system configuration eprom address data[0:15] sram address ce we /be [0:3] data cs [1] oe address data cs [0] we /be [0:3] ce oe oe [0:15] [0:31] we /be [0:1] mpc565/mpc566 10-4 mpc565/mpc566 reference manual motorola memory controller architecture 10.2 memory controller architecture the memory controller consists of a basic machine that handles the memory access cycle: the general-purpose chip-select machine (gpcm). when any of the internal masters request a new access to external memory, the address of the transfer (with 17 bits having mask) and the address type (with three bits having mask) are compared to each one of the valid banks defined in the memory controller. refer to figure 10-4. figure 10-4. bank base address and match structure when a match is found on one of the memory banks, its attributes are selected for the functional operation of the external memory access: read-only or read/write operation number of wait states for a single memory access, and for any beat in a burst access burst-inhibit indication. internal burst requests are still possible during burst-inhibited cycles; the memory controller emulates the burst cycles port size of the external device note that if more than one region matches the internal address supplied, then the lowest region is selected to provide the attributes and the chip select. if the dual mapping region is matched, it has the highest priority (refer to section 10.5, ?dual mapping of the internal flash eeprom array"). m [0] m [1] m [2] m [3] m [4] m [5] m [6] m [7] rba [2] cmp cmp cmp cmp cmp cmp cmp cmp cmp cmp m[0:16] a[0:16] rba [1] rba [0] base address address mask match ............. m [16] .... cmp rba [3] rba [4] rba [16] rba [15] motorola chapter 10. memory controller 10-5 memory controller architecture 10.2.1 associated registers status bits for each memory bank are found in the memory control status register (mstat). the mstat reports write-protect violations for all the banks. each of the four memory banks has a base register (br) and an option register (or). the brx and orx registers contain the attributes specific to memory bank x. the base register contains a valid bit (v) that indicates the register information for that particular chip select is valid. 10.2.2 port size configuration the memory controller supports dynamic bus sizing. defined 8-bit ports can be accessed as odd or even bytes. defined 16-bit ports, when connected to data bus lines zero to 15, can be accessed as odd bytes, even bytes, or even half-words. defined 32-bit ports can be accessed as odd bytes, even bytes, odd half-words, even half-words, or words on word boundaries. the port size is specified by the ps bits in the base register. 10.2.3 write-protect configuration the wp bit in each base register can restrict write access to its range of addresses. any attempt to write this area results in the associated wper bit being set in the mstat. if an attempt to access an external device results in a write-protect violation, the memory controller considers the access to be no match. no chip-select line is asserted externally, and the memory controller does not terminate the cycle. the external bus interface generates a normal cycle on the external bus. since the memory controller does not acknowledge the cycle internally, the cycle may be terminated by external logic asserting ta or by the on-chip bus monitor asserting tea . 10.2.4 address and address space checking the base address is written to the br. the address mask bits for the address are written to the or. the address type access value, if desired, is written to the at bits in the br. the atm bits in the or can be used to mask this value. if address type checking is not desired, program the atm bits to zero. each time an external bus cycle access is requested, the address and address type are compared with each one of the banks. if a match is found, the attributes defined for this bank in its br and or are used to control the memory access. if a match is found in more than one bank, the lowest bank matched handles the memory access (e.g., bank zero is selected over bank one). 10-6 mpc565/mpc566 reference manual motorola memory controller architecture note when an external master accesses a slave on the bus, the internal at[0:2] lines reaching the memory controller are forced to 100. 10.2.5 burst support the memory controller supports burst accesses of external burstable memory. to enable bursts, clear the burst inhibit (bi) bit in the appropriate base register. burst support is for read only. bursts can be four or eight beats depending on the value of the burst_en bit in the siumcr register and the bl bit in the br register. that is, the memory controller executes up to eight one-word accesses, but when a modulo eight limit is reached, the burst is terminated (even if fewer than eight words have been accessed). when the siu initiates a burst access, if no match is found in any of the memory controller?s regions then a burst access is initiated to the external bus. the termination of each beat for this access is externally controlled. to support different types of memory devices, the memory controller supports two types of timing for the bdip signal: normal and late. note the bdip pin itself is controlled by the external bus interface logic. refer to figure 9-13 and figure 9-14 in chapter 9, ?external bus interface." if the memory controller is used to support an external master accessing an external device with bursts, the bdip input pin is used to indicate to the memory controller when the burst is terminated. for addition details, refer to section 9.5.4, ?burst transfer." 10.2.6 reduced data setup time in order to meet timing requirements when interfacing to external memories, the data setup time can be reduced. this mode can be selected by programming the brx registers. thus there is flexibility in how each region can be configured to operate. the operation mode will be determined dynamically according to a particular access type. this means that for a memory region with the reduced setup time mode enabled, the mode will automatically switch to disabled when there is no requirement for the reduced setup time, (e.g., a back to back load store access). for a new access with burst length more than 1, the operation mode will be automatically switched back to the reduced setup time mode. motorola chapter 10. memory controller 10-7 memory controller architecture reduced setup time can be selected via the sst bit in br[0 : 3]. see section 10.9.3, ?memory controller base registers (br[0] ? br[3])" for more details. the reduced setup time mode may or may not have a performance impact, depending on the properties of the memory. namely, there is always an additional empty cycle between two burst sequences. on the other hand, this cycle, under certain conditions, may be compensated for by reducing the number of cycles in initial data access and sequential burst beats. example: case 1: normal set-up time initial access : to derive the number of clocks required, divide by the system clock cycle time therefore four cycles are required burst access : the number of clocks required therefore two clocks are required this case is illustrated in figure 10-5. case 2: with short setup time initial access : enabling short setup time requires one clock cycle cpu specification memory device cycletimeat56mhz=17.9ns initialaccesstime=50ns short setup time = 2 ns burst access time = 13 ns normalsetuptime=6ns additional delay arising from on-board wires and clock skew between internal clock and clkout iinitial access time of memory data setup time of cpu delays ++ 5061 ++ = 57ns = 57 17.9 --------- - 3.18 = bburst access time of memory data setup time of cpu delays ++ 1361 ++ = 20ns = 20 17.9 ---------- = 1.11 = 10-8 mpc565/mpc566 reference manual motorola memory controller architecture burst access : =13+2+1=16ns the number of clocks required therefore one clock is required this case is illustrated in figure 10-6. conclusion : with normal setup time and a 4-beat burst, a 4-2-2-2 burst cycle is required which is reduced to a 4-1-1-1 burst cycle with a short setup time. short setup time creates a saving of three clock cycles with a 4-beat burst and can result in even better performance with an 8-beat burst, saving seven clock cycles. initial access time of memory data setup time of cpu delays ++ 5021 ++ = 53ns = 53 17.9 = = 2.96 + 1 (sst enable clock) = 3.96 are required therefore four clocks the number of clocks required burst access time of memory data setup time of cpu delays ++ 16 17.9 ---------- = 0.89 = motorola chapter 10. memory controller 10-9 memory controller architecture figure 10-5. a 4-2-2-2 burst read cycle (one wait state between bursts) clkout addr[0:31] ts br bg bb data ta rd/wr burst tsiz[0:1] bdip 00 addr[28:31] = 0b0000 normal late last beat no data expected expects another data 123456 78910 1st data is valid 3rd data is valid 4th data is valid 2nd data is valid 10-10 mpc565/mpc566 reference manual motorola memory controller architecture figure 10-6. 4 beat burst read with short setup time (zero wait state) note an extra clock cycle is required to enable short set-up time, resulting in a 4-1-1-1 cycle. lkout addr ts br bg bb data ta rd/wr burst siz[0:1] bdip 2nd data 3rd data 4th data is valid is valid is valid is valid last beat expects another data 00 addr[28:31] = 0000 no data expected 1234 567 1st data [0:31] motorola chapter 10. memory controller 10-11 chip-select timing 10.3 chip-select timing the general-purpose chip-select machine (gpcm) allows a glueless and flexible interface between the mpc565/mpc566mpc565/mpc566 and external sram, eprom, eeprom, rom peripherals. when an address and address type match the values programmed in the br and or for one of the memory controller banks, the attributes for the memory cycle are taken from the or and br registers. these attributes include the following fields: csnt, acs, scy, bscy, wp, trlx, bi, ps, and seta. table 10-1 summarizes the chip-select timing options. byte write and read-enable signals (we /be [0:3]) are available for each byte that is written to or read from memory. an output enable (oe ) signal is provided to eliminate external glue logic for read cycles. upon system reset, a global (boot) chip select is available. (refer to section 10.7, ?global (boot) chip-select operation? for more information on the global chip select.) this provides a boot rom chip select before the system is fully configured. note when a bank is configured for ta to be generated externally (seta bit is set) and the trlx is set, the memory controller requires the external device to provide at least one wait state before asserting ta to complete the transfer. in this case, the minimum transfer time is three clock cycles. table 10-1. timing attributes summary timing attribute bits/fields description access speed trlx the trlx (timing relaxed) bit determines strobe timing to be fast or relaxed. intercycle space time ehtr the ehtr (extended hold time on read accesses) bit is provided for devices that have long disconnect times from the data bus on read accesses. ehtr specifies whether the next cycle is delayed one clock cycle following a read cycle, to avoid data bus contentions. ehtr applies to all cycles following a read cycle except for another read cycle tothesameregion. synchronous or asynchronous device acs, csnt the acs (address-to-chip-select setup) and csnt (chip-select negation time) bits cause the timing of the strobes to be the same as the address bus timing, or cause the strobes to have setup and hold times relative to the address bus. wait states scy, bscy, seta, trlx from zero to 15 wait states can be programmed for any cycle that the memory controller generates. the transfer is then terminated internally. in simplest case, the cycle length equals (2 + scy) clock cycles, where scy represents the programmed number of wait states (cycle length in clocks). the number of wait states is doubled if the trlx bit is set (2 + (scy x 2)). when the seta (external transfer acknowledge) bit is set, ta must be generated externally, so that external hardware determines the number of wait states. 10-12 mpc565/mpc566 reference manual motorola chip-select timing the internal ta generation mode is enabled if the seta bit in the or register is cleared. however, if the ta pin is asserted externally at least two clock cycles before the wait states counter has expired, this assertion terminates the memory cycle. when seta is cleared, it is forbidden to assert external ta less than two clocks before the wait states counter expires. 10.3.1 memory devices interface example figure 10-7 describes the basic connection between the mpc565/mpc566 and a static memory device. in this case cs x is connected directly to the chip enable (ce )ofthe memory device. the we /be [0:3] lines are connected to the respective we in the memory device where each we /be line corresponds to a different data byte. figure 10-7. gpcm?memory devices interface in figure 10-8, the csx timing is the same as that of the address lines output. the strobes for the transaction are supplied by the oe and the we /be lines (if programmed as we /be ). when the acs bits in the corresponding orx register = 00, cs is asserted at the same time that the address lines are valid. note if csnt is set, the we signal is negated a quarter of a clock earlier than normal. memory address ce oe w data address csx oe we /be data mpc565/mpc566 motorola chapter 10. memory controller 10-13 chip-select timing note: in this and subsequent timing diagrams in this section, the data bus refers to a read cycle. in a write cycle, the data immediately follows ts . figure 10-8. memory devices interface basic timing (acs = 00,trlx = 0) 10.3.2 peripheral devices interface example figure 10-9 illustrates the basic connection between the mpc565/mpc566 and an external peripheral device. in this case csx is connected directly to the chip enable (ce )ofthe memory device and the r/w line is connected to the r/w in the peripheral device. the csx line is the strobe output for the memory access. clock address cs we /be oe data ts ta csnt = 1, acs = 00 10-14 mpc565/mpc566 reference manual motorola chip-select timing figure 10-9. peripheral devices interface the cs x timing is defined by the setup time required between the address lines and the ce line. the memory controller allows specification of the cs timing to meet the setup time required by the peripheral device. this is accomplished through the acs field in the base register. in figure 10-10, the acs bits are set to 0b11, so csx is asserted half a clock cycle after the address lines are valid. figure 10-10. peripheral devices basic timing (acs = 11,trlx = 0) peripheral address ce r/w data address csx rd /wr data mpc565/mpc566 clock address ts ta cs rd/wr data acs = 11 csnt = 1 motorola chapter 10. memory controller 10-15 chip-select timing 10.3.3 relaxed timing examples the trlx field is provided for memory systems that need a more relaxed timing between signals. when trlx is set and acs = 0b00, the memory controller inserts an additional cycle between address and strobes (cs line and we /oe ). when trlx and csnt are both set in a write to memory, the strobe lines (we /be [0:3] and cs , if acs = 0b00) are negated one clock earlier than in the regular case. note in the case of a bank selected to work with external transfer acknowledge (seta = 1) and trlx = 1, the memory controller does not support external devices that provide ta to complete the transfer with zero wait states. the minimum access duration in this case equals three clock cycles. figure 10-11 shows a read access with relaxed timing. note the following: strobes (oe and cs ) assertion time is delayed one clock relative to address (trlx bit set effect). strobe (cs ) is further delayed (half-clock) relative to address due to acs field being set to 11. total cycle length = 5, is determined as follows: ? two clocks for basic cycle ? scy = 1 determines 1 wait state, which is multiplied by two due to trlx being set (2 + (scy x 2)). ? extra clock is added due to trlx effect on the strobes. 10-16 mpc565/mpc566 reference manual motorola chip-select timing figure 10-11. relaxed timing ? read access (acs = 11, scy = 1, trlx = 1) figure 10-12 through figure 10-14 are examples of write accesses using relaxed timing. in figure 10-12, note the following points: because trlx is set, assertion of the cs and we strobes is delayed by one clock cycle. cs assertion is delayed an additional one quarter clock cycle because acs = 10. the total cycle length = three clock cycles, determined as follows: ? the basic memory cycle requires two clock cycles. ? an extra clock cycle is required due to the effect of trlx on the strobes. clock address ts ta cs rd/wr we /be data oe acs=?11?&trlx=?1? acs=?00?&trlx=?1? webs=?1?,lineactsasbe in read. motorola chapter 10. memory controller 10-17 chip-select timing figure 10-12. relaxed timing ? write access (acs = 10, scy = 0, csnt = 0, trlx = 1) in figure 10-13, note the following: because the trlx bit is set, the assertion of the cs and we strobes is delayed by one clock cycle. because acs = 11, the assertion of cs is delayed an additional half clock cycle. because csnt = 1, we is negated one clock cycle earlier than normal. (refer to figure 10-8). the total cycle length is four clock cycles, determined as follows: ? the basic memory cycle requires two clock cycles. ? two extra clock cycles are required due to the effect of trlx on the assertion and negation of the cs and we strobes. clock address ts ta cs rd/wr we /be data oe acs = 10 acs = 00 10-18 mpc565/mpc566 reference manual motorola chip-select timing figure 10-13. relaxed timing ? write access (acs = 11, scy = 0, csnt = 1, trlx = 1) in figure 10-14, notice the following: because acs = 0, trlx being set does not delay the assertion of the cs and we strobes. because csnt = 1, we /be is negated one clock cycle earlier than normal. (refer to figure 10-8). cs is not negated one clock cycle earlier, since acs = 00. the total cycle length is three clock cycles, determined as follows: ? the basic memory cycle requires two clock cycles. ? one extra clock cycle is required due to the effect of trlx on the negation of the we /be strobes. clock address ts ta cs rd/wr we /be data oe acs =11 acs=00 & csnt = 1 csnt = 1 motorola chapter 10. memory controller 10-19 chip-select timing figure 10-14. relaxed timing ? write access (acs = 00, scy = 0, csnt = 1, trlx = 1 10.3.4 extended hold time on read accesses for devices that require a long disconnection time from the data bus on read accesses, the bit ehtr in the corresponding or register can be set. in this case any mpc565/mpc566 access to the external bus following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access to the same bank. figure 10-15 through figure 10-18 show the effect of the ehtr bit on memory controller timing. figure 10-15 shows a write access following a read access. because ehtr = 0, no extra clock cycle is inserted between memory cycles. clock address ts ta cs rd/wr we /be data oe csnt = 1 no effect, acs = 00 10-20 mpc565/mpc566 reference manual motorola chip-select timing figure 10-15. consecutive accesses (write after read, ehtr = 0) figure 10-16 shows a write access following a read access when ehtr = 1. an extra clock is inserted between the cycles. for a write cycle following a read, this is true regardless of whether both accesses are to the same region. clock address ts ta csx csy rd/wr data oe tdt motorola chapter 10. memory controller 10-21 chip-select timing figure 10-16. consecutive accesses (write after read, ehtr = 1) figure 10-17 shows consecutive accesses from different banks. because ehtr = 1 (and the accesses are to different banks), an extra clock cycle is inserted. clock address ts ta csx csy rd/wr data oe tdt long tdt allowed extra clock before next cycle starts. 10-22 mpc565/mpc566 reference manual motorola chip-select timing figure 10-17. consecutive accesses (read after read from different banks, ehtr = 1) figure 10-18 shows two consecutive read cycles from the same bank. even though ehtr = 1, no extra clock cycle is inserted between the memory cycles. (in the case of two consecutive read cycles to the same region, data contention is not a concern.) clock address ts ta csx csy rd/ wr data oe tdt long tdt allowed extra clock before next cycle starts motorola chapter 10. memory controller 10-23 chip-select timing figure 10-18. consecutive accesses (read after read from same bank, ehtr = 1) 10.3.5 summary of gpcm timing options table 10-2 summarizes the different combinations of timing options. table 10-2. programming rules for timing strobes trlx access type acs csnt address to cs asserted cs negated to add/data invalid address to we /be or oe asserted we /be negated to add/data invalid oe negated to add/data invalid total number of cycles 0 read 00 x 0 1/4 * clock 3/4 * clock x 1/4 * clock 2 + scy 0 read 10 x 1/4 * clock 1/4 * clock 3/4 * clock x 1/4 * clock 2 + scy 0 read 11 x 1/2 * clock 1/4 * clock 3/4 * clock x 1/4 * clock 2 + scy 0 write 00 0 0 1/4 * clock 3/4 * clock 1/4 * clock x 2 + scy 0 write 10 0 1/4 * clock 1/4 * clock 3/4 * clock 1/4 * clock x 2 + scy 0 write 11 0 1/2 * clock 1/4 * clock 3/4 * clock 1/4 * clock x 2 + scy clock address ts ta csx csy rd/ wr data oe tdt 10-24 mpc565/mpc566 reference manual motorola chip-select timing note: timing in this table refers to the typical timing only. consult the electrical characteristics for exact worst-case timing values. 1/4 clock actually means 0 to 1/4 clock, 1/2 clock means 1/4 to 1/2 clock. additional timing rules not covered in table 10-2 include the following: if seta = 1, an external ta signal is required to terminate the cycle. if trlx = 1 and seta = 1, the minimum cycle length = 3 clock cycles (even if scy = 0000) if trlx = 1, the number of wait states = 2 * scy & 2 * bscy acs = 01 is not defined (reserved). if ehtr = 1, an extra (idle) clock cycle is inserted between a read cycle and a following read cycle to another region, or between a read cycle and a following write cycle to any region. if lbdip = 1 (late bdip assertion), the bdip pin is asserted only after the number of wait states for the first beat in a burst have elapsed. see figure 9-13 in chapter 9, ?external bus interface" as well as section 9.5.5, ?burst mechanism." 0 write 00 1 0 1/4 * clock 3/4 * clock 1/2 * clock x 2 + scy 0 write 10 1 1/4 * clock 1/2 * clock 3/4 * clock 1/2 * clock x 2 + scy 0 write 11 1 1/2 * clock 1/2 * clock 3/4 * clock 1/2 * clock x 2 + scy 1 read 00 x 0 1/4 * clock 3/4 clock x 1/4 * clock 2 + 2*scy 1 read 10 x (1 + 1/4) * clock 1/4 * clock (1 + 3/4) * clock x1/4*clock3+ 2*scy 1 read 11 x (1 + 1/2) * clock 1/4 * clock (1 + 3/4) * clock x1/4*clock3+ 2*scy 1 write 00 0 0 1/4 * clock 3/4 clock 1/4 * clock x 2 + 2*scy 1 write 10 0 (1 + 1/4) * clock 1/4 * clock (1 + 3/4) * clock 1/4 * clock x 3 + 2*scy 1write110(1+1/2)* clock 1/4 * clock (1 + 3/4) clock 1/4 * clock x 3 + 2*scy 1 write 00 1 0 1/4 * clock 3/4 clock (1 + 1/2) * clock x3+ 2*scy 1 write 10 1 (1 + 1/4) * clock (1 + 1/2) * clock (1 + 3/4) clock (1 + 1/2) * clock x4+ 2*scy 1write111(1+1/2)* clock (1 + 1/2) * clock (1 + 3/4) clock (1 + 1/2) * clock x4+ 2*scy table 10-2. programming rules for timing strobes (continued) trlx access type acs csnt address to cs asserted cs negated to add/data invalid address to we /be or oe asserted we /be negated to add/data invalid oe negated to add/data invalid total number of cycles motorola chapter 10. memory controller 10-25 write and byte enable signals note the lbdip/tbdip function can operate only when the cycle termination is internal, using the number of wait states programmed in one of the orx registers. the lbdip/tbdip function cannot be activated at the same time?results are unknown. 10.4 write and byte enable signals the gpcm determines the timing and value of the we /be signals if allowed by the port size of the accessed bank, the transfer size of the transaction and the address accessed. the functionality of the we /be [0:3] pins depends upon the value of the write enable/byte select (webs) bit in the corresponding br register. setting webs to 1 will enable these pins as be , while clearing it to zero will enable them as we .we is asserted only during write access, while be is asserted for both read and write accesses. the timing of the we /be pins remains the same in either case, and is determined by the trlx, acs and csnt bits. the upper we /be (we [0]/be[0] ) indicates that the upper eight bits of the data bus (d0?d7) contains valid data during a write/read cycle. the upper-middle write byte enable (we [1]/be [1]) indicates that the upper-middle eight bits of the data bus (d8?d15) contains valid data during a write/read cycle. the lower-middle write byte enable (we [2]/be [2]) indicates that the lower-middle eight bits of the data bus (d16?d23) contains valid data during a write/read cycle. the lower write/read enable (we [3]/be [3]) indicates that the lower eight bits of the data bus contains valid data during a write cycle. the write/byte enable lines affected in a transaction for 32-bit port (ps = 00), a 16-bit port (ps = 10) and a 8-bit port (ps = 01) are shown in table 10-3. this table shows which write enables are asserted (indicated with an ?x?) for different combinations of port size and transfer size 10-26 mpc565/mpc566 reference manual motorola dual mapping of the internal flash eeprom array 10.5 dual mapping of the internal flash eeprom array the internal flash eeprom (uc3f) module can be mapped to an external memory region controlled by the memory controller. only one region can be programmed to be dual-mapped. when dual mapping is enabled (dme bit is set in the dmbr register) and when an internal address matches the dual-mapped address range (as programmed in the dmbr) with the cycle type matching the at/atm field in dmbr/dmor registers, the following occurs: the internal flash memory does not respond to that address the memory controller takes control of the external access the attributes for the access are taken from one of the base and option registers of the appropriate chip select the chip-select region selected is determined by the ?cs line select? bit field (section 10.9.5, ?dual-mapping base register (dmbr)"). note dual mapping can operate only for addresses within the flash pre-allocated address (up to two mbytes). this is achieved by programming only six bits for the base address [11:16]; the upper bits are always set as follows: bus_addr[0:10]={0000000,isb[0:2],0} where isb[0:2] represents the bit field in immr register that determines the location of the address map of the mpc565/mpc566. table 10-3. write enable/byte enable signals function transfer size tsiz address 32-bit port size 16-bit port size 8-bit port size a30 a31 we[0]/ be[0] we[1]/ be[1] we[2]/ be[2] we[3]/ be[3] we[0]/ be[0] we[1]/ be[1] we[2]/ be[2] we[3]/ be[3] we[0]/ be[0] we[1]/be[1] we[2]/be[2] we[3]/be[3] byte 0 1 v 0 x x x 01 0 1 x x x 01 1 0 x x x 01 1 1 x x x half- word 1000xx xx x 1010 xxxx x word0000xxxxxx x motorola chapter 10. memory controller 10-27 dual mapping of the internal flash eeprom array with dual mapping, aliasing of address spaces may occur. this happens when the region is dual-mapped into a region which is also mapped into one of the four regions available in the memory controller. if code or data is written to the dual-mapped region, care must be taken to avoid overwriting this code or data by normal accesses of the chip-select region. there is a match if: bus_address[0:16] == {0000000,isb[0:2],0,ba[1:6]} where ba represents the bit field in the dmbr register. care must also be taken to avoid overwriting ?normal? csx data with dual-mapped code or data. one way to avoid this situation is by disabling the chip-select region and enabling only the dual-mapped region (dmbr[dme] = 1, but brx[v] = 0). figure 10-19 illustrates the phenomenon. 10-28 mpc565/mpc566 reference manual motorola dual mapping of the internal flash eeprom array figure 10-19. aliasing phenomenon illustration the default state is to allow dual-mapping data accesses only; this means that dual mapping is possible only for data accesses on the internal bus. also, the default state takes the lower two mbytes of the mpc566 internal flash memory. hence, caution should be taken to change the dual-mapping setup before the first data access. note dual mapping is not supported for an external master when the memory controller serves the access; in such a case, the mpc566 terminates the cycle by asserting tea . csx physical external memory mpc565/mpc566 memory map external csx flash dual mapping dual-map region motorola chapter 10. memory controller 10-29 dual mapping of an external flash region 10.6 dual mapping of an external flash region the dual mapping feature also enables mapping of external memory to alternative memory regions controlled by the memory controller. when dual mapping is enabled and an external address matches a dual mapped address, and the cycle type matches at/atm field in dmbr/dmor register, then the following occur: the chip-select that is mapped to the access does not respond to that address (it remains negated) the chip-select region selected is determined by the dmcs bit field in the dmbr register the attributes for the access are taken from the corresponding chip select region dual mapping can only be enabled over memory addresses in the range 0x0000 0000 through 0x000f ffff. note internal flash must be disabled to use dual mapping over an external memory. 10.7 global (boot) chip-select operation global (boot) chip-select operation allows address decoding for a boot rom before system initialization. if the global chip-select feature is enabled then the memory controller is enabled from reset. the global chip select port size is programmable at system reset using the bps pins (pins [4:5]) of the reset configuration word (rcw). the global chip select does not provide write protection and responds to all address types, allowing a boot rom to be located anywhere in the address space. the memory controller will operate in this boot mode until the first write to any chip select option register (orx).the chip select pin can be programmed to continue decoding a range of addresses after this write, provided the preferred address range is first loaded into the chip select base register (brx). after the first write to orx, the global chip select can only be restarted with a system reset. which chip-select line is used as the global chip select, and how it operates, is determined by the reset configuration parameters flen ? internal flash enable (bit 20) bdis ? boot disable (bit 3) dme ? dual mapping enable (bit 31) table 10-4 summarizes global chip select operations for all combinations of values on these reset configuration word lines. 10-30 mpc565/mpc566 reference manual motorola global (boot) chip-select operation . in case 1, where flen, bdis, dme = 0b000 (all cleared) at reset, cs [0] is the global chip-select output. when the rcpu begins accessing memory after system reset, cs [0] is asserted for every address, for accesses to both internal and external instructions and data. in case 2, where flen, bdis, dme = 0b001 at reset, cs [0] is asserted for all external address accesses (instructions and data) and for internal instruction accesses. however, cs [3] is asserted for all internal data accesses. cs [3]isusedinthiscasetoallowdual mapping of loads/stores to/from an alternative bank which is not the memory bank normally used for instructions/data. in this way cs [3] can be used to allow load/store from a different memory bank from reset. dme can then be disabled as required. the global chip select feature is disabled by driving only the bdis line of the rcw (flen, bdis, dme = 0b010). this is shown in case 3 of table 10-4. table 10-5 shows the initial values of the ?boot bank? in the memory controller. table 10-4. memory controller functionality from reset case flen ? flash enable bdis ? boot disable dme ? dual map enabled internal instructions fetches internal data loads external instructions fetches external data loads 1000cs [0] cs [0] cs [0] cs [0] 2001cs [0] cs [3] cs [0] cs [3] 3010noglobalchip select no global chip select no global chip select no global chip select 4011cs [3] cs [3] cs [3] cs [3] 5 1 1 the internal flash reset config word uses hc , which forces flen to 1. 1 0 0 internal flash internal flash cs [0] cs [0] 6 1 1 0 1 internal flash cs [0] cs [0] cs [0] 7 1 1 1 0 internal flash internal flash no global chip select no global chip select 8 1 1 1 1 internal flash cs [0] no global chip select no global chip select table 10-5. boot bank fields values after hard reset field value (binary) ps rcw[4:5] bps sst 0 bl 0 wp 0 seta 0 bi 0b1 motorola chapter 10. memory controller 10-31 memory controller external master support 10.8 memory controller external master support the memory controller in the mpc565/mpc566 supports accesses initiated by both internal and external bus masters to external memories. if the address of any master is mapped within the internal mpc565/mpc566 address space, the access will be directed to the internal device, and will be ignored by the memory controller. if the address is not mapped internally, but rather mapped to one of the memory controller regions, the memory controller will provide the appropriate chip select and strobes as programmed in the corresponding region (see section 6.14.1.3, ?external master control register (emcr)?). the mpc565/mpc566 supports only synchronous external bus masters. this means that the external master works with clkout and implements the mpc565/mpc566 bus protocol to access a slave device. a synchronous master initiates a transfer by asserting ts . the addr[0:31] signals must be stable from the rising edge of clkout during which ts is sampled, until the last ta acknowledges the transfer. since the external master works synchronously with the mpc565/mpc566, only setup and hold times around the rising edge of clkout are important. once the ts is detected/asserted, the memory controller compares the address with each one of its defined valid banks to find a possible match. but, since the external address space is shorter than the internal space, the actual address that is used for comparing against the memory controller regions is in the format of: {00000000, bits [8:16] of the external address}. in the case where a match is found, the controls to the memory devices are generated and the transfer acknowledge indication (ta ) is supplied to the master. since it takes two clocks for the external address to be recognized and handled by the memory controller, the ts which is generated by the external master is ahead of the corresponding cs and strobes which are asserted by the memory controller. this 2-clock delay might cause problems in some synchronous memories. to overcome this, the v cs [0] = id [3] cs [3] = id [20] & id[31] am[0:16] 0 0000 0000 0000 0000 atm[0:2] 000 csnt 0 acs[0:1] 00 ehtr 0 scy[0:3] 0b1111 bscy[0:2] 0b011 trlx 0 table 10-5. boot bank fields values after hard reset (continued) field value (binary) 10-32 mpc565/mpc566 reference manual motorola memory controller external master support memory controller generates the mts (memory transfer start) strobe which can be used in the slave?s memory instead of the external master?s ts signal. as seen in figure 10-20, the mts strobe is synchronized to the assertion of cs by the memory controller so that the external memory can latch the external master?s address correctly. to activate this feature, the mtsc bit must be set in the siumcr register. on mpc566, when the external master accesses the internal flash when it is disabled, the access is terminated with transfer error acknowledge (tea ) pin asserted, and the memory controller does not support this access in any way. when the memory controller serves an external master, the bdip pin becomes an input pin. this pin is watched by the memory controller to detect when the burst is terminated. figure 10-20. synchronous external master configuration for gpcm-handled memory devices memory address ce oe w data address csx oe we /be data synchronous external master ts ta ta ts addr data bdip bdip bdip burst note: the memory controller?s bdip line is used as a burst_in_progress signal. burst burst mts ts mpc565/mpc566 motorola chapter 10. memory controller 10-33 memory controller external master support figure 10-21. synchronous external master basic access (gpcm controlled) clock addr[0:31] cs we /be oe data ts ta address match & compare memory device access rd/wr burst tsize mts 10-34 mpc565/mpc566 reference manual motorola programming model note since the mpc565/mpc566 has only 24 address pins, the eight most significant internal address lines are driven as 0b0000_0000, and so compared in the memory controller?s regions. 10.9 programming model the following registers are used to control the memory controller. note in all subsequent register bit tables, if two reset values are given: the lower is for cs x, x = 1, 2, 3, and the upper is dedicated to cs[ 0]. 10.9.1 general memory controller programming notes 1. in the case of an external master that accesses an internal mpc565/mpc566 module (in slave or peripheral mode), if that slave device address also matches one of the memory controller?s regions, the memory controller will not issue any cs for this access, nor will it terminate the cycle. thus, this practice should be avoided. be aware also that any internal slave access prevents memory controller operation. table 10-6. memory controller address map address register 0x2f c100 base register bank 0 (br[0]) 0x2f c104 option register bank 0 (or[0]) 0x2f c108 base register bank 1 (br[1]) 0x2f c10c option register bank 1 (or[1]) 0x2f c110 base register bank 2 (br[2]) 0x2f c114 option register bank 2 (or[2]) 0x2f c118 base register bank 3 (br[3]) 0x2f c11c option register bank 3 (or[3]) 0x2f c120 ? 0x13f reserved 0x2f c140 dual-mapping base register (dmbr) 0x2f c144 dual-mapping option register (dmor) 0x2f c148 ? 0x2f c174 reserved 0x2f c178 memory status register (mstat) motorola chapter 10. memory controller 10-35 programming model 2. if the memory controller serves an external master, then it can support accesses to 32-bit port devices only. this is because the mpc565/mpc566 external bus interface cannot initiate extra cycles to complete an access to a smaller port-size device as it does not own the external bus. 3. when the seta bit in the base register is set, then the timing programming for the various strobes (cs ,oe and we /be ) may become meaningless. 10.9.2 memory controller status registers (mstat) , msb 0 1234567 8 9 1011121314lsb 15 reserved wper 0 wper 1 wper 2 wper 3 reserved hreset 00000000 0 0 0 0 0000 figure 10-22. mstat ? memory controller status register 0x2f c178 table 10-7. mstat bit descriptions bit(s) name description 0:7 ? reserved 8:11 wper0 ? wper3 write protection error for bank x. this bit is asserted when a write-protect error occurs for the associated memory bank. a bus monitor (responding to tea assertion) will, if enabled, prompt the read of this register if ta is not asserted during a write cycle. wperx is cleared by writing one to the bit or by performing a system reset. writing a zero has no effect on wper. 12:15 ? reserved 10-36 mpc565/mpc566 reference manual motorola programming model 10.9.3 memory controller base registers (br[0] ? br[3]) , msb 0 12345678910 11 12131415 ba hreset (br[0]) 0000000000 0 0 0 000 hreset (br[1:3]) uuuuuuuuuu u u u uuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 ba at ps sst wp rese rved bl webs tbdip lbdip seta bi v hreset (br[0]) 0 0 0 0 id[4:5] 0 0 u u 0 u u u 1 id[3] hreset (br[1:3]) uuuu0 0 0000 0 0 0 00x 1 the reset value is determined by the value on the internal data bus during reset (reset-configuration word). 2 see table 10-9 for reset value. figure 10-23. br[0] ? br[3] ? memory controller base registers 0 ? 30x2f c100 0x2f c108 0x2f c110 0x2f c118 table 10-8. br[0] ? br[3] bit descriptions bit(s) name description 0:16 ba base address. these bits are compared to the corresponding unmasked address signals among addr[0:16] to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master. (the address types are also compared.) these bits are used in conjunction with the am[0:16] bits in the or. 17:19 at address type. this field can be used to require accesses of the memory bank to be limited to a certain address space type. these bits are used in conjunction with the atm bits in the or. note that the address type field uses only at[0:2] and does not need at[3] to define the memory type space. for a full definition of address types, refer to section 9.5.8.6, ?address types". 20:21 ps port size 00 32-bit port 01 8-bit port 10 16-bit port 11 reserved 22 sst short setup time ? this field specifies the setup time required for this memory region. 0 normal setup time (like the mpc555) 1 short setup time selected motorola chapter 10. memory controller 10-37 programming model 23 wp write protect. an attempt to write to the range of addresses specified in a base address register that has this bit set can cause the tea signal to be asserted by the bus-monitor logic (if enabled), causing termination of this cycle. 0 both read and write accesses are allowed 1 only read accesses are allowed. the csx signal and ta are not asserted by the memory controller on write cycles to this memory bank. wper is set in the mstat register if a write to this memory bank is attempted 24 ? reserved 25 bl 1 burst length ? this field specifies the maximum number of words that may comprise a burst access for this memory region. this field has an effect only in the case when the burst accesses are initiated by the usiu (siumcr[burst_en] =1). 0 burst access of up to 4 words 1 burst access of up to 8 words 26 webs write-enable/byte-select. this bit controls the functionality of the we /be pads. 0thewe /be pads operate as we 1thewe /be pads operate as be 27 tbdip toggle-burst data in progress. tbdip determines how long the bdip strobe will be asserted for each data beat in the burst cycles. 28 lbdip late-burst-data-in-progress (lbdip). this bit determines the timing of the first assertion of the bdip pin in burst cycles. note: it is not allowed to set both lbdip and tbdip bits in a region?s base registers; the behavior of the design in such cases is unpredictable. 0 normal timing for bdip assertion (asserts one clock after negation of ts 1 late timing for bdip assertion (asserts after the programmed number of wait states 29 seta external transfer acknowledge 0ta generated internally by memory controller 1ta generated by external logic. note that programming the timing of cs /we /oe strobes may have no meaning when this bit is set 30 bi burst inhibit 0 memory controller drives bi negated (high). the bank supports burst accesses. 1 memory controller drives bi asserted (low). the bank does not support burst accesses. note: following a system reset, the bi bit is set. 31 v valid bit. when set, this bit indicates that the contents of the base-register and option-register pair are valid. the cs signal does not assert until the v-bit is set. note: an access to a region that has no v-bit set may cause a bus monitor timeout. see table 10-9 for the reset value of this bit in br [0]. 1 this feature is not available in mask sets prior to l99n. table 10-9. brx[v] reset value branch register brx[v] reset value br0 id[3] br1 0 br2 0 br3 id [20] & id[31] table 10-8. br[0] ? br[3] bit descriptions (continued) bit(s) name description 10-38 mpc565/mpc566 reference manual motorola programming model 10.9.4 memory controller option registers (or[0] ? or[3]) 1, msb 0 123456789101112131415 am 1 hreset (or[0]) 0000000000000000 hreset (or[1:3]) uuuuuuuuuuuuuuuu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 am atm csnt acs ehtr scy bscy trlx hreset (or[0]) 0000000011110110 hreset (or[1:3]) uuuuuuuuuuuuuuuu 1 it is recommended that this field would hold values that are the power of 2 minus 1 (e.g., 2 3 - 1 = 7 [0b111]). figure 10-24. or[0] ? or[3] ? memory controller option registers 1:3 0x2f c104 0x2f c10c 0x2f c114 0x2f c11c table 10-10. or[0] ? or[3] bit descriptions bit(s) name description 0:16 am address mask. this field allows masking of any corresponding bits in the associated base register. masking the address bits independently allows external devices of different size address ranges to be used. any clear bit masks the corresponding address bit. any set bit causes the corresponding address bit to be used in comparison with the address pins. address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. this field can be read or written at anytime. following a system reset, the am bits are cleared in or[0]. 17:19 atm address type mask. this field masks selected address type bits, allowing more than one address space type to be assigned to a chip-select. any set bit causes the corresponding address type code bits to be used as part of the address comparison. any cleared bit masks the corresponding address type code bit. clear the atm bits to ignore address type codes as part of the address comparison. note that the address type field uses only at[0:2] and does not need at[3] to define the memory type space. following a system reset, the atm bits are cleared in or[0]. 20 csnt chip-select negation time. following a system reset, the csnt bit is reset in or[0]. 0cs /we are negated normally. 1cs /we are negated a quarter of a clock earlier than normal following a system reset, the csnt bit is cleared in or[0]. motorola chapter 10. memory controller 10-39 programming model 21:22 acs address to chip-select setup. following a system reset, the acs bits are reset in or[0]. 00 cs is asserted at the same time that the address lines are valid. 01 reserved 10 cs is asserted a quarter of a clock after the address lines are valid. 11 cs is asserted half a clock after the address lines are valid following a system reset, the acs bits are cleared in or[0]. 23 ehtr extended hold time on read accesses. this bit, when asserted, inserts an idle clock cycle after a read access from the current bank and any mpc565/mpc566 write accesses or read accesses to a different bank. 0 memory controller generates normal timing 1 memory controller generates extended hold timing following a system reset, the ehtr bits are cleared in or[0]. 24:27 scy cycle length in clocks. this four-bit value represents the number of wait states inserted in the single cycle, or in the first beat of a burst, when the gpcm handles the external memory access. values range from 0 (0b0000) to 15 (0b1111). this is the main parameter for determining the length of the cycle. the total cycle length may vary depending on the settings of other timing attributes. the total memory access length is (2 + scy) x clocks. if an external ta response is selected for this memory bank (by setting the seta bit), then the scy field is not used. following a system reset, the scy bits are set to 0b1111 in or[0]. 28:30 bscy burst beats length in clocks. this field determines the number of wait states inserted in all burst beats except the first, when the gpcm starts handling the external memory access and thus using scy[0:3] as the main parameter for determining the length of that cycle. the total cycle length may vary depending on the settings of other timing attributes. the total memory access length for the beat is (1 + bscy) x clocks. if an external ta response has been selected for this memory bank (by setting the seta bit) then bscy[0:3] are not used. 000 0-clock-cycle (1 clock per data beat) 001 1-clock-cycle wait states (2 clocks per data beat) 010 2-clock-cycle wait states (3 clocks per data beat) 011 3-clock-cycle wait states (4 clocks per data beat) 1xx reserved following a system reset, the bscy bits are set to 0b011 in or[0]. 31 trlx timing relaxed. this bit, when set, modifies the timing of the signals that control the memory devices during a memory access to this memory region. relaxed timing multiplies by two the number of wait states determined by the scy and bscy fields. refer to section 10.3.5, ?summary of gpcm timing options" for a full list of the effects of this bit on pins timing. 0 normal timing is generated by the gpcm. 1 relaxed timing is generated by the gpcm following a system reset, the trlx bit is set in or[0]. table 10-10. or[0] ? or[3] bit descriptions (continued) bit(s) name description 10-40 mpc565/mpc566 reference manual motorola programming model 10.9.5 dual-mapping base register (dmbr) , msb 0 123456789101112131415 0 ba reserved at reserved hard reset: 0uuuuuu0 0000100 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved dmcs dme hard reset: 0000000000000id [20] id [20] id[31] 1 1 the reset value is a reset configuration word value extracted from the indicated internal data bus lines. refer to 7.5.2 hard reset configuration word figure 10-25. dmbr ? dual-mapping base register 0x2f c140 table 10-11. dmbr bit descriptions bit(s) name description 0?reserved 1:6 ba base address. ba field corresponds to address bits [11:16]. the base address field is compared (along with the address type field) to the address of the address bus to determine whether an address should be dual-mapped by one of the memory banks controlled by the memory controller. these bits are used in conjunction with the am[11:16] bits in the dmor. 7:9 ? reserved 10:12 at address type. this field can be used to specify that accesses involving the memory bank are limited to a certain address space type. these bits are used in conjunction with the atm bits in the or. the default value at reset is to map data only. for a full definition of address types, refer to section 9.5.8.6, ?address types." 13:27 ? reserved 28:30 dmcs dual-mapping chip select. this field determines which chip-select pin is assigned for dual mapping. 000 cs [0] 001 cs [1] 010 cs [2] 011 cs [3] 1xx reserved 31 dme dual mapping enabled. this bit indicates that the contents of the dual-mapping registers and associated base and option registers are valid and enables the dual-mapping operation. the default value at reset comes from the internal data bus that reflects the reset configuration word. see section 10.5, ?dual mapping of the internal flash eeprom array" for more information. 0 dual mapping is not active 1 dual mapping is active motorola chapter 10. memory controller 10-41 programming model 10.9.6 dual-mapping option register , msb 0 123456789101112131415 0am 1 reserved atm reserved reset: 0000000000001000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved reset: 0000000000000000 1 it is recommended that this field hold values that are the power of 2 minus 1 (e.g., 2 3 - 1 = 7 [0b111]). figure 10-26. dmor ? dual-mapping option register 0x2f c144 table 10-12. dmor bit descriptions bit(s) name description 0?reserved 1:6 am address mask. the address mask field of each option register provides for masking any of the corresponding bits in the associated base register. by masking the address bits independently, external devices of different size address ranges can be used. any clear bit masks the corresponding address bit. any set causes the corresponding address bit to be used in the comparison with the address pins. address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. this field can be read or written at any time. 7:9 ? reserved 10:12 atm address type mask. this field can be used to mask certain address type bits, allowing more than one address space type to be assigned to a chip select. any set bit causes the corresponding address type code bits to be used as part of the address comparison. any cleared bit masks the corresponding address type code bit. to instruct the memory controller to ignore address type codes as part of the address comparison, clear the atm bits. note: following a system reset, the atm bits are cleared in dmor, except the atm2 bit. this means that only data accesses are dual mapped. refer to the address types definition in tab l e 9 - 8. 13:31 ? reserved 10-42 mpc565/mpc566 reference manual motorola programming model motorola chapter 11. l-bus to u-bus interface (l2u) 11-1 chapter 11 l-bus to u-bus interface (l2u) the l-bus to u-bus interface unit (l2u) provides an interface between the load/store bus (l-bus) and the unified bus (u-bus). the l2u module includes the data memory protection unit (dmpu), which provides protection for data memory accesses. the l2u is bidirectional. it allows load/store accesses not intended for the l-bus data ram to go to the u-bus. it also allows code execution from the l-bus data ram and read/write accesses from the u-bus to the l-bus. the l2u directs bus traffic between the l-bus and the u-bus. when transactions start concurrently on both buses, the l2u interface arbitrates to select which transaction is handled. the top priority is assigned to u-bus to l-bus accesses; lower priority is assigned to the load/store accesses by the rcpu. 11.1 general features non-pipelined master and slave on u-bus ? does not start two back-to-back accesses on the u-bus ? supports the u-bus pipelining by starting a cycle on the u-bus when u-bus pipe depth is zero or one ? does not accept back-to-back accesses from the u-bus master non-pipelined master and slave on the l-bus generates module selects for l-bus memory-mapped resources within a programmable, contiguous block of storage programmable data memory protection unit (dmpu) l-bus and u-bus snoop logic for the reservation protocol implemented by the powerpc compatible architecture l2u does not support dual mapping of l-bus or imb3 space show cycles for rcpu accesses to the sram (none, all, writes) ? protection for sram accesses from the u-bus side (all accesses to the sram from the u-bus side are blocked once the sram protection bit is set) 11-2 mpc565/mpc566 reference manual motorola dmpu features 11.2 dmpu features supports four memory regions whose base address and size can be programmed ? available sizes are 4 kbytes, 8 kbytes, 16 kbytes, 32 kbytes, 64 kbytes, 128 kbytes, 256 kbytes, 512 kbytes, 1 mbyte, 2 mbytes, 4 mbytes, 8 mbytes, and 16 mybtes ? region must start on the specified region size boundary (modulo addressing) ? overlap between regions is allowed each of the four regions supports the following attributes: ? access protection: user or supervisor ? guarded attribute: speculative or non-speculative ? enable/disable option ? read only option supports a default global entry for memory space not covered by other regions: ? default access protection ? default guarded attribute interrupt generated upon: ? access violation ? load from guarded region ? write to read-only region the mpc500 msr[dr] bit (data relocate) controls dmpu protection on/off operation programming is done using the mpc500?s mtspr/mfspr instructions to/from implementation specific special purpose registers. no protection for accesses to the sram module on the l-bus (sram has its own protection options) 11.3 l2u block diagram figure 11-1 shows a block diagram of the l-bus to u-bus interface as implemented in the overall mpc565/mpc566 bus architecture. motorola chapter 11. l-bus to u-bus interface (l2u) 11-3 modes of operation figure 11-1. l2u bus interface block diagram 11.4 modes of operation the l2u module can operate in the following modes: normal mode reset operation peripheral mode 11.4.1 normal mode in normal mode (master or slave) the l2u module acts as a bidirectional protocol translator. in master mode the rcpu is fully operational, and there is no external master access to the u-bus. slave mode enables an external master to access any internal bus slave while the rcpu is fully operational. the l2u transfers load/store accesses from the rcpu to the u-bus and the read/write accesses by the u-bus master to the l-bus. in addition to the bus protocol translation, the l2u supports other functions such as show cycles, data memory protection and mpc500 reservation protocol. when a load from the u-bus resource or store to the u-bus resource is issued by the rcpu, it is compared against the dmpu region access (address and attribute) comparators. if none e-bus mpc500 core l-bus u-bus + fp usiu burst buffer controller dmpu reservation control address decode u-bus interface l-bus interface uimb interface l-bus to u-bus interface imb3 11-4 mpc565/mpc566 reference manual motorola data memory protection of the access attributes are compared/matched/true, the access is directed to the u-bus by the l2u module. if the dmpu detects an access violation, it informs the error status to the master initiating the cycle. when show cycles are enabled, accesses to all of the l-bus resources by the rcpu are made visible on the u-bus side by the l2u. the l2u is responsible for handling the effects of reservations on the l-bus and the u-bus. for the l-bus and the u-bus, the l2u detects reservation losses and updates the rcpu core with the reservation status. 11.4.2 reset operation upon soft reset assertion, the l2u goes to an idle state and all pending accesses are ignored. the l2u module control registers are not initialized on the assertion of a soft reset, keeping the system configuration unchanged. upon assertion of hard reset, the l2u control registers are initialized to their reset states. while reset (hard or soft) is asserted on the u-bus, the l2u asserts the corresponding l-bus reset signals. the l2u also drives the reset configuration word from the u-bus to the l-bus upon assertion of hard reset. 11.4.3 peripheral mode in the peripheral mode of operation the rcpu is shut down and an alternative master on the external bus can perform accesses to any internal bus (u-bus and l-bus) slave. the external master can also access the internal mpc500 special registers that are located in the l2u module. in order to access one of these mpc500 registers the emcr[cont] bit in the usiu must be cleared. 11.5 data memory protection the data memory protection unit (dmpu) in the l2u module provides access protection for the memory regions on the u-bus side from load/store accesses by the rcpu. (only u-bus space is protected.) the dmpu does not protect mpc500 register accesses initiated by the rcpu on the l-bus. the user can assign up to four regions of access protection attributes and can assign global attributes to any space not included in the active regions. when it detects an access violation, the l2u generates an exception request to the cpu. a functional diagram of the dmpu is shown in figure 11-2. motorola chapter 11. l-bus to u-bus interface (l2u) 11-5 data memory protection figure 11-2. dmpu basic functional diagram 11.5.1 functional description data memory protection is assigned on a regional basis. default manipulation of the dmpu is done on a global region. the dmpu has control registers which contain the following information: region protection on/off, region base address, region size, and the region?s access permissions. each region?s protection attributes can be turned on/off by configuring the enable attribute bit (enrx) located in the global region attribute register. during each load/store access from the rcpu to the u-bus, the address is compared to the value in the region base address register of each enabled region. any access that matches the specific region within its appropriate size, as defined by the region size field (rs) of the region attribute register, sets a match indication. when more than one match indication occurs, the effective region is the region with the highest priority. priority is determined by region number; highest priority corresponds to the lowest region number, e.g. region 0 is highest priority, while region 3 is lowest. when no match occurs, the effective region is the global region. the global region has the lowest priority. the region attribute register also contains the region?s protection fields. the protection field (pp) of the effective region is compared to the access attributes. if the attributes match, region0 protection/attribute exception logic specific error interrupts to core address access attribute region1 protection/attribute region2 protection/attribute region3 protection/attribute global protection/attribute access region0 address and size region1 address and size region2 address and size region3 address and size granted match select msr[dr] region protection/attribute 11-6 mpc565/mpc566 reference manual motorola data memory protection the access is permitted. when the access is permitted, a u-bus access may be generated according to the specific attribute of the effective region. when the access by the rcpu is not permitted, the l2u module asserts a data memory storage exception to the rcpu. for speculative load/store accesses from the rcpu to a region marked as guarded (g bit of region attribute register is set), the l2u asks the rcpu to retry the l-bus cycle until either the access is not speculative, or it is canceled by the rcpu. in the case of attempted accesses to a guarded region together with any other protection violation (no access), the l2u retries the access. the l2u handles this event as a data storage violation only when the access becomes non-speculative. note access protection is active only when the mpc500?s msr[dr] = 1. when msr[dr] = 0, dmpu exceptions are disabled, all accesses are considered to be to a guarded memory area, and no speculative accesses are allowed. in this case, if the l-bus master [rcpu] initiates a non-sram cycle (access through the l2u) that is marked speculative, the l2u asks the rcpu to retry the l-bus cycle until either the access is not speculative, or it is canceled by the rcpu core. note the programmer must not overlap the sram memory space with any enabled region. overlapping an enabled region with sram memory space disables the l2u data memory protection for that region. if an enabled region overlaps with the l-bus space, the dmpu ignores all accesses to addresses within the l-bus space. if an enabled region overlaps with mpc500 register addresses, the dmpu ignores any access marked as an mpc500 access. 11.5.2 associated registers the following registers are used to control the dmpu of the l2u module. all the registers are special purpose registers which are accessed via the mpc500 mtspr/mfspr instructions. the registers are also accessed by an external master when emcr[cont] = 0. see section 11.8, ?l2u programming model? for register diagrams and bit descriptions. motorola chapter 11. l-bus to u-bus interface (l2u) 11-7 data memory protection . note the appropriate dmpu registers must be programmed before the msr[dr] bit is set. otherwise, dmpu operation is not guaranteed. program the region base address in the l2u_rbax registers to the lower boundary of the region specified by the corresponding l2u_rax[rs] field. if the region base address does not correspond to the boundary of the block size programmed in the l2u_rax, the dmpu snaps the region base to the lower boundary of that block. for example, if the block size is programmed to 16 kbytes for region zero (i.e., l2u_ra0[rs] = 0x3) and the region base address is programmed to 0x1fff(i.e., l2u_rba0[rba] = 0x1), then the effective base address of region zero is 0x0. see figure 11-3. figure 11-3. region base address example it requires external action to program only legal region sizes. the l2u does not check whether the value is legal. if an illegal region size is programmed, the region calculation may not be successful. table 11-1. dmpu registers name description l2u_rba0 region base address register 0 l2u_rba1 region base address register 1 l2u_rba2 region base address register 2 l2u_rba3 region base address register 3 l2u_ra0 region attribute register 0 l2u_ra1 region attribute register 1 l2u_ra2 region attribute register 2 l2u_ra3 region attribute register 3 l2u_gra global region attribute region 0 (16 kbytes) actual programmed region resulting region 0x0000 0000 0x0000 1fff 0x0000 3fff 0x0000 5fff 11-8 mpc565/mpc566 reference manual motorola reservation support 11.5.3 l-bus memory access violations all l-bus slaves have their own access protection logic. for consistency, all storage access violations have the same termination result. thus access violations for load/store accesses started by the rcpu always have the same termination from all slaves: assertion of the data storage exception. all other l-bus masters cause machine check exceptions. 11.6 reservation support in general terms, a reservation activity is the process whereby a load and store instruction pair is accompanied by a reservation of the data, the goal being to achieve an atomic operation. if a bus master other than the one holding the reservation accesses the data (or some other specific condition occurs as described in section 11.6.1, ?the reservation protocol?) the reservation is lost and is indicated accordingly. the rcpu storage reservation protocol supports a multi-level bus structure. for each local bus, storage reservation is handled by the local reservation logic. the protocol tries to optimize reservation cancellation such that an mpc500 processor (rcpu) is notified of storage reservation loss on a remote bus (u-bus, imb or external bus) only when it has issued a stwcx cycle to that address. that is, the reservation loss indication comes as part of the stwcx cycle. 11.6.1 the reservation protocol the reservation protocol operates under the following assumptions: each processor has at most 1 reservation flag a lwarx instruction sets the reservation flag another lwarx instruction by same processor clears the reservation flag related to a previous lwarx instruction and sets again the reservation flag a stwcx instruction by the same processor clears the reservation flag a store instruction by the same processor does not clear the reservation flag some other processor (or other mechanism) store to an address with an existing reservation clears the reservation flag in case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage 11.6.2 l2u reservation support the l2u is responsible for handling the effects of reservations on the l-bus and the u-bus. for the l-bus and the u-bus, the l2u detects reservation losses. motorola chapter 11. l-bus to u-bus interface (l2u) 11-9 reservation support the reservation logic in the l2u performs the following functions: snoops accesses to all l-bus and u-bus slaves holds one reservation (address) for the core sets the reservation flag when the cpu issues a load-with-reservation request the unit for reservation is one word. a byte or half-word store request by another master will clear the reservation flag. a load-with-reservation request by the cpu updates the reservation address related to a previous load-with-reservation request and sets the reservation flag for the new location. a store-with-reservation request by the cpu clears the reservation flag. a store request by the cpu does not clear the flag. a store request by some other master to the reservation address clears the reservation flag. if the storage reservation is lost, it is guaranteed that a store-with-reservation request by the cpu will not modify the storage. the l2u does not start a store-with-reservation cycle on the u-bus if the reserved location on the u-bus has been touched by another master. the l2u drives the reservation status back to the core. when the reserved location in the sram on the l-bus is touched by an alternate master, on the following clock, the l2u indicates to the cpu that the reservation has been touched. on assertion of the cancel-reservation signal, the rcpu clears the internal reservation bit. if an stwcx cycle has been issued at the same time, the rcpu aborts the cycle. software must check the cr0[eq] bit to determine if the stwcx instruction completed successfully. storage reservation is set regardless of the termination status (address or data phase) of the lwarx access. storage reservation is cleared regardless of the data phase termination status of the stwcx access if the address phase is terminated normally. storage reservation will be cleared regardless of the data phase termination status of the write requests by another master to the reserved address if the address phase of the write access is terminated normally on the destination (u-bus/l-bus) bus. if the programmable memory map of the part is modified between a lwarx and a stwcx instruction, the reservation is not guaranteed. 11.6.3 reserved location (bus) and possible actions once the cpu core reserves a memory location, the l2u module is responsible for snooping l-bus and u-bus for possible intrusion of the reserved location. under certain circumstances, the l2u depends on the usiu or the uimb to provide status of reservation on external bus and the imb3 respectively. table 11-2 lists all reservation protocol cases supported by the l2u snooping logic. 11-10 mpc565/mpc566 reference manual motorola l-bus show cycle support 11.7 l-bus show cycle support the l2u module provides support for l-bus show cycles. l-bus show cycles are external visibility cycles that reflect activity on the l-bus that would otherwise not be visible to the external bus. l-bus show cycles are software controlled. 11.7.1 programming show cycles l-bus show cycles are disabled during reset and must be configured by writing the appropriate bits in the l2u_mcr control register. l-bus show cycles are programmed by setting the lshow[0:1] bits in the l2u_mcr. table 11-3 shows the configurations of the lshow[0:1] bits. table 11-2. reservation snoop support reserved location on intruding alternate master action taken on stwcx cycle l-bus l-master request to cancel the reservation. 1 1 if the rcpu tries to modify (stwcx) that location, the l2u does not have enough time to stop the write access from completing. in this case, the l2u will drive cancel-reservation signal back to the core as soon as it comes to know that the alternate master on the u-bus has touched the reserved location. u-master request to cancel the reservation. u-bus l-master block stwcx 2 2 if the rcpu tries to modify (stwcx) that location, the l2u does not start the cycle on the u-bus and it communicates to the core that the current write has been aborted by the slave with no side effects. u-master block stwcx external bus l-master block stwcx u-master block stwcx ext-master transfer status 3 3 if the rcpu tries to modify (stwcx) that location, the l2u runs a write-cycle-with-reservation request on the u-bus. the l2u samples the status of the reservation along with the u-bus cycle termination signals and it communicates to the core if the current write has been aborted by the slave with no side effects. imb3 l-master block stwcx u-master block stwcx imb3-master transfer status table 11-3. l2u_mcr lshow modes lshow action 00 disable l-bus show cycles 01 show address and data of all l-bus space write cycles 10 reserved (disable l-bus show cycles) 11 show address and data of all l-bus space read and write cycles motorola chapter 11. l-bus to u-bus interface (l2u) 11-11 l-bus show cycle support 11.7.2 performance impact when show cycles are enabled in the l2u module, there is a performance penalty on the l-bus. this occurs because the l2u module does not support more than one access being processed at any time. to ensure that only one access at a time can be processed, and not lose an l-bus access that would have been show cycled, the l2u module will arbitrate for the l-bus whenever it is processing any access. this l-bus arbitration will prevent any other l-bus master from starting a cycle that might turn out to be a qualifiable l-bus show cycle. for l-bus show cycles, the minimum performance impact on the l-bus will be three clocks. this minimum impact assumes that the l-bus slave access is a 1-clock access, and the l2u module acquires immediate bus grant on the u-bus. the l2u has to wait two clocks before completing the show cycle on the u-bus, thus using up five clocks for the complete process. a retried access on the l-bus (no address acknowledge) that qualifies to be show cycled, will be accepted when it is actually acknowledged. this will cause a 1-clock delay before an l-bus master can retry the access on the l-bus, because the l2u module will release l-bus one clock later. l2u asserts the internal bus request signal on the u-bus for a minimum of two clocks when starting a show cycle on the u-bus. 11.7.3 show cycle protocol the l2u module behaves as both a master and a slave on the u-bus during show cycles. the l2u starts the u-bus transfer as a bus master and then completes the address phase and data phase of the cycle as a slave. the l2u follows u-bus protocol of in-order termination of the data phase. the usiu can control the start of show cycles on the u-bus by asserting the no-show cycle indicator. this will cause the l2u module to release the u-bus for at least one clock before retrying the show cycle. 11.7.4 l-bus write show cycle flow the l2u performs the following sequence of actions for an l-bus-write show cycle. 1. arbitrates for the l-bus to prevent any other l-bus cycles from starting 2. latches the address and the data of the l-bus access, along with all address attributes 3. waits for the termination of the l-bus access and latches the termination status (data error) 11-12 mpc565/mpc566 reference manual motorola l-bus show cycle support 4. arbitrate for the u-bus, and when granted, starts the u-bus access, asserting show cycle request on the u-bus, along with address, attributes and the write data. the l2u module provides address recognition and acknowledgment for the address phase. if the no-show cycle indicator from the u-bus is asserted, the l2u does not start the show cycle. the l2u module releases the u-bus until the no-show cycle indicator is negated and then arbitrates for the u-bus again. 5. when the l2u module has u-bus data bus grant, it drives the data phase termination handshakes on the u-bus. 6. releases the l-bus 11.7.5 l-bus read show cycle flow the l2u performs the following sequence of actions for an l-bus read show cycle. 1. arbitrates for the l-bus to prevent any other l-bus cycle from starting 2. latches the address of the l-bus access, along with all address attributes 3. waits for the data phase termination on the l-bus and latches the read data, and the termination status from the l-bus 4. arbitrates for the u-bus, and when granted, starts the u-bus access, asserting the show cycle request on the u-bus, along with address attributes. the l2u module provides address recognition/acknowledgment for the address phase. if the no-show cycle indicator from the u-bus is asserted, the l2u does not start the show cycle. the l2u module releases the u-bus until the no-show cycle indicator is negated and then arbitrates for the u-bus again. 5. when the l2u module has u-bus data bus grant, it drives the read data and the data phase termination handshakes on the u-bus 6. release the l-bus. 11.7.6 show cycle support guidelines the following are the guidelines for l2u show cycle support: the l2u module provides address and data for all qualifying l-bus cycles when the appropriate mode bits are set in the l2u_mcr. the l2u-module-only provides show cycles l-bus activity that is not targeted for the u-bus or the l2u module internal registers, irrespective of the termination status of such activity. the l2u module does not provide show cycle access to any mpc500 special purpose register. the l2u does not start a show cycle for an l-bus access that is retried. this decision to not start the show cycle causes a clock delay before the cycle can be retried, since motorola chapter 11. l-bus to u-bus interface (l2u) 11-13 l2u programming model the l2u module will have arbitrated away the l-bus immediately on detecting the show cycle, before the retry information is available. the l2u module does not show cycle any l-bus activity that is aborted. the l2u module does not access the u-bus if the usiu inhibits show cycle activity on the u-bus. the l2u does not provide show cycle for any l-bus addresses that fall in the l-bus sram address space if the sram protection [sp] bit is set in the l2u_mcr. table 11-4 summarizes the l2u show cycle support. 11.8 l2u programming model the l2u control registers control the l2u bus interface and the dmpu. they are accessible via the mpc565/mpc566 mtspr and mfspr instructions. they are also accessible by an external master when emcr[cont] bit is cleared. l2u control registers are accessible from both the l-bus side and the u-bus side in one clock cycle. as with all sprs, l2u registers are accessible in supervisor mode only. any unimplemented bits in l2u registers return 0?s on a read, and the writes to those register bits are ignored. table 11-5 shows l2u registers along with their spr numbers and hexadecimal addresses which are used to access l2u registers during a peripheral mode access. table 11-4. l2u show cycle support chart case destination lb aack lb abort comments 1 l-bus slave 1 1 l-bus slave includes all address in the l-bus address space. no x 2 2 x indicates don?t care conditions. not show cycled [cycle will be retried one clock later] 3 3 there will be a 1-clock turnaround because the l-bus retry information is not available in time to negate the l-bus arbitration. 2l2u 4 4 l2u indicates l2u registers. xx notshowcycled 3 u-bus/e-bus 5 5 u-bus/e-bus refers to all destinations through the l2u interface. xx notshowcycled 4 l-bus slave 1 yes no show cy cled 5 l-bus slave 1 yes yes not show c yc led [l-bus will be released next clock] 11-14 mpc565/mpc566 reference manual motorola l2u programming model . for these registers a bus cycle will be performed on the l-bus and the u-bus with the address as shown in table 11-6. . 11.8.1 u-bus access the l2u registers are accessible from the u-bus side only if it is a supervisor mode data access and the register address is correct and it is indicated on the u-bus that it is a ppc register access. a user mode access, or an access marked as instruction, to l2u registers from the u-bus side will cause a data error on the u-bus. 11.8.2 transaction size all l2u registers are defined by mpc500 architecture as being 32-bit registers in normal mode. there is no mpc500 instruction to access either a half word or a byte of the special purpose register. all l2u registers are only word accessible (read and write) in peripheral mode. a half-word or byte access in peripheral mode will result in a word transaction. table 11-5. l2u (ppc) register decode name spr # spr[5:9] spr[0:4] address for external master access access description l2u_mcr 568 10001 11000 0x0000_3110 supr l2u module configuration register l2u_rba[0] 792 11000 11000 0x0000_3180 supr region base address register 0 l2u_rba[1] 793 11000 11001 0x0000_3380 supr region base address register 1 l2u_rba[2] 794 11000 11010 0x0000_3580 supr region base address register 2 l2u_rba[3] 795 11000 11011 0x0000_3780 supr region base address register 3 l2u_ra[0] 824 11001 11000 0x0000_3190 supr region attribute register 0 l2u_ra[1] 825 11001 11001 0x0000_3390 supr region attribute register 1 l2u_ra[2] 826 11001 11010 0x0000_3590 supr region attribute register 2 l2u_ra[3] 827 11001 11011 0x0000_3790 supr region attribute register 3 l2u_gra 536 10000 11000 0x0000_3100 supr global region attribute table 11-6. hex address for spr cycles a[0:17] a[18:22] a[23:27] a[28:31] 0 spr[0:4] spr[5:9] 0 motorola chapter 11. l-bus to u-bus interface (l2u) 11-15 l2u programming model 11.8.3 l2u module configuration register (l2u_mcr) the l2u module configuration register (l2u_mcr) is used to control the l2u module operation. 11.8.4 region base address registers (l2u_rbax) the l2u region base address register (l2u_rbax) defines the base address of a specific region protected by the data memory protection unit. there are four registers (x = 0...3), one for each supported region. msb 0 123456789101112131415 sp lshow reserved reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved reset: 0000000000000000 figure 11-4. l2u_mcr ? l2u module configuration register spr 568 table 11-7. l2u_mcr bit descriptions bit(s) name description 0 sp sram protection (sp) bit is used to protect the sram on the l-bus from u-bus accesses. any attempt to set or clear the sp bit from the u-bus side has no affect. once this bit is set, the l2u blocks all sram accesses initiated by the u-bus masters and the access is terminated with a data error on the u-bus. if l-bus show cycles are enabled, setting this bit will disable l-bus sram show cycles. 1:2 lshow lshow bits are used to configure the show cycle mode for cycles accessing the l-bus slave e.g. sram 00 disable show cycles 01 show address and data of all l-bus space write cycles 10 reserved 11 show address and data of all l-bus space read and write cycles 3:31 ? reserved 11-16 mpc565/mpc566 reference manual motorola l2u programming model 11.8.5 region attribute registers (l2u_rax) each l2u region attribute register defines the protection attributes associated with a specific region protected by the data memory protection unit. there are four registers (x = 0...3), one for each supported region. msb 0 123456789101112131415 rba reset: xxxxxxxxxxxxxxxx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 rba reserved reset: xxxx000000000000 note: x = undefined figure 11-5. l2u_rbax ? l2u region x base address register spr 792 ? 795 table 11-8. l2u_rbax bit descriptions bit(s) name description 0:19 rba region base address. the rba field provides the base address of the region. the region base address should start on the block boundary for the corresponding block size attribute specified in the region attribute register (l2u_rax). 20:31 ? reserved msb 0 123456789101112131415 reserved rs reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 rs pp reserved g reserved reset: 0000000000000000 figure 11-6. l2u_rax ? l2u region x attribute register spr 824 ? 827 motorola chapter 11. l-bus to u-bus interface (l2u) 11-17 l2u programming model 11.8.6 global region attribute register (l2u_gra) the l2u global region attribute register (l2u_gra) defines the protection attributes associated with the memory region which is not protected under the four dmpu regions. this register also provides enable/disable control for the four dmpu regions. table 11-9. l2u_rax bit descriptions bit(s) name description 0:7 ? reserved 8:19 rs region size 0000_0000_0000 = 4 kbytes 0000_0000_0001 = 8 kbytes 0000_0000_0011 = 16 kbytes 0000_0000_0111 = 32 kbytes 0000_0000_1111 = 64 kbytes 0000_0001_1111 = 128 kbytes 0000_0011_1111 = 256 kbytes 0000_0111_1111 = 512 kbytes 0000_1111_1111 = 1 mbyte 0001_1111_1111 = 2 mbytes 0011_1111_1111 = 4 mbytes 0111_1111_1111 = 8 mbytes 1111_1111_1111 = 16 mbytes 20:21 pp protection bits 00 no supervisor access, no user access 01 supervisor read/write access, no user access 10 supervisor read/write access, user read-only access 11 supervisor read/write access, user read/write access 22:24 ? reserved 25 g guarded attribute 0 not guarded from speculative accesses 1 guarded from speculative accesses 26:31 ? reserved msb 0 123456789101112131415 enr0 enr1 enr2 enr3 reserved reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved pp reserved g reserved reset: 0000000000000000 figure 11-7. l2u_gra ? l2u global region attribute register spr 536 11-18 mpc565/mpc566 reference manual motorola l2u programming model table 11-10. l2u_gra bit descriptions bit(s) name description 0 enr0 enable attribute for region 0 0 region attribute is off 1 region attribute is on 1 enr1 enable attribute for region 1 0 region attribute is off 1 region attribute is on 2 enr2 enable attribute for region 2 0 region attribute is off 1 region attribute is on 3 enr3 enable attribute for region 3 0 region attribute is off 1 region attribute is on 4:19 ? reserved 20:21 pp protection bits 00 no supervisor access, no user access 01 supervisor read/write access, no user access 10 supervisor read/write access, user read-only access 11 supervisor read/write access, user read/write access 22:24 ? reserved 25 g guarded attribute 0 not guarded from speculative accesses 1 guarded from speculative accesses 26:31 ? reserved motorola chapter 12. u-bus to imb3 bus interface (uimb) 12-1 chapter 12 u-bus to imb3 bus interface (uimb) the u-bus to imb3 bus interface (uimb) structure is used to connect the cpu internal unified bus (u-bus) to the intermodule bus 3 (imb3). it controls bus communication between the u-bus and the imb3. the uimb interface (see figure 12-1) consists of seven submodules that control bus interface timing, address decode, data multiplexing, intrasystem communication (interrupts), and clock generation to allow communication between u-bus and the imb3. the seven submodules are: u-bus interface imb3 interface address decoder data multiplexer interrupt synchronizer clock control scan control 12.1 features provides complete interfacing between the u-bus and the imb3: ? 15 bits (32 kbytes) of address decode on imb3 ? 32-bit data bus ? read/write access to imb3 module registers ? interrupt synchronizer ? monitoring of accesses to unimplemented addresses within uimb interface address range ? burst-inhibited accesses to the modules on imb3 support of 32-bit and 16-bit bius for imb3 modules half and full speed operation of imb3 bus with respect to u-bus 12-2 mpc565/mpc566 reference manual motorola uimb block diagram simple ?slave only? u-bus interface implementation ? transparent mode operation not supported ? relinquish and retry not supported supports scan control for modules on the imb3 and on the u-bus note modules on the imb3 bus can only be reset by sreset . some modules may have a module reset, as well. warning the user should not perform instruction fetches from modules on the imb. 12.2 uimb block diagram figure 12-1. uimb interface module block diagram 12.3 clock module the clock module within the uimb interface generates the imb clock. the imb clock is the main timing reference used within the imb modules. the imb clock is generated based on the stop and hspeed bits in the uimb module configuration register (umcr). if the stop bit is 1, the imb clock is not generated. if the stop bit is 0 and the hspeed bit is 0, the imb clock is generated as the inversion of the internal system clock. this is the same frequency as the clkout if ebdf is 0b00 ? full address decode data mux interrupt synchronizer scan control u-bus interface imb3 interface clock control u-bus imb3 motorola chapter 12. u-bus to imb3 bus interface (uimb) 12-3 clock module speed external bus. (see figure 12-2.) if the hspeed bit is 1, then the imb clock is one-half of the internal system frequency. (see figure 12-3.) figure 12-2. imb clock ? full-speed imb bus figure 12-3. imb clock ? half-speed imb bus table 12-2 shows the number of system clock cycles that the uimb requires to perform each type of bus cycle. it is assumed in this table that the imb3 is available to the uimb at all times (fastest possible case). note the uimb interface dynamically interprets the port size of the addressed module during each bus cycle, allowing bus transfers to and from 16-bit and 32-bit imb modules. during a bus transaction, the slave module on the imb signals its port size (16- or 32-bit) via an internal port size signal. table 12-1. stop and hspeed bit functionality stop hspeed functionality 0 0 imb bus frequency is the same as u-bus frequency. 0 1 imb bus frequency is half that of the u-bus frequency. 1 x imb clock is not generated. table12-2.buscyclesandsystemclockcycles bus cycle (from u-bus transfer start to u-bus transfer acknowledge) number of system clock cycles full speed half speed normal write 4 6 normal read 4 6 dynamically-sized write 6 10 dynamically-sized read 6 10 imb clock clkout t1 t2 t3 t4 t1 t2 t3 t4 t1 t2 t3 t4 t1 t2 t3 t4 b4 b1 b2 b3 b4 b1 b2 b3 imb clock clkout t1 t2 t3 t4 t1 t2 t3 t4 t1 t2 t3 t4 t1 t2 t3 t4 b4 b1 b2 b3 12-4 mpc565/mpc566 reference manual motorola interrupt operation 12.4 interrupt operation the interrupts from the modules on the imb3 are propagated to the interrupt controller in the usiu through the uimb interface. the uimb interrupt synchronizer latches the interrupts from the imb3 and drives them onto the u-bus, where they are latched by the usiu interrupt controller. 1 12.4.1 interrupt sources and levels on imb the imb3 has eight interrupt lines. there can be a maximum of 32 levels of interrupts from the modules on imb bus. a single module can be a source for more than one interrupt. for example, the qsmcm can generate two interrupts (one for qsci1/qsci2 and another for qspi). in this case, the qsmcm has two interrupt sources. each of these two sources can assert the interrupt on any of the 32 levels. it is possible for multiple interrupt sources to assert the same interrupt level. to reduce the latency, it is a good practice for each interrupt source to assert an interrupt on a level on which no other interrupt source is mapped. 12.4.2 imb interrupt multiplexing the imb has 10 lines for interrupt support. eight lines are for interrupts and two are for interrupt level byte select (ilbs). these lines will transfer the 32 interrupt levels to the interrupt synchronizer. a diagram of the interrupt flow is shown in figure 12-4. figure 12-4. interrupt synchronizer signal flow 1 the mpc565/mpc566 includes an option for an enhanced interrupt controller. see section 6.4.4, ?enhanced interrupt controller? for operation details. uipend imb interrupt 8 block byte count byte-enables [24:31] [16:23] [8:15] [0:7] 8 to imb byte-enable 2 4 u-bus interrupt u-bus data[0:31] level[0:7] motorola chapter 12. u-bus to imb3 bus interface (uimb) 12-5 interrupt operation latching 32 interrupt levels using eight imb interrupt lines is accomplished with a 4:1 time-multiplexing scheme. the uimb drives two signals (ilbs[0:1]) with a multiplexer select code that tells all interrupting modules on the imb about which group of signals to drive during the next clock. see figure 12-5. 12.4.3 ilbs sequencing the imb interface drives the ilbs signals continuously, incrementing through a code sequence (0b00, 0b01, 0b10, 0b11) once every clock. the irqmux[0:1] bits in the imb module configuration register select which type of multiplexing the interrupt synchronizer will perform. the irqmux field can select time-multiplexing protocols for 8, 16, 24 or 32 interrupt sources. these protocols would take one, two, three or four clocks, respectively. table 12-3 shows ilbs sequencing. programming irqmux[0:1] to 0b00 disables time multiplexing. in this case the ilbs lines remain at 0b00 at all times. in this mode, no interrupts from imb modules which assert on levels 8 through 31 are ever latched by the interrupt synchronizer. time multiplexing is disabled during reset, and enabled as soon as reset is released unless the reset default value is 0b00. in that case time multiplexing remains disabled. the timing for the scheme and the values of ilbs and the interrupt levels driven onto the imb irq lines are shown in figure 12-5. this scheme causes a maximum latency of four clocks and an average latency of two clocks before the interrupt request can reach the interrupt synchronizer. note: this diagram represents the ilbs behavior when irqmux[0:1] = 11 figure 12-5. time-multiplexing protocol for irq pins table 12-3. ilbs signal functionality ilbs[0:1] description 00 imb interrupt sources mapped onto 0:7 levels will drive interrupts onto imb lvl[0:7] 01 imb interrupt sources mapped onto 8:15 levels will drive interrupts onto imb lvl[0:7] imb clock ilbs [0:1] imb lvl[0:7] lvl [0:7] 00 01 11 10 lvl [8:15] lvl 16:23 lvl 24:31 lvl 0:7 00 01 11 10 12-6 mpc565/mpc566 reference manual motorola interrupt operation the irqmux bits determine how many levels of imb interrupts are sampled. refer to table 12-4. . 12.4.4 interrupt synchronizer the interrupt synchronizer latches the 32 levels of interrupts from the imb bus into a register which can be read by the cpu or other u-bus master. since there are only eight lines for interrupts on the imb and 32 levels of interrupts are possible, the 32 interrupt levels are multiplexed onto eight imb interrupt lines. apart from latching these interrupts in the register (uipend register), the interrupt synchronizer drives the interrupts onto the u-bus, where they are latched by the interrupt controller in the usiu. if imb modules drive interrupts on any of the 24 levels (levels eight through 31), they will be latched in the interrupt pending register (uipend) in the uimb. if any of the register bits 7 to 31 are set, then bit 7 will be set as well. software must poll this register to find out which of the levels 7 to 31 are asserted. the uipend register contains a status bit for each of the 32 interrupt levels. each bit of the register is a read-only status bit, reflecting the current state of the corresponding interrupt signal. for each of the 32 interrupt levels, a corresponding bit of the uipend register is set. figure 12-4 shows how the eight interrupt lines are connected to the uipend register to represent 32 levels of interrupts. figure 12-6 shows the implementation of the interrupt synchronizer. 10 imb interrupt sources mapped onto 16:23 levels will drive interrupts onto imb lvl[0:7] 11 imb interrupt sources mapped onto 24:31 levels will drive interrupts onto imb lvl[0:7] table 12-4. irqmux functionality irqmux[0:1] ilbs sequence description 00 00, 00, 00..... latch 0:7 imb interrupt levels 01 00, 01, 00, 01.... latch 0:15 imb interrupt levels 10 00, 01, 10, 00, 01, 10,..... latch 0:23 imb interrupt levels 11 00, 01, 10, 11, 00, 01, 10, 11,.... latch 0:31 imb interrupt levels table 12-3. ilbs signal functionality (continued) ilbs[0:1] description motorola chapter 12. u-bus to imb3 bus interface (uimb) 12-7 programming model figure 12-6. interrupt synchronizer block diagram 12.5 programming model table 12-5 lists the registers used for configuring and testing the uimb module. the address offset shown in this table is from the start of the block reserved for uimb registers. as shown in figure 1-2, this block begins at offset 0x30 7f80 from the start of the mpc565/mpc566 internal memory map (the last 128-byte sub-block of the uimb interface memory map). table 12-5. uimb interface register map access 1 base address register s 0x30 7f80 uimb module configuration register (umcr) see table 12-6 for bit descriptions. ? 0x30 7f84 ? 0x30 7f8c reserved s/t 0x30 7f90 uimb test control register (utstcreg) reserved ? 0x30 7f94 ? 0x30 7f9c reserved s 0x30 7fa0 pending interrupt request register (uipend) see section 12.5.3, ?pending interrupt request register (uipend)? for bit descriptions. lvl [8:31] lvl[0:7] ilbs [0:1] state 4 imbclock uipend reset imb lvl [0:7] machine u-bus interrupt level[0:7] or 24 7 lvl7 8 u-bus 32 data[0:31] 12-8 mpc565/mpc566 reference manual motorola programming model any word, half-word or byte access to a 32-bit location within the uimb interface register decode block that is unimplemented (defined as reserved) causes the uimb interface to assert a data error exception on the u-bus.the entire 32-bit location must be defined as reserved in order for a data error exception to be asserted. unimplemented bits in a register return zero when read. 12.5.1 uimb module configuration register (umcr) the uimb module configuration register (umcr) is accessible in supervisor mode only. 1 s = supervisor mode only; t = test mode only msb 0 12 3 456789101112131415 stop irqmux hspeed reserved hreset: 000 1 000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved hreset: 000 0 000000000000 figure 12-7. umcr ? uimb module configuration register 0x30 7f80 table 12-6. umcr bit descriptions bit(s) name description 0 stop stop enable. 0 enable system clock for imb bus 1 disable imb system clock to avoid complications at restart and data corruption, system software must stop each slave on the imb before setting the stop bit. software must also ensure that all imb interrupts have been serviced before setting this bit. 1:2 irqmux interrupt request multiplexing. these bits control the multiplexing of the 32 possible interrupt requests onto the eight imb interrupt request lines. 00 disables the multiplexing scheme on the interrupt controller within this interface. what this means is that the imb irq [0:7] signals are non-multiplexed, only providing 8 [0:7] interrupt request lines to the interrupt controller 01 enables the imb irq control logic to perform a 2-to-1 multiplexing to allow transferring of 16 [0:15] interrupt sources 10 enables the imb irq control logic to perform a 3-to-1 multiplexing to allow transferring of 24 [0:23]interrupt sources 11 enables the imb irq control logic to perform a 4-to-1 multiplexing to allow transferring of 32 [0:31] interrupt sources motorola chapter 12. u-bus to imb3 bus interface (uimb) 12-9 programming model 12.5.2 test control register (utstcreg) the utstcreg register is used for factory testing only. 12.5.3 pending interrupt request register (uipend) the uipend register is a read-only status register which reflects the state of the 32 interrupt levels. the state of the irq[0] is shown in bit 0, the state of irq[1] is shown in bit 1 and so on. this register is accessible only in supervisor mode. 3 hspeed half speed. the hspeed bit controls the frequency at which the imb3 runs with respect to the u-bus. this is a modify-once bit. software can write the reset value of this bit any number of times. however, once logic 0 is written to this location, any attempt to rewrite this bit to a logic 1 will have no effect. 0 imb frequency is the same as that of the u-bus 1 imb frequency is one half that of the u-bus 4:31 ? reserved msb 0 123456789101112131415 lvl0 lvl1 lvl2 lvl3 lvl4 lvl5 lvl6 lvl7 lvl8 lvl9 lvl0 lvl11 lvl1 2 lvl1 3 lvl1 4 lvl1 5 hreset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 lvl1 6 lvl1 7 lvl1 8 lvl1 9 lvl2 0 lvl2 1 lvl2 2 lvl2 3 lvl2 4 lvl2 5 lvl2 6 lvl2 7 lvl2 8 lvl2 9 lvl3 0 lvl3 1 hreset: 0000000000000000 figure 12-8. uipend ? pending interrupt request register 0x30 7fa0 table 12-7. uipend bit descriptions bit(s) name description 0:31 lvlx pending interrupt request level. accessible only in supervisor mode. lvlx identifies the interrupt source as uimb lvlx, where x is the interrupt number. table 12-6. umcr bit descriptions (continued) bit(s) name description 12-10 mpc565/mpc566 reference manual motorola programming model motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-1 chapter 13 queued analog-to-digital converter (qadc64e) the two queued analog-to-digital converter (qadc) modules on mpc565/mpc566 are 10-bit, unipolar, successive approximation converters with analog multiplexers. these modules are configured so each module can access all 40 of the part?s analog inputs. for this revision of the qadc, the name qadc64e implies an enhanced version of the qadc64. for simplicity, the names qadc and qadc64e may be used interchangeably throughout this document. 13.1 features, overview and quick reference diagrams this section gives an overview of the implementation of the two qadc64e modules on mpc565/mpc566. it can also be used for a quick reference while programming the modules. 13.1.1 features of the qadc64e (each module) internal sample and hold up to 40 analog input channels using qadc64e multiplexing and amux multiplexing directly supports up to four external multiplexers (for example, the mc14051) up to 65 total input channels using qadc64e, amux, and external multiplexing supports amux without loss of port a and port b functionality programmable input sample time for various source impedances typical conversion time of less than 5 s (> 200k samples/s) modulus prescaler can divide the system clock for the converter by two to 128 two conversion command queues with a total of 64 entries sub-queues possible using pause mechanism queue complete and pause software interrupts available on both queues 13-2 mpc565/mpc566 reference manual motorola features, overview and quick reference diagrams queue pointers indicate current location for each queue automated queue modes initiated by: ? external edge trigger and gated trigger ? periodic/interval timer, within qadc64e module [queue 1 and 2] ? software command single-scan or continuous-scan of queues 64 result registers in each qadc64e output data readable in three formats: ? right-justified unsigned ? left-justified signed ? left-justified unsigned unused analog channels can be used as digital ports multi-module operation allows shared channels (in all queues) and shared clock for synchronization alternate reference input, with control in ccw 13.1.2 qadc64e block diagrams figure 13-1 displays the major components of the qadc64e modules on the mpc565/mpc566 including the pads, amux and both qadcs. figure 13-2 shows the sub-module arrangement of the qadc64e. motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-3 features, overview and quick reference diagrams figure 13-1. dual qadc64es on mpc565/mpc566 multi- port amux an[44:59] analog a/d inter- module bus interface control queue &port logic qadc64e module b multi- port amux vrh an[64]/b_pqb[0] an[65]/b_pqb[1] an[66]/b_pqb[2] an[67]/b_pqb[3] an[72]/b_ma[0]/pqa[0] an[73]/b_ma[1]/pqa[1] an[74]/b_ma[2]/pqa[2] an[77]/b_pqa[5] an[78]/b_pqa[6] an[59]/a_pqa[7] an[68]/b_pqb[4] an[69]/b_pqb[5] an[70]/b_pqb[6] an[71]/b_pqb[7] an[75]/b_pqa[3] an[76]/b_pqa[4] vrl vssa digital port functions: analog input external mux triggers altref vdda onchip amux an[44]/anw/a_pqb[0] an[45]/anx/a_pqb[1] an[46]/any/a_pqb[2] an[47]/anz/a_pqb[3] an[52]/a_ma[0]/pqa[0] an[53]/a_ma[1]/pqa[1] an[54]/a_ma[2]/pqa[2] an[57]/a_pqa[5] an[58]/a_pqa[6 ] an[48]/a_pqb[4] an[49]/a_pqb[5] an[50]/a_pqb[6] an[51]/a_pqb[7] an[55]/a_pqa[3] an[56]/a_pqa[4] an[79]/b_pqa[7] 46 16 analog power clock module a pad logic module b pad logic 4 (module specific) (module specific) amux pad logic an[80] an[87] ... 8 (both modules) (both modules) b_pqb[0:7] b_pqa[0:7] a_pqb[0:7] a_pqa[0:7] etrig1 etrig2 2 2 16 16 50 2 (both modules). imb3 & references 16 24 50 pads modules qadc64e module a amux an[64:87] ie oe mux & converter inter- module bus interface control queue &port logic an[44:59] analog a/d mux & converter amux an[64:87] module port port module 13-4 mpc565/mpc566 reference manual motorola features, overview and quick reference diagrams figure 13-2. block diagram of qadc64e the analog section includes input pins, an analog multiplexer, and the sample and hold circuits. the analog conversion is performed by the digital-to-analog converter (dac) resistor-capacitor array and a high-gain comparator. the digital control section contains queue control logic to sequence the conversion process and interrupt generation logic. also included are the periodic/interval timer, control and status registers, the conversion command word (ccw) table ram, and the result table ram. the bus interface unit (biu) allows the qadc64e to operate with the applications software through the imb environment. 13.1.3 memory map the qadc64e occupies one kbyte, or 512 16-bit entries, of address space. ten 16-bit registers are control, port, and status registers, 64 16-bit entries are the ccw table, and 64 16-bit entries are the result table, and occupy 192 16-bit address locations because the result data is readable in three data alignment formats. clock pqb[7] pqb[0] pqa[7] pqa[0] chan. mux mux 2: 1 cs+ 7-bit compar- successive port pqa port pqb result periodic/ cimb address addr data clock alignment decode i/o i/o timer 17: 1 ator rdac vrh vrl address decode result ta b l e ccw table 10-bit, 10-bit, 64-word ram 64-word ram cdac buffer amp prescaler approximation register 4-bit analog sequencer ccw etrig1 etrig2 port a/b ddr control registers & queue control logic result a/d converter convert control & biu port logic qclk eos/eoc wccw queue logic altref amux port multi- module port interval vdda vssa motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-5 features, overview and quick reference diagrams each qadc on mpc565/mpc566 has its own memory location. table 13-1 shows the memory map for qadc64e module a. module b has the same offset scheme starting at 0x30 4c00 (refer to table 13-2). qadc64e_a occupies 0x30 4800 to 0x30 4bff qadc64e_b occupies 0x30 4c00 to 0x30 4fff table 13-1. qadc64e_a address map address msb lsb register 0123456789101112131415 0x30 4800 stop frz -- supv mstr ext clk -- module config. 0x30 4802 test mode --- test 0x30 4804 irl1 irl2 -- interrupt 0x30 4806 portqa portqb port data 0x30 4808 ddrqa ddrqb port direction 0x30 480a emux --- trig -- qclk prescaler control 0 0x30 480c cie1 pie1 sse1 mq1 --- control 1 0x30 480e cie2 pie2 sse2 mq2 resu. bq2 control 2 0x30 4810 cf1 pf1 cf2 pf2 tor1 tor2 qs cwp status 0 0x30 4812 -- cwpq1 --- cwpq2 status 1 0x30 4814- 0x30 49ff --14 words reserved -- reserved 0x30 4a00- 0x30 4a7f -- p ref ist chan ccws 0x30 4a80- 0x30 4aff 0000 00 unsigned right justified results 0x30 4b00- 0x30 4b7f sign signed left justified 00 0000 results 0x30 4b80 0x30 4bff unsigned left justified 00 0000 results note: registers in bold are accessible only as supervisor data space 13-6 mpc565/mpc566 reference manual motorola features, overview and quick reference diagrams access to supervisor-only data space is permitted only when the bus master is operating in supervisor access mode. assignable data space can be either restricted to supervisor-only access or unrestricted to both supervisor and user data space addresses. see section 13.2.1.3, ?supervisor/unrestricted address space.? table 13-2. qadc64e_b address map address msb lsb register 0123456789101112131415 0x30 4c00 stop frz -- supv mstr ext clk -- module config. 0x30 4c02 test mode --- test 0x30 4c04 irl1 irl2 -- interrupt 0x30 4c06 portqa portqb port data 0x30 4c08 ddrqa ddrqb port direction 0x30 4c0a emux --- trig -- qclk prescaler control 0 0x30 4c0c cie1 pie1 sse1 mq1 --- control 1 0x30 4c0e cie2 pie2 sse2 mq2 resu. bq2 control 2 0x30 4c10 cf1 pf1 cf2 pf2 tor1 tor2 qs cwp status 0 0x30 4c12 -- cwpq1 --- cwpq2 status 1 0x30 4c14- 0x30 4dff --246 words reserved -- reserved 0x30 4e00- 0x30 4e7f -- p ref ist chan ccws 0x30 4e80- 0x30 4eff 0000 00 unsigned right justified results 0x30 4f00- 0x30 4f7f sign signed left justified 00 0000 results 0x30 4f80 0x30 4fff unsigned left justified 00 0000 results note: registers in bold are accessible only as supervisor data space motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-7 features, overview and quick reference diagrams 13.1.4 using the queue and result word table the heart of the qadc is its conversion command word (ccw) queues. this is where the module is programmed to convert a particular channel according to a particular requirement. the queues are created by writing ccws into the ccw table in the register memory. the queues are controlled by the three control registers, and their status can be read from status registers. as conversions are completed the digital value is written into the result word table. figure 13-3 shows the ccw queue and the result word table. note: these offsets must be added to the module base address: a = 0x30 4800 or b = 0x30 4c00. figure 13-3. ccw queue and result table block diagram 13.1.5 external multiplexing the qadc can use from one to four 8-input external multiplexer chips to expand the number of analog signals that may be converted. the externally multiplexed channels are automatically selected from the channel field of the conversion command word (ccw) table. the software selects the external multiplexed mode by setting the mux bit in control register 0 (qacr0). 0 7 815 conversion command word (ccw) table 0x200 (ccw0) bq2 x27e (ccw63) a/d converter result word table result 0 result 63 address offsets 0x280 0x2fe1 0x380 0x3fe1 0x380 0x3fe1 0 7 815 0 7 815 channel select, sample, hold, and analog to digital conversion begin queue 1 begin queue 2 end of queue 1 endofqueue2 p ref ist chan right justified, unsigned result format left justified, signed result format left justified, unsigned result format 000 000 000 000 s 000 000 result result result 10-bit conversion command word (ccw) format 10-bit result is software readable in 3 different 16-bit formats p = pause until next trigger ref = use alternate reference voltage ist = input sample time (0=2 clk, 1=16 clk) chan = channel number and end_of_queue code s = sign bit 13-8 mpc565/mpc566 reference manual motorola features, overview and quick reference diagrams figure 13-4 shows the maximum configuration of four external multiplexer chips connected to the qadc. the qadc provides three multiplexed address signals ? ma[0], ma[1], and ma[2], to select one of eight inputs. these inputs are connected to all four external multiplexer chips. the analog output of the four multiplex chips are each connected to four separate qadc inputs ? an w ,an x ,an y ,andan z . the qadc converts the proper input channel (an w , an x ,an y ,andan z ) by interpreting the ccw channel number. figure 13-4. example of external multiplexing in the external multiplexed mode, four of the port b pins are redefined to each represent eight input channels. refer to table 13-3 for more information. table 13-4 shows the total number of analog input channels supported with zero to four external multiplexer chips using one qadc module. table 13-3. multiplexed analog input channels multiplexed analog input channels anw (an[44]) channels from 0 to 7 anx (an[45]) channels from 8 to 15 any (an[46]) channels from 16 to 23 anz (an[47]) channels from 24 to 31 an[52]/ma[0]/pqa[0] an[53]/ma[1]/pqa[1] an[54]/ma[2]/pqa[2] an[55]/pqa[3] an[56]/pqa[4] an[57]pqa[5] an[58]/pqa[6] an[59]/pqa[7] an[44]/anx/pqb[0] an[45]/anx/pqb[1 ] an[46]/any/pqb[2 ] an[47]anz/pqb[3] an[48]/pqb[4] an[49]/pqb[5] an[50]/pqb[6] an[51]/pqb[7] v sse v dda v ssa v rl v rh mux an[0] an[1] an[2] an[3] an[4] an[5] an[6] an[7] mux an[8] an[9] an[10] an[11] an[12] an[13] an[14] an[15] mux an[16] an[17] an[18] an[19] an[20] an[21] an[22] an[23] mux an[24] an[25] an[26] an[27] an[28] an[29] an[30] an[31] analog power analog references external triggers port b port a etrig1 etrig2 altref qadc amux an[64] ? an[87] digital control analog converter analog multiplexer port logic and motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-9 programming the qadc64e registers note: qadc64e external mux users if either qadc64e_a or qadc64e_b is in external mux (emux) mode, an[44:47] (analog inputs) and an[52:54] and/or an[72:74] should not be programmed into queues as they will be emux input and address pins. if both qadc64e_a or qadc64e_b are in external mux mode, they independently control mux addresses, but share input pins so a total of four external multiplexers can be used, but each should be assigned to only a or b qadcs. each qadc module queue can only control external addresses that are controlled by its own ma[2:0] multiplexer address pins. 13.2 programming the qadc64e registers the qadc64e has three global registers for configuring module operation: the module configuration register (section 13.2.1, ?qadc64e module configuration register?), the interrupt register (section 13.2.2, ?qadc64e interrupt register?), and a test register (qadctest). the global registers are always defined to be in supervisor-only data space. refer to table 13-1 for the qadc64e_a address map and table 13-2 for the qadc64e_b address map. see section 13.2.1.3, ?supervisor/unrestricted address space? for access modes of these registers. the remaining five registers in the control register block control the operation of the queuing mechanism, and provide a means of monitoring the operation of the qadc64e. control register 0 (qacr0) contains hardware configuration information (section 13.2.5, ?control register 0?) control register 1 (qacr1) is associated with queue 1 (section 13.2.6, ?control register 1?) control register 2 (qacr2) is associated with queue 2 (section 13.2.7, ?control register 2?) status registers (qasr0 and qasr1) provide visibility on the status of each queue and the particular conversion that is in progress (section 13.2.8, ?status registers?) table 13-4. analog input channels number of analog input channels available directly connected + external multiplexed = total channels no external mux chips one external mux chip two external mux chips three external mux chips four external mux chips 40 36 + 8 = 44 35 + 16 = 51 34 + 24 = 58 33 + 32 = 65 13-10 mpc565/mpc566 reference manual motorola programming the qadc64e registers the ccw table follows the register block in the address map. there are 64 entries to hold the desired analog conversion sequences. each ccw is a 16-bit entry, with ten implemented bits in four fields. the final block of address space belongs to the result word table, which appears in three places in the memory map. each result word table location holds one 10-bit conversion value. 13.2.1 qadc64e module configuration register the qadcmcr contains fields and bits that control freeze and stop modes and determine the privilege level required to access most registers . msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 stop frz reserved supv mstr ext clk reserved reset: 0000 0 0001 0000000 figure 13-5. qadcmcr ? module configuration register 0x30 4800 0x30 4c00 table 13-5. qadcmcr bit descriptions bit(s) name description 0 stop stop enable ? refer to section 13.2.1.1, ?low power stop mode? for more information. 0 disable stop mode 1 enable stop mode 1 frz freeze enable ? refer to section 13.2.1.2, ?freeze mode? for more information. 0 ignores the imb internal freeze signal 1 finish any conversion in progress, then freeze 2:7 ? reserved 8 supv supervisor/unrestricted data space ? refer to section 13.2.1.3, ?supervisor/unrestricted address space? and table 13-6 for more information. 0 only the module configuration register, test register, and interrupt register are designated as supervisor-only data space.access to all other locations is unrestricted. 1 all qadc64e registers and ccw/result tables are designated as supervisor-only data space. 9 mstr master/slave operation ? refer to section 13.2.1.4, ?master/slave operation and multi-module synchronous clocks? for more information. 0 module is a slave, and qadcmcr extclk should be used to select the conversion clock source. 1 module is the master, and qadcmcr extclk should be left clear. 10 extclk external clock select ? 0 internal conversion clock derived from imb3 clock will be used for the converter and qadc periodic/interval timer. 1 internal conversion clock derived from a master qadc module (see mstr, bit 9). refer to section 13.2.1.4, ?master/slave operation and multi-module synchronous clocks.? 11:15 ? reserved. these bits are used for the iarb (interrupt arbitration id) field in qadc64e implementations that use hardware interrupt arbitration. these bits are not used on the mpc565/mpc566. motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-11 programming the qadc64e registers 13.2.1.1 low power stop mode when the stop bit in the qadcmcr is set, the qadc64e clock (qclk) which clocks the a/d converter, is disabled and the analog circuitry is powered down. this results in a static, low power consumption, idle condition. the stop mode aborts any conversion sequence in progress. because the bias currents to the analog circuits are turned off in stop mode, the qadc64e requires some recovery time (t sr in appendix e, ?electrical characteristics?) to stabilize the analog circuits after the stop enable bit is cleared. in stop mode: biu state machine and logic do not shut down the ram is not reset and is not accessible the module configuration register (qadcmcr), the interrupt register (qadcint), and the test register (qadctest) are fully accessible and are not reset the data direction register (ddrqa), port data register (portqa/portqb), and control register 0 (qacr0) are not reset and are read-only accessible control register 1 (qacr1), control register 2 (qacr2), and the status registers (qasr0 and qasr1) are reset and are read-only accessible in addition, the periodic/interval timer is held in reset during stop mode if the stop bit is clear, stop mode is disabled. 13.2.1.2 freeze mode freeze mode occurs when the background debug mode is enabled in the device integration module and a breakpoint is encountered. this is indicated by the assertion of the internal freeze line on the imb. the frz bit in the qadcmcr determines whether or not the qadc64e responds to an imb internal freeze signal assertion. freeze is very useful when debugging an application. when the internal freeze signal is asserted and the frz bit is set, the qadc64e finishes any conversion in progress and then freezes. depending on when the freeze signal is asserted, there are three possible queue "freeze" scenarios: when a queue is not executing, the qadc64e freezes immediately when a queue is executing, the qadc64e completes the conversion in progress and then freezes if, during the execution of the current conversion, the queue operating mode for the active queue is changed, or a queue 2 abort occurs, the qadc64e freezes immediately when the qadc64e enters the freeze mode while a queue is active, the current ccw location of the queue pointer is saved. 13-12 mpc565/mpc566 reference manual motorola programming the qadc64e registers during freeze, the analog clock, qclk, is held in reset and the periodic/interval timer is held in reset. external trigger events that occur during the freeze mode are not captured. the biu remains active to allow imb access to all qadc64e registers and ram. although the qadc64e saves a pointer to the next ccw in the current queue, the software can force the qadc64e to execute a different ccw by writing new queue operating modes for normal operation. the qadc64e looks at the queue operating modes, the current queue pointer, and any pending trigger events to decide which ccw to execute when exiting freeze. if the frz bit is clear, the internal freeze signal is ignored. 13.2.1.3 supervisor/unrestricted address space the qadc64e memory map is divided into two segments: supervisor-only data space and assignable data space. access to supervisor-only data space is permitted only when the software is operating in supervisor access mode. assignable data space can be either restricted to supervisor-only access or unrestricted to both supervisor and user data space accesses. the supv bit in the qadcmcr designates the assignable space as supervisor or unrestricted. the following information applies to accesses to address space located within the modules? 16-bit boundaries and where the response is a bus error. see table 13-6 for more information. attempts to read a supervisor-only data space when not in the supervisor access mode and supv = 1, causes the bus master to assert a bus error condition. no data is returned. if supv = 0, the qadc64e asserts a bus error condition and no data is returned, attempts to write supervisor-only when not in the supervisor access mode and supv = 1, causes the bus master to assert a bus error condition. no data is written. if supv = 0, the qadc64e asserts a bus error condition and the register is not written. attempts to read unimplemented data space in the unrestricted access mode and supv = 1, causes the bus master to assert a bus error condition and no data is returned. in all other attempts to read unimplemented data space, the qadc64e causes a bus error condition and no data is returned. attempts to write unimplemented data space in the unrestricted access mode and supv= 1, causes the bus master to assert a bus error condition and no data is written. in all other attempts to write unimplemented data space, the qadc64e causes a bus error condition and no data is written. motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-13 programming the qadc64e registers attempts to read assignable data space in the unrestricted access mode when the space is programmed as supervisor space causes the bus master to assert a bus error condition and no data is returned. attempts to write assignable data space in the unrestricted access mode when the space is programmed as supervisor space causes the bus master to assert a bus error condition and the register is not written. s/u = supervisor/unrestricted qadc64e bus error = caused by qadc64e master bus error = caused by bus master access to qadctest register will act as a reserved/unimplemented register unless in factory test mode the bus master indicates the supervisor and user space access with the function code bits (fc[2:0]) on the imb. for privilege violations, refer to the chapter 9, ?external bus interface? to determine the consequence of a bus error cycle termination. the supervisor-only data space segment contains the qadc64e global registers, which include the qadcmcr, the qadctest, and the qadcint. the supervisor/unrestricted space designation for the ccw table, the result word table, and the remaining qadc64e registers is programmable. 13.2.1.4 master/slave operation and multi-module synchronous clocks master/slave mode operation is controlled by two bits in the module configuration register. the first is qadcmcr mstr field, which, when set makes the module the master and causes that module?s conversion clock to be output on the slave clock input/output. if the qadcmcr mstr bit is cleared, then that module is set up as a slave. when set as a slave, the module?s qadcmcr extclk may be set, causing the module to use the slave clock signal input as the conversion clock. if a module is configured as a master, then the qadcmcr extclk bit should be set low. if a module is configured as a slave, then the qadcmcr extcclk bit may be left clear, in which case the module will operate off of the internal conversion clock, or it may be set, in which case the module will operate off of the slave clock input/output. table 13-6. qadc64e bus error response s/u mode supv bit supervisor-only register supervisor/ unrestricted register reserved/ unimplemented register u 0 qadc64e bus error valid access qadc64e bus error u 1 master bus error master bus error master bus error s 0 valid access valid access qadc64e bus error s 1 valid access valid access qadc64e bus error 13-14 mpc565/mpc566 reference manual motorola programming the qadc64e registers 13.2.2 qadc64e interrupt register qadcint specifies the priority level of qadc64e interrupt requests. the interrupt level for queue 1 and queue 2 may be different. the interrupt register is read/write accessible in supervisor data space only. the implemented interrupt register fields can be read and written, reserved bits read zero and writes have no effect. they are typically written once when the software initializes the qadc64e, and not changed afterwards. the qadc64e conditionally generates interrupts to the bus master via the imb irq signals. when the qadc64e sets a status bit assigned to generate an interrupt, the qadc64e drives the irq bus. the value driven onto irq[7:0] represents the interrupt level assigned to the interrupt source. under the control of ilbs, each interrupt request level is driven during the time multiplexed bus during one of four different time slots, with eight levels communicated per time slot. no hardware priority is assigned to interrupts. furthermore, if more than one source on a module requests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. figure 13-7 displays the interrupt levels on irq with ilbs. msb 0 1234567891011121314lsb 15 irl1 irl2 reserved reset: 0000000000000000 figure 13-6. qadcint ? qadc interrupt register0x30 4804 0x30 4c04 table 13-7. qadcint bit descriptions bit(s) name description 0:4 irl1 queue 1 interrupt request level ? the irl1 field establishes the queue 1 interrupt request level. the 00000 state provides a level 0 interrupt while 11111 provides a level 31 interrupt. all interrupts are presented on the imb. interrupt level priority software determines which level has the highest priority request. 5:9 irl2 queue 2 interrupt request level ? the irl2 field establishes the queue 2 interrupt request level. the 00000 state provides a level 0 interrupt while 11111 provides a level 31 interrupt. all interrupts are presented on the imb. interrupt level priority software determines which level has the highest priority request. 10:15 ? reserved. these bits are used for the iarb (interrupt arbitration id) field in qadc64e implementations that use hardware interrupt arbitration. these bits are not used on the mpc565/mpc566. motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-15 programming the qadc64e registers figure 13-7. interrupt levels on irq with ilbs 13.2.3 port data register qadc64e ports a and b are accessed through two 8-bit port data registers (portqa and portqb) in each qadc64e. port a pins are referred to as pqa[7:0] when used as a bidirectional 8-bit input/output port that may be used for general-purpose digital input signals or digital output signals. port a of module a can also be used for analog inputs (an[59:52]) and external multiplexer address outputs (ma[2:0]). module b port a pins are shared with an[79:72] and ma[2:0]. port b pins are referred to as pqb[7:0] when used as a bidirectional 8-bit input/output port that may be used for general-purpose digital input signals or digital output signals. data for pqb[7:0] is accessed in the lower half of the module a. port b can also be used for non-multiplexed (an[51:44]) and multiplexed portqb anw, anx, any, anz) analog inputs. module b port b is shared with analog inputs an[71:64]. during a port data register read, the actual value of the pin is reported when its corresponding bit in the data direction register defines the pin to be an input. when the data direction bit specifies the pin to be an output, the content of the port data register is read. portqa and portqb are not initialized by reset. imb clock ilbs [1:0] imb irq [7:0] irq 7:0 00 01 11 10 irq 15:8 irq 23:16 irq 31:24 irq 7:0 00 01 11 10 13-16 mpc565/mpc566 reference manual motorola programming the qadc64e registers 13.2.4 port data direction register the port data direction registers (ddrqa and ddrqb) are associated with the port a and port b digital i/o pins of each qadc64e module. refer to appendix e, ?electrical characteristics for more information. any bit set to one in this register configures the corresponding pin as an output. any bit cleared to zero in this register configures the corresponding pin as an input. the software is responsible for ensuring that ddr bits are not set to one on pins used for analog inputs. when the ddr bit is set to one and the pin is selected for analog conversion, the voltage sampled is that of the output digital driver as influenced by the load. note caution should be exercised when mixing digital and analog inputs. this should be isolated as much as possible. rise and fall times should be as large as possible to minimize ac coupling effects. there are two special cases to consider for the digital i/o port operation. when the mux (externally multiplexed) bit is set in qacr0, the data direction register settings are ignored for the bits corresponding to portqa[2:0], the three multiplexed address (ma[2:0]) output pins. the ma[2:0] pins are forced to be digital outputs, regardless of the data direction setting, and the multiplexed address outputs are driven. the data returned during msb 0 1234567891011121314lsb 15 pqa7 pqa6 pqa5 pqa4 pqa3 pqa2 pqa1 pqa0 pqb7 pqb6 pqb5 pqb4 pqb3 pqb2 pqb1 pqb0 reset: uuuuuuu uuuuu uuuu qadc64e_a analog channel: an59 an58 an57 an56 an55 an54 an53 an52 an51 an50 an49 an48 an47 an46 an45 an44 qadc64e_b analog channel: an79 an78 an77 an76 an75 an74 an73 an72 an71 an70 an69 an68 an67 an66 an65 an64 qadc64e_a and qadc64e_b multiplexed address outputs: ma2 ma1 ma0 qadc64e_a (only) multiplexed analog inputs: anz any anx anw figure 13-8. portqa ? port a data register 0x30 4806, 0x30 4c06 portqb ? port b data register 0x30 4807, 0x30 4c07 motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-17 programming the qadc64e registers a port data register read is the value of the multiplexed address latches which drive ma[2:0], regardless of the data direction setting. 13.2.5 control register 0 control register 0 is used to define whether external multiplexing is enabled, assign external triggers to the conversion queues and to sets up the qclk prescaler parameter field. all of the implemented control register fields can be read or written but reserved fields read zero and writes have no effect. typically, they are written once when software initializes the qadc64e and are not changed afterwards. msb 0 1234567891011121314lsb 15 ddq a7 ddq a6 ddq a5 ddq a4 ddq a3 ddq a2 ddq a1 ddq a0 ddq b7 ddq b6 ddq b5 ddq b4 ddq b3 ddq b2 ddq b1 ddqb 0 reset: 0000000000000000 figure 13-9. ddrqa ? port a data direction register 0x30 4808, 0x30 4c08 ddrqb ? port b data direction register 0x30 4809, 0x30 4c09 msb 0 1234567891011121314lsb 15 mux reserved trg reserved prescaler reset: 0000000000010011 figure 13-10. qacr0 ? control register 0 0x30 480a, 0x30 4c0a table 13-8. qacr0 bit descriptions bit(s) name description 0 mux externally multiplexed mode ? the mux bit allows the software to select the externally multiplexed mode, which affects the interpretation of the channel numbers and forces the ma[0], ma[1] and ma[2] pins to be outputs. 0 internally multiplexed, 40 possible channels 1 externally multiplexed, up to 65 possible channels see table 13-4 1:2 ? reserved 3 trg trigger assignment ? the trg bit allows the software to assign the etrig[2:1] pins to queue 1 and queue 2.refer to section 13.6.2, ?external trigger input pins.? 0 etrig[1] triggers queue 1, etrig[2] triggers queue 2 1 etrig[1] triggers queue 2, etrig[2] triggers queue 1 13-18 mpc565/mpc566 reference manual motorola programming the qadc64e registers table 13-9 displays the bits in prescaler field which enable a range of qclk frequencies 4:8 ? reserved 9:15 prescaler prescaler value ? the prescaler value determines the qclk frequency (f qclk ). refer to appendix e, ?electrical characteristics for more information on the maximum qadc64e operating clock frequency (f qclk ). f qclk can range from 2 to 128 system clock cycles (f sysclk ). to keep f qclk within the specified range, the value of prescaler+1 is the f sysclk divisor. refer to section 13.4.5, ?qadc64e clock (qclk) generation? for more information on selecting a prescaler value. table 13-9. prescaler f sysclk divide-by values prescaler [6:0] f sysclk div prescaler [6:0] f sysclk div prescaler [6:0] fsysclk div prescaler [6:0] f sysclk div 0000000 2 0100000 33 1000000 65 1100000 97 0000001 2 0100001 34 1000001 66 1100001 98 0000010 3 0100010 35 1000010 67 1100010 99 0000011 4 0100011 36 1000011 68 1100011 100 0000100 5 0100100 37 1000100 69 1100100 101 0000101 6 0100101 38 1000101 70 1100101 102 0000110 7 0100110 39 1000110 71 1100110 103 0000111 8 0100111 40 1000111 72 1100111 104 0001000 9 0101000 41 1001000 73 1101000 105 0001001 10 0101001 42 1001001 74 1101001 106 0001010 11 0101010 43 1001010 75 1101010 107 0001011 12 0101011 44 1001011 76 1101011 108 0001100 13 0101100 45 1001100 77 1101100 109 0001101 14 0101101 46 1001101 78 1101101 110 0001110 15 0101110 47 1001110 79 1101110 111 0001111 16 0101111 48 1001111 80 1101111 112 0010000 17 0110000 49 1010000 81 1110000 113 0010001 18 0110001 50 1010001 82 1110001 114 0010010 19 0110010 51 1010010 83 1110010 115 0010011 20 0110011 52 1010011 84 1110011 116 0010100 21 0110100 53 1010100 85 1110100 117 0010101 22 0110101 54 1010101 86 1110101 118 0010110 23 0110110 55 1010110 87 1110110 119 table 13-8. qacr0 bit descriptions (continued) bit(s) name description motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-19 programming the qadc64e registers 13.2.6 control register 1 control register 1 is the mode control register for the operation of queue 1. the applications software defines the queue operating mode for the queue, and may enable a completion and/or pause interrupt. all of the control register fields are read/write data. however, the sse1 bit always reads as zero unless the test mode is enabled. most of the bits are typically written once when the software initializes the qadc64e, and not changed afterwards. 0010111 24 0110111 56 1010111 88 1110111 120 0011000 25 0111000 57 1011000 89 1111000 121 0011001 26 0111001 58 1011001 90 1111001 122 0011010 27 0111010 59 1011010 91 1111010 123 0011011 28 0111011 60 1011011 92 1111011 124 0011100 29 0111100 61 1011100 93 1111100 125 0011101 30 0111101 62 1011101 94 1111101 126 0011110 31 0111110 63 1011110 95 1111110 127 0011111 32 0111111 64 1011111 96 1111111 128 msb 0 1234567891011121314lsb 15 cie1 pie1 sse1 mq1 reserved reset: 0000000000000000 figure 13-11. qacr1 ? control register 1 0x30 480c, 0x30 4c0c table 13-10. qacr1 bit descriptions bit(s) name description 0 cie1 queue 1 completion interrupt enable ? cie1 enables an interrupt upon completion of queue 1. the interrupt request is initiated when the conversion is complete for the ccw in queue 1. 0 disable the queue completion interrupt associated with queue 1 1 enable an interrupt after the conversion of the sample requested by the last ccw in queue 1 1 pie1 queue 1 pause interrupt enable ? pie1 enables an interrupt when queue 1 enters the pause state. the interrupt request is initiated when conversion is complete for a ccw that has the pause bit set. 0 disable the pause interrupt associated with queue 1 1 enable an interrupt after the conversion of the sample requested by a ccw in queue 1 which has the pause bit set table 13-9. prescaler f sysclk divide-by values (continued) prescaler [6:0] f sysclk div prescaler [6:0] f sysclk div prescaler [6:0] fsysclk div prescaler [6:0] f sysclk div 13-20 mpc565/mpc566 reference manual motorola programming the qadc64e registers 2 sse1 queue 1 single-scan enable bit ? sse1 enables a single-scan of queue 1 to start after a trigger event occurs. the sse1 bit may be set to a one during the same write cycle when the mq1 bits are set for one of the single-scan queue operating modes the single-scan enable bit can be written as a one or a zero, but is always read as a zero, unless a test mode is selected. the sse1 bit enables a trigger event to initiate queue execution for any single-scan operation on queue 1. the qadc64e clears the sse1 bit when the single-scan is complete. refer to table 13-11 for more information. 0 trigger events are not accepted for single-scan modes 1 accept a trigger event to start queue 1 in a single-scan mode 3:7 mq1 queue 1 operating mode ? the mq1 field selects the queue operating mode for queue 1. table 13-11 shows the bits in the mq1 field which enable different queue 1 operating mode 8:15 ? reserved table 13-11. queue 1 operating modes mq1[3:7] operating modes 00000 disabled mode, conversions do not occur 00001 software triggered single-scan mode (started with sse1) 00010 external trigger rising edge single-scan mode 00011 external trigger falling edge single-scan mode 00100 interval timer single-scan mode: time = qclk period x 2 7 00101 interval timer single-scan mode: time = qclk period x 2 8 00110 interval timer single-scan mode: time = qclk period x 2 9 00111 interval timer single-scan mode: time = qclk period x 2 10 01000 interval timer single-scan mode: time = qclk period x 2 11 01001 interval timer single-scan mode: time = qclk period x 2 12 01010 interval timer single-scan mode: time = qclk period x 2 13 01011 interval timer single-scan mode: time = qclk period x 2 14 01100 interval timer single-scan mode: time = qclk period x 2 15 01101 interval timer single-scan mode: time = qclk period x 2 16 01110 interval timer single-scan mode: time = qclk period x 2 17 01111 external gated single-scan mode (started with sse1) 10000 reserved mode 10001 software triggered continuous-scan mode 10010 external trigger rising edge continuous-scan mode 10011 external trigger falling edge continuous-scan mode 10100 periodic timer continuous-scan mode: time = qclk period x 2 7 10101 periodic timer continuous-scan mode: time = qclk period x 2 8 table 13-10. qacr1 bit descriptions (continued) bit(s) name description motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-21 programming the qadc64e registers 13.2.7 control register 2 control register 2 is the mode control register for the operation of queue 2. software specifies the queue operating mode of queue 2, and may enable a completion and/or a pause interrupt. all control register fields are read/write data, except the sse2 bit, which is readable only when the test mode is enabled. most of the bits are typically written once when the software initializes the qadc64e, and not changed afterwards. 10110 periodic timer continuous-scan mode: time = qclk period x 2 9 10111 periodic timer continuous-scan mode: time = qclk period x 2 10 11000 periodic timer continuous-scan mode: time = qclk period x 2 11 11001 periodic timer continuous-scan mode: time = qclk period x 2 12 11010 periodic timer continuous-scan mode: time = qclk period x 2 1 11011 periodic timer continuous-scan mode: time = qclk period x 2 14 11100 periodic timer continuous-scan mode: time = qclk period x 2 15 11101 periodic timer continuous-scan mode: time = qclk period x 2 16 11110 periodic l timer continuous-scan mode: time = qclk period x 2 17 11111 external gated continuous-scan mode msb 0 1234567 8 91011121314lsb 15 cie2 pie2 sse2 mq2 resume bq2 reset: 00000000 0 1111111 figure 13-12. qacr2 ? control register 2 0x30 480e, 0x30 4c0e table 13-12. qacr2 bit descriptions bit(s) name description 0 cie2 queue 2 completion software interrupt enable ? cie2 enables an interrupt upon completion of queue 2. the interrupt request is initiated when the conversion is complete for the ccw in queue 2. 0 disable the queue completion interrupt associated with queue 2 1 enable an interrupt after the conversion of the sample requested by the last ccw in queue 2 1 pie2 queue 2 pause software interrupt enable ? pie2 enables an interrupt when queue 2 enters the pause state. the interrupt request is initiated when conversion is complete for a ccw that has the pause bit set. 0 disable the pause interrupt associated with queue 2 1 enable an interrupt after the conversion of the sample requested by a ccw in queue 2 which has the pause bit set table 13-11. queue 1 operating modes (continued) mq1[3:7] operating modes 13-22 mpc565/mpc566 reference manual motorola programming the qadc64e registers table 13-13 shows the bits in the mq2 field which enable different queue 2 operating modes. 2 sse2 queue 2 single-scan enable bit ? sse2 enables a single-scan of queue 2 to start after a trigger event occurs. the sse2 bit may be set to a one during the same write cycle when the mq2 bits are set for one of the single-scan queue operating modes. the single-scan enable bit can be written as a one or a zero, but is always read as a zero, unless a test mode is selected. the sse2 bit enables a trigger event to initiate queue execution for any single-scan operation on queue 2. the qadc64e clears the sse2 bit when the single-scan is complete. refer to table 13-13 for more information. 0 trigger events are not accepted for single-scan modes 1 accept a trigger event to start queue 2 in a single-scan mode 3:7 mq2 queue 2 operating mode ? the mq2 field selects the queue operating mode for queue 2. refer to table 13-13 for more information. 8 resume 0 after suspension, begin executing with the first ccw in queue 2 or the current sub-queue 1 after suspension, begin executing with the aborted ccw in queue 2 9:15 bq2 beginning of queue 2 ? the bq2 field indicates the ccw location where queue 2 begins. to allow the length of queue 1 and queue 2 to vary, a programmable pointer identifies the ccw table location where queue 2 begins. the bq2 field also serves as an end-of-queue condition for queue 1. setting bq2 beyond physical ccw table memory space allows queue 1 all 64 entries. software defines the beginning of queue 2 by programming the bq2 field in qacr2. bq2 is usually programmed before or at the same time as the queue operating mode for queue 2 is selected. if bq2 is 64 or greater, queue 2 has no entries, and the entire ccw table is dedicated to queue 1 and ccw63 is the end-of-queue 1. if bq2 is zero, the entire ccw table is dedicated to queue 2. as a special case, when a queue operating mode for queue 1 is selected and a trigger event occurs for queue 1 with bq2 set to zero, queue 1 execution is terminated after ccw0 is read. conversions do not occur. the bq2 pointer may be changed dynamically, to alternate between queue 2 scan sequences. a change in bq2 after queue 2 has begun or if queue 2 has a trigger pending does not affect queue 2 until queue 2 is started again.for example, two scan sequences could be defined as follows: the first sequence starts at ccw10, with a pause after ccw11 and an eoq programmed in ccw15; the second sequence starts at ccw16, with a pause after ccw17 and an eoq programmed in ccw39. with bq2 set to ccw10 and the continuous-scan mode selected, queue execution begins. when the pause is encountered in ccw11, a software interrupt routine can redefine bq2 to be ccw16. therefore, after the end-of-queue is recognized in ccw15, an internal retrigger event is generated and execution restarts at ccw16. when the pause software interrupt occurs again, software can change bq2 back to ccw10. after the end-of-queue is recognized in ccw39, an internal retrigger event is created and execution now restarts at ccw10. if bq2 is changed while queue 1 is active, the effect of bq2 as an end-of-queue indication for queue 1 is immediate. however, beware of the risk of losing the end-of-queue 1 through moving bq2. recommend use of eoq (chan63) to end queue 1. table 13-13. queue 2 operating modes mq2[3:7] operating modes 00000 disabled mode, conversions do not occur 00001 software triggered single-scan mode (started with sse2) 00010 external trigger rising edge single-scan mode 00011 external trigger falling edge single-scan mode table 13-12. qacr2 bit descriptions (continued) bit(s) name description motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-23 programming the qadc64e registers note if bq2 was assigned to the ccw that queue 1 is currently working on, then that conversion is completed before bq2 takes effect. each time a ccw is read for queue 1, the ccw location is compared with the current value of the bq2 pointer to detect a possible end-of-queue condition. for example, if bq2 is changed to ccw3 while queue 1 is converting ccw2, queue 1 is terminated after the conversion is completed. however, if bq2 is changed to ccw1 while queue 1 is converting ccw2, the qadc64e would not recognize a bq2 end-of-queue condition until queue 1 execution reached ccw1 again, presumably on the next pass through the queue. 00100 interval timer single-scan mode: time = qclk period x 2 7 00101 interval timer single-scan mode: time = qclk period x 2 8 00110 interval timer single-scan mode: time = qclk period x 2 9 00111 interval timer single-scan mode: time = qclk period x 2 10 01000 interval timer single-scan mode: time = qclk period x 2 11 01001 interval timer single-scan mode: time = qclk period x 2 12 01010 interval timer single-scan mode: time = qclk period x 2 13 01011 interval timer single-scan mode: time = qclk period x 2 14 01100 interval timer single-scan mode: time = qclk period x 2 15 01101 interval timer single-scan mode: time = qclk period x 2 16 01110 interval timer single-scan mode: time = qclk period x 2 17 01111 reserved mode 10000 reserved mode 10001 software triggered continuous-scan mode 10010 external trigger rising edge continuous-scan mode 10011 external trigger falling edge continuous-scan mode 10100 periodic timer continuous-scan mode: time = qclk period x 2 7 10101 periodic timer continuous-scan mode: time = qclk period x 2 8 10110 periodic timer continuous-scan mode: time = qclk period x 2 9 10111 periodic timer continuous-scan mode: time = qclk period x 2 10 11000 periodic timer continuous-scan mode: time = qclk period x 2 11 11001 periodic timer continuous-scan mode: time = qclk period x 2 12 11010 periodic timer continuous-scan mode: time = qclk period x 2 13 11011 periodic timer continuous-scan mode: time = qclk period x 2 14 11100 periodic timer continuous-scan mode: time = qclk period x 2 15 11101 periodic timer continuous-scan mode: time = qclk period x 2 16 11110 periodic timer continuous-scan mode: time = qclk period x 2 17 11111 reserved mode table 13-13. queue 2 operating modes (continued) mq2[3:7] operating modes 13-24 mpc565/mpc566 reference manual motorola programming the qadc64e registers 13.2.8 status registers the status registers contains information about the state of each queue and the current a/d conversion. except for the four flag bits (cf1, pf1, cf2, and pf2) and the two trigger overrun bits (tor1 and tor2), all of the status register fields contain read-only data. the four flag bits and the two trigger overrun bits are cleared by writing a zero to the bit after the bit was previously read as a one. msb 0 1234567891011121314lsb 15 cf1 pf1 cf2 pf2 tor1 tor2 qs cwp reset: 0000000000000000 figure 13-13. qasr0 ? status register 0 0x30 4810, 0x30 4c10 table 13-14. pause response scan mode q operation pf asserts? external trigger single-scan pauses yes external trigger continuous-scan pauses yes periodic/interval timer trigger single-scan pauses yes periodic/interval timer continuous-scan pauses yes software initiated single-scan continues yes software initiated continuous-scan continues yes external gated single-scan continues no external gated continuous-scan continues no table 13-15. queue status qs[9:6] queue 1/queue 2 states 0000 queue 1 idle, queue 2 idle 0001 queue 1 idle, queue 2 paused 0010 queue 1 idle, queue 2 active 0011 queue 1 idle, queue 2 trigger pending 0100 queue 1 paused, queue 2 idle 0101 queue 1 paused, queue 2 paused 0110 queue 1 paused, queue 2 active 0111 queue 1 paused, queue 2 trigger pending 1000 queue 1 active, queue 2 idle 1001 queue 1 active, queue 2 paused motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-25 programming the qadc64e registers one or both queues may be in the idle state. when a queue is idle, ccws are not being executed for that queue, the queue is not in the pause state, and there is not a trigger pending. the idle state occurs when a queue is disabled, when a queue is in a reserved mode, or when a queue is in a valid queue operating mode awaiting a trigger event to initiate queue execution. a queue is in the active state when a valid queue operating mode is selected, when the selected trigger event has occurred, or when the qadc64e is performing a conversion specified by a ccw from that queue. only one queue can be active at a time. either or both queues can be in the paused state. a queue is paused when the previous ccw executed from that queue had the pause bit set. the qadc64e does not execute any ccws from the paused queue until a trigger event occurs. consequently, the qadc64e can service queue 2 while queue 1 is paused. only queue 2 can be in the suspended state. when a trigger event occurs on queue 1 while queue 2 is executing, the current queue 2 conversion is aborted. the queue 2 status is reported as suspended. queue 2 transitions back to the active state when queue 1 becomes idle or paused. a trigger pending state is required since both queues cannot be active at the same time. the status of queue 2 is changed to trigger pending when a trigger event occurs for queue 2 while queue 1 is active. in the opposite case, when a trigger event occurs for queue 1 while queue 2 is active, queue 2 is aborted and the status is reported as queue 1 active, queue 2 suspended. so due to the priority scheme, only queue 2 can be in the trigger pending state. there are two transition cases which cause the queue 2 status to be trigger pending before queue 2 is shown to be in the active state. when queue 1 is active and there is a trigger pending on queue 2, after queue 1 completes or pauses, queue 2 continues to be in the trigger pending state for a few clock cycles. the following are fleeting status conditions: queue 1 idle with queue 2 trigger pending queue 1 paused with queue 2 trigger pending 1010 queue 1 active, queue 2 suspended 1011 queue 1 active, queue 2 trigger pending 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 13-15. queue status (continued) qs[9:6] queue 1/queue 2 states 13-26 mpc565/mpc566 reference manual motorola programming the qadc64e registers figure 13-14 displays the status conditions of the queue status field as the qadc64e goes through the transition from queue 1 active to queue 2 active. figure 13-14. qadc64e queue status transition the queue status field is affected by the stop mode. since all of the analog logic and control registers are reset, the queue status field is reset to queue 1 idle, queue 2 idle. during the freeze mode, the queue status field is not modified. the queue status field retains the status it held prior to freezing. as a result, the queue status can show queue 1 active, queue 2 idle, even though neither queue is being executed during freeze. msb 0 1234567891011121314lsb 15 reserved cwpq1 reserved cwpq2 reset: 0011111100111111 figure 13-15. qasr1 ? status register 1 0x30 4812, 0x30 4c12 queue 1 queue 2 trigger pending trigger pending active idle active active idle (paused) idle (paused) motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-27 programming the qadc64e registers 13.2.9 conversion command word table the conversion command word (ccw) table is a ram, 64 words long on 16-bit address boundaries where 10-bits of each entry are implemented. a ccw can be programmed by the software to request a conversion of one analog input channel. the ccw table is written by software and is not modified by the qadc64e. each ccw requests the conversion of an analog channel to a digital result. the ccw specifies the analog channel number, the input sample time, and whether the queue is to pause after the current ccw. the ten implemented bits of the ccw word are read/write data, where they may be written when the software initializes the qadc64e. the remaining 6-bits are unimplemented so these read as zeros, and write operations have no effect. each location in the ccw table corresponds to a location in the result word table. when a conversion is completed for a ccw entry, the 10-bit result is written in the corresponding result word entry. the qadc64e provides 64 ccw table entries. the beginning of queue 1 is the first location in the ccw table. the first location of queue 2 is specified by the beginning of queue 2 pointer (bq2) in qacr2. to dedicate the entire ccw table to queue 1, queue 2 is programmed to be in the disabled mode, and bq2 is programmed to 64 or greater. to dedicate the entire ccw table to queue 2, queue 1 is programmed to be in the disabled mode, and bq2 is specified as the first location in the ccw table table 13-16. qasr1 bit descriptions bit(s) name description 0:1 ? reserved 2:7 cwpq1 command word pointer for q1 ? cwpq1 allows the software to know what ccw was last completed for queue 1 this field is a software read-only field, and write operations have no effect. cwpq1 allows software to read the last executed ccw in queue 1, regardless of which queue is active the cwpq1 field is a ccw word pointer with a valid range of 0 to 63. in contrast to cwp, cpwq1 is updated when the conversion result is written when the qadc64e finishes a conversion in queue 1, both the result register is written and the cwpq1 are updated finally, when queue 1 operation is terminated after a ccw is read that is defined as bq2, cwp points to bq2 while cwpq1 points to the last ccw queue 1 during the stop mode, the cwpq1 is reset to 63, since the control registers and the analog logic are reset.when the freeze mode is entered, the cwpq1 is unchanged; it points to the last executed ccw in queue 1. 8:9 ? reserved 10:15 cwpq2 command word pointer for q2 ? cwpq2 allows the software to know what ccw was last completed for queue 2 this field is a software read-only field, and write operations have no effect. cwpq2 allows software to read the last executed ccw in queue 2, regardless which queue is active the cwpq2 field is a ccw word pointer with a valid range of 0 to 63. in contrast to cwp, cpwq2 is updated when the conversion result is written when the qadc64e finishes a conversion in queue 2, both the result register is written and the cwpq2 are updated during the stop mode, the cwpq2 is reset to 63, since the control registers and the analog logic are reset when the freeze mode is entered, the cwp is unchanged; it points to the last executed ccw in queue 2 13-28 mpc565/mpc566 reference manual motorola programming the qadc64e registers figure 13-16 illustrates the operation of the queue structure. figure 13-16. qadc64e conversion queue operation to prepare the qadc64e for a scan sequence, the software writes to the ccw table to specify the desired channel conversions. the software also establishes the criteria for initiating the queue execution by programming the queue operating mode. the queue operating mode determines what type of trigger event causes queue execution to begin. a ?trigger event? is used to refer to any of the ways to cause the qadc64e to begin executing the ccws in a queue or sub-queue. an ?external trigger? is only one of the possible ?trigger events.? a scan sequence may be initiated by the following: a software command expiration of the periodic/interval timer external trigger signal external gated signal (queue 1 only) result word tab l e 0x27e (ccw63) bq2 conversion command word (ccw) table 10 bit result s result 0 right justified, unsigned result format left justified, unsigned result format left justified, signed result format 15 0 15 0 s= sign bit result 15 0 begin queue 2 0x200 (ccw0) begin queue 1 end of queue 1 end of queue 2 conversion command word (ccw) format 10-bit result is software readable in 3 different 16-bit formats 00 00 0 000 00 0 000 00 0 8 7 8 7 8 7 15 6 7 89 address offsets 0x280 0x2fe1 0x300 0x37e1 0x3800 0x3fe1 result 0 result 63 a/d converter chan ist p ref channel select, sample, hold, and analog to digital conversion note 1: these offsets must be added to the module base address: a = 0x30 4800 or b = 0x30 4c00. p = pause until next trigger ref = use alternate reference voltage ist = input sample time (0=2 clk, 1=16 clk) chan = channel number (0-62), (64-87), and end-of-queue code (63 or 127) motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-29 programming the qadc64e registers the software also specifies whether the qadc64e is to perform a single pass through the queue or is to scan continuously. when a single-scan mode is selected, the software selects the queue operating mode and sets the single-scan enable bit. when a continuous-scan mode is selected, the queue remains active in the selected queue operating mode after the qadc64e completes each queue scan sequence. during queue execution, the qadc64e reads each ccw from the active queue and executes conversions in three stages: initial sample final sample resolution during initial sample, a buffered version of the selected input channel is connected to the sample capacitor at the input of the sample buffer amplifier. during the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges the sample capacitor directly. each ccw specifies a final input sample time of two or 16 qclk cycles. when an analog-to-digital conversion is complete, the result is written to the corresponding location in the result word table. the qadc64e continues to sequentially execute each ccw in the queue until the end of the queue is detected or a pause bit is found in a ccw. when the pause bit is set in the current ccw, the qadc64e stops execution of the queue until a new trigger event occurs. the pause status flag bit is set, which may cause an interrupt to notify the software that the queue has reached the pause state. after the trigger event occurs, the paused state ends and the qadc64e continues to execute each ccw in the queue until another pause is encountered or the end of the queue is detected. the following indicate the end-of-queue condition: the ccw channel field is programmed with 63 (0x3f) or 127 (0x7f) to specify the end of the queue the end-of-queue 1 is implied by the beginning of queue 2, which is specified in the bq2 field in qacr2 the physical end of the queue ram space defines the end of either queue when any of the end-of-queue conditions is recognized, a queue completion flag is set, and if enabled, an interrupt is issued to the software. the following situations prematurely terminate queue execution: since queue 1 is higher in priority than queue 2, when a trigger event occurs on queue 1 during queue 2 execution, the execution of queue 2 is suspended by aborting the execution of the ccw in progress, and the queue 1 execution begins. when queue 1 execution is completed, queue 2 conversions restart with the first ccw entry in queue 2 or the first ccw of the queue 2 sub-queue being executed when queue 2 was suspended. alternately, conversions can restart with the aborted queue 13-30 mpc565/mpc566 reference manual motorola programming the qadc64e registers 2 ccw entry. the resume bit in qacr2 allows the software to select where queue 2 begins after suspension. by choosing to re-execute all of the suspended queue 2 queue and sub-queue ccws, all of the samples are guaranteed to have been taken during the same scan pass. however, a high trigger event rate for queue 1 can prohibit the completion of queue 2. if this occurs, the software may choose to begin execution of queue 2 with the aborted ccw entry. software can change the queue operating mode to disabled mode. any conversion in progress for that queue is aborted. putting a queue into the disabled mode does not power down the converter. software can change the queue operating mode to another valid mode. any conversion in progress for that queue is aborted. the queue restarts at the beginning of the queue, once an appropriate trigger event occurs. for low power operation, software can set the stop mode bit to prepare the module for a loss of clocks. the qadc64e aborts any conversion in progress when the stop mode is entered. when the freeze enable bit is set by software and the imb internal freeze line is asserted, the qadc64e freezes at the end of the conversion in progress. when internal freeze is negated, the qadc64e resumes queue execution beginning with the next ccw entry. refer to section 13.4.7, ?configuration and control using the imb interface ? for more information. msb 0 1234567891011121314lsb 15 reserved p ref ist chan[6:0] reset: uuuuuuuuuuuuuuuu figure 13-17. ccw ? conversion command word table 0x30 4a00 ? 0x30 4a7f, 0x30 4e00 ? 0x30 4e7f table 13-17. ccw bit descriptions bit(s) name description 0:5 ? reserved 6 p pause ? the pause bit allows software to create sub-queues within queue 1 and queue 2. the qadc64e performs the conversion specified by the ccw with the pause bit set, and then the queue enters the pause state. another trigger event causes execution to continue from the pause to the next ccw 0 do not enter the pause state after execution of the current ccw 1 enter the pause state after execution of the current ccw note: the pause bit will not cause the queue to pause in the software controlled modes or external gated modes. motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-31 programming the qadc64e registers 7 ref alternate reference enabled ? setting ref high in the ccw enables the use of an alternate reference. 0 vrh is used as high reference 1 altref pin is used as the high reference 8 ist input sample time ? the ist field allows software to specify the length of the sample window. provision is made to vary the input sample time, through software control, to offer flexibility in the source impedance of the circuitry providing the qadc64e analog channel inputs. longer sample times permit more accurate a/d conversions of signals with higher source impedances. the programmable sample time can also be used to increase the time interval between conversions to adjust the queue execution time or the sampling rate. table 13-18 shows the two selectable input sample times. 9:15 chan[6:0] chan[6:0] ? channel number ? the chan field selects the input channel number. the software programs the channel field of the ccw with the channel number corresponding to the analog input pin to be sampled and converted. the analog input pin channel number assignments and the pin definitions vary depending on whether the multiplexed or non-multiplexed mode is used by the application. as far as the queue scanning operations are concerned, there is no distinction between an internally or externally multiplexed analog input. refer to section 13.1.5, ?external multiplexing? for more information on external multiplexing. table 13-19 shows the channel number assignments table 13-18. input sample times ist input sample times 0 input sample time = qclk period x 2 1 input sample time = qclk period x 16 table 13-19. multiplexed channel assignments and pin designations multiplexed input pins channel number in ccw chan field port pin name analog pin name other functions / descriptions pin type binary decimal anw/a_pqb[0] an[00] to an[07] ? input 0000000 to 0000111 0to7 anx/a_pqb[1] an[08] to an[15] ? input 0001000 to 0001111 8to15 any/a_pqb[2] an[16] to an[23] ? input 0010000 to 0010111 16 to 23 anz/a_pqb[3] an[24] to an[31] ? input 0011000 to 0011111 24 to 31 ? reserved ? ? 0100000 to 0101001 32 to 41 ? reserved ? ? 0101010 42 ? reserved ? ? 0101011 43 table 13-17. ccw bit descriptions (continued) bit(s) name description 13-32 mpc565/mpc566 reference manual motorola programming the qadc64e registers a_pqb[0] a_pqb[1] a_pqb[2] a_pqb[3] an[44] an[45] an[46] an[47] anw anx any anz input/output input/output input/output input/output 0101100 0101101 0101110 0101111 44 45 46 47 a_pqb[4] a_pqb[5] a_pqb[6] a_pqb[7] an[48] an[49] an[50] an[51] ? ? ? ? input/output input/output input/output input/output 0110000 0110001 0110010 0110011 48 49 50 51 a_pqa[0] a_pqa[1] a_pqa[2] a_pqa[3] an[52] an[53] an[54] an[55] ma[0] ma[1] ma[2] ? input/output input/output input/output input/output 0110100 0110101 0110110 0110111 52 53 54 55 a_pqa[4] a_pqa[5] a_pqa[6] a_pqa[7] an[56] an[57] an[58] an[59] ? ? ? ? input/output input/output input/output input/output 0111000 0111001 0111010 0111011 56 57 58 59 vrl vrh/altref 1 ? low ref high ref ? ? ? (vrh ? vrl)/2 input input ? 0111100 0111101 0111110 60 61 62 ? ? end of queue code ? 0111111 63 b_pqb[0] b_pqb[1] b_pqb[2] b_pqb[3] b_pqb[4] b_pqb[5] b_pqb[6] b_pqb[7] b_pqa[0] b_pqa[1] b_pqa[2] b_pqa[3] b_pqa[4] b_pqa[5] b_pqa[6] b_pqa[7] ? ? ? ? ? ? ? ? an[64] an[65] an[66] an[67] an[68] an[69] an[70] an[71] an[72] an[73] an[74] an[75] an[76] an[77] an[78] an[79] an[80] an[81] an[82] an[83] an[84] an[85] an[86] an[87] ? ? ? ? ? ? ? ? ma[0] ma[1] ma[2] ? ? ? ? ? ? ? ? ? ? ? ? ? amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input amux input 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 table 13-19. multiplexed channel assignments and pin designations (continued) multiplexed input pins channel number in ccw chan field port pin name analog pin name other functions / descriptions pin type binary decimal motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-33 programming the qadc64e registers the channel field is programmed for channel 63 or 127 to indicate the end of the queue. channels 60 to 62 are special internal channels. when one of the special channels is selected, the sampling amplifier is not used. the value of v r l , v r h ,or( v r h - v r l )/2 is placed directly onto the converter. also for the internal special channels, programming any input sample time other than two has no benefit except to lengthen the overall conversion time. 13.2.10result word table the result word table is a ram, 64 words long and 10 bits wide. an entry is written by the qadc64e after completing an analog conversion specified by the corresponding ccw table entry. software can read or write the result word table, but in normal operation, the software reads the result word table to obtain analog conversions from the qadc64e. unimplemented bits are read as zeros, and write operations do not have any effect. see figure 13-16 for a diagram of the result word table while there is only one result word table, the data can be accessed in three different data formats: right justified in the 16-bit word, with zeros in the higher order unused bits left justified, with the most significant bit inverted to form a sign bit, and zeros in the unused lower order bits left justified, with zeros in the lower order unused bits the left justified, signed format corresponds to a half-scale, offset binary, two?s complement data format. the data is routed onto the imb according to the selected format. the address used to access the table determines the data alignment format. all write operations to the result word table are right justified. ? reserved ? ? 1011000 to 1111110 88 to 126 ? ? end of queue code ? 1111111 127 1 whichever is selected in the ccw. table 13-19. multiplexed channel assignments and pin designations (continued) multiplexed input pins channel number in ccw chan field port pin name analog pin name other functions / descriptions pin type binary decimal reserved channels 13-34 mpc565/mpc566 reference manual motorola programming the qadc64e registers the three result data formats are produced by routing the ram bits onto the data bus. the software chooses among the three formats by reading the result at the memory address which produces the desired data alignment. the result word table is read/write accessible by software. during normal operation, applications software only needs to read the result table. write operations to the table may occur during test or debug breakpoint operation. when locations in the ccw table are not used by an application, software could use the corresponding locations in the result word table as scratch pad ram, remembering that only 10 bits are implemented. the result alignment is only implemented for software read operations. since write operations are not the normal use for the result registers, only one write data format is supported, which is right justified data. note some write operations, like bit manipulation, may not operate as expected because the hardware cannot access a true 16-bit value. msb 0 1234567891011121314lsb 15 reserved result reset: uuuuuuuuuuuuuuuu figure 13-18. rjurr ? right justified, unsigned result format 0x30 4a80 ? 0x30 4aff, 0x30 4e80 ? 0x30 4eff msb 0 1234567891011121314lsb 15 s 1 1 s = sign bit. result reserved reset: uuuuuuuuuuuuuuuu figure 13-19. ljsrr ? left justified, signed result format 0x30 4b00 ? 0x03 4b7f, 0x30 4f00 ? 0x03 4f7f msb 0 1234567891011121314lsb 15 result reserved reset: uuuuuuuuuuuuuuuu figure 13-20. ljurr ? left justified, unsigned result register 0x30 4b80 ? 0x03 4bff, 0x30 4f80 ? 0x03 4fff motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-35 analog subsystem 13.3 analog subsystem this section describes the qadc64e analog subsystem, which includes the front-end analog multiplexer and analog-to-digital converter. 13.3.1 analog-to-digital converter operation the analog subsystem consists of the path from the input pins to the a/d converter block. signals from the queue control logic are fed to the multiplexer and state machine. the end of convert (eoc) signal and the successive-approximation register (sar) are the result of the conversion. figure 13-21 shows a block diagram of the qadc64e analog subsystem. figure 13-21. qadc64e analog subsystem block diagram 13.3.1.1 conversion cycle times total conversion time is made up of initial sample time, final sample time, and resolution time. initial sample time refers to the time during which the selected input channel is coupled through the buffer amplifier to the sample capacitor. this buffer is used to quickly reproduce its input signal on the sample capacitor and minimize charge sharing errors. during the final sampling period the amplifier is bypassed, and the multiplexer input charges the sample capacitor array directly for improved accuracy. during the resolution stop state mach, sar, & sar buffer an44 an59 + - final sample buffer chan decoder + - comp. 2 vrh vrl cdac (4 bit) rdac (7 bit) conv. crh crl 4(one is offset) 7 ccw buffer data bus 10 result ist ref wccweos/eoc standard converter interface clk cap array equals cdac sample zero 7 altref buffer amp bias 13-36 mpc565/mpc566 reference manual motorola analog subsystem period, the voltage in the sample capacitor is converted to a digital value and stored in the sar. initial sample time is fixed at two qclk cycles. final sample time can be two or sixteen qclk cycles, depending on the value of the ist field in the ccw. resolution time is ten qclk cycles. therefore, conversion time requires a minimum of 14 qclk clocks (seven s with a 2.0-mhz qclk). if the maximum final sample time period of 16 qclks is selected, the total conversion time is 28 qclks or 14 s (with a 2.0-mhz qclk) figure 13-22 illustrates the timing for conversions. figure 13-22. conversion timing 13.3.2 channel decode and multiplexer the internal multiplexer selects one of the 40 analog input pins for conversion. the selected input is connected to the sample buffer amplifier. the multiplexer also includes positive and negative stress protection circuitry, which prevents deselected channels from affecting the selected channel when current is injected into the deselected channels. refer to appendix e, ?electrical characteristics? for specific current levels. 13.3.3 sample buffer amplifier the sample buffer is used to raise the effective input impedance of the a/d converter, so that external components (higher bandwidth or higher impedance) are less critical to accuracy. the input voltage is buffered onto the sample capacitor to reduce crosstalk between channels. 13.3.4 digital to analog converter (dac) array the digital to analog converter (dac) array consists of binary-weighted capacitors and a resistor-divider chain. the reference voltages, v rh and v rl , are used by the dac to sample time ?final? sample time resolution (?conv?) time sample time successive approximation resolution sequence 2 cycles n cycles: 10 cycles qclk (2 or 16) ?buffer? motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-37 analog subsystem perform ratiometric conversions. the dac also converts the following three internal channels: v rh ? reference voltage high v rl ? reference voltage low (v rh ?v rl )/2 ? reference voltage the dac array serves to provide a mechanism for the successive approximation a/d conversion. resolution begins with the most significant bit (msb) and works down to the least significant bit (lsb). the switching sequence is controlled by the comparator and successive-approximation register (sar) logic. sample capacitor ? the sample capacitor is employed to sample and hold the voltage to be converted. 13.3.5 comparator the comparator is used during the approximation process to sense whether the digitally selected arrangement of the dac array produces a voltage level higher or lower than the sampled input. the comparator output feeds into the sar which accumulates the a/d conversion result sequentially, beginning with the msb. 13.3.6 bias the bias circuit is controlled by the stop signal to power-up and power-down all the analog circuits. 13.3.7 successive approximation register the input of the successive approximation register (sar) is connected to the comparator output. the sar sequentially receives the conversion value one bit at a time, starting with the msb. after accumulating the 10 bits of the conversion result, the sar data is transferred to the appropriate result location, where it may be read from the imb by user software. 13.3.8 state machine the state machine receives the qclk, rst, stop, ist, chan[6:0], and start conv. signals, from which it generates all timing to perform an a/d conversion. the start convert (start conv.) signal indicates to the a/d converter that the desired channel has been sent to the mux. ist indicates the desired sample time. byp indicates whether to bypass the sample amplifier. the end of conversion (eoc) signal, notifies the queue control logic that a result is available for storage in the result ram. 13-38 mpc565/mpc566 reference manual motorola digital subsystem 13.4 digital subsystem the digital control subsystem includes the control logic to sequence the conversion activity, the clock and periodic/interval timer, control and status registers, the conversion command word table ram, and the result word table ram. the central element for control of the qadc64e conversions is the 64-entry ccw table. each ccw specifies the conversion of one input channel. depending on the application, one or two queues can be established in the ccw table. a queue is a scan sequence of one or more input channels. by using a pause mechanism, sub queues can be created in the two queues. each queue can be operated using one of several different scan modes. the scan modes for queue 1 and queue 2 are programmed in qacr1 and qacr2 (control registers 1 and 2). once a queue has been started by a trigger event (any of the ways to cause the qadc64e to begin executing the ccws in a queue or sub-queue), the qadc64e performs a sequence of conversions and places the results in the result word table. 13.4.1 queue priority queue 1 has priority over queue 2 execution. the following cases show the conditions under which queue 1 asserts its priority: when a queue is not active, a trigger event for queue 1 or queue 2 causes the corresponding queue execution to begin. when queue 1 is active and a trigger event occurs for queue 2, queue 2 cannot begin execution until queue 1 reaches completion or the paused state. the status register records the trigger event by reporting the queue 2 status as trigger pending. additional trigger events for queue 2, which occur before execution can begin, are captured as trigger overruns. when queue 2 is active and a trigger event occurs for queue 1, the current queue 2 conversion is aborted. the status register reports the queue 2 status as suspended. any trigger events occurring for queue 2 while queue 2 is suspended are captured as trigger overruns. once queue 1 reaches the completion or the paused state, queue 2 begins executing again. the programming of the resume bit in qacr2 determines which ccw is executed in queue 2. refer to section 13.2.7, ?control register 2? for more information. when simultaneous trigger events occur for queue 1 and queue 2, queue 1 begins execution and the queue 2 status is changed to trigger pending. 13.4.2 sub-queues that are paused the pause feature can be used to divide queue 1 and/or queue 2 into multiple subqueues. a sub-queue is defined by setting the pause bit in the last ccw of the sub-queue. motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-39 digital subsystem figure 13-23 shows the ccw format and an example of using pause to create subqueues. queue 1 is shown with four ccws in each sub-queue and queue 2 has two ccws in each sub-queue. figure 13-23. qadc64e queue operation with pause the queue operating mode selected for queue 1 determines what type of trigger event causes the execution of each of the sub-queues within queue 1. similarly, the queue operating mode for queue 2 determines the type of trigger event required to execute each of the sub-queues within queue 2. for example, when the external trigger rising edge continuous-scan mode is selected for queue 1, and there are six sub-queues within queue 1, a separate rising edge is required on the external trigger pin after every pause to begin the execution of each sub-queue (refer to figure 13-23). refer to section 13.4.4, ?scan modes,? for information on different scan modes. the choice of single-scan or continuous-scan applies to the full queue, and is not applied to each sub-queue. once a sub-queue is initiated, each ccw is executed sequentially until the last ccw in the sub-queue is executed and the pause state is entered. execution can only continue with the next ccw, which is the beginning of the next sub-queue. a sub-queue qadc64e cqp 00 begin queue 1 bq2 63 end of queue 1 begin queue 2 end of queue 2 00 63 conversion command word (ccw) table result word table 0 p 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 p 1 p 0 pause pause pause pause pause pause channel select, sample, hold, and a/d conversion 13-40 mpc565/mpc566 reference manual motorola digital subsystem cannot be executed a second time before the overall queue execution has been completed. refer to section 13.2.7, ?control register 2? for more information. trigger events which occur during the execution of a sub-queue are ignored, except that the trigger overrun flag is set. when a continuous-scan mode is selected, a trigger event occurring after the completion of the last sub-queue (after the queue completion flag is set), causes the execution to continue with the first sub-queue, starting with the first ccw in the queue. when the qadc64e encounters a ccw with the pause bit set, the queue enters the paused state after completing the conversion specified in the ccw with the pause bit. the pause flag is set and a pause software interrupt may optionally be issued. the status of the queue is shown to be paused, indicating completion of a sub-queue. the qadc64e then waits for another trigger event to again begin execution of the next sub-queue. 13.4.3 boundary conditions the following are queue operation boundary conditions: the first ccw in a queue contains channel 63 or 127, the end-of-queue (eoq) code. the queue becomes active and the first ccw is read. the end-of-queue is recognized, the completion flag is set, and the queue becomes idle. a conversion is not performed. bq2 (beginning of queue 2) is set at the end of the ccw table (63 or 127) and a trigger event occurs on queue 2. refer to section 13.2.7, ?control register 2,? for more information on bq2. the end-of-queue condition is recognized, a conversion is performed, the completion flag is set, and the queue becomes idle. bq2 is set to ccw0 and a trigger event occurs on queue 1. after reading ccw0, the end-of-queue condition is recognized, the completion flag is set, and the queue becomes idle. a conversion is not performed. bq2 is set beyond the end of the ccw table (64 ? 127) and a trigger event occurs on queue 2. the end-of-queue condition is recognized immediately, the completion flag is set, and the queue becomes idle. a conversion is not performed. note multiple end-of-queue conditions may be recognized simultaneously, although there is no change in the qadc64e behavior. for example, if bq2 is set to ccw0, ccw0 contains the eoq code, and a trigger event occurs on queue 1, the qadc64e reads ccw0 and detects both end-of-queue conditions. the completion flag is set and queue 1 becomes idle. boundary conditions also exist for combinations of pause and end-of-queue. one case is when a pause bit is in one ccw and an end-of-queue condition is in the next ccw. the conversion specified by the ccw with the pause bit set completes normally. the pause flag motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-41 digital subsystem is set. however, since the end-of-queue condition is recognized, the completion flag is also set and the queue status becomes idle, not paused. examples of this situation include: the pause bit is set in ccw5 and the channel 63 or 127 (eoq) code is in ccw6 the pause is in ccw63 during queue 1 operation, the pause bit is set in ccw20 and bq2 points to ccw21 another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue condition occur in the same ccw. both the pause and end-of-queue conditions are recognized simultaneously. the end-of-queue condition has precedence so a conversion is not performed for the ccw and the pause flag is not set. the qadc64e sets the completion flag and the queue status becomes idle. examples of this situation are: the pause bit is set in ccw10 and eoq is programmed into ccw10 during queue 1 operation, the pause bit set in ccw32, which is also bq2 13.4.4 scan modes the qadc64e queuing mechanism allows the application to utilize different requirements for automatically scanning input channels. in single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. in continuous-scan mode, multiple passes through a sequence of conversions defined by a queue are executed. the possible modes are: disabled and reserved mode software initiated single-scan mode external trigger single-scan mode external gated single-scan mode interval timer single-scan mode software initiated continuous-scan mode external trigger continuous-scan mode external gated continuous-scan mode periodic timer continuous-scan mode the following paragraphs describe single-scan and continuous-scan operations. 13.4.4.1 disabled mode when the disabled mode is selected, the queue is not active. trigger events cannot initiate queue execution. when both queue 1 and queue 2 are disabled, wait states are not encountered for imb accesses of the ram. when both queues are disabled, it is safe to change the qclk prescaler values. 13-42 mpc565/mpc566 reference manual motorola digital subsystem 13.4.4.2 reserved mode reserved mode allows for future mode definitions. when the reserved mode is selected, the queue is not active. it functions the same as disabled mode. caution do not use a reserved mode. unspecified operations may result. 13.4.4.3 single-scan modes when the application software wants to execute a single pass through a sequence of conversions defined by a queue, a single-scan queue operating mode is selected. by programming the mq field in qacr1 or qacr2, the following modes can be selected: software initiated single-scan mode external trigger single-scan mode external gated single-scan mode interval timer single-scan mode note queue 2 cannot be programmed for external gated single-scan mode. in all single-scan queue operating modes, the software must also enable the queue to begin execution by writing the single-scan enable bit to a one in the queue?s control register. the single-scan enable bits, sse1 and sse2, are provided for queue 1 and queue 2 respectively. until the single-scan enable bit is set, any trigger events for that queue are ignored. the single-scan enable bit may be set to a one during the write cycle, which selects the single-scan queue operating mode. the single-scan enable bit is set through software, but will always read as a zero. once set, writing the single-scan enable bit to zero has no effect. only the qadc64e can clear the single-scan enable bit. the completion flag, completion interrupt, or queue status are used to determine when the queue has completed. after the single-scan enable bit is set, a trigger event causes the qadc64e to begin execution with the first ccw in the queue. the single-scan enable bit remains set until the queue is completed. after the queue reaches completion, the qadc64e resets the single-scan enable bit to zero. if the single-scan enable bit is written to a one or a zero by the software before the queue scan is complete, the queue is not affected. however, if the software changes the queue operating mode, the new queue operating mode and the value of the single-scan enable bit are recognized immediately. the conversion in progress is aborted and the new queue operating mode takes effect. in the software-initiated single-scan mode, the writing of a one to the single-scan enable bit causes the qadc64e to internally generate a trigger event and the queue execution begins motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-43 digital subsystem immediately. in the other single-scan queue operating modes, once the single-scan enable bit is written, the selected trigger event must occur before the queue can start. the single-scan enable bit allows the entire queue to be scanned once. a trigger overrun is captured if a trigger event occurs during queue execution in an edge-sensitive external trigger mode or a periodic/interval timer mode. in the periodic/interval timer single-scan mode, the next expiration of the timer is the trigger event for the queue. after the queue execution is complete, the queue status is shown as idle. the software can restart the queue by setting the single-scan enable bit to a one. queue execution begins with the first ccw in the queue. 13.4.4.4 software initiated single-scan mode software can initiate the execution of a scan sequence for queue 1 or 2 by selecting the software initiated single-scan mode, and writing the single-scan enable bit in qacr1 or qacr2. a trigger event is generated internally and the qadc64e immediately begins execution of the first ccw in the queue. if a pause occurs, another trigger event is generated internally, and then execution continues without pausing. the qadc64e automatically performs the conversions in the queue until an end-of-queue condition is encountered. the queue remains idle until the software again sets the single-scan enable bit. while the time to internally generate and act on a trigger event is very short, software can momentarily read the status conditions, indicating that the queue is paused. the trigger overrun flag is never set while in the software initiated single-scan mode. the software initiated single-scan mode is useful in the following applications: allows software complete control of the queue execution allows the software to easily alternate between several queue sequences. 13.4.4.5 external trigger single-scan mode the external trigger single-scan mode is available on both queue 1 and queue 2. the software programs the polarity of the external trigger edge that is to be detected, either a rising or a falling edge. the software must enable the scan to occur by setting the single-scan enable bit for the queue. the first external trigger edge causes the queue to be executed one time. each ccw is read and the indicated conversions are performed until an end-of-queue condition is encountered. after the queue is completed, the qadc64e clears the single-scan enable bit. software may set the single-scan enable bit again to allow another scan of the queue to be initiated by the next external trigger edge. the external trigger single-scan mode is useful when the input trigger rate can exceed the queue execution rate. analog samples can be taken in sync with an external event, even 13-44 mpc565/mpc566 reference manual motorola digital subsystem though the software is not interested in data taken from every edge. the software can start the external trigger single-scan mode and get one set of data, and at a later time, start the queue again for the next set of samples. when a pause bit is encountered during external trigger single-scan mode, another trigger event is required for queue execution to continue. software involvement is not needed to enable queue execution to continue from the paused state. 13.4.4.6 external gated single-scan mode the qadc64e provides external gating for queue 1 only. when external gated single-scan mode is selected, the input level on the associated external trigger pin enables and disables queue execution. the polarity of the external gated signal is fixed so only a high level opens the gate and a low level closes the gate. once the gate is open, each ccw is read and the indicated conversions are performed until the gate is closed. software must enable the scan to occur by setting the single-scan enable bit for queue 1. if a pause in a ccw is encountered, the pause flag will not set, and execution continues without pausing. while the gate is open, queue 1 executes one time. each ccw is read and the indicated conversions are performed until an end-of-queue condition is encountered. when queue 1 completes, the qadc64e sets the completion flag (cf1) and clears the single-scan enable bit. software may set the single-scan enable bit again to allow another scan of queue 1 to be initiated during the next open gate. if the gate closes before queue 1 completes execution, the current ccw completes, execution of queue 1 stops, the single-scan enable bit is cleared, and the pf1 bit is set. software can read the cwpq1 to determine the last valid conversion in the queue. software must set the single-scan enable bit again and should clear the pf1 bit before another scan of queue 1 is initiated during the next open gate. the start of queue 1 is always the first ccw in the ccw table. since the condition of the gate is only sampled after each conversion during queue execution, closing the gate for a period less than a conversion time interval does not guarantee the closure will be captured. 13.4.4.7 periodic/interval timer single-scan mode both queues can use the periodic/interval timer in a single-scan queue operating mode. the timer interval can range from 128- to 128-kbyte qclk cycles in binary multiples. when the periodic/ interval timer single-scan mode is selected and the software sets the single-scan enable bit in qacr1 or qacr2, the timer begins counting. when the time interval elapses, an internal trigger event is created to start the queue and the qadc64e begins execution with the first ccw. the qadc64e automatically performs the conversions in the queue until a pause or an end-of-queue condition is encountered. when a pause occurs, queue execution stops until motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-45 digital subsystem the timer interval elapses again, and then queue execution continues. when the queue execution reaches an end-of-queue situation, the single-scan enable bit is cleared. software may set the single-scan enable bit again, allowing another scan of the queue to be initiated by the periodic/interval timer. the periodic/interval timer generates a trigger event whenever the time interval elapses. the trigger event may cause the queue execution to continue following a pause, or may be considered a trigger overrun. once the queue execution is completed, the single-scan enable bit must be set again to enable the timer to count again. normally only one queue will be enabled for periodic/interval timer single-scan mode and the timer will reset at the end-of-queue. however, if both queues are enabled for either single-scan or continuous periodic/interval timer mode, the end-of-queue condition will not reset the timer while the other queue is active. in this case, the timer will reset when both queues have reached end-of-queue. see section 13.4.6, ?periodic/interval timer? for a definition of periodic/interval timer reset conditions. the periodic/interval timer single-scan mode can be used in applications which need coherent results, for example: when it is necessary that all samples are guaranteed to be taken during the same scan of the analog pins when the interrupt rate in the periodic/interval timer continuous-scan mode would be too high in sensitive battery applications, where the single-scan mode uses less power than the software initiated continuous-scan mode 13.4.4.8 continuous-scan modes when the application software wants to execute multiple passes through a sequence of conversions defined by a queue, a continuous-scan queue operating mode is selected. by programming the mq1 field in qacr1 or the mq2 field in qacr2, the following software initiated modes can be selected: software initiated continuous-scan mode external trigger continuous-scan mode external gated continuous-scan mode periodic/interval timer continuous-scan mode when a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control register does not have any meaning or effect. as soon as the queue operating mode is programmed, the selected trigger event can initiate queue execution. in the case of the software-initiated continuous-scan mode, the trigger event is generated internally and queue execution begins immediately. in the other continuous-scan queue 13-46 mpc565/mpc566 reference manual motorola digital subsystem operating modes, the selected trigger event must occur before the queue can start. a trigger overrun is captured if a trigger event occurs during queue execution in the external trigger continuous-scan mode and the periodic/interval timer continuous-scan mode. after the queue execution is complete, the queue status is shown as idle. since the continuous-scan queue operating modes allow the entire queue to be scanned multiple times, software involvement is not needed to enable queue execution to continue from the idle state. the next trigger event causes queue execution to begin again, starting with the first ccw in the queue. note coherent samples are guaranteed. the time between consecutive conversions has been designed to be consistent. however, there is one exception. for queues that end with a ccw containing eoq code (channel 63 or 127), the last queue conversion to the first queue conversion requires 1 additional ccw fetch cycle. therefore continuous samples are not coherent at this boundary. in addition, the time from trigger to first conversion cannot be guaranteed since it is a function of clock synchronization, programmable trigger events, queue priorities, and so on. 13.4.4.9 software initiated continuous-scan mode when the software initiated continuous-scan mode is programmed, the trigger event is generated automatically by the qadc64e. queue execution begins immediately. if a pause is encountered, another trigger event is generated internally, and then execution continues without pausing. when the end-of-queue is reached, another internal trigger event is generated, and queue execution begins again from the beginning of the queue. while the time to internally generate and act on a trigger event is very short, software can momentarily read the status conditions, indicating that the queue is idle. the trigger overrun flag is never set while in the software-initiated continuous-scan mode. the software initiated continuous-scan mode keeps the result registers updated more frequently than any of the other queue operating modes. the software can always read the result table to get the latest converted value for each channel. the channels scanned are kept up to date by the qadc64e without software involvement. software can read a result value at any time. the software initiated continuous-scan mode may be chosen for either queue, but is normally used only with queue 2. when the software initiated continuous-scan mode is chosen for queue 1, that queue operates continuously and queue 2, being lower in priority, never gets executed. the short interval of time between a queue 1 completion and the subsequent trigger event is not sufficient to allow queue 2 execution to begin. motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-47 digital subsystem the software initiated continuous-scan mode is a useful choice with queue 2 for converting channels that do not need to be synchronized to anything, or for the slow-to-change analog channels. interrupts are normally not used with the software initiated continuous-scan mode. rather, the software reads the latest conversion result from the result table at any time. once initiated, software action is not needed to sustain conversions of channel. 13.4.4.10 external trigger continuous-scan mode the qadc64e provides external trigger pins for both queues. when the external trigger software initiated continuous-scan mode is selected, a transition on the associated external trigger pin initiates queue execution. the polarity of the external trigger signal is programmable, so that the software can select a mode which begins queue execution on the rising or falling edge. each ccw is read and the indicated conversions are performed until an end-of-queue condition is encountered. when the next external trigger edge is detected, the queue execution begins again automatically. software initialization is not needed between trigger events. when a pause bit is encountered in external trigger continuous-scan mode, another trigger event is required for queue execution to continue. software involvement is not needed to enable queue execution to continue from the paused state. some applications need to synchronize the sampling of analog channels to external events. there are cases when it is not possible to use software initiation of the queue scan sequence, since interrupt response times vary. 13.4.4.11 external gated continuous-scan mode the qadc64e provides external gating for queue 1 only. when external gated continuous-scan mode is selected, the input level on the associated external trigger pin enables and disables queue execution. the polarity of the external gated signal is fixed so a high level opens the gate and a low level closes the gate. once the gate is open, each ccw is read and the indicated conversions are performed until the gate is closed. when the gate opens again, the queue execution automatically begins again from the beginning of the queue. software initialization is not needed between trigger events. if a pause in a ccw is encountered, the pause flag will not set, and execution continues without pausing. the purpose of external gated continuous-scan mode is to continuously collect digitized samples while the gate is open and to have the most recent samples available. it is up to the programmer to ensure that the queue is large enough so that a maximum gate open time will not reach an end-of-queue. however it is useful to take advantage of a smaller queue in the manner described in the next paragraph. in the event that the queue completes before the gate closes, a completion flag will be set and the queue will roll over to the beginning and continue conversions until the gate closes. if the gate remains open and the completion flag is not cleared, when the queue completes 13-48 mpc565/mpc566 reference manual motorola digital subsystem a second time the trigger overrun flag will be set and the queue will roll-over again. the queue will continue to execute until the gate closes or the mode is disabled. if the gate closes before queue 1 completes execution, the current ccw completes execution of queue 1 stops and qadc64e sets the pf1 bit to indicate an incomplete queue. software can read the cwpq1 to determine the last valid conversion in the queue. in this mode, if the gate opens again, execution of queue 1 begins again. the start of queue 1 is always the first ccw in the ccw table. since the condition of the gate is only sampled after each conversion during queue execution, closing the gate for a period less than a conversion time interval does not guarantee the closure will be captured. 13.4.4.12 periodic/interval timer continuous-scan mode the qadc64e includes a dedicated periodic/interval timer for initiating a scan sequence on queue 1 and/or queue 2. software selects a programmable timer interval ranging from 128 to 128 kbytes times the qclk period in binary multiples. the qclk period is prescaled down from the imb mcu clock. when a periodic/interval timer continuous-scan mode is selected for queue 1 and/or queue 2, the timer begins counting. after the programmed interval elapses, the timer generated trigger event starts the appropriate queue. meanwhile, the qadc64e automatically performs the conversions in the queue until an end-of-queue condition or a pause is encountered. when a pause occurs, the qadc64e waits for the periodic interval to expire again, then continues with the queue. once end-of-queue has been detected, the next trigger event causes queue execution to begin again with the first ccw in the queue. the periodic/interval timer generates a trigger event whenever the time interval elapses. the trigger event may cause the queue execution to continue following a pause or queue completion, or may be considered a trigger overrun. as with all continuous-scan queue operating modes, software action is not needed between trigger events. since both queues may be triggered by the periodic/interval timer, see section 13.4.6, ?periodic/interval timer? for a summary of periodic/interval timer reset conditions. software enables the completion interrupt when using the periodic/interval timer continuous-scan mode. when the interrupt occurs, the software knows that the periodically collected analog results have just been taken. the software can use the periodic interrupt to obtain non-analog inputs as well, such as contact closures, as part of a periodic look at all inputs. 13.4.5 qadc64e clock (qclk) generation figure 13-24 is a block diagram of the clock subsystem. the qclk provides the timing for the a/d converter state machine which controls the timing of the conversion. the qclk is also the input to a 17-stage binary divider which implements the periodic/interval timer. motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-49 digital subsystem to retain the specified analog conversion accuracy, the qclk frequency (f qclk ) must be within the tolerance specified in appendix e, ?electrical characteristics.? before using the qadc64e, the software must initialize the prescaler with values that put the qclk within the specified range. though most software applications initialize the prescaler once and do not change it, write operations to the prescaler fields are permitted. caution a change in the prescaler value while a conversion is in progress is likely to corrupt the result from any conversion in progress. therefore, any prescaler write operation should be done only when both queues are in the disabled modes. figure 13-24. qadc64e clock subsystem functions to accommodate wide variations of the main mcu clock frequency (imb system clock ? f sys ), qclk is generated by a programmable prescaler which divides the mcu system clock. to allow the a/d conversion time to be maximized across the spectrum of system clock frequencies, the qadc64e prescaler permits the frequency of qclk to be software selectable. the software establishes the frequency of the qclk waveform by setting the prescaler rate selection (from control register 0) binary counter periodic/interval timer select 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 16 2 17 clock generate qclk qadc clock ( fsys / 2 to fsys/40 ) input sample time (from ccw) queue 1 & 2 timer mode rate selection sar control sar[9:0] periodic/interval trigger event system clock (fsys) a/d converter state machine for q1 and q2 2 8 int/ext qclk mux external qclk 13-50 mpc565/mpc566 reference manual motorola digital subsystem prescalar field in qacr0. the frequency resulting from a value in the prescalar field that is > 0, is calculated by the following formula: f qclk =f sysclk / (prescalar + 1) if the value in the prescalar field is set to 0, the resulting qclk frequency may be calculated to be: f qclk =f sysclk /2 the mcu system clock frequency is the basis of the qadc64e timing. the qadc64e requires that the system clock frequency be at least twice the qclk frequency. the qclk frequency is established by the prescaler parameter in qacr0. 13.4.6 periodic/interval timer the on-chip periodic/interval timer can be used to generate trigger events at a programmable interval, initiating execution of queue 1 and/or queue 2. the periodic/interval timer stays reset under the following conditions: both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval timer imb system reset or the master reset is asserted stop mode is selected freeze mode is selected note interval timer single-scan mode does not use the periodic/interval timer until the single-scan enable bit is set. the following two conditions will cause a pulsed reset of the periodic/interval timer during use: a queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue 2 is already using the timer a queue 2 operating mode change to a mode which uses the periodic/interval timer, provided queue 1 is not in a mode which uses the periodic/interval timer table 13-20. qadc64e clock programmability control register 0 information input sample time (ist) =%00 example number frequency prescaler qclk (mhz) conversion time ( motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-51 digital subsystem roll over of the timer during the low power stop mode, the periodic timer is held in reset. since low power stop mode causes qacr1 and qacr2 to be reset to zero, a valid periodic or interval timer mode must be written after stop mode is exited to release the timer from reset. when the imb internal freeze line is asserted and a periodic or interval timer mode is selected, the timer counter is reset after the conversion in progress completes. when the periodic or interval timer mode has been enabled (the timer is counting), but a trigger event has not been issued, the freeze mode takes effect immediately, and the timer is held in reset. when the internal freeze line is negated, the timer counter starts counting from the beginning. refer to section 13.4.7, ?configuration and control using the imb interface,? for more information. 13.4.7 configuration and control using the imb interface the qadc64e module communicates with other microcontroller modules via the imb. the qadc64e bus interface unit (biu) coordinates imb activity with internal qadc64e bus activity. this section describes the operation of the biu, imb read/write accesses to qadc64e memory locations, module configuration, and general-purpose i/o operation. 13.4.7.1 qadc64e bus interface unit the biu is designed to act as a slave device on the imb. the biu has the following functions: to respond with the appropriate bus cycle termination, and to supply imb interface timing to all internal module signals. biu components consist of imb buffers address match and module select logic the biu state machine clock prescaler logic data bus routing logic interface to the internal module data bus note normal accesses from the imb to the qadc64e require two clocks. however, if the cpu tries to access table locations while the qadc64e is accessing them, the qadc64e produces imb wait states. from one to four imb wait states may be inserted by the qadc64e in the process of reading and writing. 13-52 mpc565/mpc566 reference manual motorola digital subsystem 13.4.7.2 qadc64e bus accessing the qadc64e supports 8-bit, 16-bit, and 32-bit data transfers, at even and odd addresses. coherency of results read (ensuring that all results read were taken consecutively in one scan) is not guaranteed. for example, if a read of two consecutive 16-bit locations in a result area is made, the qadc64e could change one 16-bit location in the result area between the bus cycles. there is no holding register for the second 16-bit location. all read and write accesses that require more than one 16-bit access to complete occur as two or more independent bus cycles. depending on bus master protocol, these accesses could include misaligned and 32-bit accesses. figure 13-25 shows the three bus cycles which are implemented by the qadc64e. the following paragraphs describe how the three types of accesses are used, including misaligned 16-bit and 32-bit accesses. figure 13-25. bus cycle accesses byte access to an even address of a qadc64e location is shown in the top illustration of figure 13-25. in the case of write cycles, byte1 of the register is not disturbed. in the case of a read cycle, the qadc64e provides both byte 0 and byte1. qadc64e bus cyc acc intermodule bus 8-bit access of an even address (isiz = 01, a0 = 0) byte 0 byte 1 byte 0 byte 1 qadc location wr wr intermodule bus 8-bit access of an odd address (isiz = 01, a0 = 1; or isiz = 10, a0 = 1) byte 0 byte 1 byte 0 byte 1 qadc location wr wr intermodule bus 16-bit aligned access (isiz = 10, a0 = 0) byte 0 byte 1 byte 0 byte 1 qadc location wr wr motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-53 trigger and queue interaction examples byte access to an odd address of a qadc64e location is shown in the center illustration of figure 13-25. in the case of write cycles, byte 0 of the register is not disturbed. in the case of read cycles, the qadc64e provides both byte 0 and byte1. 16-bit accesses to an even address read or write byte 0 and byte 1 as shown in the lowest illustration of figure 13-25. the full 16 bits of data is written to and read from the qadc64e location with each access. 16-bit accesses to an odd address require two bus cycles; one byte of two different 16-bit qadc64e locations is accessed. the first bus cycle is treated by the qadc64e as an 8-bit read or write of an odd address. the second cycle is an 8-bit read or write of an even address. the qadc64e address space is organized into 16-bit even address locations, so a 16-bit read or write of an odd address obtains or provides the lower half of one qadc64e location, and the upper half of the following qadc64e location. 32-bit accesses to an even address require two bus cycles to complete the access, and two full 16-bit qadc64e locations are accessed. the first bus cycle reads or writes the addressed 16-bit qadc64e location and the second cycle reads or writes the following 16-bit location. 32-bit accesses to an odd address require three bus cycles. portions of three different qadc64e locations are accessed. the first bus cycle is treated by the qadc64e as an 8-bit access of an odd address, the second cycle is a 16-bit aligned access, and the third cycle is an 8-bit access of an even address. the qadc64e address space is organized into 16-bit even address locations, so a 32-bit read or write of an odd address provides the lower half of one qadc64e location, the full 16-bit content of the following qadc64e location, and the upper half of the third qadc64e location. 13.5 trigger and queue interaction examples this section contains examples describing queue priority and conversion timing schemes. 13.5.1 queue priority schemes since there are two conversion command queues and only one a/d converter, there is a priority scheme to determine which conversion is to occur. each queue has a variety of trigger events that are intended to initiate conversions, and they can occur asynchronously in relation to each other and other conversions in progress. for example, a queue can be idle awaiting a trigger event, a trigger event can have occurred but the first conversion has not started, a conversion can be in progress, a pause condition can exist awaiting another trigger event to continue the queue, and so on. the following paragraphs and figures outline the prioritizing criteria used to determine which conversion occurs in each overlap situation. 13-54 mpc565/mpc566 reference manual motorola trigger and queue interaction examples note the situations in figure 13-26 through figure 13-44 are labeled s1 through s19. in each diagram, time is shown increasing from left to right. the execution of queue 1 and queue 2 (q1 and q2) is shown as a string of rectangles representing the execution time of each ccw in the queue. in most of the situations, there are four ccws (labeled c1 to c4) in both queue 1 and queue 2. in some of the situations, ccw c2 is presumed to have the pause bit set, to show the similarities of pause and end-of-queue as terminations of queue execution. trigger events are described in table 13-21. when a trigger event causes a ccw execution in progress to be aborted, the aborted conversion is shown as a ragged end of a shortened ccw rectangle. the situation diagrams also show when key status bits are set. table 13-22 describes the status bits. below the queue execution flows are three sets of blocks that show the status information that is made available to the software. the first two rows of status blocks show the condition of each queue as: idle active pause table 13-21. trigger events trigger events t1 events that trigger queue 1 execution (external trigger, software initiated single-scan enable bit, or completion of the previous continuous loop) t2 events that trigger queue 2 execution (external trigger, software initiated single-scan enable bit, timer period/interval expired, or completion of the previous continuous loop) table 13-22. status bits bit function cf flag set when the end of the queue is reached pf flag set when a queue completes execution up through a pause bit trigger overrun error (tor) set when a new trigger event occurs before the queue is finished serving the previous trigger event motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-55 trigger and queue interaction examples suspended (queue 2 only) trigger pending the third row of status blocks shows the 4-bit qs status register field that encodes the condition of the two queues. two transition status cases, qs = 0011 and qs = 0111, are not shown because they exist only very briefly between stable status conditions. the first three examples in figure 13-26 through figure 13-28 (s1, s2, and s3) show what happens when a new trigger event is recognized before the queue has completed servicing the previous trigger event on the same queue. in situation s1 (figure 13-26), one trigger event is being recognized on each queue while that queue is still working on the previously recognized trigger event. the trigger overrun error status bit is set, and otherwise, the premature trigger event is ignored. a trigger event which occurs before the servicing of the previous trigger event is through does not disturb the queue execution in progress. figure 13-26. ccw priority situation 1 in situation s2 (figure 13-26), more than one trigger event is recognized before servicing of a previous trigger event is complete, the trigger overrun bit is again set, but otherwise, the additional trigger events are ignored. after the queue is complete, the first newly detected trigger event causes queue execution to begin again. when the trigger event rate is high, a new trigger event can be seen very soon after completion of the previous queue, leaving software little time to retrieve the previous results. also, when trigger events are occurring at a high rate for queue 1, the lower priority queue 2 channels may not get serviced at all. q1 q2 qs idle idle active idle 0000 1000 0000 0010 0000 tor1 t1 t1 q1: c1 c2 c3 c4 cf1 c1 c2 c3 c4 tor2 t2 t2 q2: cf2 idle qadc s active 13-56 mpc565/mpc566 reference manual motorola trigger and queue interaction examples figure 13-27. ccw priority situation 2 situation s3 (figure 13-27) shows that when the pause feature is in use, the trigger overrun error status bit is set the same way, and that queue execution continues unchanged. figure 13-28. ccw priority situation 3 the next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is actively being serviced. situation s4 (figure 13-29) shows that a queue 2 trigger event that is recognized while queue 1 is active is saved, and as soon as queue 1 is finished, queue 2 servicing begins. qadc s2 active idle q1 q2 qs idle active idle active idle 1000 1000 0000 0010 0000 c1 c2 c3 c4 tor2 t2 t2 q2: cf2 idle c1 c2 c3 c4 t1 cf1 c1 c2 c3 c4 tor1 t1 t1 q1: cf1 tor1 t1 tor1 t1 tor2 t2 qadc s pause q1 q2 qs idle active idle active idle 1000 0110 0001 0010 active 0000 idle c1 c2 t1 t1 q1: tor1 pf1 c1 c2 0000 q2: 0100 tor2 pf2 t2 t2 0101 c3 c4 t1 t1 tor1 cf1 active pause 1001 c3 c4 cf2 t2 t2 tor2 motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-57 trigger and queue interaction examples figure 13-29. ccw priority situation 4 situation s5 (figure 13-30) shows that when multiple queue 2 trigger events are detected while queue 1 is busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed. situation s5 also shows that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is in use in either queue. figure 13-30. ccw priority situation 5 the remaining situations, s6 through s11, show the impact of a queue 1 trigger event occurring during queue 2 execution. queue 1 is higher in priority the conversion taking place in queue 2 is aborted, so that there is not a variable latency time in responding to queue 1 trigger events. qadc s q1 q2 qs idle idle active idle 0000 1000 0010 active 0000 c1 c2 c3 c4 t1 q1: cf1 q2: c1 c2 c3 c4 t2 cf2 idle 1011 triggered qadc s5 q1 q2 qs idle idle idle 0000 1000 0010 active 0000 c1 c2 t1 q1: c1 c2 pf2 c3 c4 c3 c4 cf2 idle 1011 trig q2: t2 t2 pf1 pause active pause tor2 t2 t2 cf1 tor2 t1 active trig 0110 active active 0101 1001 1011 13-58 mpc565/mpc566 reference manual motorola trigger and queue interaction examples in situation s6 (figure 13-31), the conversion initiated by the second ccw in queue 2 is aborted just before the conversion is complete, so that queue 1 execution can begin. queue 2 is considered suspended. after queue 1 is finished, queue 2 starts over with the first ccw, when the res (resume) control bit is set to 0. situation s7 (figure 13-32) shows that when pause operation is not in use with queue 2, queue 2 suspension works the same way. figure 13-31. ccw priority situation 6 figure 13-32. ccw priority situation 7 situations s8 and s9 (figure 13-33 and figure 13-34) repeat the same two situations with the resume bit set to a one. when the res bit is set, following suspension, queue 2 resumes execution with the aborted ccw, not the first ccw in the queue. qadc s idle q1 q2 qs idle idle 0000 1000 active c1 c2 t1 q1: c1 c3 c4 idle q2: pf1 pause active cf1 t1 active suspend 0100 active active 0110 1010 c1 c2 c3 c4 cf2 t2 0010 0000 resume=0 c2 qadc s7 t1 t1 pause q1 q2 qs idle idle idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 c1 q2: t2 pf2 c1 c2 c3 c4 cf1 c3 c4 cf2 t2 c3 active act active resume=0 c2 active suspend suspend motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-59 trigger and queue interaction examples figure 13-33. ccw priority situation 8 figure 13-34. ccw priority situation 9 situations s10 and s11 (figure 13-35 and figure 13-36) show that when an additional trigger event is detected for queue 2 while the queue is suspended, the trigger overrun error bit is set, the same as if queue 2 were being executed when a new trigger event occurs. trigger overrun on queue 2 thus permits the software to know that queue 1 is taking up so much qadc64e time that queue 2 trigger events are being lost. qadc s8 idle q1 q2 qs idle idle 0000 1000 0010 active c1 c2 t1 q1: c1 c3 c4 idle q2: pf1 pause active cf1 t1 active suspend 0100 active active 0110 1010 c2 c3 c4 cf2 t2 0000 resume=1 c2 qadc s9 t1 pause q1 q2 qs idle idle act idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 pause 0110 c1 q2: t2 c2 pf2 t1 c3 c4 cf1 c4 cf2 suspend act active suspend t2 c3 c1 resume=1 c2 c4 active active 13-60 mpc565/mpc566 reference manual motorola trigger and queue interaction examples figure 13-35. ccw priority situation 10 figure 13-36. ccw priority situation 11 the above situations cover normal overlap conditions that arise with asynchronous trigger events on the two queues. an additional conflict to consider is that the freeze condition can arise while the qadc64e is actively executing ccws. the conventional use for the freeze mode is for software/hardware debugging. when the cpu background debug mode is enabled and a breakpoint occurs, the freeze signal is issued, which can cause peripheral modules to stop operation. when freeze is detected, the qadc64e completes the conversion in progress, unlike queue 1 suspending queue 2. after the freeze condition is removed, the qadc64e continues queue execution with the next ccw in sequence. qadc s10 t1 t1 pause q1 q2 qs idle active idle active idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active 0110 q2: t2 pf2 c1 c2 c3 c4 cf1 c3 c4 cf2 t2 c3 active c1 act t2 tor2 t2 tor2 resume=0 c2 active active suspend suspend paus qadc s11 t1 t1 c3 c4 cf1 pause q1 q2 qs idle idle act idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 q2: t2 suspend act c1 active suspend t2 tor2 t2 tor2 c2 pf2 c4 cf2 t2 c3 c2 c4 resume=1 active motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-61 trigger and queue interaction examples trigger events that occur during freeze are not captured. when a trigger event is pending for queue 2 before freeze begins, that trigger event is remembered when the freeze is passed. similarly, when freeze occurs while queue 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished. situations 12 through 19 (figure 13-37 to figure 13-44) show examples of all of the freeze situations. figure 13-37. ccw freeze situation 12 figure 13-38. ccw freeze situation 13 figure 13-39. ccw freeze situation 14 qadc s12 c3 c4 cf1 c1 c2 t1 q1: freeze qadc s13 c1 c2 t2 q2: cf2 c3 c4 freeze qadc s14 c1 c2 t1 q1: cf1 c3 c4 freeze t1 t1 t2 t2 (triggers ignored) 13-62 mpc565/mpc566 reference manual motorola trigger and queue interaction examples figure 13-40. ccw freeze situation 15 figure 13-41. ccw freeze situation 16 figure 13-42. ccw freeze situation 17 figure 13-43. ccw freeze situation 18 qadc s15 c1 c2 t2 q2: cf2 c3 c4 freeze t2 t2 t1 t1 (triggers ignored) qadc s16 c1 c2 t1 q1: cf1 c3 c4 freeze t1 t1 pf1 (triggers ignored) qadc s17 c1 c2 t2 q2: cf2 c3 c4 freeze t2 t2 pf2 (triggers ignored) qadc s1 c1 c2 t1 q1: cf1 c3 c4 freeze t2 c1 c2 q2: c3 cf2 c4 (trigger captured, response delayed after freeze) motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-63 trigger and queue interaction examples figure 13-44. ccw freeze situation 19 13.5.2 conversion timing schemes this section contains some conversion timing examples. example 1 below shows the timing for basic conversions where the following is assumed: q1 begins with ccw0 and ends with ccw3 ccw0 has pause bit set ccw1 does not have pause bit set external trigger rise-edge for q1 ccw4 = bq2 and q2 is disabled q1 res shows relative result register updates figure 13-45. external trigger mode (positive edge) timing with pause qadc s1 c1 c2 t1 q1: cf1 c4 freeze cf2 c4 c1 c2 t2 q2: c3 c3 c4 qclk trig1 eoc qs cwp cwpq1 q1 res ccw1 04 ccw0 last ccw1 ccw2 84 8 r0 r1 conversion time is >= 14 qclks ccw0 last time between triggers 13-64 mpc565/mpc566 reference manual motorola trigger and queue interaction examples recall qs = 0 => queues disabled; qs = 8 => q1 active, q2 disabled; qs= 4 => q1 paused, q2 disabled. a time separator was provided between the triggers and end of conversion (eoc). the relationship to qclk displayed is not guaranteed. cwpq1 and cwpq2 typically lag cwp and only match cwp when the associated queue is inactive. another way to view cwpq1 and cwpq2 is that these registers update when eoc triggers the result register to be written. when the pause bit is set (ccw0), please note that cwp does not increment until triggered. when the pause is not set (ccw1), the cwp increments with eoc. the conversion results q1 res(x) show the result associated with ccw(x). so that r0 represents the result associated with ccw0. example 2 below shows the timing for conversions in gated mode single-scan with the same assumptions as example 1 except: no pause bits set in any ccw external trigger gated single-scan mode for q1 single-scan bit is set when the gate closes and opens again the conversions start with the first ccw in q1. when the gate closes the active conversion completes before the queue goes idle. when q1 completes both the cf1 bit sets and the sse bit clears. motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-65 trigger and queue interaction examples figure 13-46. gated mode, single-scan timing example 3 below shows the timing for conversions in gated continuous-scan mode with the same assumptions in the amended definition for the pf bit in this mode to reflect the condition that a gate closing occurred before the queue completed is a proposal under consideration at this time as example 2. note at the end of q1,the completion flag cf1 sets and the queue restarts. also, note that if the queue starts a second time and completes, the trigger overrun flag tor1 sets. trig1 eoc qs cwp cwpq1 q1 res ccw1 0 8 ccw1 last ccw1 ccw2 last 08 r0 r1 ccw0 last ccw1 ccw0 ccw0 r1 ccw0 r0 ccw2 ccw3 r2 sse ccw3 r3 cf1 software must set sse pf1 software must clear pf1 0 (gate) 13-66 mpc565/mpc566 reference manual motorola qadc64e integration requirements figure 13-47. gated mode, continuous scan timing 13.6 qadc64e integration requirements the qadc64e requires accurate, noise-free input signals for proper operation. this section discusses the design of external circuitry to maximize qadc64e performance. the qadc64e uses the external pins shown in figure 13-1. there are 32 channel/port pins and a total of 40 analog input channels. with external multiplexing mpc565/mpc566 can support 65 analog inputs. 32 of the channel pins can also be used as general-purpose digital port pins. in addition, there are also two analog reference pins, and two analog submodule power shared by both qadc modules. 13.6.1 port digital input/output pins the sixteen port pins can be used as analog inputs, or as a bidirectional 16-bit digital input/output port. port a pins are referred to as pqa[7:0] when used as a bidirectional 8-bit digital input/output port. these eight pins may be used for general-purpose digital input signals or push-pull digital output signals. port b pins are referred to as pqb[7:0] and operate the same as port a port a and b pins are connected to a digital input synchronizer during reads and may be used as general purpose digital inputs when the applied voltages meet high voltage input trig1 eoc qs cwp cwpq1 q1 res 0 8 last ccw0 ccw1 r1 ccw3 r3 cf1 tor1 ccw0 last xx ccw2 r2 ccw2 ccw1 ccw0 r0 ccw0 ccw3 r3 ccw3 ccw2 r2 ccw3 qrestart qrestart (gate) motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-67 qadc64e integration requirements (v ih ) and low voltage input (v il ) requirements. refer to appendix e, ?electrical characteristics,? for more information on voltage requirements. each port a or b pin is configured as an input or output by programming the port data direction register (ddrqa or ddrqb). the digital input signal states are read by the software in the port data register when the port data direction register specifies that the pins are inputs. the digital data in the port data register is driven onto the port a or b pins when the corresponding bit in the port data direction register specifies output. refer to section 13.2.3, ?port data register,? for more information. since the outputs are configured as push-pull drivers, external pull-up provisions are not necessary when the output is used to drive another integrated circuit. 13.6.2 external trigger input pins the qadc64e uses two external trigger pins (etrig[2:1]). each of the two input external trigger pins is associated with one of the scan queues, queue 1 or queue 2 the assignment of etrig[2:1] to a queue is made in the qacr0 register by the trg bit. when trg=0, etrig[1] triggers queue 1 and etrig[2] triggers queue 2. when trg=1, etrig[1] triggers queue 2 and etrig[2] triggers queue 1. 13.6.3 analog power pins v dda and v ssa pins supply power to the analog subsystems of the qadc64e module. dedicated power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the digital power supply. refer to appendix e, ?electrical characteristics,? for more information. the analog supply pins (v dda and v ssa ) define the limits of the analog reference voltages (v rh and v rl ) and of the analog multiplexer inputs. figure 13-48 is a diagram of the analog input circuitry. 13-68 mpc565/mpc566 reference manual motorola qadc64e integration requirements figure 13-48. equivalent analog input circuitry since the sample amplifier is powered by v dda and v ssa , it can accurately transfer input signal levels up to but not exceeding v dda and down to but not below v ssa. if the input signal is outside of this range, the output from the sample amplifier is clipped. in addition, v rh and v rl must be within the range defined by v dda and v ssa. as long as v rh is less than or equal to v dda and v rl is greater than or equal to v ssa and the sample amplifier has accurately transferred the input signal, resolution is ratiometric within the limits defined by v rl and v rh. if v rh is greater than v dda , the sample amplifier can never transfer a full-scale value. if v rl is less than v ssa , the sample amplifier can never transfer a zero value. figure 13-49 shows the results of reference voltages outside the range defined by v dda and v ssa . at the top of the input signal range, v dda is 10 mv lower than v rh. this results in a maximum obtainable 10-bit conversion value of 0x3fe. at the bottom of the signal range, v ssa is 15 mv higher than v rl , resulting in a minimum obtainable 10-bit conversion value of three. sample amp 16 channels v ssa v rl vdda qadc64e 16ch sample amp vrh s/h rc dac comparator cp motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-69 qadc64e integration requirements figure 13-49. errors resulting from clipping 13.6.3.1 analog supply filtering and grounding two important factors influencing performance in analog integrated circuits are supply filtering and grounding. generally, digital circuits use bypass capacitors on every vdd/vss pin pair. this applies to analog sub-modules also. the distribution of power and ground is equally important. analog supplies should be isolated from digital supplies as much as possible. this necessity stems from the higher performance requirements often associated with analog circuits. therefore, deriving an analog supply from a local digital supply is not recommended. however, if for economic reasons digital and analog power are derived from a common regulator, filtering of the analog power is recommended in addition to the bypassing of the supplies already mentioned. for example, an rc low pass filter could be used to isolate the digital and analog supplies when generated by a common regulator. if multiple high precision analog circuits are locally employed (i.e., two a/d converters), the analog supplies should be isolated from each other as sharing supplies introduces the potential for interference between analog circuits. qadc64e clipping 0 .020 5.100 5.110 input in volts (v rh = 5.120, = 0 v) 1 2 3 4 5 6 7 8 3fa 3fb 3fc 3fd 3fe 3ff .010 .030 5.120 5.130 10-bit result (hexadecimal) vrl 13-70 mpc565/mpc566 reference manual motorola qadc64e integration requirements grounding is the most important factor influencing analog circuit performance in mixed signal systems (or in stand-alone analog systems). close attention must be paid not to introduce additional sources of noise into the analog circuitry. common sources of noise include ground loops, inductive coupling, and combining digital and analog grounds together inappropriately. the problem of how and when to combine digital and analog grounds arises from the large transients which the digital ground must handle. if the digital ground is not able to handle the large transients, the current from the large transients can return to ground through the analog ground. it is the excess current overflowing into the analog ground which causes performance degradation by developing a differential voltage between the true analog ground and the microcontroller?s ground pin. the end result is that the ground observed by the analog circuit is no longer true ground and often ends in skewed results. two similar approaches designed to improve or eliminate the problems associated with grounding excess transient currents involve star-point ground systems. one approach is to star-point the different grounds at the power supply origin, thus keeping the ground isolated. . another approach is to star-point the different grounds near the analog ground pin on the microcontroller by using small traces for connecting the non-analog grounds to the analog ground. the small traces are meant only to accommodate dc differences, not ac transients. note this star-point scheme still requires adequate grounding for digital and analog subsystems in addition to the star-point ground. other suggestions for pcb layout in which the qadc64e is employed include: analog ground must be low impedance to all analog ground points in the circuit. bypass capacitors should be as close to the power pins as possible. the analog ground should be isolated from the digital ground. this can be done by cutting a separate ground plane for the analog ground non-minimum traces should be utilized for connecting bypass capacitors and filters to their corresponding ground/power points. distance for trace runs should be minimized where possible motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-71 qadc64e integration requirements figure 13-50. star-ground at the point of power supply origin 13.6.4 analog reference pins v rh and v rl are the dedicated input pins for the high and low reference voltages.separating the reference inputs from the power supply pins allows for additional external filtering, which increases reference voltage precision and stability, and subsequently contributes to a higher degree of conversion accuracy. the altref pin may be selected through the ccw as the high reference for a conversion. this allows for the ability to ?zoom? in on a portion of the convertible range with the full 10 bits. refer to table 13-17. no a/d converter can be more accurate than its analog reference. any noise in the reference can result in at least that much error in a conversion. the reference for the qadc64e, supplied by pins v rh , altref, and v rl , should be low-pass filtered from its source to obtain a noise-free, clean signal. in many cases, simple capacitive bypassing may sufficed. in extreme cases, inductors or ferrite beads may be necessary if noise or rf energy is present. series resistance is not advisable since there is an effective dc current requirement from the reference voltage by the internal resistor string in the rc dac array. external resistance may introduce error in this architecture under certain conditions. any series devices in the filter network should contain a minimum amount of dc resistance. qadc64e vrh vrl vssa vdda vdd vss analog power supply +5v +5v agnd digital power +5v pgnd pcb supply 13-72 mpc565/mpc566 reference manual motorola qadc64e integration requirements 13.6.5 analog input pins analog inputs should have low ac impedance at the pins. low ac impedance can be realized by placing a capacitor with good high frequency characteristics at the input pin of the part. ideally, that capacitor should be as large as possible (within the practical range of capacitors that still have good high frequency characteristics). this capacitor has two effects: it helps attenuate any noise that may exist on the input. it sources charge during the sample period when the analog signal source is a high-impedance source. series resistance can be used with the capacitor on an input pin to implement a simple rc filter. the maximum level of filtering at the input pins is application dependent and is based on the bandpass characteristics required to accurately track the dynamic characteristics of an input. simple rc filtering at the pin may be limited by the source impedance of the transducer or circuit supplying the analog signal to be measured. refer to section 13.6.5.3, ?error resulting from leakage,? for more information. in some cases, the size of the capacitor at the pin may be very small. figure 13-51 is a simplified model of an input channel. refer to this model in the following discussion of the interaction between the external circuitry and the circuitry inside the qadc64e. figure 13-51. electrical model of an a/d input pin qadc64e sample amp model s1 amp r f s3 s2 csamp vi cp cf vsrc internal circuit model external filter =source voltage = internal parasitic capacitance v src r f c f c p csamp = sample capacitor v i = filter impedance = filter capacitor = internal voltage source during sample and hold source rsrc rsrc = source impedance motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-73 qadc64e integration requirements in figure 13-51, r f ,r src and c f comprise the external filter circuit. c p is the internal parasitic capacitor. c samp is the capacitor array used to sample and hold the input voltage. v i is an internal voltage source used to provide charge to c samp during sample phase. the following paragraphs provide a simplified description of the interaction between the qadc64e and the external circuitry. this circuitry is assumed to be a simple rc low-pass filter passing a signal from a source to the qadc64e input pin. the following simplifying assumptions are made: the external capacitor is perfect (no leakage, no significant dielectric absorption characteristics, etc.) all parasitic capacitance associated with the input pin is included in the value of the external capacitor inductance is ignored the ?on? resistance of the internal switches is 0 ? and the ?off? resistance is infinite 13.6.5.1 analog input considerations the source impedance of the analog signal to be measured and any intermediate filtering should be considered whether external multiplexing is used or not. figure 13-52 shows the connection of eight typical analog signal sources to one qadc64e analog input pin through a separate multiplexer chip. also, an example of an analog signal source connected directly to a qadc64e analog input channel is displayed. 13-74 mpc565/mpc566 reference manual motorola qadc64e integration requirements 1 typical value 2 r filter typically 10k??20k? figure 13-52. external multiplexing of analog signal sources ~ ~ ~ ~ ~ ~ ~ ~ c p c samp c p c sam p c in = c p +c samp r muxout r source 2 analog signal source filtering and interconnect typical mux chip inter qadc64e qadc64e ext mux ex ~ c filter c source r filter 2 c muxin 0.01 mf 1 c muxout (mc54hc4051, mc74hc4051, mc54hc4052, mc74hc4052, mc54hc4053, etc.) r source 2 c filter c source r filter 2 c muxin 0.01 mf 1 2 motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-75 qadc64e integration requirements 13.6.5.2 settling time for the external circuit the values for r src ,r f and c f in the external circuitry determine the length of time required to charge c f to the source voltage level (v src ). at time t = 0, v src changes in figure 13-51 while s1 is open, disconnecting the internal circuitry from the external circuitry. assume that the initial voltage across c f is zero. as c f charges, the voltage across it is determined by the following equation, where t is the total charge time: as t approaches infinity, v cf will equal v src . (this assumes no internal leakage.) with 10-bit resolution, 1/2 of a count is equal to 1/2048 full-scale value. assuming worst case (v src = full scale), table 13-23 shows the required time for c f to charge to within 1/2 of a count of the actual source voltage during 10-bit conversions. table 13-23 is based on the rc network in figure 13-51. note the following times are completely independent of the a/d converter architecture (assuming the qadc64e is not affecting the charging). the external circuit described in table 13-23 is a low-pass filter. a user interested in measuring an ac component of the external signal must take the characteristics of this filter into account. 13.6.5.3 error resulting from leakage a series resistor limits the current to a pin, therefore input leakage acting through a large source impedance can degrade a/d accuracy. the maximum input leakage current is specified in appendix e, ?electrical characteristics.? input leakage is greater at higher operating temperatures. in the temperature range from 125 c to 50 c, the leakage current is halved for every 8 ? 12 c reduction in temperature. table 13-23. external circuit settling time to 1/2 lsb (10-bit conversions) filter capacitor (cf) source resistance (r f +r src ) 100 ? ? ? ? ? t ? r f r src + () ?? ?? ?? 13-76 mpc565/mpc566 reference manual motorola qadc64e integration requirements assuming v rh ?v rl = 5.12 v, one count (assuming 10-bit resolution) corresponds to 5 mv of input voltage. a typical input leakage of 200 na acting through 10 k ? of external series resistance results in an error of 0.4 count (2.0 mv). if the source impedance is 100 k ? and a typical leakage of 100 na is present, an error of two counts (10 mv) is introduced. in addition to internal junction leakage, external leakage (e.g., if external clamping diodes are used) and charge sharing effects with internal capacitors also contribute to the total leakage current. table 13-24 illustrates the effect of different levels of total leakage on accuracy for different values of source impedance. the error is listed in terms of 10-bit counts. caution leakage from the part below 200 na is obtainable only within a limited temperature range. 13.6.5.4 accommodating positive/negative stress conditions positive or negative stress refers to conditions which exceed nominally defined operating limits. examples include applying a voltage exceeding the normal limit on an input (for example, voltages outside of the suggested supply/reference ranges) or causing currents into or out of the pin which exceed normal limits. qadc64e specific considerations are voltages greater than v dda ,v rh or less than v ssa applied to an analog input which cause excessive currents into or out of the input. refer to appendix e, ?electrical characteristics,? to for more information on exact magnitudes. either stress condition can potentially disrupt conversion results on neighboring inputs. parasitic devices, associated with cmos processes, can cause an immediate disruptive influence on neighboring pins. common examples of parasitic devices are diodes to substrate and bipolar devices with the base terminal tied to substrate (v ssi /v ssa ground). under stress conditions, current injected on an adjacent pin can cause errors on the selected channel by developing a voltage drop across the selected channel?s impedances. figure 13-53 shows an active parasitic bipolar npn transistor when an input pin is subjected to negative stress conditions. figure 13-54 shows positive stress conditions can activate a similar pnp transistor. table 13-24. error resulting from input leakage (ioff) source impedance leakage value (10-bit conversions) 100 na 200 na 500 na 1000 na 1k ? ? ? motorola chapter 13. queued analog-to-digital converter (qadc64e) 13-77 qadc64e integration requirements figure 13-53. input pin subjected to negative stress figure 13-54. input pin subjected to positive stress the current into the pin (i injn or i injp ) under negative or positive stress is determined by the following equations: where: v stress = adjustable voltage source v eb = parasitic pnp emitter/base voltage (refer to v negclamp in appendix e, ?electrical characteristics?) v be = parasitic npn base/emitter voltage (refer to v negclamp in appendix e, ?electrical characteristics?) qadc64e par stress conn r stress r selected adjacent 10k pin under parasitic i injn i in + stress v stress device pin v in an n an n+1 qadc64e par stress conn r stress r selected adjacent 10k pin under parasitic i injp i in + stress v stress device pin v in v dda an n an n+1 i injn v stress v be ? () ? r stress ------------------------------------------------ - = i injp v stress v eb ? v dda ? r stress ------------------------------------------------------------ - = 13-78 mpc565/mpc566 reference manual motorola qadc64e integration requirements r stress = source impedance (10- k ? resistor in figure 13-53 and figure 13-54 on stressed channel) r selected = source impedance on channel selected for conversion the current into (i in ) the neighboring pin is determined by the k n (current coupling ratio) of the parasitic bipolar transistor (k n << 1). the i in can be expressed by the following equation: i in =-k n *i inj where i inj is either i injn or i injp . a method for minimizing the impact of stress conditions on the qadc64e is to strategically allocate qadc64e inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress conditions. also, suitable source impedances should be selected to meet design goals and minimize the effect of stress conditions. motorola chapter 14. queued serial multi-channel module 14-1 chapter 14 queued serial multi-channel module 14.1 overview the mpc565/mpc566 contains two queued serial multi-channel modules (qsmcm_a and qsmcm_b). the qsmcm provides three serial communication interfaces: the queued serial peripheral interface (qspi) and two serial communications interfaces (sci1 and sci2). these submodules communicate with the cpu via a common slave bus interface unit (sbiu). the qspi is a full-duplex, synchronous serial interface for communicating with peripherals and other mcus. it is enhanced from the original spi in the qsmcm (queued serial module) to include a total of 160 bytes of queue ram to accommodate more receive, transmit, and control information. the duplicate, independent scis are full-duplex universal asynchronous receiver transmitter (uart) serial interface. the original qsm sci is enhanced by the addition of an sci, a common external baud clock source, and receive/transmit buffers on one sci. the sbiu provides an interface between the qsmcm module and the intermodule bus (imb3). 14.2 block diagram figure 14-1 depicts the major components of the qsmcm. 14-2 mpc565/mpc566 reference manual motorola block diagram figure 14-1. qsmcm block diagram 14.2.1 mpc565/mpc566 qsmcm details the mpc565/mpc566 has two qsmcm modules, qsmcm_a and qsmcm_b. qsmcm_a has the same functionality as the qsmcm on the mpc555/mpc556. qsmcm_b has its rxd2and pcs[3] pins muxed with the dlcmd2 (j1850) module. the muxing of the pins is controlled by the qpapcs3 bit in qsmcm_b pin assignment register (pqspar_b), according to table 14-1. the muxed pins default to dlcmd2 function at reset. since the normal function of the pcs pins within the qsmcm require that this bit be written before the pcs pin is used, the muxing appears transparent to both the qsmcm and the dlcmd2. however, only one of the modules, dlcmd2 or qsmcm can use the pins in a system. table 14-1. dlcmd2 / qsmcm_b sci2 pin mux control qpapcs3 bit value qsmcm_b / dlcmd2 pin function 0 pcs[3]_j1850_tx_b pin assigned to j1850_tx. rxd2_j1850_rx_b pin assigned to j1850_rx. pins are assigned to dlcmd2 (j1850_tx & j1850_rx) 1 pcs[3]_j1850_tx_b pin assigned to pcs[3]. rxd2_j1850_rx_b pin assigned to b_rxd2. pins are assigned to qsmcm_b sci2 (pcs[3]_b, rxd2_b) port qs sbiu imb3* qspi miso/qgpio4 sck/qgpio6 txd1/qgpo1 txd2/qgpo2 rxd1/qgpi1 rxd2/qgpi2 7 eck qspi queue ram note: sbiu bus and interface to imb3 are each 16 bits wide. pcs3/qgpio3 2 2 dsci sci2 pcs2/qgpio2 mosi/qgpio5 pcs1/qgpio1 pcs0/ss/qgpi sci1 receive and transmit queue motorola chapter 14. queued serial multi-channel module 14-3 signal descriptions because of this muxed function on qsmcm_b, the general purpose i/o functions are not available on the b_pcs[3] and b_rxd2 pins. table 14-2 shows the pin names for the modified pins. 14.3 signal descriptions the qsmcm has 12 external pins, as shown in figure 14-1. seven of the pins, if not in use for their submodule function, can be used as general-purpose i/o port pins. the rxdx and txdx pins can alternately serve as general-purpose input-only and output-only signals, respectively. eck is a dedicated input clock pin. for detailed descriptions of qsmcm signals, refer to section 14.6, ?qsmcm pin control registers,? section 14.7.3, ?qspi pins,? and section 14.8.6, ?sci pins.? 14.4 memory maps the qsmcm memory maps, shown in table 14-3 and table 14-4, include the global registers, the qspi and dual sci control and status registers, and the qspi ram. the qsmcm memory map can be divided into supervisor-only data space and assignable data space. the address offsets shown are from the base address of the qsmcm module. refer to figure 1-2 for a diagram of the mpc565/mpc566 internal memory map. table 14-2. qsmcm pins on qsmcm_a and qsmcm_b qsmcm_a pins qsmcm_b pins different pcs[0]/ss /qgpio[0]_a pcs[0]/ss /qgpio[0]_b pcs[1]/qgpio[1]_a pcs[1]/qgpio[1]_b pcs[2]/qgpio[2]_a pcs[2]/qgpio[2]_b pcs[3]/qgpio[3]_a pcs[3]/j1850/tx_b * miso/qgpio[4]_a miso/qgpio[4]_b mosi/qgpio[5]_a mosi/qgpio[5]_b sck/qgpio[6]_a sck/qgpio[6]_b ?eck_b txd1/qgpo[1]_a txd1/qgpo[1]_b txd2/qgpo[2]_a txd2/qgpo[2]_b rxd1/qgpi[1]_a rxd1/qgpi[1]_b rxd2/qgpi[2]_a rxd2/j1850_rx_b * 14-4 mpc565/mpc566 reference manual motorola memory maps table 14-3. qsmcm_a and qsmcm_b register map access 1 address msb 2 0 lsb 15 s 0x30 5000(a) 0x30 5400(b) qsmcm module configuration register (qsmcmmcr) see table 14-7 for bit descriptions. t 0x30 5002(a) 0x30 5402(b) qsmcm test register (qtest) s 0x30 5004(a) 0x30 5404(b) dual sci interrupt level (qdsci_il) see table 14-8 for bit descriptions. reserved s 0x30 5006(a) 0x30 5406(b) reserved queued spi interrupt level (qspi_il) see table 14-9 for bit descriptions. s/u 0x30 5008(a) 0x30 5408(b) sci1control register 0 (scc1r0) see table 14-27 for bit descriptions. s/u 0x30 500a(a) 0x30 540a(b) sci1control register 1 (scc1r1) see table 14-28 for bit descriptions. s/u 0x30 500c(a) 0x30 540c(b) sci1 status register (sc1sr) see table 14-29 for bit descriptions. s/u 0x30 500e(a) 0x30 540e(b) sci1 data register (sc1dr) see table 14-30 for bit descriptions. s/u 0x30 5010(a) 0x30 5410(b) reserved s/u 0x30 5012(a) 0x30 5412(b) reserved s/u 0x30 5014(a) 0x30 5414(b) reserved qsmcm port q data register (portqs) see section 14.6.1, ?port qs data register (portqs)? for bit descriptions. s/u 0x30 5016(a) 0x30 5416(b) qsmcm pin assignment register (pqspar) see table 14-14 for bit descriptions. qsmcm data direction register (ddrqs) see table 14-15 for bit descriptions. s/u 0x30 5018(a) 0x30 5418(b) qspi control register 0 (spcr0) see table 14-17 for bit descriptions. s/u 0x30 501a(a) 0x30 541a(b) qspi control register 1 (spcr1) see table 14-19 for bit descriptions. s/u 0x30 501c(a) 0x30 541c(b) qspi control register 2 (spcr2) see table 14-20 for bit descriptions. s/u 0x30 501e(a) 0x30 541e(b) qspi control register 3 (spcr3) see table 14-21 for bit descriptions. qspi status register (spsr) see table 14-22 for bit descriptions. s/u 0x30 5020(a) 0x30 5420(b) sci2 control register 0 (scc2r0) s/u 0x30 5022(a) 0x30 5422(b) sci2 control register 1 (scc2r1) s/u 0x30 5024(a) 0x30 5424(b) sci2 status register (sc2sr) motorola chapter 14. queued serial multi-channel module 14-5 memory maps the supervisor-only data space segment contains the qsmcm global registers. these registers define parameters needed by the qsmcm to integrate with the mcu. access to these registers is permitted only when the cpu is operating in supervisor mode. assignable data space can be either restricted to supervisor-only access or unrestricted to both supervisor and user accesses. the supervisor (supv) bit in the qsmcm module configuration register (qsmcmmcr) designates the assignable data space as either supervisor or unrestricted. if supv is set, then the space is designated as supervisor-only s/u 0x30 5026(a) 0x30 5426(b) sci2 data register (sc2dr) s/u 0x30 5028(a) 0x30 5428(b) qsci1 control register (qsci1cr) see table 14-35 for bit descriptions. s/u 0x30 502a(a) 0x30 542a(b) qsci1 status register (qsci1sr) see table 14-36 s/u 0x30 502c ? 0x30 504a(a) 0x30 542c ? 0x30 544a(b) transmit queue locations (sctq) s/u 0x30 504c ? 0x30 506a(a) 0x30 544c ? 0x30 546a(b) receive queue locations (scrq) s/u 0x30 506c ? 0x30 513f(a) 3 0x30 546c ? 0x30 553f(b) reserved s/u 0x305140? 0x30 517f(a) 0x30 5540 ? 0x30 557f(b) receive data ram (rec.ram) s/u 0x305180? 0x30 51bf(a) 0x30 5580 ? 0x30 55bf(b) transmit data ram (tran.ram) s/u 0x3051c0? 0x30 51df(a) 0x30 55c0 ? 0x30 55df(b) command ram (comd.ram) 1 s = supervisor access only s/u = supervisor access only or unrestricted user access (assignable data space). t=test 2 8-bit registers, such as spcr3 and spsr, are on 8-bit boundaries. 16-bit registers such as spcr0 are on 16-bit boundaries. 3 note that qram offsets have been changed from the original (modular family) qsmcm. table 14-3. qsmcm_a and qsmcm_b register map (continued) access 1 address msb 2 0 lsb 15 14-6 mpc565/mpc566 reference manual motorola qsmcm global registers space. access is then permitted only when the cpu is operating in supervisor mode. if supv is clear, both user and supervisor accesses are permitted. to clear supv, the cpu must be in supervisor mode. the qsmcm assignable data space segment contains the control and status registers for the qspi and sci submodules, as well as the qspi ram. all registers and ram can be accessed on byte (8-bit), half-word (16-bit), and word (32-bit) boundaries. word accesses require two consecutive imb3 bus cycles. 14.5 qsmcm global registers the qsmcm global registers contain system parameters used by the qspi and sci submodules for interfacing to the cpu and the intermodule bus. the global registers are listed in table 14-4 and table 14-5. table 14-4. qsmcm_a global registers access 1 1 s = supervisor access only s/u = supervisor access only or unrestricted user access (assignable data space). address msb 2 2 8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries. lsb s 0x30 5000 qsmcm module configuration register (qsmcmmcr_a) see table 14-7 for bit descriptions. t 0x30 5002 qsmcm test register (qtest_a) s 0x30 5004 dual sci interrupt level (qdsci_il_a) see table 14-8 for bit descriptions. reserved s 0x30 5006 reserved queued spi interrupt level (qspi_il_a) see table 14-9 for bit descriptions. table 14-5. qsmcm_b global registers access 1 1 s = supervisor access only s/u = supervisor access only or unrestricted user access (assignable data space). address msb 2 2 8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries. lsb s 0x30 5400 qsmcm module configuration register (qsmcmmcr_b) see table 14-7 for bit descriptions. t 0x30 5402 qsmcm test register (qtest_b) s 0x30 5404 dual sci interrupt level (qdsci_il_b) see table 14-8 for bit descriptions. reserved s 0x30 5406 reserved queued spi interrupt level (qspi_il_b) see table 14-9 for bit descriptions. motorola chapter 14. queued serial multi-channel module 14-7 qsmcm global registers 14.5.1 low-power stop operation when the stop bit in qsmcmmcr is set, the imb3 clock input to the qsmcm is disabled and the module enters a low-power operating state. qsmcmmcr is the only register guaranteed to be readable while stop is asserted. the qspi ram is not readable in low-power stop mode. however, writes to ram or any register are guaranteed valid while stop is asserted. stop can be written by the cpu and is cleared by reset. note system software must bring each submodule to an orderly stop before setting stop to avoid data corruption. the sci receiver and transmitter should be disabled after transfers in progress are complete. the qspi can be halted by setting the halt bit in spcr3 and then setting stop after the halta flag is set. 14.5.2 freeze operation the frz1 bit in qsmcmmcr determines how the qsmcm responds when the imb3 freeze signal is asserted. freeze is asserted when the cpu enters background debug mode. setting frz1 causes the qspi to halt on the first transfer boundary following freeze assertion. freeze causes the sci1 transmit queue to halt on the first transfer boundary following freeze assertion. 14.5.3 access protection the supv bit in the qsmcmmcr defines the assignable qsmcm registers as either supervisor-only data space or unrestricted data space. when the supv bit is set, all registers in the qsmcm are placed in supervisor-only space. for any access from within user mode, the imb3 address acknowledge (aack ) signal is asserted and a bus error is generated. because the qsmcm contains a mix of supervisor and user registers, aack is asserted for either supervisor or user mode accesses, and the bus cycle remains internal. if a supervisor-only register is accessed in user mode, the module responds as if an access had been made to an unauthorized register location, and a bus error is generated. 14.5.4 qsmcm interrupts the interrupt structure of the imb3 supports a total of 32 interrupt levels that are time multiplexed on the irqb [0:7] lines as seen in figure 14-2. 14-8 mpc565/mpc566 reference manual motorola qsmcm global registers figure 14-2. qsmcm interrupt levels in this structure, all interrupt sources place their asserted level on a time multiplexed bus during four different time slots, with eight levels communicated per slot. the ilbs[0:1] signals indicate which group of eight are being driven on the interrupt request lines. the qsmcm module is capable of generating one of the 32 possible interrupt levels on the imb3. the levels that the interrupt will drive can be programmed into the interrupt request level (ildsci and ilqspi) bits located in the interrupt configuration register (qdsci_il and qspi_il). this value determines which interrupt signal (irqb [0:7]) is driven onto the bus during the programmed time slot. figure 14-3 shows a block diagram of the interrupt hardware. table 14-6. interrupt levels ilbs[0:1] levels 00 0:7 01 8:15 10 16:23 11 24:31 imb3 clock ilbs[0:1] imb3 irq[7:0] irq 7:0 00 01 11 10 irq 15:8 irq 23:16 irq 31:24 irq 7:0 00 01 11 10 motorola chapter 14. queued serial multi-channel module 14-9 qsmcm global registers figure 14-3. qspi interrupt generation 14.5.5 qsmcm configuration register (qsmcmmcr) the qsmcmmcr contains parameters for interfacing to the cpu and the intermodule bus. this register can be modified only when the cpu is in supervisor mode. attempted access from user mode will cause a bus error to be generated. msb 0 1234567891011121314lsb 15 stop frz1 reserved supv reserved reset: 0 000000010000000 figure 14-4. qsmcmmcr ? qsmcm configuration register 0x30 5000 0x30 5400 irq[7:0] interrupt level encoder ilbs[0:1] sci1 and 2 int qspi[4:0] int lev reg. [4:0] 2 lev reg. [4:0] 5 5 sci_1 interrupt sci_2 interrupt qspi interrupt 8 interrupt level decoder 8 8 14-10 mpc565/mpc566 reference manual motorola qsmcm global registers 14.5.6 qsmcm test register (qtest) the qtest register is used for factory testing of the mcu. 14.5.7 qsmcm interrupt level registers (qdsci_il, qspi_il) the qdsci_ili and qspi_il registers determine the interrupt level requested by the qsmcm. the two sci submodules (dsci) share a 5-bit interrupt level field, ildsci. the qspi uses a separate field, ilqspi. the level value is used to determine which interrupt is serviced first when two or more modules or external peripherals simultaneously request an interrupt. the user can select among 32 levels. this register can be accessed only when the cpu is in supervisor mode. table 14-7. qsmcmmcr bit descriptions bit(s) name description 0 stop stop enable. refer to section 14.5.1, ?low-power stop operation.? 0 normal clock operation 1 internal clocks stopped 1 frz1 freeze1 bit. refer to section 14.5.2, ?freeze operation.? 0 ignore the freeze signal 1 halt the qsmcm (on transfer boundary) 2:7 ? reserved 8 supv supervisor / unrestricted. refer to section 14.5.3, ?access protection.? 0 assigned registers are unrestricted (user access allowed) 1 assigned registers are restricted (only supervisor access allowed) 9:11 ? reserved 12:15 ? reserved. these bits are used for the iarb (interrupt arbitration id) field in qsm implementations that use hardware interrupt arbitration. msb 0 1234567891011121314lsb 15 reserved ildsci reserved reset: 0 0000000 figure 14-5. qdsci_il ? qsm2 dual sci interrupt level register 0x30 5004 0x30 5404 motorola chapter 14. queued serial multi-channel module 14-11 qsmcm pin control registers 14.6 qsmcm pin control registers table 14-10 lists the three qsmcm pin control registers. each qsmcm uses 12 pins. eleven of the pins (nine on qsmcm_b), when not being used by the serial sub-systems, form a parallel port on the mcu. (the eck pin is a dedicated external clock source.) table 14-8. qdsci_il bit descriptions bit(s) name description 0:2 ? reserved 3:7 ildsci interrupt level of dual scis 00000lowest interrupt level request (level 0) 11111 highest interrupt level request (level 31) 8:15 ? reserved msb 0 1234567891011121314lsb 15 reserved ilqspi reset: 0 00000000 0000000 figure 14-6. qspi_il ? qspi interrupt level register 0x30 5006 0x30 5406 table 14-9. qspi_il bit descriptions bit(s) name description 0:10 ? reserved 11:15 ilqspi interrupt level of spi 00000lowest interrupt level request (level 0) 11111 highest interrupt level request (level 31) table 14-10. qsmcm pin control registers address register 0x30 5014 0x30 5414 qsmcm port data register (portqs) see section 14.6.1, ?port qs data register (portqs)? for bit descriptions. 0x30 5016 0x30 5416 portqs pin assignment register (pqspar) see table 14-14 for bit descriptions. 0x30 5017 0x30 5417 portqs data direction register (ddrqs) see table 14-15 for bit descriptions. 14-12 mpc565/mpc566 reference manual motorola qsmcm pin control registers the port qs pin assignment register (pqspar) governs the usage of qspi pins. clearing a bit assigns the corresponding pin to general-purpose i/o; setting a bit assigns the pin to the qspi. qpapcs[3] (bit 1) of pqspar_b selects between the j1850_tx/j1850_rx and b_pcs[3]/b_rxd2. pqspar does not affect operation of the sci. when the scix transmitter is disabled, txdx is a digital output; when the scix receiver is disabled, rxdx is a digital input. when the scix transmitter or receiver is enabled, the associated txdx or rxdx pin is assigned its sci function. the port qs data direction register (ddrqs) determines whether qspi pins are inputs or outputs. clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. ddrqs affects both qspi function and i/o function. table 14-15 summarizes the effect of ddrqs bits on qspi pin function. ddrqs does not affect sci pin function. txdx pins are always outputs, and rxdx pins are always inputs, regardless of whether they are functioning as sci pins or as portqs pins. the port qs data register (portqs) latches i/o data. portqs writes drive pins defined as outputs. portqs reads return data present on the pins. to avoid driving undefined data, write data to portqs before configuring ddrqs. table 14-11. effect of ddrqs on qspi pin function qsmcm pin mode ddrqs bit bit state pin function miso master ddqs[0] 0 serial data input to qspi 1 disables data input slave 0 disables data output 1 serial data output from qspi mosi master ddqs[1] 0 disables data output 1 serial data output from qspi slave 0 serial data input to qspi 1 disables data input sck 1 master ddqs[2] ? clock output from qspi slave ? clock input to qspi pcs[0]/ss master ddqs[3] 0 assertion causes mode fault 1 chip-select output slave 0 qspi slave select input 1 disables slave select input motorola chapter 14. queued serial multi-channel module 14-13 qsmcm pin control registers 14.6.1 port qs data register (portqs) portqs determines the actual input or output value of a qsmcm port pin if the pin is defined as general-purpose input or output. all qsmcm pins except the eck pin can be used as general-purpose input and/or output. when the scix transmitter is disabled, txdx is a digital output; when the scix receiver is disabled, rxdx is a digital input. writes to this register affect the pins defined as outputs; reads of this register return the actual value of the pins. 14.6.2 portqs pin assignment register (pqspar) pqspar determines which of the qspi pins, with the exception of the sck pin, are used by the qspi submodule, and which pins are available for general-purpose i/o. pins may be assigned on a pin-by-pin basis. if the qspi is disabled, the sck pin is automatically assigned its general-purpose i/o function (qgpio6). qspi pins designated by pqspar as general-purpose i/o pins are controlled only by pqsddr and pqspdr; the qspi has no effect on these pins. pqspar does not affect the operation of the sci submodule. table 14-12 and table 14-13 summarizes the qsmcm pin functions. pcs[1:3] master ddqs[4:6] 0 disables chip-select output 1 chip-select output slave 0 inactive 1inactive 1 sck/qgpio6 is a digital i/o pin unless the spi is enabled (spe set in spcr1), in which case it becomes the qspi serial clock sck. msb 0 1234567891011121314lsb 15 reserved qdr xd2 qdtx d2 qdr xd1 qdtx d1 0qdp cs3 qdp cs2 qdp cs1 qdp cs0 qds ck qdm osi qdmi so reset: 0 000010100000000 figure 14-7. portqs ? port qs data register 0x30 5014 0x30 5414 table 14-11. effect of ddrqs on qspi pin function (continued) qsmcm pin mode ddrqs bit bit state pin function 14-14 mpc565/mpc566 reference manual motorola qsmcm pin control registers table 14-12. qsmcm_a pin functions portqs function qsmcm function qgpi2 rxd2 qgpo2 txd2 qgpi1 rxd1 qgpo1 txd1 qgpio6 sck qgpio5 mosi qgpio4 miso qgpio3 pcs3 qgpio2 pcs2 qgpio1 pcs1 qgpio0 pcs0 table 14-13. qsmcm_b pin functions portqs function qsmcm function j1850_rx rxd2 qgpo2 txd2 qgpi1 rxd1 qgpo1 txd1 qgpio6 sck qgpio5 mosi qgpio4 miso j1850_tx pcs3 qgpio2 pcs2 qgpio1 pcs1 qgpio0 pcs[0] msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 0 qpapcs 3 qpapcs 2 qpapcs 1 qpapcs 0 0qpamo si qpamiso ddrqs* reset: 0000000 0 note: see bit descriptions in table 14-15 figure 14-8. pqspar ? portqs pin assignment register 0x30 5016 0x30 5416 motorola chapter 14. queued serial multi-channel module 14-15 qsmcm pin control registers 14.6.3 portqs data direction register (ddrqs) ddrqs assigns qspi pin as an input or an output regardless of whether the qspi submodule is enabled or disabled. all qspi pins are configured during reset as general-purpose inputs. this register does not affect sci operation. the txd1 and txd2 remain output pins dedicated to the sci submodules, and the rxd1, rxd2 and eck pins remain input pins dedicated to the sci submodules. table 14-14. pqspar bit descriptions bit(s) name description 0?reserved 1 qpapcs3 0 pin is assigned qgpio[3] in qsmcm_a or j1850_tx on qsmcm_b 1 pin is assigned pcs[3] function when j1850_tx is selected, b_rxd2 becomes j1850_rx 2 qpapcs2 0 pin is assigned qgpio[2] 1 pin is assigned pcs[2] function 3 qpapcs1 0 pin is assigned qgpio[3] 1 pin is assigned pcs[3] 4 qpapcs0 0 pin is assigned qgpio[0] 1 pin is assigned pcs[0] function 5?reserved 6 qpamosi 0 pin is assigned qgpio[5] 1 pin is assigned mosi function 7 qpamiso 0 pin is assigned qgpio[4] 1 pin is assigned miso function 8:15 ddrqs porstqs data direction register. see section 14.6.3, ?portqs data direction register (ddrqs),? on page 14-15. msb 0 1234567 8 9 10 11 12 13 14 lsb 15 pqspar* 0 qddpcs 3 qddpcs 2 qddpcs 1 qddp cs0 qdds ck qddm osi qddmi so reset: 0 0 0 0 0000 note: see bit descriptions in table 14-14 figure 14-9. ddrqs ? portqs data direction register 0x30 5016 0x30 5416 14-16 mpc565/mpc566 reference manual motorola queued serial peripheral interface 14.7 queued serial peripheral interface the queued serial peripheral interface (qspi) is used to communicate with external devices through a synchronous serial bus. the qspi is fully compatible with spi systems found on other motorola products, but has enhanced capabilities. the qspi can perform full duplex three-wire or half duplex two-wire transfers. several transfer rates, clocking, and interrupt-driven communication options are available. figure 14-10 is a block diagram of the qspi. table 14-15. ddrqs bit descriptions bit(s) name description 0:7 pqspar portsqs pin assignment register. see section 14.6.2, ?portqs pin assignment register (pqspar).? 8?reserved 9 qddpcs3 qspi pin data direction for the pin pcs3 0 pin direction is input 1 pin direction is output 10 qddpcs2 qspi pin data direction for the pin pcs2 0 pin direction is input 1 pin direction is output 11 qddpcs1 qspi pin data direction for the pin pcs1 0 pin direction is input 1 pin direction is output 12 qddpcs0 qspi pin data direction for the pin pcs0 0 pin direction is input 1 pin direction is output 13 qddsck qspi pin data direction for the pin sck 0 pin direction is input 1 pin direction is output 14 qpdmosi qspi pin data direction for the pin mosi 0 pin direction is input 1 pin direction is output 15 qpdmiso qspi pin data direction for the pin miso 0 pin direction is input 1 pin direction is output motorola chapter 14. queued serial multi-channel module 14-17 queued serial peripheral interface figure 14-10. qspi block diagram serial transfers of eight to 16 bits can be specified. programmable transfer length simplifies interfacing to devices that require different data lengths. an inter-transfer delay of approximately 0.8 to 204 s (using a 40-mhz imb3 clock) can be programmed. the default delay is 17 clocks (0.425 s at 40 mhz). programmable delay simplifies the interface to devices that require different delays between transfers. qspi block control registers end queue pointer queue pointer status register delay counter comparator programmable logic array 160-byte qspi ram chip select command done 4 4 2 baud rate generator pcs[2:1] pcs0/ss miso mosi sck m s m s 8/16-bit shift register rx/tx data register msb lsb 4 4 queue control block control logic a d d r e s s r e g i s t e r tx data rx data 14-18 mpc565/mpc566 reference manual motorola queued serial peripheral interface a dedicated 160-byte ram is used to store received data, data to be transmitted, and a queue of commands. the cpu can access these locations directly. this allows serial peripherals to be treated like memory-mapped parallel devices. the command queue allows the qspi to perform up to 32 serial transfers without cpu intervention. each queue entry contains all the information needed by the qspi to independently complete one serial transfer. a pointer identifies the queue location containing the data and command for the next serial transfer. normally, the pointer address is incremented after each serial transfer, but the cpu can change the pointer value at any time. support for multiple tasks can be provided by segmenting the queue. the qspi has four peripheral chip-select pins. the chip-select signals simplify interfacing by reducing cpu intervention. if the chip-select signals are externally decoded, 16 independent select signals can be generated. wrap-around mode allows continuous execution of queued commands. in wraparound mode, newly received data replaces previously received data in the receive ram. wrap-around mode can simplify the interface with a/d converters by continuously updating conversion values stored in the ram. continuous transfer mode allows transfer of an uninterrupted bit stream. from eight to 512 bits can be transferred without cpu intervention. longer transfers are possible, but minimal intervention is required to prevent loss of data. a standard delay of 17 imb3 clocks (0.8 s with a 40-mhz imb3 clock) is inserted between the transfer of each queue entry. 14.7.1 qspi registers the qspi memory map, shown in table 14-16, includes the qsmcm global and pin control registers, four qspi control registers (spcr[0:3]), the status register (spsr), and the qspi ram. registers and ram can be read and written by the cpu. the memory map can be divided into supervisor-only data space and assignable data space. the address offsets shown are from the base address of the qsmcm module. refer to figure 1-2 for a diagram of the mpc565/mpc566 internal memory map. table 14-16. qspi register map access 1 address msb 2 lsb s/u 0x30 5018(a) 0x30 5418(b) qspi control register 0 (spcr0) see table 14-17 for bit descriptions. s/u 0x30 501a(a) 0x30 541a(b) qspi control register 1 (spcr1) see table 14-19 for bit descriptions. s/u 0x30 501c(a) 0x30 541c(b) qspi control register 2 (spcr2) see table 14-20 for bit descriptions. motorola chapter 14. queued serial multi-channel module 14-19 queued serial peripheral interface to ensure proper operation, set the qspi enable bit (spe) in spcr1 only after initializing the other control registers. setting this bit starts the qspi. rewriting the same value to a control register does not affect qspi operation with the exception of writing newqp in spcr2. rewriting the same value to these bits causes the ram queue pointer to restart execution at the designated location. before changing control bits, the qspi should be halted. writing a different value into a control register other than spcr2 while the qspi is enabled may disrupt operation. spcr2 is buffered, preventing any disruption of the current serial transfer. after the current serial transfer is completed, the new spcr2 value becomes effective. 14.7.1.1 qspi control register 0 spcr0 contains parameters for configuring the qspi before it is enabled. the cpu has read/write access to spcr0, but the qspi has read access only. spcr0 must be initialized before qspi operation begins. writing a new value to spcr0 while the qspi is enabled disrupts operation. s/u 0x30 501e/ 0x30 501f(a) 0x30 541e/ 0x30 541f(b) qspi control register 3 (spcr3) see table 14-21 for bit descriptions. qspi status register (spsr) see table 14-22 for bit descriptions. s/u 0x30 5140 ? 0x30 517f(a) 0x30 5540 ? 0x30 557f(b) receivedataram(32half-words) s/u 0x30 5180 ? 0x30 51bf(a) 0x30 5580 ? 0x30 55bf(b) transmit data ram (32 half-words) s/u 0x30 51c0 ? 0x30 51df(a) 0x30 55c0 ? 0x30 55df(b) command ram (32 bytes) 1 s = supervisor access only s/u = supervisor access only or unrestricted user access (assignable data space). 2 8-bit registers, such as spcr3 and spsr, are on 8-bit boundaries. 16-bit registers such as spcr0 are on 16-bit boundaries. table 14-16. qspi register map (continued) access 1 address msb 2 lsb 14-20 mpc565/mpc566 reference manual motorola queued serial peripheral interface msb 0 1 23456 7 891011121314lsb 15 mstr womq bits cpol cpha spbr reset: 0 0 00000 1 00000100 figure 14-11. spcr0 ? qspi control register 0 0x30 5018 0x30 5418 table 14-17. spcr0 bit descriptions bit(s) name description 0 mstr master/slave mode select 0 qspi is a slave device and only responds to externally generated serial transfers. 1 qspi is the system master and can initiate transmission to external spi devices. 1 womq wired-or mode for qspi pins. this bit controls the qspi pins regardless of whether they are used as general-purpose outputs or as qspi outputs, and regardless of whether the qspi is enabled or disabled. 0 pins designated for output by ddrqs operate in normal mode. 1 pins designated for output by ddrqs operate in open drain mode. 2:5 bits bits per transfer. in master mode, when bitse is set in a command ram byte, bits determines the number of data bits transferred. when bitse is cleared, eight bits are transferred regardless of the value in bits. in slave mode, the bits field always determines the number of bits the qspi will receive during each transfer before storing the received data. data transfers from 8 to 16 bits are supported. illegal (reserved) values default to eight bits.table 14-18 shows the number of bits per transfer. 6 cpol clock polarity. cpol is used to determine the inactive state of the serial clock (sck). it is used with cpha to produce a desired clock/data relationship between master and slave devices. 0 the inactive state of sck is logic zero. 1 the inactive state of sck is logic one. 7 cpha clock phase. cpha determines which edge of sck causes data to change and which edge causes data to be captured. cpha is used with cpol to produce a desired clock/data relationship between master and slave devices. 0 data is captured on the leading edge of sck and changed on the trailing edge of sck. 1 data is changed on the leading edge of sck and captured on the trailing edge of sck 8:15 spbr serial clock baud rate. the qspi uses a modulus counter to derive the sck baud rate from the mcu imb3 clock. baud rate is selected by writing a value from 2 to 255 into spbr. the following equation determines the sck baud rate: refer to section 14.7.5.2, ?baud rate selection? for more information. table 14-18. bits per transfer bits[3:0] bits per transfer 0000 16 0001 to 0111 reserved (defaults to 8) sck baud rate f sys 2 spbr motorola chapter 14. queued serial multi-channel module 14-21 queued serial peripheral interface 14.7.1.2 qspi control register 1 spcr1 enables the qspi and specifies transfer delays. the cpu has read/write access to spcr1, but the qspi has read access only to all bits except spe. spcr1 must be written last during initialization because it contains spe. the qspi automatically clears this bit after it completes all serial transfers or when a mode fault occurs. writing a new value to spcr1 while the qspi is enabled disrupts operation. 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 msb 0 1234567891011121314lsb 15 spe dsckl dtl reset: 0 000010000000100 figure 14-12. spcr1 ? qspi control register 10x30 501a 0x30 541a table 14-19. spcr1 bit descriptions bit(s) name description 0 spe qspi enable. refer to section 14.7.4.1, ?enabling, disabling, and halting the qspi.? 0 qspi is disabled. qspi pins can be used for general-purpose i/o. 1 qspi is enabled. pins allocated by pqspar are controlled by the qspi. table 14-18. bits per transfer (continued) bits[3:0] bits per transfer 14-22 mpc565/mpc566 reference manual motorola queued serial peripheral interface 14.7.1.3 qspi control register 2 spcr2 contains qspi queue pointers, wraparound mode control bits, and an interrupt enable bit. the cpu has read/write access to spcr2, but the qspi has read access only. writes to this register are buffered. new spcr2 values become effective only after completion of the current serial transfer. rewriting newqp in spcr2 causes execution to restart at the designated location. reads of spcr2 return the current value of the register, not the buffer. 1:7 dsckl delay before sck. when the dsck bit is set in a command ram byte, this field determines the length of the delay from pcs valid to sck transition. the following equation determines the actual delay before sck: where dsckl is in the range of 1 to 127. refer to section 14.7.5.3, ?delay before transfer? for more information. 8:15 dtl length of delay after transfer. when the dt bit is set in a command ram byte, this field determines the length of the delay after a serial transfer. when the dt bit is cleared (default) in the command ram byte, the standard delay is inserted. the following equation is used to calculate the delay: a dtl value of 0 is a special case and causes the delay to be calculated as follows: refer to section 14.7.5.4, ?delay after transfer? for more information. msb 0 1 2 34567891011121314lsb 15 spifie wren wrto endqp reserved newqp reset: 0 0 0 0000000000000 figure 14-13. spcr2 ? qspi control register 2 0x30 501c 0x30 541c table 14-19. spcr1 bit descriptions (continued) bit(s) name description pcs to sck delay dsckl f sys ------------------- - = delay after transfer 32 dtl ? 32 256 ? motorola chapter 14. queued serial multi-channel module 14-23 queued serial peripheral interface 14.7.1.4 qspi control register 3 spcr3 contains the loop mode enable bit, halt and mode fault interrupt enable, and the halt control bit. the cpu has read/write access to spcr3, but the qspi has read access only. spcr3 must be initialized before qspi operation begins. writing a new value to spcr3 while the qspi is enabled disrupts operation. table 14-20. spcr2 bit descriptions bit(s) name description 0 spifie spi finished interrupt enable. refer to section 14.7.4.2, ?qspi interrupts.? 0 qspi interrupts disabled 1 qspi interrupts enabled 1 wren wrap enable. refer to section 14.7.5.7, ?master wraparound mode.? 0 wraparound mode disabled. 1 wraparound mode enabled. 2 wrto wrap to. when wraparound mode is enabled and after the end of queue has been reached, wrto determines which address the qspi executes next. the end of queue is determined by an address match with endqp. 0 wrap to pointer address 0x0 1 wrap to address in newqp 3:7 endqp ending queue pointer. this field determines the last absolute address in the queue to be completed by the qspi. after completing each command, the qspi compares the queue pointer valueofthejust-completedcommandwiththevalueofendqp.ifthetwovaluesmatch,theqspi sets spif to indicate it has reached the end of the programmed queue. refer to section 14.7.4, ?qspi operation? for more information. 8:10 ? reserved 11:15 newqp new queue pointer value. this field contains the first qspi queue address. refer to section 14.7.4, ?qspi operation? for more information. msb 0 1234 5 67891011121314lsb 15 reserved loopq hmie halt spsr* reset: 00000 0 00 note: see bit descriptions in table 14-22 figure 14-14. spcr3 ? qspi control register0x30 501e 0x30 541e table 14-21. spcr3 bit descriptions bit(s) name description 0:4 ? reserved 5 loopq qspi loop mode. loopq controls feedback on the data serializer for testing. 0 feedback path disabled. 1 feedback path enabled. 14-24 mpc565/mpc566 reference manual motorola queued serial peripheral interface 14.7.1.5 qspi status register the spsr contains information concerning the current serial transmission. only the qspi can set bits in this register. to clear status flags, the cpu reads spsr with the flags set and then writes the spsr with zeros in the appropriate bits. writes to cptqp have no effect. * 6 hmie halta and modf interrupt enable. hmie enables interrupt requests generated by the halta status flag or the modf status flag in spsr. 0 halta and modf interrupts disabled. 1 halta and modf interrupts enabled. 7 halt halt qspi. when halt is set, the qspi stops on a queue boundary. it remains in a defined state from which it can later be restarted. refer to section 14.7.4.1, ?enabling, disabling, and halting the qspi.? 0 qspi operates normally. 1 qspi is halted for subsequent restart. 8:15 ? spsr. seetable 14-22 for bit descriptions. msb 0 12345678 9 1011121314lsb 15 spcr3 1 spif modf halta cptqp 0 0 0 00000 1 see bit descriptions intable 14-21 2 spsr can be accessed as an 8-bit register at location 0x30 501f or 0x30 541f. figure 14-15. spsr ? qspi status register 0x30 501e 2 0x30 541e 2 table 14-22. spsr bit descriptions bit(s) name description 0:7 spcr3 see bit descriptions in table 14-21. 8 spif qspi finished flag. spif is set after execution of the command at the address in endqp in spcr2. if wraparound mode is enabled (wren = 1), the spif is set, after completion of the command defined by endqp, each time the qspi cycles through the queue. 0 qspi is not finished 1 qspi is finished 9 modf mode fault flag. the qspi asserts modf when the qspi is in master mode (mstr = 1) and the ss input pin is negated by an external driver. refer to section 14.7.8, ?mode fault? for more information. 0 normal operation 1 another spi node requested to become the network spi master while the qspi was enabled in master mode (ss input taken low). table 14-21. spcr3 bit descriptions (continued) bit(s) name description motorola chapter 14. queued serial multi-channel module 14-25 queued serial peripheral interface 14.7.2 qspi ram the qspi contains a 160-byte block of dual-ported static ram that can be accessed by both the qspi and the cpu. because of this dual access capability, up to two wait states may be inserted into cpu access time if the qspi is in operation. the size and type of access of the qspi ram by the cpu affects the qspi access time. the qspi allows byte, half-word, and word accesses. only word accesses of the ram by the cpu are coherent because these accesses are an indivisible operation. if the cpu makes a coherent access of the qspi ram, the qspi cannot access the qspi ram until the cpu is finished. however, a word or misaligned word access is not coherent because the cpu must break its access of the qspi ram into two parts, which allows the qspi to access the qspi ram between the two accesses by the cpu. the ram is divided into three segments: receive data ram, transmit data ram, and command data ram. receive data is information received from a serial device external to the mcu. transmit data is information stored for transmission to an external device. command data defines transfer parameters. figure 14-16 shows ram organization. figure 14-16. qspi ram 10 halta halt acknowledge flag. halta is set when the qspi halts in response to setting the halt bit in spcr3. halta is also set when the imb3 freeze signal is asserted, provided the frz1 bit in the qsmcmmcr is set. to prevent undefined operation, no modification should be made to any qspi control registers or ram while the qspi is halted. if hmie in spcr3 is set the qspi sends interrupt requests to the cpu when halta is asserted. 0 qspi is not halted. 1 qspi is halted 11:15 cptqp completed queue pointer. cptqp points to the last command executed. it is updated when the current command is complete. when the first command in a queue is executing, cptqp contains either the reset value 0x0 or a pointer to the last command completed in the previous queue. if the qspi is halted, cptqp may be used to determine which commands have not been executed. the cptqp may also be used to determine which locations in the receive data segment of the qspi ram contain valid received data. table 14-22. spsr bit descriptions (continued) bit(s) name description receive ram transmit ram 0x30 5140 0x30 517f 0x30 5180 0x30 51bf half-word 0x30 51c0 0x30 51df command ram byte half-word rr0 rr1 rr2 rrd rre rrf tr0 tr1 tr2 trd tre trf cr0 cr1 cr2 crd cre crf or 0x30 5540 or 0x30 557f or 0x30 55c0 or 0x30 55df or 0x30 5580 oe 0x30 55bf 14-26 mpc565/mpc566 reference manual motorola queued serial peripheral interface 14.7.2.1 receive ram data received by the qspi is stored in this segment, to be read by the cpu. data stored in the receive ram is right-justified, (i.e., the least significant bit is always in the right-most bit position within the word regardless of the serial transfer length). unused bits in a receive queue entry are set to zero by the qspi upon completion of the individual queue entry. the cpu can access the data using byte, half-word, or word addressing. the cptqp value in spsr shows which queue entries have been executed. the cpu uses this information to determine which locations in receive ram contain valid data before reading them. 14.7.2.2 transmit ram data that is to be transmitted by the qspi is stored in this segment. the cpu normally writes one word of data into this segment for each queue command to be executed. if the corresponding peripheral, such as a serial input port, is used solely to input data, then this segment does not need to be initialized. data must be written to transmit ram in a right-justified format. the qspi cannot modify information in the transmit ram. the qspi copies the information to its data serializer for transmission. information remains in transmit ram until overwritten. 14.7.2.3 command ram command ram is used by the qspi in master mode. the cpu writes one byte of control information to this segment for each qspi command to be executed. the qspi cannot modify information in command ram. command ram consists of 32 bytes. each byte is divided into two fields. the peripheral chip-select field, enables peripherals for transfer. the command control field provides transfer options. a maximum of 32 commands can be in the queue. these bytes are assigned an address from 0x00 to 0x1f. queue execution by the qspi proceeds from the address in newqp through the address in endqp. (both of these fields are in spcr2.) motorola chapter 14. queued serial multi-channel module 14-27 queued serial peripheral interface refer to section 14.7.5, ?master mode operation? for more information on the command ram. 14.7.3 qspi pins seven pins are associated with the qspi. when not needed by the qspi, they can be configured for general-purpose i/o. table 14-24 identifies the qspi pins and their functions. register ddrqs determines whether the pins are designated as input or output. the user must initialize ddrqs for the qspi to function correctly. msb 0 123456lsb 7 cont bitse dt dsck pcs3 pcs2 pcs1 pcs0 1 1 ???????? cont bitse dt dsck pcs3 pcs2 pcs1 pcs0 1 command control peripheral chip select 1 the pcs[0] bit represents the dual-function pcs[0]/ss. figure 14-17. cr[0:f] ? command ram0x30 51c0 ? 0x30 51df 0x30 55c0 ? 0x30 55df table 14-23. command ram bit descriptions bit(s) name description 0 cont continue 0 control of chip selects returned to portqs after transfer is complete. 1 peripheral chip selects remain asserted after transfer is complete. 1 bitse bits per transfer enable 0eightbits 1 number of bits set in bits field of spcr0. 2 dt delay after transfer 0 delay after transfer is 17 14-28 mpc565/mpc566 reference manual motorola queued serial peripheral interface 14.7.4 qspi operation the qspi uses a dedicated 160-byte block of static ram accessible by both the qspi and the cpu to perform queued operations. the ram is divided into three segments: 32 command control bytes, 64 transmit data bytes, and 64 receive data bytes. once the cpu has set up a queue of qspi commands, written the transmit data segment with information to be sent, and enabled the qspi, the qspi operates independently of the cpu. the qspi executes all of the commands in its queue, sets a flag indicating completion, and then either interrupts the cpu or waits for cpu intervention. qspi ram is organized so that one byte of command data, one word of transmit data, and one word of receive data correspond to each queue entry, 0x0 to 0x2f. the cpu initiates qspi operation by setting up a queue of qspi commands in command ram, writing transmit data into transmit ram, then enabling the qspi. the qspi executes the queued commands, sets a completion flag (spif), and then either interrupts the cpu or waits for intervention. there are four queue pointers. the cpu can access three of them through fields in qspi registers. the new queue pointer (newqp), contained in spcr2, points to the first command in the queue. an internal queue pointer points to the command currently being executed. the completed queue pointer (cptqp), contained in spsr, points to the last command executed. the end queue pointer (endqp), contained in spcr2, points to the final command in the queue. table 14-24. qspi pin functions pin names mnemonic mode function master in slave out miso master slave serial data input to qspi serial data output from qspi master out slave in mosi master slave serial data output from qspi serial data input to qspi serial clock sck 1 1 all qspi pins (except sck) can be used as general-purpose i/o if they are not used by the qspi while the qspi is operating. sck can only be used for general-purpose i/o if the qspi is disabled. master slave clock output from qspi clock input to qspi peripheral chip selects pcs[1:3] master outputs select peripheral(s) peripheral chip select 2 slave select 3 2 an output (pcs[0]) when the qspi is in master mode. 3 an input (ss ) when the qspi is in slave mode. pcs[0]/ ss master slave output selects peripheral(s) input selects the qspi slave select 4 4 an input (ss ) when the qspi is in master mode; useful in multimaster systems. ss master may cause mode fault motorola chapter 14. queued serial multi-channel module 14-29 queued serial peripheral interface the internal pointer is initialized to the same value as newqp. during normal operation, the command pointed to by the internal pointer is executed, the value in the internal pointer is copied into cptqp, the internal pointer is incremented, and then the sequence repeats. execution continues at the internal pointer address unless the newqp value is changed. after each command is executed, endqp and cptqp are compared. when a match occurs, the spif flag is set and the qspi stops and clears spe, unless wraparound mode is enabled. at reset, newqp is initialized to 0x0. when the qspi is enabled, execution begins at queue address 0x0 unless another value has been written into newqp. endqp is initialized to 0x0 at reset but should be changed to the last queue entry before the qspi is enabled. newqp and endqp can be written at any time. when newqp changes, the internal pointer value also changes. however, if newqp is written while a transfer is in progress, the transfer is completed normally. leaving newqp and endqp set to 0x0 transfers only the data in transmit ram location 0x0. 14.7.4.1 enabling, disabling, and halting the qspi the spe bit in the spcr1 enables or disables the qspi submodule. setting spe causes the qspi to begin operation. if the qspi is a master, setting spe causes the qspi to begin initiating serial transfers. if the qspi is a slave, the qspi begins monitoring the pcs0/ss pin to respond to the external initialization of a serial transfer. when the qspi is disabled, the cpu may use the qspi ram. when the qspi is enabled, both the qspi and the cpu have access to the qspi ram. the cpu has both read and write access to all 160 bytes of the qspi ram. the qspi can read-only the transmit data segment and the command control segment and can write-only the receive data segment of the qspi ram. the qspi turns itself off automatically when it is finished by clearing spe. an error condition called mode fault (modf) also clears spe. this error occurs when pcs0/ss is configured for input, the qspi is a system master (mstr = 1), and pcs0/ss is driven low externally. setting the halt bit in spcr3 stops the qspi on a queue boundary. the qspi halts in a known state from which it can later be restarted. when halt is set, the qspi finishes executing the current serial transfer (up to 16 bits) and then halts. while halted, if the command control bit (cont of the qspi ram) for the last command was asserted, the qspi continues driving the peripheral chip select pins with the value designated by the last command before the halt. if cont was cleared, the qspi drives the peripheral chip-select pins to the value in register portqs. if halt is set during the last command in the queue, the qspi completes the last command, sets both halta and spif, and clears spe. if the last queue command has not 14-30 mpc565/mpc566 reference manual motorola queued serial peripheral interface been executed, asserting halt does not set spif or clear spe. qspi execution continues when the cpu clears halt. to stop the qspi, assert the halt bit in spcr3, then wait until the halta bit in spsr is set. spe can then be safely cleared, providing an orderly method of shutting down the qspi quickly after the current serial transfer is completed. the cpu can disable the qspi immediately by clearing spe. however, loss of data from a current serial transfer may result and confuse an external spi device. 14.7.4.2 qspi interrupts the qspi has three possible interrupt sources but only one interrupt vector. these sources are spif, modf, and halta. when the cpu responds to a qspi interrupt, the interrupt cause must ascertained by reading the spsr. any interrupt that was set may then be cleared by writing to spsr with a zero in the bit position corresponding to the interrupt source. the spifie bit in spcr2 enables the qspi to generate an interrupt request upon assertion of the spif status flag. because it is buffered, the value written to spifie applies only upon completion of the queue (the transfer of the entry indicated by endpq). thus, if a single sequence of queue entries is to be transferred (i.e., no wrap), then spifie should be set to the desired state before the first transfer. if a sub-queue is to be used, the same cpu write that causes a branch to the sub-queue may enable or disable the spif interrupt for the sub-queue. the primary queue retains its own selected interrupt mode, either enabled or disabled. the spif interrupt must be cleared by clearing spif. subsequent interrupts may then be prevented by clearing spifie. clearing spifie does not immediately clear an interrupt already caused by spif. 14.7.4.3 qspi flow the qspi operates in either master or slave mode. master mode is used when the mcu initiates data transfers. slave mode is used when an external device initiates transfers. switching between these modes is controlled by mstr in spcr0. before entering either mode, appropriate qsmcm and qspi registers must be initialized properly. in master mode, the qspi executes a queue of commands defined by control bits in each command ram queue entry. chip-select pins are activated, data is transmitted from the transmit ram and received by the receive ram. in slave mode, operation proceeds in response to ss pin assertion by an external spi bus master. operation is similar to master mode, but no peripheral chip selects are generated, and the number of bits transferred is controlled in a different manner. when the qspi is selected, it automatically executes the next queue transfer to exchange data with the external device correctly. motorola chapter 14. queued serial multi-channel module 14-31 queued serial peripheral interface although the qspi inherently supports multi-master operation, no special arbitration mechanism is provided. a mode fault flag (modf) indicates a request for spi master arbitration. system software must provide arbitration. note that unlike previous spi systems, mstr is not cleared by a mode fault being set nor are the qspi pin output drivers disabled. the qspi and associated output drivers must be disabled by clearing spe in spcr1. figure 14-18 shows qspi initialization. figure 14-19 and figure 14-22 show qspi master and slave operation. the cpu must initialize the qsmcm global and pin registers and the qspi control registers before enabling the qspi for either mode of operation. the command queue must be written before the qspi is enabled for master mode operation. any data to be transmitted should be written into transmit ram before the qspi is enabled. during wraparound operation, data for subsequent transmissions can be written at any time. 14-32 mpc565/mpc566 reference manual motorola queued serial peripheral interface figure 14-18. flowchart of qspi initialization operation initialize qsmcm global registers initialize qspi control registers initialize pqspar, portqs, and ddrqs initialize qspi ram enable qspi begin a2 qspi initialization mstr = 1 ? a1 y n in this order motorola chapter 14. queued serial multi-channel module 14-33 queued serial peripheral interface figure 14-19. flowchart of qspi master operation (part 1) read command control and transmit data from ram using queue pointer address a1 working queue pointer changedtonewqp is qspi disabled? n y n execute serial transfer store received data in ram using queue pointer address b1 qspi cycle begins (master mode) y assert peripheral chip select(s) is pcs to sck delay programmed? n execute standard delay y execute programmed delay has newqp been written? 14-34 mpc565/mpc566 reference manual motorola queued serial peripheral interface figure 14-20. flowchart of qspi master operation (part 2) is delay after transfer asserted? y n execute programmed delay b1 write queue pointer to cptqp status bits c1 negate peripheral chip selects y n is continue bit asserted? execute standard delay motorola chapter 14. queued serial multi-channel module 14-35 queued serial peripheral interface figure 14-21. flowchart of qspi master operation (part 3) assert spif status flag request interrupt is interrupt enable bit spifie set? is wrap enable bit set? y n reset working queue pointer to newqp or 0x0000 y disable qspi a1 n increment working queue pointer n is halt or freeze asserted? a1 halt qspi and set halta n is interrupt enable bit hmie set? y y n is halt or freeze asserted? c1 y n y is this the last command in the queue? request interrupt 14-36 mpc565/mpc566 reference manual motorola queued serial peripheral interface figure 14-22. flowchart of qspi slave operation (part 1) read transmit data from ram using queue pointer address a2 queue pointer changed to newqp n y n write queue pointer to cptqp status bits store received data in ram using queue pointer address b2 qspi cycle bgins (slave mode y execute serial transfer when sck received n y is slave select pin asserted? has newqp been written? is qspi disabled? motorola chapter 14. queued serial multi-channel module 14-37 queued serial peripheral interface figure 14-23. flowchart of qspi slave operation (part 2) normally, the spi bus performs synchronous bidirectional transfers. the serial clock on the spi bus master supplies the clock signal sck to time the transfer of data. four possible set spif status flag request interrupt is interrupt enable bit spifie set? is wrap enable bit asserted? y n reset working queue pointer to newqp or 0x0000 y disable qspi a2 n increment working queue pointer n is halt or freeze asserted? a2 halt qspi and set halta n is interrupt enable bit hmie set? y y n is halt or freeze asserted? c2 y n y is this the last command in the queue? qspi slv2 flow6 request interrupt 14-38 mpc565/mpc566 reference manual motorola queued serial peripheral interface combinations of clock phase and polarity can be specified by the cpha and cpol bits in spcr0. data is transferred with the most significant bit first. the number of bits transferred per command defaults to eight, but can be set to any value from eight to sixteen bits by writing a value into the bits field in spcr0 and setting bitse in command ram. typically, spi bus outputs are not open drain unless multiple spi masters are in the system. if needed, the womq bit in spcr0 can be set to provide wired-or, open drain outputs. an external pull-up resistor should be used on each output line. womq affects all qspi pins regardless of whether they are assigned to the qspi or used as general-purpose i/o. 14.7.5 master mode operation setting the mstr bit in spcr0 selects master mode operation. in master mode, the qspi can initiate serial transfers, but cannot respond to externally initiated transfers. when the slave select input of a device configured for master mode is asserted, a mode fault occurs. before qspi operation begins, pqspar must be written to assign the necessary pins to the qspi. the pins necessary for master mode operation are miso, mosi, sck, and one or more of the chip-select pins. miso is used for serial data input in master mode, and mosi is used for serial data output. either or both may be necessary, depending on the particular application. sck is the serial clock output in master mode and must be assigned to the qspi for proper operation. the portqs data register must next be written with values that make the qgpio[6]/sck (bit 13 qdsck of portqs) and qgpio[3:0]/pcs[3:0] (bits 12:9 qdpcs[3:0] of portqs) outputs inactive when the qspi completes a series of transfers. pins allocated to the qspi by pqspar are controlled by portqs when the qspi is inactive. portqs i/o pins driven to states opposite those of the inactive qspi signals can generate glitches that momentarily enable or partially clock a slave device. for example, if a slave device operates with an inactive sck state of logic one (cpol = 1) and uses active low peripheral chip-select pcs0, the qdsck and qdpcs0 bits in portqs must be set to 0b11. if qdsck and qdpcs0 = 0b00, falling edges will appear on qgpio[6]/sck and gpio[0]/pcs0 as the qspi relinquishes control of these pins and portqs drives them to logic zero from the inactive sck and pcs0 states of logic one. before master mode operation is initiated, qsmcm register ddrqs is written last to direct the data flow on the qspi pins used. configure the sck, mosi and appropriate chip-select pins pcs[3:0] as outputs. the miso pin must be configured as an input. after pins are assigned and configured, write appropriate data to the command queue. if data is to be transmitted, write the data to transmit ram. initialize the queue pointers as appropriate. motorola chapter 14. queued serial multi-channel module 14-39 queued serial peripheral interface qspi operation is initiated by setting the spe bit in spcr1. shortly after spe is set, the qspi executes the command at the command ram address pointed to by newqp. data at the pointer address in transmit ram is loaded into the data serializer and transmitted. data that is simultaneously received is stored at the pointer address in receive ram. when the proper number of bits have been transferred, the qspi stores the working queue pointer value in cptqp, increments the working queue pointer, and loads the next data for transfer from transmit ram. the command pointed to by the incremented working queue pointer is executed next, unless a new value has been written to newqp. if a new queue pointer value is written while a transfer is in progress, that transfer is completed normally. when the cont bit in a command ram byte is set, pcs pins are continuously driven to specified states during and between transfers. if the chip-select pattern changes during or between transfers, the original pattern is driven until execution of the following transfer begins. when cont is cleared, the data in register portqs is driven between transfers. the data in portqs must match the inactive states of sck and any peripheral chip-selects used. when the qspi reaches the end of the queue, it sets the spif flag. if the spifie bit in spcr2 is set, an interrupt request is generated when spif is asserted. at this point, the qspi clears spe and stops unless wraparound mode is enabled. 14.7.5.1 clock phase and polarity in master mode, data transfer is synchronized with the internally-generated serial clock sck. control bits, cpha and cpol, in spcr0, control clock phase and polarity. combinations of cpha and cpol determine upon which sck edge to drive outgoing data from the mosi pin and to latch incoming data from the miso pin. 14.7.5.2 baud rate selection baud rate is selected by writing a value from two to 255 into the spbr field in spcr0. the qspi uses a modulus counter to derive the sck baud rate from the mcu imb3 clock. the following expressions apply to the sck baud rate: or sck baud rate f sys 2spbr ----------------------- = spbr f sys 2 sck baud rate desired ------------------------------------------------------------------- = 14-40 mpc565/mpc566 reference manual motorola queued serial peripheral interface giving spbr a value of zero or one disables the baud rate generator. sck is disabled and assumes its inactive state. at reset, the sck baud rate is initialized to one eighth of the imb3 clock frequency. table 14-25 provides some example sck baud rates with a 40-mhz imb3 clock. 14.7.5.3 delay before transfer the dsck bit in each command ram byte inserts either a standard (dsck = 0) or user-specified (dsck = 1) delay from chip-select assertion until the leading edge of the serial clock. the dsckl field in spcr1 determines the length of the user-defined delay before the assertion of sck. the following expression determines the actual delay before sck when dsckl is in the range of 1?127: note a zero value for dsckl causes a delay of 128 imb3 clocks, which equals 3.2 s for a 40-mhz imb3 clock. because of design limits, a dsckl value of one is valid, but defaults to the same timing as a value of two. when dsck equals zero, dsckl is not used. instead, the pcs valid-to-sck transition is one-half the sck period. 14.7.5.4 delay after transfer delay after transfer can be used to provide a peripheral deselect interval. a delay can also be inserted between consecutive transfers to allow serial a/d converters to complete table 14-25. example sck frequencies with a 40-mhz imb3 clock division ratio spbr value sck frequency 4210.00mhz 636.67mhz 845.00mhz 14 7 2.86 mhz 28 14 1.43 mhz 58 29 689 khz 280 140 143 khz 510 255 78.43 khz pcs to sck delay dsckl f sys ------------------- = motorola chapter 14. queued serial multi-channel module 14-41 queued serial peripheral interface conversion. writing a value to the dtl field in spcr1 specifies a delay period. the dt bit in each command ram byte determines whether the standard delay period (dt = 0) or the specified delay period (dt = 1) is used. the following expression is used to calculate the delay: where dtl is in the range from 1 to 255. a dtl value of 0 is a special case and results in a delay calculated as follows: if dt is zero in a command ram byte, a standard delay is inserted. adequate delay between transfers must be specified for long data streams because the qspi requires time to load a transmit ram entry for transfer. receiving devices need at least the standard delay between successive transfers. if the imb3 clock is operating at a slower rate, the delay between transfers must be increased proportionately. 14.7.5.5 transfer length there are two transfer length options. the user can choose a default value of eight bits, or a programmed value from eight (0b1000) to 16 (0b0000) bits, inclusive. reserved values (from 0b0001 to 0b0111) default to eight bits. the programmed value must be written into the bits field in spcr0. the bitse bit in each command ram byte determines whether the default value (bitse = 0) or the bits value (bitse = 1) is used. 14.7.5.6 peripheral chip selects peripheral chip-select signals are used to select an external device for serial data transfer. chip-select signals are asserted when a command in the queue is executed. signals are asserted at a logic level corresponding to the value of the pcs[3:0] bits in each command byte. more than one chip-select signal can be asserted at a time, and more than one external device can be connected to each pcs pin, provided proper fanout is observed. pcs0 shares a pin with the slave select ss signal, which initiates slave mode serial transfer. if ss is taken low when the qspi is in master mode, a mode fault occurs. to configure a peripheral chip select, set the appropriate bit in pqspar, then configure the chip-select pin as an output by setting the appropriate bit in ddrqs. the value of the bit in portqs that corresponds to the chip-select pin determines the base state of the delay after transfer 32 dtl f sys ------------------------ = delay after transfer 32 256 f sys -------------------- - = standard delay after transfer 17 f sys ----------- = 14-42 mpc565/mpc566 reference manual motorola queued serial peripheral interface chip-select signal. if the base state is zero, chip-select assertion must be active high (pcs bit in command ram must be set); if base state is one, assertion must be active low (pcs bit in command ram must be cleared). portqs bits are cleared during reset. if no new data is written to portqs before pin assignment and configuration as an output, the base state of chip-select signals is zero and chip-select pins are configured for active-high operation. 14.7.5.7 master wraparound mode wraparound mode is enabled by setting the wren bit in spcr2. the queue can wrap to pointer address 0x0 or to the address pointed to by newqp, depending on the state of the wrto bit in spcr2. in wraparound mode, the qspi cycles through the queue continuously, even while the qspi is requesting interrupt service. spe is not cleared when the last command in the queue is executed. new receive data overwrites previously received data in receive ram. each time the end of the queue is reached, the spif flag is set. spif is not automatically reset. if interrupt-driven qspi service is used, the service routine must clear the spif bit to end the current interrupt request. additional interrupt requests during servicing can be prevented by clearing spifie, but spifie is buffered. clearing it does not end the current request. wraparound mode is exited by clearing the wren bit or by setting the halt bit in spcr3. exiting wraparound mode by clearing spe is not recommended, as clearing spe may abort a serial transfer in progress. the qspi sets spif, clears spe, and stops the first time it reaches the end of the queue after wren is cleared. after halt is set, the qspi finishes the current transfer, then stops executing commands. after the qspi stops, spe can be cleared. 14.7.6 slave mode clearing the mstr bit in spcr0 selects slave mode operation. in slave mode, the qspi is unable to initiate serial transfers. transfers are initiated by an external spi bus master. slave mode is typically used on a multi-master spi bus. only one device can be bus master (operate in master mode) at any given time. before qspi operation is initiated, qsmcm register pqspar must be written to assign necessary pins to the qspi. the pins necessary for slave mode operation are miso, mosi, sck, and pcs0/ss . miso is used for serial data output in slave mode, and mosi is used for serial data input. either or both may be necessary, depending on the particular application. sck is the serial clock input in slave mode and must be assigned to the qspi for proper operation. assertion of the active-low slave select signal ss initiates slave mode operation. motorola chapter 14. queued serial multi-channel module 14-43 queued serial peripheral interface before slave mode operation is initiated, ddrqs must be written to direct data flow on the qspi pins used. configure the mosi, sck and pcs0/ss pins as inputs. the miso pin must be configured as an output. after pins are assigned and configured, write data to be transmitted into transmit ram. command ram is not used in slave mode, and does not need to be initialized. set the queue pointers, as appropriate. when spe is set and mstr is clear, a low state on the slave select pcs0/ss pin begins slave mode operation at the address indicated by newqp. data that is received is stored at the pointer address in receive ram. data is simultaneously loaded into the data serializer from the pointer address in transmit ram and transmitted. transfer is synchronized with the externally generated sck. the cpha and cpol bits determine upon which sck edge to latch incoming data from the miso pin and to drive outgoing data from the mosi pin. because the command ram is not used in slave mode, the cont, bitse, dt, dsck, and peripheral chip-select bits have no effect. the pcs0/ss pinisusedonlyasaninput. the spbr, dt and dsckl fields in spcr0 and spcr1 bits are not used in slave mode. the qspi drives neither the clock nor the chip-select pins and thus cannot control clock rate or transfer delay. because the bitse option is not available in slave mode, the bits field in spcr0 specifies the number of bits to be transferred for all transfers in the queue. when the number of bits designated by bits[3:0] has been transferred, the qspi stores the working queue pointer value in cptqp, increments the working queue pointer, and loads new transmit data from transmit ram into the data serializer. the working queue pointer address is used the next time pcs0/ss is asserted, unless the rcpu writes to newqp first. the qspi shifts one bit for each pulse of sck until the slave select input goes high. if ss goes high before the number of bits specified by the bits field is transferred, the qspi resumes operation at the same pointer address the next time ss is asserted. the maximum value that the bits field can have is 16. if more than 16 bits are transmitted before ss is negated, pointers are incremented and operation continues. the qspi transmits as many bits as it receives at each queue address, until the bits value is reached or ss is negated. ss does not need to go high between transfers as the qspi transfers data until reaching the end of the queue, whether ss remains low or is toggled between transfers. when the qspi reaches the end of the queue, it sets the spif flag. if the spifie bit in spcr2 is set, an interrupt request is generated when spif is asserted. at this point, the qspi clears spe and stops unless wraparound mode is enabled. slave wraparound mode is enabled by setting the wren bit in spcr2. the queue can wrap to pointer address 0x0 or to the address pointed to by newqp, depending on the state of 14-44 mpc565/mpc566 reference manual motorola queued serial peripheral interface the wrto bit in spcr2. slave wraparound operation is identical to master wraparound operation. 14.7.6.1 description of slave operation after reset, the qsmcm registers and the qspi control registers must be initialized as described above. although the command control segment is not used, the transmit and receive data segments may, depending upon the application, need to be initialized. if meaningful data is to be sent out from the qspi, the data to be transmitted should be written to the segment before enabling the qspi. if spe is set and mstr is not set, a low state on the slave select (pcs0/ss ) pin commences slave mode operation at the address indicated by newqp. the qspi transmits the data found in the transmit data segment at the address indicated by newqp, and the qspi stores received data in the receive data segment at the ad-dress indicated by newqp. data is transferred in response to an external slave clock input at the sck pin. because the command control segment is not used, the command control bits and peripheral chip-select codes have no effect in slave mode operation. the qspi does not drive any of the four peripheral chip-selects as outputs. pcs0/ss is used as an input. although cont cannot be used in slave mode, a provision is made to enable receipt of more than 16 data bits. while keeping the qspi selected (pcs0/ss is held low), the qspi stores the number of bits, designated by bits, in the current receive data segment address, increments newqp, and continues storing the remaining bits (up to the bits value) in the next receive data segment address. as long as pcs0/ss remains low, the qspi continues to store the incoming bit stream in sequential receive data segment addresses, until either the value in bits is reached or the end-of-queue address is used with wraparound mode disabled. when the end of the queue is reached, the spif flag is asserted, optionally causing an interrupt. if wraparound mode is disabled, any additional incoming bits are ignored. if wraparound mode is enabled, storing continues at either address 0x0 or the address of newqp, depending on the wrto value. when using this capability to receive a long incoming data stream, the proper delay between transfers must be used. the qspi requires time, approximately 0.425 s with a 40-mhz imb3 clock, to prefetch the next transmit ram entry for the next transfer. therefore, a baud rate may be selected that provides at least a 0.6-s delay between successive transfers to ensure no loss of incoming data. if the imb3 clock is operating at a slower rate, the delay between transfers must be increased proportionately. because the bitse option in the command control segment is no longer available, bits sets the number of bits to be transferred for all transfers in the queue until the cpu changes the bits value. as mentioned above, until pcs0/ss is negated (brought high), the qspi motorola chapter 14. queued serial multi-channel module 14-45 queued serial peripheral interface continues to shift one bit for each pulse of sck. if pcs0/ss is negated before the proper number of bits (according to bits) is received, the next time the qspi is selected it resumes storing bits in the same receive-data segment address where it left off. if more than 16 bits are transferred before negating the pcs0/ss , the qspi stores the number of bits indicated by bits in the current receive data segment address, then increments the address and continues storing as described above. note pcs0/ss does not necessarily have to be negated between transfers. once the proper number of bits (designated by bits) are transferred, the qspi stores the received data in the receive data segment, stores the internal working queue pointer value in cptqp, increments the internal working queue pointer, and loads the new transmit data from the transmit data segment into the data serializer. the internal working queue pointer address is used the next time pcs0/ss is asserted, unless the cpu writes to the newqp first. the dt and dsck command control bits are not used in slave mode. as a slave, the qspi does not drive the clock line nor the chip-select lines and, therefore, does not generate a delay. in slave mode, the qspi shifts out the data in the transmit data segment. the transmit data is loaded into the data serializer (refer to figure 14-1) for transmission. when the pcs0/ss pin is pulled low the miso pin becomes active and the serializer then shifts the 16 bits of data out in sequence, most significant bit first, as clocked by the incoming sck signal. the qspi uses cpha and cpol to determine which incoming sck edge the mosi pin uses to latch incoming data, and which edge the miso pin uses to drive the data out. the qspi transmits and receives data until reaching the end of the queue (defined as a match with the address in endqp), regardless of whether pcs0/ss remains selected or is toggled between serial transfers. receiving the proper number of bits causes the received data to be stored. the qspi always transmits as many bits as it receives at each queue address, until the bits value is reached or pcs0/ss is negated. 14.7.7 slave wraparound mode when the qspi reaches the end of the queue, it always sets the spif flag, whether wraparound mode is enabled or disabled. an optional interrupt to the cpu is generated when spif is asserted. at this point, the qspi clears spe and stops unless wraparound mode is enabled. a description of the spifie bit can be found in section 14.7.1.3, ?qspi control register 2.? in wraparound mode, the qspi cycles through the queue continuously. each time the end of the queue is reached, the spif flag is set. if the cpu fails to clear spif, it remains set, 14-46 mpc565/mpc566 reference manual motorola serial communication interface and the qspi continues to send interrupt requests to the cpu (assuming spifie is set). the user may avoid causing cpu interrupts by clearing spifie. as spifie is buffered, clearing it after the spif flag is asserted does not immediately stop the cpu interrupts, but only prevents future interrupts from this source. to clear the current interrupt, the cpu must read qspi register spsr with spif asserted, followed by a write to spsr with zero in spif (clear spif). execution continues in wraparound mode even while the qspi is requesting interrupt service from the cpu. the internal working queue pointer is incremented to the next address and the commands are executed again. spe is not cleared by the qspi. new receive data overwrites previously received data located in the receive data segment. wraparound mode is properly exited in two ways: a) the cpu may disable wrap-around mode by clearing wren. the next time end of the queue is reached, the qspi sets spif, clears spe, and stops; and, b) the cpu sets halt. this second method halts the qspi after the current transfer is completed, allowing the cpu to negate spe. the cpu can immediately stop the qspi by clearing spe; however, this method is not recommended, as it causes the qspi to abort a serial transfer in process. 14.7.8 mode fault modf is asserted by the qspi when the qspi is the serial master (mstr = 1) and the slave select (pcs0/ss ) input pin is pulled low by an external driver. this is possible only if the pcs0/ss pin is configured as input by qddr. this low input to ss is not a normal operating condition. it indicates that a multimaster system conflict may exist, that another mcu is requesting to become the spi network master, or simply that the hardware is incorrectly affecting pcs0/ss . spe in spcr1 is cleared, disabling the qspi. the qspi pins revert to control by qpdr. if modf is set and hmie in spcr3 is asserted, the qspi generates an interrupt to the cpu. the cpu may clear modf by reading spsr with modf asserted, followed by writing spsr with a zero in modf. after correcting the mode fault problem, the qspi can be re-enabled by asserting spe. the pcs0/ss pin may be configured as a general-purpose output instead of input to the qspi. this inhibits the mode fault checking function. in this case, modf is not used by the qspi. 14.8 serial communication interface the dual, independent, serial communication interface (dsci) communicates with external devices through an asynchronous serial bus. the two sci modules are functionally equivalent, except that the sci1 also provides 16-deep queue capabilities for the transmit and receive operations. the scis are fully compatible with other motorola sci systems. motorola chapter 14. queued serial multi-channel module 14-47 serial communication interface the dsci has all of the capabilities of previous sci systems as well as several significant new features. figure 14-24 is a block diagram of the sci transmitter. figure 14-25 is a block diagram of the sci receiver. 14-48 mpc565/mpc566 reference manual motorola serial communication interface figure 14-24. sci transmitter block diagram loops woms ilt pt pe m wake tie tcie rie ilie te re rwu sbk transmitter control logic pin buffer and control h(8)76543210l 10 (11)-bit tx shift register txd scxdr tx buffer transfer tx buffer shift enable jam enable preamble?jam 1's break?jam 0's force pin direction (out) size 8/9 parity generator transmitter baud rate clock tc tdre sci rx requests sci interrupt request fe nf or idle rdrf tc tdre scxsr status register pf internal data bus raf tie tcie sccxr1 control register 1 0 15 15 0 start stop open drain output mode enable (write-only) motorola chapter 14. queued serial multi-channel module 14-49 serial communication interface figure 14-25. sci receiver block diagram 0 loops woms ilt pt pe m wake rie ilie te re rwu sbk tie tcie sccxr1 control register 1 0 15 fe nf or idle rdrf tc tdre scxsr status register pf raf 15 0 wake-up logic pin buffer rxd stop (8)76543210 10 (11)-bit rx shift register start msb all ones data recovery 16 parity detect receiver baud rate clock scxdr rx buffer (read-only) sci tx requests sci interrupt request internal data bus l h 14-50 mpc565/mpc566 reference manual motorola serial communication interface 14.8.1 sci registers the sci programming model includes the qsmcm global and pin control registers and the dsci registers. the dsci registers, listed in table 14-26, consist of five control registers, three status registers, and 34 data registers. all registers may be read or written at any time by the cpu. rewriting the same value to any dsci register does not disrupt operation; however, writing a different value into a dsci register when the dsci is running may disrupt operation. to change register values, the receiver and transmitter should be disabled with the transmitter allowed to finish first. the status flags in register scxsr can be cleared at any time. note: reads access the rdrx; writes access the tdrx. table 14-26. sci registers address name usage 0x30 5008(a) 0x30 5408(b) scc1r0 sci1 control register 0 see table 14-27 for bit descriptions. 0x30 500a(a) 0x30 540a(b) scc1r1 sci1 control register 1 see table 14-28 for bit descriptions. 0x30 500c(a) 0x30 540c(b) sc1sr sci1 status register see table 14-29 for bit descriptions. 0x30 500e(a) 0x30 540e(b) (non-queue mode only) sc1dr sci1 data register transmit data register (tdr1)* receive data register (rdr1)* see table 14-30 for bit descriptions. 0x30 5020(a) 0x30 5420(b) scc2r0 sci2 control register 0 0x30 5022(a) 0x30 5422(b) scc2r1 sci2 control register 1 0x30 5024(a) 0x30 5424(b) sc2sr sci2 status register 0x30 5026(a) 0x30 5426(b) sc2dr sci2 data register transmit data register (tdr2)* receive data register (rdr2)* 0x30 5028(a) 0x30 5428(b) qsci1cr qsci1 control register interrupts, wrap, queue size and enables for receive and transmit, qtpnt. see table 14-35 for bit descriptions. 0x30 502a(a) 0x30 542a(b) qsci1sr qsci1 status register overrun error flag, queue status flags, qrpnt, and qpend. see table 14-36 for bit descriptions. 0x30 502c ? 0x30 504a(a) 0x30 542c ? 0x30 544a(b) qsci1 transmit queue memory area qsci1 transmit queue data locations (on half-word boundary) 0x30 504c-6a(a) 0x30 544c-6a(b) qsci1 receive queue memory area qsci1 receive queue data locations (on half-word boundary) motorola chapter 14. queued serial multi-channel module 14-51 serial communication interface during scix initialization, two bits in the sccxr1 should be written last: the transmitter enable (te) and receiver enable (re) bits, which enable scix. registers sccxr0 and sccxr1 should both be initialized at the same time or before te and re are asserted. a single half-word write to sccxr1 can be used to initialize scix and enable the transmitter and receiver. 14.8.2 sci control register 0 sccxr0 contains the scix baud rate selection field and two bits controlling the clock source. the baud rate must be set before the sci is enabled. the cpu can read and write sccxr0 at any time. changing the value of sccxr0 bits during a transfer operation can disrupt the transfer. before changing register values, allow the sci to complete the current transfer, then disable the receiver and transmitter. 14.8.3 sci control register 1 sccxr1 contains scix configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. the cpu can read or write this register at any time. the sci can modify the rwu bit under certain circumstances. msb 0 1234567891011121314lsb 15 rsvd scxbr reset: 0 000000000000100 figure 14-26. sccxr0 ? sci control register 0 0x30 5020 0x30 5420 table 14-27. sccxr0 bit descriptions bit(s) name description 0?2 ? these bits are reserved and should always be programmed to 0. 3:15 scxbr sci baud rate. the sci baud rate is programmed by writing a 13-bit value to this field. writing a value of zero to scxbr disables the baud rate generator. baud clock rate is calculated as follows: where scxbr is in the range of 1 to 8191. refer to section 14.8.7.3, ?baud clock? for more information. sci baud rate f sys 32 scxbr 14-52 mpc565/mpc566 reference manual motorola serial communication interface changing the value of sccxr1 bits during a transfer operation can disrupt the transfer. before changing register values, allow the sci to complete the current transfer, then disable the receiver and transmitter. msb 0 1 2 3456 7 891011121314lsb 15 rsvd loops woms ilt pt pe m wake tie tcie rie ilie te re rwu sbk reset: 0 0 0 0000 0 00000000 figure 14-27. sccxr1 ? sci control register 10x30 500a, 0x30 5022 0x30 540a, 0x30 5422 table 14-28. sccxr1 bit descriptions bit(s) name description 0?reserved 1 loops loop mode 0 normal sci operation, no looping, feedback path disabled. 1 sci test operation, looping, feedback path enabled. 2 woms wired-or mode for sci pins 0 if configured as an output, txd is a normal cmos output. 1 if configured as an output, txd is an open drain output. 3 ilt idle-line detect type. refer to section 14.8.7.8, ?idle-line detection.? 0 short idle-line detect (start count on first one). 1 long idle-line detect (start count on first one after stop bit(s)). 4 pt parity type. refer to section 14.8.7.4, ?parity checking.? 0 even parity. 1oddparity. 5 pe parity enable. refer to section 14.8.7.4, ?parity checking. 0 sci parity disabled. 1 sci parity enabled. 6 m mode select. refer to section 14.8.7.2, ?serial formats.? 0 10-bit sci frame. 1 11-bit sci frame. 7 wake wakeup by address mark. refer to section 14.8.7.9, ?receiver wake-up.? 0 sci receiver awakened by idle-line detection. 1 sci receiver awakened by address mark (last bit set). 8 tie transmit interrupt enable 0 sci tdre interrupts disabled. 1 sci tdre interrupts enabled. 9 tcie transmit complete interrupt enable 0 sci tc interrupts disabled. 1 sci tc interrupts enabled. 10 rie receiver interrupt enable 0 sci rdrf and or interrupts disabled. 1 sci rdrf and or interrupts enabled. motorola chapter 14. queued serial multi-channel module 14-53 serial communication interface 14.8.4 sci status register (scxsr) scxsr contains flags that show sci operating conditions. these flags are cleared either by scix hardware or by a read/write sequence. the sequence consists of reading the scxsr (either the upper byte, lower byte, or the entire half-word) with a flag bit set, then reading (or writing, in the case of flags tdre and tc) the scxdr (either the lower byte or the half-word). the contents of the two 16-bit registers scxsr and scxdr appear as upper and lower half-words, respectively, when the scxsr is read into a 32-bit register. an upper byte access of scxsr is meaningful only for reads. note that a word read can simultaneously access both registers scxsr and scxdr. this action clears the receive status flag bits that were set at the time of the read, but does not clear the tdre or tc flags. to clear tc, the scxsr read must be followed by a write to register scxdr (either the lower byte or the half-word). the tdre flag in the status register is read-only. if an internal sci signal for setting a status bit comes after the cpu has read the asserted status bits but before the cpu has read or written the scxdr, the newly set status bit is not cleared. instead, scxsr must be read again with the bit set and scxdr must be read or written before the status bit is cleared. 11 ilie idle-line interrupt enable 0 sci idle interrupts disabled. 1 sci idle interrupts enabled. 12 te transmitter enable 0 sci transmitter disabled (txd pin can be used as general-purpose output) 1 sci transmitter enabled (txd pin dedicated to sci transmitter). 13 re receiver enable 0 sci receiver disabled (rxd pin can be used as general-purpose input). 1 sci receiver enabled (rxd pin is dedicated to sci receiver). 14 rwu receiver wakeup. refer to section 14.8.7.9, ?receiver wake-up.? 0 normal receiver operation (received data recognized). 1 wakeup mode enabled (received data ignored until receiver is awakened). 15 sbk send break 0 normal operation. 1 break frame(s) transmitted after completion of current frame. table 14-28. sccxr1 bit descriptions (continued) bit(s) name description 14-54 mpc565/mpc566 reference manual motorola serial communication interface note none of the status bits are cleared by reading a status bit while it is set and then writing zero to that same bit. instead, the procedure outlined above must be followed. note further that reading either byte of scxsr causes all 16 bits to be accessed, and any status bits already set in either byte are armed to clear on a subsequent read or write of scxdr. msb 0 12345 67891011121314lsb 15 reserved tdre tc rdrf raf idle or nf fe pf reset: 000000 0110 000000 figure 14-28. scxsr ? scix status register 0x30 500c 0x30 5024 0x30 540c 0x30 5424 table 14-29. scxsr bit descriptions bit(s) name description 0:6 ? reserved 7 tdre transmit data register empty. tdre is set when the byte in tdrx is transferred to the transmit serial shifter. if this bit is zero, the transfer is yet to occur and a write to tdrx will overwrite the previous value. new data is not transmitted if tdrx is written without first clearing tdre. 0 transmit data register still contains data to be sent to the transmit serial shifter. 1 a new character can now be written to the transmit data register. for transmit queue operation, this bit should be ignored by software. 8 tc transmit complete. tc is set when the transmitter finishes shifting out all data, queued preambles (mark/idle-line), or queued breaks (logic zero). 0 sci transmitter is busy. 1 sci transmitter is idle. for transmit queue operation, tc is cleared when scxsr is read with tc set, followed by a write to sctq[0:15]. 9 rdrf receive data register full. rdrf is set when the contents of the receive serial shifter are transferred to register rdrx. if one or more errors are detected in the received word, the appropriate flag(s) (nf, fe, or pf) are set within the same clock cycle. 0 receive data register is empty or contains previously read data. 1 receive data register contains new data. for receiver queue operation, this bit should be ignored by software. 10 raf receiver active flag. raf indicates whether the receiver is busy. this flag is set when the receiver detects a possible start bit and is cleared when the chosen type of idle line is detected. raf can be used to reduce collisions in systems with multiple masters. 0 sci receiver is idle. 1 sci receiver is busy. motorola chapter 14. queued serial multi-channel module 14-55 serial communication interface 14.8.5 sci data register (scxdr) the scxdr consists of two data registers located at the same address. the receive data register (rdrx) is a read-only register that contains data received by the sci serial interface. data is shifted into the receive serial shifter and is transferred to rdrx. the 11 idle idle line detected. idle is set when the receiver detects an idle-line condition (reception of a minimum of 10 or 11 consecutive ones as specified by ilt in sccxr1). this bit is not set by the idle-line condition when rwu in sccxr1 is set. once cleared, idle is not set again until after rdrf is set (after the line is active and becomes idle again). if a break is received, rdrf is set, allowing a subsequent idle line to be detected again. under certain conditions, the idle flag may be set immediately following the negation of re in sccxr1. system designs should ensure this causes no detrimental effects. 0 sci receiver did not detect an idle-line condition. 1 sci receiver detected an idle-line condition. for receiver queue operation, idle is cleared when scxsr is read with idle set, followed by a read of scrq[0:15]. 12 or overrun error. or is set when a new byte is ready to be transferred from the receive serial shifter to register rdrx, and rdrx is already full (rdrf is still set). data transfer is inhibited until or is cleared. previous data in rdrx remains valid, but additional data received during an overrun condition (including the byte that set or) is lost. note that whereas the other receiver status flags (nf, fe, and pf) reflect the status of data already transferred to rdrx, the or flag reflects an operational condition that resulted in a loss of data to rdrx. 0 rdrf is cleared before new data arrives. 1 rdrf is not cleared before new data arrives. 13 nf noise error flag. nf is set when the receiver detects noise on a valid start bit, on any of the data bits, or on the stop bit(s). it is not set by noise on the idle line or on invalid start bits. each bit is sampled three times for noise. if the three samples are not at the same logic level, the majority value is used for the received data value, and nf is set. nf is not set until the entire frame is received and rdrf is set. although no interrupt is explicitly associated with nf, an interrupt can be generated with rdrf, and the interrupt handler can check nf. 0 no noise detected in the received data. 1 noise detected in the received data. for receiver queue operation nf is cleared when scxsr is read with nf set, followed by a read of scrq[0:15]. 14 fe framing error. fe is set when the receiver detects a zero where a stop bit (one) was expected. a framing error results when the frame boundaries in the received bit stream are not synchronized with the receiver bit counter. fe is not set until the entire frame is received and rdrf is set. although no interrupt is explicitly associated with fe, an interrupt can be generated with rdrf, and the interrupt handler can check fe. 0 no framing error detected in the received data. 1 framing error or break detected in the received data. 15 pf parity error. pf is set when the receiver detects a parity error. pf is not set until the entire frame is received and rdrf is set. although no interrupt is explicitly associated with pf, an interrupt can be generated with rdrf, and the interrupt handler can check pf. 0 no parity error detected in the received data. 1 parity error detected in the received data. table 14-29. scxsr bit descriptions (continued) bit(s) name description 14-56 mpc565/mpc566 reference manual motorola serial communication interface transmit data register (tdrx) is a write-only register that contains data to be transmitted. data is first written to tdrx, then transferred to the transmit serial shifter, where additional format bits are added before transmission. 14.8.6 sci pins the rxd1 and rxd2 pins are the receive data pins for the sci1 and sci2, respectively. txd1 and txd2 are the transmit data pins for the two sci modules. an external clock pin, eck, is common to both scis. the pins and their functions are listed in table 14-31. 14.8.7 sci operation the sci can operate in polled or interrupt-driven mode. status flags in scxsr reflect sci conditions regardless of the operating mode chosen. the tie, tcie, rie, and ilie bits in msb 0 1234567891011121314lsb 15 reserved r8/t8 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 reset: 0 000000 uuuuuuuuu figure 14-29. scxdr ? sci data register0x30 500e 0x30 540e table 14-30. scxdr bit descriptions bit(s) name description 0:6 ? reserved 7:15 r[8:0]/ t[8:0] r[7:0]/t[7:0] contain either the eight data bits received when scxdr is read, or the eight data bits to be transmitted when scxdr is written. r8/t8 are used when the sci is configured for nine-bit operation (m = 1). when the sci is configured for 8-bit operation, r8/t8 have no meaning or effect. accesses to the lower byte of scxdr triggers the mechanism for clearing the status bits or for initiating transmissions whether byte, half-word, or word accesses are used. table 14-31. sci pin functions pin names mnemonic mode function receive data rxd1, rxd2 receiver disabled receiver enabled general purpose input serial data input to sci transmit data txd1, txd2 transmitter disabled transmitter enabled general purpose output serial data output from sci external clock eck receiver disabled receiver enabled transmitter disabled transmitter enabled not used alternate input source to baud not used alternate input source to baud motorola chapter 14. queued serial multi-channel module 14-57 serial communication interface sccxr1 enable interrupts for the conditions indicated by the tdre, tc, rdrf, and idle bits in scxsr, respectively. 14.8.7.1 definition of terms bit-time ? the time required to transmit or receive one bit of data, which is equal to one cycle of the baud frequency. start bit ? one bit-time of logic zero that indicates the beginning of a data frame. a start bit must begin with a one-to-zero transition and be preceded by at least three receive time samples of logic one. stop bit? one bit-time of logic one that indicates the end of a data frame. frame ? a complete unit of serial information. the sci can use 10-bit or 11-bit frames. data frame ? a start bit, a specified number of data or information bits, and at least one stop bit. idle frame ? a frame that consists of consecutive ones. an idle frame has no start bit. break frame ? a frame that consists of consecutive zeros. a break frame has no stop bits. 14.8.7.2 serial formats all data frames must have a start bit and at least one stop bit. receiving and transmitting devices must use the same data frame format. the sci provides hardware support for both 10-bit and 11-bit frames. the m bit in sccxr1 specifies the number of bits per frame. the most common data frame format for nrz (non-return to zero) serial interfaces is one start bit, eight data bits (lsb first), and one stop bit (ten bits total). the most common 11-bit data frame contains one start bit, eight data bits, a parity or control bit, and one stop bit. ten-bit and 11-bit frames are shown in table 14-32. table 14-32. serial frame formats 10-bit frames start data parity/control stop 17?2 1711 18?1 11-bit frames start data parity/control stop 14-58 mpc565/mpc566 reference manual motorola serial communication interface 14.8.7.3 baud clock the sci baud rate is programmed by writing a 13-bit value to the scxbr field in sci control register zero (sccxr0). the baud rate is derived from the mcu imb3 clock by a modulus counter. writing a value of zero to scxbr[12:0] disables the baud rate generator. the baud rate is calculated as follows: or where scxbr is in the range {1, 2, 3, ..., 8191}. the sci receiver operates asynchronously. an internal clock is necessary to synchronize with an incoming data stream. the sci baud rate generator produces a receive time sampling clock with a frequency 16 times that of the sci baud rate. the sci determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period. table 14-33 shows possible baud rates for a 40-mhz imb3 clock. the maximum baud rate with this imb3 clock speed is 1250 kbaud. 1712 1811 table 14-32. serial frame formats (continued) 10-bit frames sci baud rate f sys 32 scxbr scxbr f sys 32 sci baud rate desired motorola chapter 14. queued serial multi-channel module 14-59 serial communication interface 14.8.7.4 parity checking the pt bit in sccxr1 selects either even (pt = 0) or odd (pt = 1) parity. pt affects received and transmitted data. the pe bit in sccxr1 determines whether parity checking is enabled (pe = 1) or disabled (pe = 0). when pe is set, the msb of data in a frame (i.e., the bit preceding the stop bit) is used for the parity function. for transmitted data, a parity bit is generated. for received data, the parity bit is checked. when parity checking is enabled, the pf bit in the sci status register (scxsr) is set if a parity error is detected. enabling parity affects the number of data bits in a frame, which can in turn affect frame size. table 14-34 shows possible data and parity formats. 14.8.7.5 transmitter operation the transmitter consists of a serial shifter and a parallel data register (tdrx) located in the sci data register (scxdr). the serial shifter cannot be directly accessed by the cpu. the transmitter is double-buffered, which means that data can be loaded into the tdrx while other data is shifted out. the te bit in sccxr1 enables (te = 1) and disables (te = 0) the transmitter. table 14-33. examples of scix baud rates 1 1 these rates are based on a 40-mhz imb3 clock. nominal baud rate actual baud rate percent error value of scxbr 1,250,000.00 57,600.00 38,400.00 32,768.00 28,800.00 19,200.00 14,400.00 9,600.00 4,800.00 2,400.00 1,200.00 600.00 300.00 1,250,000.00 56,818.18 37,878.79 32,894.74 29,069.77 19,230.77 14,367.81 9,615.38 4,807.69 2,399.23 1,199.62 600.09 299.98 0.00 -1.36 -1.36 0.39 0.94 0.16 -0.22 0.16 0.16 -0.03 -0.03 0.02 -0.01 1 22 33 38 43 65 87 130 260 521 1042 2083 4167 table 14-34. effect of parity checking on data size mpe result 00 8databits 0 1 7databits,1paritybit 10 9databits 1 1 8databits,1paritybit 14-60 mpc565/mpc566 reference manual motorola serial communication interface the shifter output is connected to the txd pin while the transmitter is operating (te = 1, or te = 0 and transmission in progress). wired-or operation should be specified when more than one transmitter is used on the same sci bus. the woms bit in sccxr1 determines whether txd is an open drain (wired-or) output or a normal cmos output. an external pull-up resistor on txd is necessary for wired-or operation. woms controls txd function, regardless of whether the pin is used by the sci or as a general-purpose output pin. data to be transmitted is written to scxdr, then transferred to the serial shifter. before writing to tdrx, the transmit data register empty (tdre) flag in scxsr should be checked. when tdre = 0, the tdrx contains data that has not been transferred to the shifter. writing to scxdr again overwrites the data. if tdre = 1, then tdrx is empty, and new data may be written to tdrx, clearing tdre. as soon as the data in the transmit serial shifter has shifted out and if a new data frame is in tdrx (tdre = 0), then the new data is transferred from tdrx to the transmit serial shifter and tdre is set automatically. an interrupt may optionally be generated at this point. the transmission complete (tc) flag in scxsr shows transmitter shifter state. when tc = 0, the shifter is busy. tc is set when all shifting operations are completed. tc is not automatically cleared. the processor must clear it by first reading scxsr while tc is set, then writing new data to scxdr, or writing to sctq[0:15] for transmit queue operation. the state of the serial shifter is checked when the te bit is set. if tc = 1, an idle frame is transmitted as a preamble to the following data frame. if tc = 0, the current operation continues until the final bit in the frame is sent, then the preamble is transmitted. the tc bit is set at the end of preamble transmission. the sbk bit in sccxr1 is used to insert break frames in a transmission. a non-zero integer number of break frames are transmitted while sbk is set. break transmission begins when sbk is set, and ends with the transmission in progress at the time either sbk or te is cleared. if sbk is set while a transmission is in progress, that transmission finishes normally before the break begins. to ensure the minimum break time, toggle sbk quickly to one and back to zero. the tc bit is set at the end of break transmission. after break transmission, at least one bit-time of logic level one (mark idle) is transmitted to ensure that a subsequent start bit can be detected. if te remains set, after all pending idle, data and break frames are shifted out, tdre and tc are set and txd is held at logic level one (mark). when te is cleared, the transmitter is disabled after all pending idle, data, and break frames are transmitted. the tc flag is set, and control of the txd pin reverts to pqspar and ddrqs. buffered data is not transmitted after te is cleared. to avoid losing data in the buffer, do not clear te until tdre is set. motorola chapter 14. queued serial multi-channel module 14-61 serial communication interface some serial communication systems require a mark on the txd pin even when the transmitter is disabled. configure the txd pin as an output, then write a one to either qdtx1 or qdtx2 of the portqs register. see section 14.6.1, ?port qs data register (portqs).? when the transmitter releases control of the txd pin, it reverts to driving a logic one output. to insert a delimiter between two messages, to place non-listening receivers in wake-up mode between transmissions, or to signal a re-transmission by forcing an idle-line, clear and then set te before data in the serial shifter has shifted out. the transmitter finishes the transmission, then sends a preamble. after the preamble is transmitted, if tdre is set, the transmitter marks idle. otherwise, normal transmission of the next sequence begins. both tdre and tc have associated interrupts. the interrupts are enabled by the transmit interrupt enable (tie) and transmission complete interrupt enable (tcie) bits in sccxr1. service routines can load the last data frame in a sequence into scxdr, then terminate the transmission when a tdre interrupt occurs. two sci messages can be separated with minimum idle time by using a preamble of 10 bit-times (11 if a 9-bit data format is specified) of marks (logic ones). follow these steps: 1. write the last data frame of the first message to the tdrx 2. wait for tdre to go high, indicating that the last data frame is transferred to the transmit serial shifter 3. clear te and then set te back to one. this queues the preamble to follow the stop bit of the current transmission immediately. 4. write the first data frame of the second message to register tdrx in this sequence, if the first data frame of the second message is not transferred to tdrx prior to the finish of the preamble transmission, then the transmit data line (txdx pin) marks idle (logic one) until tdrx is written. in addition, if the last data frame of the first message finishes shifting out (including the stop bit) and te is clear, tc goes high and transmission is considered complete. the txdx pin reverts to being a general-purpose output pin. 14.8.7.6 receiver operation the receiver can be divided into two segments. the first is the receiver bit processor logic that synchronizes to the asynchronous receive data and evaluates the logic sense of each bit in the serial stream. the second receiver segment controls the functional operation and the interface to the cpu including the conversion of the serial data stream to parallel access by the cpu. receiver bit processor ? the receiver bit processor contains logic to synchronize the bit-time of the incoming data and to evaluate the logic sense of each bit. to accomplish this an rt clock, which is 16 times the baud rate, is used to sample each bit. each bit-time can 14-62 mpc565/mpc566 reference manual motorola serial communication interface thus be divided into 16 time periods called rt1?rt16. the receiver looks for a possible start bit by watching for a high-to-low transition on the rxdx pin and by assigning the rt time labels appropriately. when the receiver is enabled by writing re in sccxr1 to one, the receiver bit processor logic begins an asynchronous search for a start bit. the goal of this search is to gain synchronization with a frame. the bit-time synchronization is done at the beginning of each frame so that small differences in the baud rate of the receiver and transmitter are not cumulative. scix also synchronizes on all one-to-zero transitions in the serial data stream, which makes scix tolerant to small frequency variations in the received data stream. the sequence of events used by the receiver to find a start bit is listed below. 1. sample rxdx input during each rt period and maintain these samples in a serial pipeline that is three rt periods deep. 2. if rxdx is low during this rt period, go to step 1. 3. if rxdx is high during this rt period, store sample and proceed to step 4. 4. if rxdx is low during this rt period, but not high for the previous three rt periods (which is noise only), set an internal working noise flag and go to step 1, since this transition was not a valid start bit transition. 5. if rxdx is low during this rt period and has been high for the previous three rt periods, call this period rt1, set raf, and proceed to step 6. 6. skip rt2 but place rt3 in the pipeline and proceed to step 7. 7. skip rt4 and sample rt5. if both rt3 and rt5 are high (rt1 was noise only), set an internal working noise flag. go to step 3 and clear raf. otherwise, place rt5 in the pipeline and proceed to step 8. 8. skip rt6 and sample rt7. if any two of rt3, rt5, or rt7 is high (rt1 was noise only), set an internal working noise flag. go to step 3 and clear raf. otherwise, place rt7 in the pipeline and proceed to step 9. 9. a valid start bit is found and synchronization is achieved. from this point on until the end of the frame, the rt clock will increment starting over again with rt1 on each one-to-zero transition or each rt16. the beginning of a bit-time is thus defined as rt1 and the end of a bit-time as rt16. upon detection of a valid start bit, synchronization is established and is maintained through the reception of the last stop bit, after which the procedure starts all over again to search for a new valid start bit. during a frame?s reception, scix resynchronizes the rt clock on any one-to-zero transitions. additional logic in the receiver bit processor determines the logic level of the received bit and implements an advanced noise-detection function. during each bit-time of a frame (including the start and stop bits), three logic-sense samples are taken at rt8, rt9, and motorola chapter 14. queued serial multi-channel module 14-63 serial communication interface rt10. the logic sense of the bit-time is decided by a majority vote of these three samples. this logic level is shifted into register rdrx for every bit except the start and stop bits. if rt8, rt9, and rt10 do not all agree, an internal working noise flag is set. additionally for the start bit, if rt3, rt5, and rt7 do not all agree, the internal working noise flag is set. if this flag is set for any of the bit-times in a frame, the nf flag in scxsr is set concurrently with the rdrf flag in scxsr when the data is transferred to register rdrx. the user must determine if the data received with nf set is valid. noise on the rxdx pin does not necessarily corrupt all data. the operation of the receiver bit processor is shown in figure 14-30. this example demonstrates the search for a valid start bit and the synchronization procedure as outlined above. the possibilities of noise durations greater than one bit-time are not considered in this examples. figure 14-30. start search example 14.8.7.7 receiver functional operation the re bit in sccxr1 enables (re = 1) and disables (re = 0) the receiver. the receiver contains a receive serial shifter and a parallel receive data register (rdrx) located in the sci data register (scxdr). the serial shifter cannot be directly accessed by the cpu. the receiver is double-buffered, allowing data to be held in the rdrx while other data is shifted in. receiver bit processor logic drives a state machine that determines the logic level for each bit-time. this state machine controls when the bit processor logic is to sample the rxd pin and also controls when data is to be passed to the receive serial shifter. a receive time clock is used to control sampling and synchronization. data is shifted into the receive serial shifter according to the most recent synchronization of the receive time clock with the incoming data stream. from this point on, data movement is synchronized with the mcu r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 2 r t 3 r t 4 r t 5 r t 6 r t 7 r t 8 r t 9 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 1 r t 2 r t 3 11 111 0 0 *** * restart rt clock perceived start bit actual start bit lsb ** ** ** 0123456 * 1 1 11 0 00 0 0 14-64 mpc565/mpc566 reference manual motorola serial communication interface imb3 clock. operation of the receiver state machine is detailed in the queued serial module reference manual (qsmrm/ad) . the number of bits shifted in by the receiver depends on the serial format. however, all frames must end with at least one stop bit. when the stop bit is received, the frame is considered to be complete, and the received data in the serial shifter is transferred to the rdrx. the receiver data register flag (rdrf) is set when the data is transferred. the stop bit is always a logic one. if a logic zero is sensed during this bit-time, the fe flag in scxsr is set. a framing error is usually caused by mismatched baud rates between the receiver and transmitter or by a significant burst of noise. note that a framing error is not always detected; the data in the expected stop bit-time may happen to be a logic one. noise errors, parity errors, and framing errors can be detected while a data stream is being received. although error conditions are detected as bits are received, the noise flag (nf), the parity flag (pf), and the framing error (fe) flag in scxsr are not set until data is transferred from the serial shifter to the rdrx. rdrf must be cleared before the next transfer from the shifter can take place. if rdrf is set when the shifter is full, transfers are inhibited and the overrun error (or) flag in scxsr is set. or indicates that the rdrx needs to be serviced faster. when or is set, the data in the rdrx is preserved, but the data in the serial shifter is lost. when a completed frame is received into the rdrx, either the rdrf or or flag is always set. if rie in sccxr1 is set, an interrupt results whenever rdrf is set. the receiver status flags nf, fe, and pf are set simultaneously with rdrf, as appropriate. these receiver flags are never set with or because the flags apply only to the data in the receive serial shifter. the receiver status flags do not have separate interrupt enables, since they are set simultaneously with rdrf and must be read at the same time as rdrf. when the cpu reads scxsr and scxdr in sequence, it acquires status and data, and also clears the status flags. reading scxsr acquires status and arms the clearing mechanism. reading scxdr acquires data and clears scxsr. 14.8.7.8 idle-line detection during a typical serial transmission, frames are transmitted isochronically and no idle time occurs between frames. even when all the data bits in a frame are logic ones, the start bit provides one logic zero bit-time during the frame. an idle line is a sequence of contiguous ones equal to the current frame size. frame size is determined by the state of the m bit in sccxr1. the sci receiver has both short and long idle-line detection capability. idle-line detection is always enabled. the idle-line type (ilt) bit in sccxr1 determines which type of detection is used. when an idle-line condition is detected, the idle flag in scxsr is set. motorola chapter 14. queued serial multi-channel module 14-65 serial communication interface for short idle-line detection, the receiver bit processor counts contiguous logic one bit-times whenever they occur. short detection provides the earliest possible recognition of an idle-line condition, because the stop bit and contiguous logic ones before and after it are counted. for long idle-line detection, the receiver counts logic ones after the stop bit is received. only a complete idle frame causes the idle flag to be set. in some applications, software overhead can cause a bit-time of logic level one to occur between frames. this bit-time does not affect content, but if it occurs after a frame of ones when short detection is enabled, the receiver flags an idle line. when the ilie bit in sccxr1 is set, an interrupt request is generated when the idle flag is set. the flag is cleared by reading scxsr and scxdr in sequence. for receiver queue operation, idle is cleared when scxsr is read with idle set, followed by a read of scrq[0:15]. idle is not set again until after at least one frame has been received (rdrf = 1). this prevents an extended idle interval from causing more than one interrupt. 14.8.7.9 receiver wake-up the receiver wake-up function allows a transmitting device to direct a transmission to a single receiver or to a group of receivers by sending an address frame at the start of a message. hardware activates each receiver in a system under certain conditions. resident software must process address information and enable or disable receiver operation. a receiver is placed in wake-up mode by setting the rwu bit in sccxr1. while rwu is set, receiver status flags and interrupts are disabled. although the software can clear rwu, it is normally cleared by hardware during wake-up. the wake bit in sccxr1 determines which type of wake-up is used. when wake = 0, idle-line wake-up is selected. when wake = 1, address-mark wake-up is selected. both types require a software-based device addressing and recognition scheme. idle-line wake-up allows a receiver to sleep until an idle line is detected. when an idle line is detected, the receiver clears rwu and wakes up. the receiver waits for the first frame of the next transmission. the data frame is received normally, transferred to the rdrx, and the rdrf flag is set. if software does not recognize the address, it can set rwu and put the receiver back to sleep. for idle-line wake-up to work, there must be a minimum of one frame of idle line between transmissions. there must be no idle time between frames within a transmission. address mark wake-up uses a special frame format to wake up the receiver. when the msb of an address-mark frame is set, that frame contains address information. the first frame of each transmission must be an address frame. when the msb of a frame is set, the receiver clears rwu and wakes up. the data frame is received normally, transferred to the rdrx, and the rdrf flag is set. if software does not recognize the address, it can set rwu and put the receiver back to sleep. address mark wake-up allows idle time between frames and 14-66 mpc565/mpc566 reference manual motorola sci queue operation eliminates idle time between transmissions. however, there is a loss of efficiency because of an additional bit-time per frame. 14.8.7.10 internal loop mode the loops bit in sccxr1 controls a feedback path in the data serial shifter. when loops is set, the sci transmitter output is fed back into the receive serial shifter. txd is asserted (idle line). both transmitter and receiver must be enabled before entering loop mode. 14.9 sci queue operation 14.9.1 queue operation of sci1 for transmit and receive the sci1 serial module allows for queueing on transmit and receive data frames. in the standard mode, in which the queue is disabled, the sci1 operates as previously defined (i.e., transmit and receive operations done via sc1dr). however, if the sci1 queue feature is enabled (by setting the qte and/or qre bits within qsci1cr) a set of 16 entry queues is allocated for the receive and/or transmit operation. through software control the queue is capable of continuous receive and transfer operations within the sci1 serial unit. 14.9.2 queued sci1 status and control registers the sci1 queue uses the following registers: qsci1 control register (qsci1cr, address offset 0x28) qsci1 status register (qsci1sr, address offset 0x2a) 14.9.2.1 qsci1 control register msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 lsb 15 qtpnt qthfi qbhfi qthei qbhei rsvd qte qre qtwe qtsz reset: 0000 0 0 0 0 000 00000 figure 14-31. qsci1cr ? qsci1 control register 0x30 5028 0x30 5428 motorola chapter 14. queued serial multi-channel module 14-67 sci queue operation table 14-35. qsci1cr bit descriptions bit(s) name description 0:3 qtpnt queue transmit pointer. qtpnt is a 4-bit counter used to indicate the next data frame within the transmit queue to be loaded into the sc1dr. this feature allows for ease of testability. 4 qthfi receiver queue top-half full interrupt. when set, qthfi enables an sci1 interrupt whenever the qthf flag in qsci1sr is set. the interrupt is blocked by negating qthfi. this bit refers to the queue locations scrq[0:7]. 0 qthf interrupt inhibited 1 queue top-half full (qthf) interrupt enabled 5 qbhfi receiver queue bottom-half full interrupt. when set, qbhfi enables an sci1 interrupt whenever the qbhf flag in qsci1sr is set. the interrupt is blocked by negating qbhfi. this bit refers to the queue locations scrq[8:15]. 0 qbhf interrupt inhibited 1 queue bottom-half full (qbhf) interrupt enabled 6 qthei transmitter queue top-half empty interrupt. when set, qthei enables an sci1 interrupt whenever the qthe flag in qsci1sr is set. the interrupt is blocked by negating qthei. this bit refers to the queue locations sctq[0:7]. 0 qthe interrupt inhibited 1 queue top-half empty (qthe) interrupt enabled 7 qbhei transmitter queue bottom-half empty interrupt. when set, qbhei enables an sci1 interrupt whenever the qbhe flag in qsci1sr is set. the interrupt is blocked by negating qbhei. this bit refers to the queue locations sctq[8:15]. 0 qbhe interrupt inhibited 1 queue bottom-half empty (qbhe) interrupt enabled 8?reserved 9 qte queue transmit enable. when set, the transmit queue is enabled and the tdre bit should be ignored by software. the tc bit is redefined to indicate when the entire queue is finished transmitting. when clear, the sci1 functions as described in the previous sections and the bits related to the queue (section 5.5 and its subsections) should be ignored by software with the exception of qte. 0 transmit queue is disabled 1 transmit queue is enabled 10 qre queue receive enable. when set, the receive queue is enabled and the rdrf bit should be ignored by software. when clear, the sci1 functions as described in the previous sections and the bits related to the queue (section 5.5 and its subsections) should be ignored by software with the exception of qre. 0 receive queue is disabled 1 receive queue is enabled 11 qtwe queue transmit wrap enable. when set, the transmit queue is allowed to restart transmitting from the top of the queue after reaching the bottom of the queue. after each wrap of the queue, qtwe is cleared by hardware. 0 transmit queue wrap feature is disabled 1 transmit queue wrap feature is enabled 12:15 qtsz queue transfer size. the qtsz bits allow programming the number of data frames to be transmitted. from 1 (qtsz = 0b0000) to 16 (qtsz = 0b1111) data frames can be specified. qtsz is loaded into qpend initially or when a wrap occurs. 14-68 mpc565/mpc566 reference manual motorola sci queue operation 14.9.2.2 qsci1 status register msb 0 1234567891011121314lsb 15 reserved qor qthf qbhf qthe qbhe qrpnt qpend reset: 0 0 0 0 1 1 1 1 0 0 0 00000 figure 14-32. qsci1sr ? qsci1 status register 0x30 502a 0x30 542a table 14-36. qsci1sr bit descriptions bit(s) name description 0:2 ? reserved 3 qor receiver queue overrun error. the qor is set when a new data frame is ready to be transferred from the sc1dr to the queue and the queue is already full (qthf or qbhf are still set). data transfer is inhibited until qor is cleared. previous data transferred to the queue remains valid. additional data received during a queue overrun condition is not lost provided the receive queue is re-enabled before or (sc1sr) is set. the or flag is set when a new data frame is received in the shifter but the data register (sc1dr) is still full. the data in the shifter that generated the or assertion is overwritten by the next received data frame, but the data in the sc1dr is not lost. 0 the queue is empty before valid data is in the sc1dr 1 the queue is not empty when valid data is in the sc1dr 4 qthf receiver queue top-half full. qthf is set when the receive queue locations scrq[0:7] are completely filled with new data received via the serial shifter. qthf is cleared when register qsci1sr is read with qthf set, followed by a write of qthf to zero. 0 the queue locations scrq[0:7] are partially filled with newly received data or is empty 1 the queue locations scrq[0:7] are completely full of newly received data 5 qbhf receiver queue bottom-half full. qbhf is set when the receive queue locations scrq[8:15] are completely filled with new data received via the serial shifter. qbhf is cleared when register qsci1sr is read with qbhf set, followed by a write of qbhf to zero. 0 the queue locations scrq[8:15] are partially filled with newly received data or is empty 1 the queue locations scrq[8:15] are completely full of newly received data 6 qthe transmitter queue top-half empty. qthe is set when all the data frames in the transmit queue locations sctq[0:7] have been transferred to the transmit serial shifter. qthe is cleared when register qsci1sr is read with qthe set, followed by a write of qthe to zero. 0 the queue locations sctq[0:7] still contain data to be sent to the transmit serial shifter 1 new data may now be written to the queue locations sctq[0:7] 7 qbhe transmitter queue bottom-half empty. qbhe is set when all the data frames in the transmit queue locations sctq[8:15] has been transferred to the transmit serial shifter. qbhe is cleared when register qsci1sr is read with qbhe set, followed by a write of qbhe to zero. 0 the queue locations sctq[8:15] still contain data to be sent to the transmit serial shifter 1 new data may now be written to the queue locations sctq[8:15] 8:11 qrpnt queue receive pointer. qrpnt is a 4-bit counter used to indicate the position where the next valid data frame will be stored within the receive queue. this field is writable in test mode only; otherwise it is read-only. 12:15 qpend queue pending. qpend is a 4-bit decrementer used to indicate the number of data frames in the queue that are awaiting transfer to the sc1dr. this field is read-only. from 1 (qpend = 0b0000) to 16 (or done, qpend = 1111) data frames can be specified. motorola chapter 14. queued serial multi-channel module 14-69 sci queue operation 14.9.3 qsci1 transmitter block diagram the block diagram of the enhancements to the sci transmitter is shown in figure 14-33. figure 14-33. queue transmitter block enhancements 14.9.4 qsci1 additional transmit operation features available on a single sci channel (sci1) implemented by the queue transmit enable (qte) bit set by software. when enabled, (qte = 1) the tdre bit should be ignored by software and the tc bit is redefined (as described later). when the queue is disabled (qte = 0), the sci functions in single buffer transfer mode where the queue size is set to one (qtsz = 0000), and tdre and tc function as previously defined. locations sctq[0:15] can be used as general purpose 9-bit registers. all other bits pertaining to the queue should be ignored by software. 10(11)-bit tx shift register stop start h(8)76543210l txd sctq[0] sctq[1] sctq[15] 9-bit 16:1 mux transmitter baud rate clock 4-bits qtsz[0:3] qthei qbhei queue control qte qpend[0:3] qthe qbhe qtwe queue status queue control logic sci interrupt request sc1dr tx buffer sci1 non-queue operation data bus 14-70 mpc565/mpc566 reference manual motorola sci queue operation programmable queue up to 16 transmits (sctq[0:15]) which may allow for infinite and continuous transmits. available transmit wrap function to prevent message breaks for transmits greater than 16. this is achieved by the transmit wrap enable (qtwe) bit. when qtwe is set, the hardware is allowed to restart transmitting from the top of the queue (sctq0). after each wrap, qtwe is cleared by hardware. ? transmissions of more than 16 data frames must be performed in multiples of 16 (qtsz = 0b1111) except for the last set of transmissions. for any single non-continuous transmissions of 16 or less or the last transmit set composed of 16 or fewer data frames, programming of qtsz to the corresponding value of 16 or less where qtwe = 0 is allowed. interrupt generation when the top half (sctq[0:7]) of the queue has been emptied (qthe) and the bottom half (sctq[8:15]) of the queue has been emptied (qbhe). this may allow for uninterrupted and continuous transmits by indicating to the cpu that it can begin refilling the queue portion that is now emptied. ? the qthe bit is set by hardware when the top half is empty or the transmission has completed. the qthe bit is cleared when the qsci1sr is read with qthe set, followed by a write of qthe to zero. ? the qbhe bit is set by hardware when the bottom half is empty or the transmission has completed. the qbhe bit is cleared when the qsci1sr is read with qbhe set, followed by a write of qbhe to zero. ? in order to implement the transmit queue, qte must be set (qsci1cr), te must be set (scc1r1), qthe must be cleared (qsci1sr), and tdre must be set (sc1sr). enable and disable options for the interrupts qthe and qbhe as controlled by qthei and qbhei respectfully. programmable 4-bit register queue transmit size (qtsz) for configuring the queue to any size up to 16 transfers at a time. this value may be rewritten after transmission has started to allow for the wrap feature. 4-bit status register to indicate the number of data transfers pending (qpend). this register counts down to all 0?s where the next count rolls over to all 1?s. this counter is writable in test mode; otherwise it is read-only. 4-bit counter (qtpnt) is used as a pointer to indicate the next data frame within the transmit queue to be loaded into the sc1dr. this counter is writable in test mode; otherwise it is read-only. a transmit complete (tc) bit re-defined when the queue is enabled (qte = 1) to indicate when the entire queue (including when wrapped) is finished transmitting. this is indicated when qpend = 1111 and the shifter has completed shifting data out. tc is cleared when the scxsr is read with tc = 1 followed by a write to sctq[0:15]. if the queue is disabled (qte = 0), the tc bit operates as originally designed. when the transmit queue is enabled (qte = 1), writes to the transmit data register (sc1dr) have no effect. motorola chapter 14. queued serial multi-channel module 14-71 sci queue operation 14.9.5 qsci1 transmit flow chart implementing the queue figure 14-34. queue transmit flow reset set qte=1 shift data out load tdr (sc1dr) with sctq[qtpnt] decrement qpend, qpend = 1111 no yes set qthei, qbhei hardware software load qpend with qtsz, increment qtpnt qtpnt=1000? qbhe=0? reset qtpnt to 0000 write qtsz=n clear qthe, tc write sctq[0:n] set te qte=1, te=1 no yes tdre=1, qthe=0? refers to action performed in parallel qte, te=1? no yes qtpnt = 1111? qtwe = 1 set qthe, qbhe clear qte no set qthe set qbhe no yes no yes yes yes write qtsz for wrap clear qthe possible set of qtwe clear qbhe clear qtwe te=0, tc=1, tdre=1 qte=0, qtpnt=0, qtwe=0 qthei=0, qthe=1 qbhei=0, qbhe=1 &qthe=0? no (tdre=1) 14-72 mpc565/mpc566 reference manual motorola sci queue operation figure 14-35. queue transmit software flow qthe = 1? yes no enable queue interrupt reset configure the transmit flow qbhe = 1? yes no qthei = 1, if transmitting greater than 16 data frames, write qtsz=n for first pass use of the queue set qte and te = 1 enable queue interrupt for first use of the queue. if finished transmitting, then clear qte and/or te if finished transmitting, then clear qte and/or te done done read status register with tc = 1, write sctq[0:n] (clears tc) read status register with qthe=1 write qthe = 0 (and qbhe if transmitting more than 8 data must have equaled 16) read qthe=1, write qthe=0 write new data sctq[0:7] to wrap, write new qtsz=n set qtwe (previous qtsz if transmitting greater than 8 data frames on wrap read qbhe=1,write qbhe=0 write new data to sctq[8:15] frames) qbhei = 1 motorola chapter 14. queued serial multi-channel module 14-73 sci queue operation 14.9.6 example qsci1 transmit for 17 data bytes figure 14-36 below shows a transmission of 17 data frames. the bold type indicates the current value for qtpnt and qpend. the italic type indicates the action just performed by hardware. regular type indicates the actions that should be performed by software before the next event. 14-74 mpc565/mpc566 reference manual motorola sci queue operation figure 14-36. queue transmit example for 17 data bytes 0000 0111 1000 1111 qtpnt qpend 1111 1000 0111 0000 qtsz=1111 (16 data frames) sctq[0] sctq[7] sctq[8] sctq[15] writenewqtszforwhenwrapoccurs qtsz=0 (16+1=17),set qtwe, clear qthe write sctq[0] for 17th transfer 0000 0111 1000 1111 qtpnt qpend 0000 qtsz=0000 (1 data frame) sctq[0] sctq[7] sctq[8] sctq[15] load qpend with qtsz (0) reset qtpnt 0000 0111 1000 1111 qtpnt qpend 1111 1000 0111 0000 qtsz=1111 (16 data frames) sctq[0] sctq[7] sctq[8] sctq[15] data to be transferred available register space 0001 1111 qthe interrupt received transmit queue enabled 1 2 3 qbhe interrupt received (wrap occurred) clear qtwe motorola chapter 14. queued serial multi-channel module 14-75 sci queue operation 14.9.7 example sci transmit for 25 data bytes figure 14-37 below is an example of a transmission of 25 data frames. figure 14-37. queue transmit example for 25 data frames 0000 0111 1000 1111 qtpnt qpend 1111 1000 0111 0000 qtsz=1111 (16 data frames) sctq[0] sctq[7] sctq[8] sctq[15] 0000 0111 1000 1111 qtpnt qpend 1000 qtsz=1000 (9 data frames) sctq[0] sctq[7] sctq[8] sctq[15] 0000 0111 1000 1111 qtpnt qpend 1111 1000 0111 0000 qtsz=1111(16dataframes) sctq[0] sctq[7] sctq[8] sctq[15] 0001 0000 0111 1000 1111 qtpnt qpend 1000 qtsz=1000(9dataframes) sctq[0] sctq[7] sctq[8] sctq[15] 0000 0000 0001 data to be transferred available register spac 1001 1111 qthe interrupt received writeqtsz=8(16+9=25) write sctq [0:7] for 8 more data frames set qtwe clear qthe load qpend with qtsz clear qtwe write sctq[8] clear qbhe 3 1 2 4 transmit queue enabled qbhe interrupt received (wrap occurred) reset qtpnt qthe interrupt received 14-76 mpc565/mpc566 reference manual motorola sci queue operation 14.9.8 qsci1 receiver block diagram the block diagram of the enhancements to the sci receiver is shown below in figure 14-38. figure 14-38. queue receiver block enhancements rxd receiver baud rate clock 10(11)-bit rx shift register stop start h(8)76543210l scrq[0] scrq[1] scrq[15] 16:1 mux 4-bits qre qthfi qbhfi queue control qrpnt[0:3] qthf qbhf queue status queue control logic sci interrupt request qor scxdr rx buffer sci1 non-queue operation data bus motorola chapter 14. queued serial multi-channel module 14-77 sci queue operation 14.9.9 qsci1 additional receive operation features available on a single sci channel (sci1) implemented by the queue receiver enable (qre) bit set by software. when the queue is enabled, software should ignore the rdrf bit. when the queue is disabled (qre = 0), the sci functions in single buffer receive mode (as originally designed) and rdrf and or function as previously defined. locations scrq[0:15] can be used as general purpose 9-bit registers. software should ignore all other bits pertaining to the queue. only data that has no errors (fe and pf both false) is allowed into the queue. the status flags fe and pf, if set, reflect the status of data not allowed into the queue. the receive queue is disabled until the error flags are cleared via the original sci mechanism and the queue is re-initialized. the pointer qrpnt indicates the queue location where the data frame would have been stored. queue size capable to receive up to 16 data frames (scrq[0:15]) which may allow for infinite and continuous receives. interrupt generation can occur when the top half (scrq[0:7]) of the queue has been filled (qthf) and the bottom half (scrq[8:15]) of the queue has been filled (qbhf). this may allow for uninterrupted and continuous receives by indicating to the cpu to start reading the queue portion that is now full. ? the qthf bit is set by hardware when the top half is full. the qthf bit is cleared when the scxsr is read with qthf set, followed by a write of qthf to zero. ? the qbhf bit is set by hardware when the bottom half is full. the qbhf bit is cleared when the scxsr is read with qbhf set, followed by a write of qbhf to zero. in order to implement the receive queue, the following conditions must be met: qre must be set (qsci1cr); re must be set (scc1r1); qor and qthf must be cleared (qsci1sr); and or, pf, and fe must be cleared (sc1sr). enable and disable options for the interrupts qthf and qbhf as controlled by the qthfi and qbhfi, respectively. 4-bit counter (qrpnt) is used as a pointer to indicate where the next valid data frame will be stored. a queue overrun error flag (qor) to indicate when the queue is already full and another data frame is ready to be stored into the queue (similar to the or bit in single buffer mode). the qor bit can be set for qthf = 1 or qbhf = 1, depending on where the store is being attempted. the queue can be exited when an idle line is used to indicate when a group of serial transmissions is finished. this can be achieved by using the ilie bit to enable the 14-78 mpc565/mpc566 reference manual motorola sci queue operation interrupt when the idle flag is set. the cpu can then clear qre and/or re allowing the receiver queue to be exited. for receiver queue operation, idle is cleared when sc1sr is read with idle set, followed by a read of scrq[0:15]. for receiver queue operation, nf is cleared when the sc1sr is read with nf set, followed by a read of scrq[0:15]. when noise occurs, the data is loaded into the receive queue, and operation continues unaffected. however, it may not be possible to determine which data frame in the receive queue caused the noise flag to be asserted. the queue is successfully filled (16 data frames) if error flags (fe and pf) are clear, qthf and qbhf are set, and qrpnt is reset to all zeroes. qor indicates that a new data frame has been received in the data register (sc1dr), but it cannot be placed into the receive queue due to either the qthf or qbhf flag being set (qsci1sr). under this condition, the receive queue is disabled (qre = 0). software may service the receive queue and clear the appropriate flag (qthf, qbhf). data is not lost provided that the receive queue is re-enabled before or (sc1sr) is set, which occurs when a new data frame is received in the shifter but the data register (sc1dr) is still full. the data in the shifter that generated the or assertion is overwritten by the next received data frame, but the data in the sc1dr is not lost. motorola chapter 14. queued serial multi-channel module 14-79 sci queue operation 14.9.10qsci1 receive flow chart implementing the queue figure 14-39. queue receive flow re=0, qrwe=0 qrpnt=0000 set qre load rx data to qrpnt = 0000? no yes scrq[qrpnt], qre=0, qor=0 hardware software refers to action performed in parallel qthf=1, qbhf=1 qthfi=0, qbhfi=0 no yes set qthfi, qbhfi clear qthf, qbhf set re reset increment qrpnt qre, re=1? no yes qre/re=1 qthf/qor=0 fe/pe/or=0 qrpnt=8 & qbhf qrpnt=0 & qthf fe, pe = 0? qrpnt = 1000? reset qrpnt to 0000 rdrf=1? clear qre set qthf set qbhf yes no no set qor clear qthf clear qbhf yes yes no no yes 14-80 mpc565/mpc566 reference manual motorola sci queue operation 14.9.11qsci1 receive queue software flow chart figure 14-40. queue receive software flow qthf=1? yes no enable queue interrupts reset configure the receive queue qbhf = 1? yes no read status register qbhf = 1 readscrq[8:15] read status register with qthfi, qbhfi = 1, set qre and re = 1 qthf = 1 read scrq[0:7] read status register with qthf & qbhf = 1, write qthf & qbhf = 0 functioncanbeusedto indicate when a group of serial transmissions is finished enable ilie=1 to detect an idle line idle = 1? yes no clear qre and/or re to exit the queue done write qthf = 0 write qbhf = 0 with motorola chapter 14. queued serial multi-channel module 14-81 sci queue operation 14.9.12example qsci1 receive operation of 17 data frames figure 14-41 shows an example receive operation of 17 data frames. the bold type indicates the current value for the qrpnt. action of the queue may be followed by starting at the top of the figure and going left to right and then down the page. figure 14-41. queue receive example for 17 data bytes 0000 0111 1000 1111 qrpnt scrq[0] scrq[7] scrq[8] scrq[15] 0000 0111 1000 1111 qrpnt scrq[0] scrq[7] scrq[8] scrq[15] read scsr and scrq[0:7] clear qthf 0000 0111 1000 1111 qrpnt scrq[0] scrq[7] scrq[8] 0000 0111 1000 1111 qrpnt scrq[0] scrq[7] 0001 data available received space qthf interrupt received scrq[15] read scrq[8:15] clear qbhf qbhf interrupt received scrq[8] scrq[15] clear qre/re receive queue enabled read scrq[0] idle interrupt received 1 2 3 4 14-82 mpc565/mpc566 reference manual motorola sci queue operation motorola chapter 15. data link controller module (dlcmd2) 15-1 chapter 15 data link controller module (dlcmd2) this section contains data for the data link controller digital module (dlcmd2). this module is based on the intermodule bus (imb) dlcmd module, but has several feature enhancements including those required for the imb3. the primary purpose of this document is to form the foundation for the functionality and features of the module. this module is designed in a modular structure and is fully compatible with the intermodule bus version 3. the dlcmd2 is designed with sufficient flexibility to accommodate feature mixes such as byte or symbol-level message buffering. 15.1 features the dlcmd2 is essentially the digital portion of a class b serial data link controller. a separate transceiver is required. the dlcmd2 will provide the following features: sae j1850 compatible gm class 2 compatible 10.4 kbytes/s vpw bit format handles all network protocol functions (access, arbitration, error detection) parallel 16-bit accesses all registers are individually addressable polling of imb3 interrupt generation with vector lookup transmit buffer first byte can be loaded without a command byte message buffering on transmit and receive eight-bit hardware crc generation and checking no on-board oscillator (uses system clock) dlcmd2 logic is clocked from imb3 interface to the external transceiver transmit and receive block mode supported transmit and receive 4x mode supported 15-2 mpc565/mpc566 reference manual motorola background two extra 1-bits sent if lose arbitration on a byte boundary transmitter underrunning indication added to status register imb3 full feature support with option plug selection software programmable prescaler to support two 128-mhz system clock range programmable receiver input polarity programmable normalization bit format digitally filtered receiver power conserving sleep mode with wakeup from bus activity and no loss of data in-frame response (ifr) type 1, 2 and 3 supported auto retry for loss of arbitration and errors symbol timing control and pre-scaler register symbol timing data register (sdata) write access to symbol timing parameter table through sdata 15.2 background the dlcmd2 is an evolution of an earlier module found on imb mcus.the analog function, or transceiver, necessary to interface to the j1850 bus must be applied external to the module. 15.3 applicable documents saej1850 class b data communications network interface 15.4 general requirements this module may be used with mcus supporting the imb3 bus architecture. refer to table 15-1. table 15-1. dlcmd2 requirements operating temperature ic package clock speed 1 1 no additional clock part needed for the dlcmd2. the dlcmd2 will adapt to the cpu (imb3) clocking using software programmable prescaler. dlcmd2 must correctly operate over any clock jitter present within the integrated device. quiescent current draw ?40 to +125 c na 2.00 mhz (min) to 128.00 mhz (max) 2 2 limitedto56mhz(max)onthempc565/mpc566. 50 a lpstop, 200 a idle motorola chapter 15. data link controller module (dlcmd2) 15-3 logic description 15.5 logic description the data link controller module (dlcmd2) provides access to an external serial communication multiplex bus, operating according to the sae j1850 protocol. this section describes the features, functions, and operation, of the dlcmd2 used as one of several nodes in a vehicle multiplex and/or diagnostic wiring network. all control, status, and message bytes (head of fifos only) are accessible as memory mapped registers within the mcu. it retains the maximum throughput performance for single-chip applications including full j1850 message-level buffering. 15.5.1 block diagram a block diagram of the dlcmd2 is shown in figure 15-1. figure 15-1. dlcmd2 block diagram 15.5.2 dlcmd2 operation the sections that follow describe the operation of the dlcmd2. dlcmd2 biu to c p u xmit fifo recv registers control logic command fifo status cl2tx cl2rx port interface rcv shift reg tx shift reg crc gen prescale r clock tx fsm f dlc rcv digital filter comp coder rx_count & tx_count txpd ctrl rxpd rdata tdata cmd thead recv cc sdata interrupt txpd buff decode dlcmd2 core dlcmd2 fifo biu fsm1 1finite state machine decode fifo 15-4 mpc565/mpc566 reference manual motorola logic description 15.5.2.1 general the dlcmd2 handles j1850 messages with minimal cpu servicing. the mcu will typically transfer complete messages into the dlcmd2 for transmission on the j1850 data link, and is interrupted only when a complete message is received off of the j1850 data link. internal buffers of 20 bytes on the receive side and 11 bytes on the transmit side allow full message length operations (maximum 12 bytes normal mode, including a one-byte crc). the dlcmd2 handles all arbitration and error detection duties internally. the class 2 data link has been defined as the gm implementation of the sae j1850 automotive communications protocol. the class 2 bus is a 10.4 kbytes/s carrier sense multiple access with collision resolution (csma/cr) communications bus. csma/cr operates by arbitrating ownership of the bus on a bit-by-bit basis. the major advantage of csma/cr is that no message is lost in a collision. if a node determines that it needs to send a message while another message is in progress, it must wait until the link is idle. when one node begins to transmit (after bus idle), all nodes desiring to transmit are obligated to begin their transmission at the same time. the rule of arbitration is that any node that transmits a 1-bit when another node transmits a 0-bit stops transmitting on the bus immediately. this is called a zero-dominant bus. see section 15.6, ?signals overview? for 1-bit and 0-bit definitions. all nodes are obligated to receive all bits of every message on the bus, even while transmitting. arbitration continues to the end of a message, if necessary, resulting in a properly transmitted message even if arbitration were to continue to the end of the message. when the bus becomes idle, the node(s) which previously lost arbitration will re-transmit its message if the txfifo was not cleared or overwritten with another message. 15.5.2.2 logic section description and relation to transceiver the logic section includes the imb3 interface, j1850 waveform generation and timing logic, buffers for data (transmit and receive), error detection code generation and checking, configuration logic, control logic, status logic, and arbitration logic. the nondestructive contention protocol of the j1850 bus requires that there be an active and a passive state of the bus. the bus is in the active or driven state when one or more of the connected transceivers is active and passive when all transceivers are inactive. this is a logical wired or arrangement. the function of the transceiver is to drive the bus active in response to a signal from the dlcmd2 logic and to detect the state of the bus for the dlcmd2 logic handler. the transceiver establishes and detects the state of the bus within a limited period of time. it does so in the presence of conducted and induced noise and without creating radio interference. operation of the transceiver is constrained by the available power and the need to tolerate a number of abnormal conditions. the j1850 bus is intended to work in a relatively noisy environment. the main source of low frequency noise is ground offset between the nodes. proper operation is assured with motorola chapter 15. data link controller module (dlcmd2) 15-5 logic description any combination of ground offsets up to a maximum differential of two volts at any frequency. induced noise tends to be short duration pulses. the protocol handler includes a digital filter to remove these pulses. additional filtering is not needed in the receiver, which responds quickly and avoids stretching large amplitude pulses. 15.5.2.3 dlcmd2 transmit/receive operation a standard data exchange is composed of one data byte and (in some cases) one command byte going from cpu to dlcmd2, or one status byte and one data byte going from dlcmd2 to cpu. the use of the byte written to the dlcmd2 is specified in the command byte that accompanies it or deduced from current dlcmd2 state. the command byte also contains instructions for the dlcmd2 regarding the receive first in/first out (fifo) buffer, transmit actions, resetting the transmitter, and sending a break signal. the status byte that the dlcmd2 sends to the cpu contains information on the status of the receive fifo buffer, the status of the transmit fifo buffer, the condition of the bus, and the type of accompanying data. the data accompanying the status byte can be data received off of the j1850 bus, a completion code which contains information about a received message, or nothing. figure 15-2 shows the dlcmd2 transmit/receive operation. figure 15-2. typical transmit/receive operation messageonbus interrupt cleared by ipr read/write access dlcmd2 cpu imb3 activity to transfer message into dlcmd2 for transmission imb3 activity to transfer received message out of dlcmd2 last byte of message and completion code placed in rxfifo interrupt asserted j1850 interrupt byte received and imb3 interface activity placed into rxfifo dlcmd2 message on bus bus activity 15-6 mpc565/mpc566 reference manual motorola logic description all messages received off of the j1850 bus will have their start bit removed and the crc replaced with a completion code. all other bytes of the message are placed in order, most significant bit (msb) first, in the receive fifo buffer. the dlcmd2 requests servicing by requesting an interrupt. interrupts may be disabled. typically, the dlcmd2 will only interrupt the cpu when a complete message has been received. the cpu then will service the dlcmd2 and remove the message. when the cpu desires to send a message on the j1850 bus, it will select the dlcmd2, and transfer a complete message (without start bit or crc). the dlcmd2 allows the cpu to continually write message bytes to be transmitted without intervening command bytes; only the last byte must be accompanied by a command byte indicating ?last byte.? user code must read both status and receive data in pairs. the dlcmd2 supports aligned word writes and reads of certain locations. the dlcmd2 can be programmed by the cpu to enter a power conserving sleep mode as soon as bus traffic stops. if interrupts are enabled, the dlcmd2 will wake-up its internal circuitry and interrupt the host when activity on the bus is sensed. the dlcmd2 will be able to correctly receive the first message that wakes it up from sleep mode. error conditions and transmit status, such as lost arbitration, are sent to the cpu either in the status byte or in the completion code that is placed in the receive fifo immediately after each received message. 15.5.2.4 message transmission as described in section 15.5.2.3, ?dlcmd2 transmit/receive operation,? the dlcmd2 is loaded with a message from the cpu for transmission. the dlcmd2 will then add a start bit to the outgoing data, and contend for a message slot on the j1850 bus. the transmit buffer in the dlcmd2 is 11 bytes long, to allow complete messages to be transferred to the dlcmd2 for transmission. information about which byte the cpu is transferring is sent to the dlcmd2 as part of the control information sent with each byte transferred. when the dlcmd2 has transmitted all of the message bytes, it will automatically append a crc to the end of the message. the dlcmd2 will automatically retry a transmission if it lost arbitration. the auto retry feature causes the dlcmd2 to signal to the cpu (via the status byte) that the transmit fifo is full until the message is successfully sent. once successfully sent, the dlcmd2 will signal the cpu that the txfifo is empty and hence ready for the next message. each time the message loses arbitration, the completion code for that received message will indicate that the transmitter attempted transmission, and lost arbitration. as soon as a transmit slot on the bus becomes open, the dlcmd2 will automatically attempt to retransmit the message. if there were any errors during the transmission of the message the auto retry feature will cause the message to be retransmitted. the auto retry feature can be terminated by the cpu through the command byte. this causes the dlcmd2 to finish its motorola chapter 15. data link controller module (dlcmd2) 15-7 logic description current transmit activity, and then clear the transmit buffer. if there is no transmit activity when the auto retry is disabled and the dlcmd2 previously attempted to transmit, the dlcmd2 will immediately clear the transmit buffer. 15.5.2.5 message reception receiving information off of the j1850 bus occurs in much the same manner as sending data. note by definition, every message a dlcmd2 sends on the data link is also received by its own receiver as if the transmission had been initiated by a different node. the dlcmd2 will automatically remove the start bit from the message, and check the crc for errors. if a crc error occurs, it is flagged in the message completion information (completion code) that takes the place of the crc byte in the receive fifo buffer (rxfifo). the dlcmd2 will interrupt the cpu to signal that a complete message has been received, or when the rxfifo is approaching full. when the cpu starts the transfer process, the status byte from the dlcmd2 indicates the data?s presence, and the amount of data left in the rxfifo. when a dlcmd2 loses arbitration to another node, it will continue to receive the remainder of the message. the completion code will indicate that the dlcmd2 contended for a transmit slot, and lost arbitration to the received message. the cpu does not need to resend the message if the auto retry feature is enabled. the timing of the transmit waveform is re-synchronized on each edge as received off of the bus. provisions have been made for immediate in-message reply to allow a path for compatibility with other j1850 implementations. in-frame response (ifr) requires a byte-by-byte interrupt mode and careful cpu attention. ifr is described in detail in a later section. a break/reset waveform on the bus is shaped such that it will win arbitration against any currently transmitting message. when the dlcmd2 senses that such a waveform has occurred on the bus, it will stop transmitting its current message, reset its transmitter [clear the data link controller module (dlcmd2) txfifo], and set a bit in the completion code and request an interrupt to indicate to the cpu that such a condition has occurred. since the break signal always wins arbitration, any in-progress messages will simply lose arbitration, and the dlcmd2 will treat the in-progress received message as complete. if a break occurs while there are no in progress messages, a completion code indicating that a break has occurred will be placed in the rxfifo and a cpu interrupt is generated. the break is sent by the dlcmd2 controller by placing a send break command in the command byte.this waveform is sent immediately upon the command byte being latched in. if there is a current 15-8 mpc565/mpc566 reference manual motorola logic description transmission, it will be stopped, and the break waveform sent. a break will also take the dlcmd2 out of 4x mode. 15.5.2.6 sleep mode the cpu may put the dlcmd2 in sleep mode by setting the stop bit in the mcr. setting this bit will tell the dlcmd2 to halt its internal clocks immediately after any currently in progress messages are completed. interrupts to the host on bus activity can be disabled by configuring the dlcmd2 in the ilr register. normal use of the sleep feature will have interrupts to the host enabled, so that the host will not miss any messages on the data link. if interrupts are disabled, and then the dlcmd2 is put to sleep, the only way to wake up the dlcmd2 is by the cpu clearing the stop bit. 15.5.2.7 debug mode the debug mode is entered from the reset state or from the run state by asserting or deasserting the appropriate signals. see section 15.7.5, ?dlcmd2 debug? for details. 15.5.2.8 4x speed mode the dlcmd2 has the ability to transfer large amounts of data in a 4x speed mode under special conditions such as memory loading, and diagnostic responses. there is a bit in the mcr to control this feature. the 4x speed mode affects only the bit timing section of the dlcmd2, including the digital filter. a break will reset any listening nodes out of 4x speed mode. the 4x speed mode is not for use during normal operation. to use 4x mode there must be coordination of all nodes on the network. this mode will not work properly at the network level unless all nodes are transmitting in 4x mode. certain nodes may elect not to take part in 4x communications; these nodes may listen but must not transmit. notification of entrance into the special 4x mode is communicated to all nodes with a regular speed message indicating the bus protocol speed switch to 4x mode. a break received will automatically take the dlcmd2 out of 4x mode. 15.5.2.9 block mode the dlcmd2 has the ability to receive a message of unlimited length, provided the cpu reads bytes out of the rxfifo before it overflows. if the txfifo was filled with no last byte indicated, the dlcmd2 will start sending that message in terminate auto-retry mode; the status will indicate ?txfifo almost full? as soon as the first byte is sent, and ?txfifo contains some data bytes? as soon as the second byte is sent. as new data is written to the txfifo, the status will accurately reflect the condition motorola chapter 15. data link controller module (dlcmd2) 15-9 logic description of the txfifo until a ?last byte? is written. when a ?last byte? command has been sent to the dlcmd2, the txfifo will indicate ?txfifo full? until the transmission is finished. the dlcmd2 will send an infinite length message if properly handled by the cpu. 15.5.2.10 error detection the dlcmd2 uses a digital filter and the cyclical redundancy check (crc) byte to detect errors. the digital filter eliminates short duration noise spikes and transition noise from the incoming waveform. it is a ?hysteresis? type filter with a time constant of approximately 8 s, depending on the imb3 clock frequency. the step response of the filter is a step function delayed by 8 s. as an example, with a 2-mhz clock (t dlc = 0.5 s) and a 4-bit up/down counter. the counter counts up for every oscillator clock pulse when the input is in the active state and down when the input is in the passive state. the counter clamps at 0 and 15. the output is defined by table 15-2. this filter will cause a receive delay of 16-17 times t dlc in addition to the delay in the transmitter and receiver analog interface circuitry. this delay?s only variation is due to the tolerance on the cpu?s oscillator. in simple terms, the effect of the filter is that a pulse low or high level on the bus is not recognized unless it?s duration is longer than about 8 s. the crc byte is used by the receiver to determine if any errors have occurred during transmission. crc generation uses the divisor polynomial: x 8 +x 4 +x 3 +x 2 +1.the transmitted crc is generated by the receiver by initially setting the remainder polynomial to all ones, serially processing the first byte and then all remaining bytes of the message, and appending the one?s complement of the remainder to the end of the transmitted message. the receiver uses the same divisor polynomial to process all received message bits including the crc but excluding the start bit. if the transmission is received correctly, at the completion of the message reception, the remainder polynomial will be: x 7 +x 6 +x 2 (0b11000100 or 0xc4). this crc code will detect all single and 2 bit errors and all 8 bit burst errors (i.e., any number of errors within a single 8-bit span). severe noise will normally be detected separately as a bit timing error. table 15-2. digital filter output count output 00 1 ? 14 unchanged 15 1 15-10 mpc565/mpc566 reference manual motorola logic description 15.5.2.11 arbitration the j1850 bus is classified as a carrier sense multiple access with collision resolution (csma/cr). this type of bus operates by arbitrating ownership of the network on a bit-by-bit basis. the major advantage of csma/cr is that no message is lost in a collision. if a node determines that it needs to send a message while another message is in progress, it must wait until the link is idle. when one node begins to transmit (after bus idle), all nodes desiring to transmit are obligated to begin their transmission at the same time. the rule of arbitration is that any node that transmits a 1-bit when another node transmits a 0-bit stops transmitting on the bus immediately. this is called a 0 dominant bus. to prevent noise from corrupting the bus, arbitration is also lost if a 1-bit is detected when a 0-bit was transmitted. all nodes are obligated to receive all bits of every message on the bus, even while transmitting. arbitration continues to the end of a message, if necessary. if an opposite bit is detected, transmission is immediately stopped unless it occurs on the 8th bit of a byte. in this case the dlcmd2 will automatically append two extra 1-bits and then stop transmitting. note two extra bits must be transmitted due to the fact that the eighth bit of a byte is an active, high level on the j1850 bus. therefore the first extra bit will be a passive, low level, and one more bit is needed in the active, high level so that after the falling edge of this bit the bus will be in the passive state. these two extra bits will be arbitrated normally and thus will not interfere with another message. 15.5.2.12 timebase generation the generation of time intervals within the dlcmd2 module takes into account the variations of mcu family, oscillator frequency, and physical interface delays that may occur. the frequency f imb3 is sent to the dlcmd2 where it is further divided by ?n? (set by the section 15.10.5, ?symbol timing control and pre-scaler register (sctl)?), such that the main dlcmd2 operating frequency (f dlc ) is approximately 2.00 mhz, depending on imb3 clock frequency. the dlcmd2 j1850 bit timings are derived from the f dlc time base and a stored table of vpw symbol values. the table of vpw symbol values is generated via the section 15.10.6, ?symbol timing data register (sdata)?. note the f dlc signal defines the fundamental resolution of the dlcmd2 module. all bit timings within the dlcmd2 are based upon integer multiples of the fundamental resolution. motorola chapter 15. data link controller module (dlcmd2) 15-11 logic description should a physical interface exhibit an unusually large delay, the length of the j1850 transmit symbol values stored in the dlcmd2 symbol table may be reduced proportionally to compensate. the vpw symbol length table is determined after the symbol lengths have been set via the transceiver rext bias resistor selection. the rext resistor values are chosen so as to minimize the radio frequency interference (rfi) from the j1850 bus by inputting a 10.4-khz square wave into the transmitter and subsequently out on the j1850 bus. these biasing resistors will affect the length of the vpw symbols to some degree due to their effect on the corners of the bus signal that is output by the transmitter. 15.5.2.13 receive and transmit message buffers the rxfifo and txfifo are 20 and 11 bytes in length respectively, to allow buffering of a complete message. the txfifo must be able to differentiate between three types of data: 1. message data byte 2. first byte in message 3. last byte in message the auto retry feature recirculates the bytes of a message in the txfifo until the message is successfully sent, at which time the fifo?s contents are flushed. when auto retry is disabled, the fifo will complete an in progress transmission, if any, and then flush the contents of the fifo. if the node is not transmitting, the fifo will be flushed immediately. if the auto retry feature is disabled as a message is being loaded into the dlcmd2, the dlcmd2 will try to transmit the message once and then clear the transmit fifo. received bytes will be placed into the rxfifo as soon as they are completely received off the bus. when an eod has occurred on the bus, a completion code will be inserted into the rxfifo after the last received byte of the message. the crc byte will be checked by the logic and discarded. 15.5.2.14 bus waveforms generation the dlcmd2 supports huntzicker encoding. each symbol generated by the dlcmd2 will be synchronized with the latest edge seen on the bus. errors due to oscillator tolerance and ground offsets will not accumulate through the message in this manner. synchronizing in this manner does require that the bit timing unit account for all known delays. the transmit timing will have a very narrow window due to oscillator tolerance and variation in the known delay. the receive timing will have a much wider window due to the uncertainty in determining edge position resulting from ground offsets, oscillator tolerance, and delay time variation. in either case, transmit or receive, the timing will be specified as beginning 15-12 mpc565/mpc566 reference manual motorola logic description when the dlcmd2 senses a transition and ending when the dlcmd2 causes or senses the next transition. 15.5.2.15 huntzicker encoding the information contained in this section describes the bit timing section of the logic on the dlcmd2. the timing of vpw (huntzicker) waveforms requires knowledge of the fixed delays in the transceiver and the logic section. the j1850 bus is a single wire ground referenced bus. this configuration has two important consequences for the bit timing section. in order to reduce the radiated emissions of the bus, each edge must be slew rate limited, and have its corners shaped. to not adversely affect the corner shaping, the specification must not place limits that force the corners. the other consequence is due to the ground offset requirement for the bus. this requirement dictates a minimal voltage swing necessary to operate in the presence of ground offset. the combination of the two factors gives rise to an uncertainty in both when the receiver (of a receiving node) detects a given transition, and when the transmitter (through its own receiver) detects the same transition. vpw encoding defines one edge for each symbol. a symbol is composed of a period of time (at a particular state of the bus) and the edge that follows that period. the point of reference for the time period is the trip point that the receiver uses to recognize the preceding transition on the bus. three independent variables are used to describe the waveform generated. these are the times from the trip point to each of the following transition threshold levels, and the time between these threshold levels. the corners of the waveform fall outside of the ?slew rate? time requirement, and may bargain for time and voltage more freely. the following symbol limits are consistent with t t,max = 16 s and an oscillator tolerance of 2%. t nom is the nominal symbol time with no oscillator error and the receiver detecting the transition at t t,max/2 .t r1 to t r2 is the required acceptance range while t r1typ to t r2typ is a typical acceptance range with a 2% guard band plus a small margin. t r1typ to t r2typ in table 15-3 represent the receiver windows. t x1 and t x2 in table 15-4 represent transmitter windows consistent with a 2% oscillator tolerance and 3 s for all other variations in the transmit path. motorola chapter 15. data link controller module (dlcmd2) 15-13 logic description the symbol waveforms seen on the bus have two important characteristics: each transition of the transmitted bus signal, as initiated by cl2tx (loti), is slew rate limited and has its corners rounded (wave shaped) so that the nominal rise or fall time is about 16 s to reduce the radiated emissions of the bus. this wave shaping is disabled when 4x mode is enabled. the received bus signal needs only a minimal voltage swing around the receiver?s nominal trip point voltage for proper detection. the point of reference for the time period is the trip point voltage (v t ) a receiver uses to recognize a transition on the bus and produce the cl2rx (lito) signal. the cl2rx signal is digitally filtered with an approximate 8 s delay at the 10.4-khz bus rate (2 s in 4x mode). since a high or low level input to the filter must last longer than the filter delay time in order to appear at the filter output, noise pulses shorter than this are eliminated. when a single node is transmitting, the symbol time period between successive transitions is controlled completely by the transmitter?s transmit symbol timing logic. when two or more nodes are contending for the bus the start point for an active to passive state transition is determined by the node with the slowest clock rate and the start point for an inactive to table 15-3. receive windows symbol 1, 2, 3 1 all waveforms less than 8 15-14 mpc565/mpc566 reference manual motorola logic description active state transition is determined by the node with the fastest clock rate, assuming that both nodes are transmitting the same symbol. the symbol width as controlled by the transmitting node?s cl2tx signal, can range from t xmin to t xmax . the receiver?s acceptance time window range (t rmin to t rmax ) is much broader to allow all widths to be classified into defined symbols. 15.5.3 tdata link controller module (dlcmd2) the time windows are not affected by multiple nodes trying to transmit at the same time during arbitration. this is because one node effectively dominates each transition (the first node to leave the passive state or the last node to leave the active state). although the fastest or slowest node dominates a particular transition, the arbitration scheme assures that the highest priority message always wins. j1850 bus transmitter output and input signal waveforms are shown in figure 15-3. motorola chapter 15. data link controller module (dlcmd2) 15-15 signals overview figure 15-3. vpw signal waveforms 1. t xmax is maximum symbol transmission time. 2. t xnom is nominal symbol transmission time. 3. t xmin is minimum symbol transmission time. 4. t rmax is maximum symbol receive window time. 5. t rnom is nominal symbol receive window time. 6. t rmin is minimum symbol receive window time. 7. v oh max is maximum logic high output voltage 8. v oh min is minimum logic high output voltage. 9. v ol max is maximum logical low output voltage. 10. v il max is maximum logic low input voltage. 11. v ih max is maximum logic high input voltage. 12. v ih min is minimum logic high input voltage. 15.6 signals overview this section provides an overview of dlcmd2 signals. 15.6.1 j1850 bus waveforms the dlcmd2 module must be able to generate and recognize the set of huntzicker waveforms described in the following sections. see figure 15-4. additionally: t x max t x nom t x min volts v ol max v ssa 90% 90% loti t t 10% 10% transmitter output receiver input t x min t x nom t x max v oh max v oh min volts t r max t r nom t r min 90% lito t r max t r nom t r min v ih max v ih min v ssa 10% t t v il max v t 15-16 mpc565/mpc566 reference manual motorola signals overview each symbol is represented by the time between two consecutive transitions there is one transition per symbol and one symbol per transition there are both active and passive symbols that are used alternately a longer active symbol will dominate a shorter one a shorter passive symbol will dominate a longer one figure 15-4. huntzicker waveform message the following sections show the nominal time duration, in microseconds ( s), of the vpw message symbols generated by the dlcmd2 as they appear on the j1850 bus when operating at the normal bus speed. when the dlcmd2 is operating at the high bus speed all 4x symbol times are one fourth that shown, except for ?break?, which will be transmitted the same length in 1x or 4x mode. 15.6.1.1 start of frame (sof) this active symbol appears at the start of every message when a transmitter drives the bus high to start a message. figure 15-5. start of frame symbol 15.6.1.2 data bits each data bit is represented by the time between two consecutive transitions. there are both passive and active bit states that are used alternately. the ?0? bit is the dominant bit in arbitration. 15.6.1.3 ?0? bit the two dominant ?0? bit waveforms are: figure 15-6. passive ?0? and active ?0? msb message time on bus ifr time idle eof eod sof idle sof msb bit 6 bits 5 2 bit 1 lsb more bytes lsb crc eod nb ifr/crc note: waveform is not to scale. ?sof? active 200m s ?0? active 128m s or passive 64 m s motorola chapter 15. data link controller module (dlcmd2) 15-17 signals overview 15.6.1.4 ?1? bit the two ?1? bit waveforms are: figure 15-7. passive ?1? and active ?1? 15.6.1.5 end of data (eod) this passive symbol appears after the first crc byte only in the ?request in-frame data? message. it ends when the responding transmitter sends its normalization/format bit prior to the start of the first in-frame response byte. if no node responds, this passive symbol will stretchintoan?endofframe?symbol. figure 15-8. end of data symbol 15.6.1.6 normalization bit the normalization bit symbol duration is the same as an active ?1? or ?0? bit time. the format of this bit, whether it is a ?1? or ?0?,? can be selected by the normalization bit format select (nbfs) bit as defined in section 15.10.5, ?symbol timing control and pre-scaler register (sctl).? j1850 protocol encourages the use of a ?0? when the in-frame response (ifr) ends with a crc byte and a ?1? when the ifr does not end with a crc byte. 15.6.1.7 end of frame (eof) this passive symbol appears at the end of every message. it is at least 280 s long. if the bus remains passive until 320 s, the bus is idle and a transmitter may begin transmitting. if a transmitter desiring bus access detects a rising edge on the bus between 280 s and 320 s (due to clock mismatch between nodes) it may join in and arbitrate for the bus. figure 15-9. end of frame symbol ?1? passive 128m s active 64 m s or ?eod? passive 200s ?end of data? ?eof? passive 280m s ?end of frame? 15-18 mpc565/mpc566 reference manual motorola signals overview 15.6.1.8 break the active ?break? signal causes any other transmitting module to stop transmitting immediately because it loses arbitration. it is at least 239 s long. figure 15-10. break symbol controller module (dlcmd2) 15.6.2 general symbol transmission the j1850 transmitter will drive the bus to active state and expect that the external rc network will pull the bus back down to the passive state, which is relative since there may be a difference of base ground potential between j1850 nodes in the vehicle. the transmitter is responding to feedback from the receiver in order to know precisely when to switch the transmitter on or off. there is a set of basic transmit timing windows for transmitted symbols within the logic section of the dlcmd2 but if the receiver detects the state of the bus as changing early, the transmitter will also change to that level unless it had not intended to transmit that symbol whereby arbitration is lost and transmission will cease immediately. thus, all j1850 devices on the j1850 bus synchronize to each other?s clock and ground mismatches. remember that there is only one train of symbols appearing on the bus. the individual symbols are pulled high and released low by various transmitters but the end result is one waveform. it just may be seen differently by the devices due to clock, ground, and power supply variations. 15.6.3 general symbol reception an external transceiver passes unfiltered bus status information to the dlcmd2?s rx pin. internal to the dlcmd2, the digital 1 or 0 is clocked through a digital delay filter for 16 ticks of its internal frequency clock (a delay of 8 s at normal (2 mhz f dlc ) speed before the filter output changes state. high and low levels on the j1850 bus are timed in the logic section and compared to a set of received symbol threshold windows. every received high or low level is translated into one of the symbols in the above sections or is flagged as a bit timing error. the bus is ?idle? when the output of the dlcmd2?s digital filter has been in the passive state for 320 s. 15.6.4 support for external transceiver as shown in figure 15-11, the dlcmd2 will be designed to use an external (ic) transceiver. ?break? ?break signal? 239m s active motorola chapter 15. data link controller module (dlcmd2) 15-19 operating modes figure 15-11. support for external transceiver 15.7 operating modes this section describes dlcmd2 operating modes. the dlcmd2 has five main modes of operation which interact with the power supplies, pins, and the rest of the mcu. refer to figure 15-12. cpu core dlcmd2 imb3 transceiver cl2tx cl2rx bus load 15-20 mpc565/mpc566 reference manual motorola operating modes figure 15-12. dlcmd2 operation modes 15.7.1 power off this mode is entered from the reset mode whenever the dlcmd2 supply voltage v dd drops below its minimum specified value for the dlcmd2 to guarantee operation. this implies that the dlcmd2 must be placed in the reset mode before being powered down. in this mode, the pin input and output specifications are not guaranteed. 15.7.2 reset this mode is entered from the power off mode whenever the dlcmd2 supply voltage v dd rises above its minimum specified value and imstrstb is asserted. this implies that imstrstb must be asserted while powering up the dlcmd2 or an unknown state will ifreezeb asserted and (frze[1] || frze[0]) in mcr is set or soft_frz bit in mcr asserted and (frze[1] || frze[0]) in mcr is set stop bit in mcr set stop bit in mcr clear or bus activity and dsae bit clear in mcr debug run ifreezeb deasserted and soft_frz bit in mcr clear or frze[1:0] in mcr clear power off reset vd d v dd(min) v dd v dd(min) imstrstb asserted imstrstb deasserted imstrstb asserted (from any mode) stop motorola chapter 15. data link controller module (dlcmd2) 15-21 operating modes be entered and correct operation cannot be guaranteed. it is also entered from any other mode on the falling edge of clock after imsrstb is asserted. in this mode v dd is supplied to the internal circuits, which are held in their reset state and the internal dlcmd2 system clock is running. registers will assume their reset condition. outputs are held in their programmed reset state, inputs and network activity are ignored. 15.7.3 run this mode is entered from the debug mode after all mcu reset sources are no longer asserted. it is entered from the dlcmd2 stop mode whenever a message is successfully received or the cpu has accessed the dlcmd2 and negated the stop bit (if previously set). it is entered from the dlcmd2 lpstop mode whenever network activity is sensed although messages will not be received properly until the clocks have stabilized and the cpuisalsointherunmode. in this mode, normal network operation takes place. the user should ensure that all dlcmd2 transmissions have ceased before exiting this mode. 15.7.4 dlcmd2 stop and lpstop 15.7.4.1 dlcmd2 stop mode this mode is automatically entered from the run mode whenever the cpu executes a stop instruction. the imb3 clocks continue to run, but the cpu clock is stopped. in this mode, the dlcmd2 internal clocks continue to run and the module will await a valid network message. if a valid network message is successfully received, a cpu interrupt request will be generated (if interrupts are enabled). dlcmd2 power is only conserved in this mode if the stop bit in the mcr is set, stopping the dlcmd2 clocks. 15.7.4.2 dlcmd2 lpstop mode this power conserving mode is automatically entered from the run mode whenever the cpu executes a lpstop instruction. in this mode, the dlcmd2 internal clocks are stopped and the module will await any j1850 activity (including noise). if network activity is sensed, then a cpu interrupt request will be generated, restarting both the imb and dlcmd2 internal clocks. 15-22 mpc565/mpc566 reference manual motorola operating modes 15.7.5 dlcmd2 debug this is a special debug mode entered by asserting the soft_frz bit in the mcr register, or by asserting imb3 ifreezeb line. for either case, activating the dlcmd2 debug mode is qualified by the frze[1:0] in mcr register. upon exiting the reset state the soft_frz bit and frze[ 1:0] bits are set in the mcr register. hence, reset mode is always followed by the debug mode. once this mode is set, the following occurs: the pre-scaler divider is stopped, thus halting all related activities. any activity on the j1850 bus will be ignored. the dlcmd2 ignores the cl2rx input pin and drives cl2tx to the passive state. the cpu can read and write into most of dlcmd2 registers except for otherwise noted in the register description section. the not_rdy and freez_ack bits in mcr register are set. after asserting the debug mode configuration bits, the freez_ack bit will be set in mcr register, before executing any other action to the dlcmd2; otherwise the dlcmd2 may operate in an unpredictable way. exiting the debug mode is done in one of the following ways: both, imb3 freeze and soft_frz bits are negated. cpu negates the frze bit. once debug mode is exited, the dlcmd2 is ready to transmit/receive normally on the j1850 bus. motorola chapter 15. data link controller module (dlcmd2) 15-23 operating modes figure 15-13. stop power mode (no stop bit set) figure 15-14. debug power mode (ifeezeb or soft_frz) dlcmd2 clock j1850 bus stop stop bit lpstop imb clocks irq dlcmd2 clock j1850 bus freeze_ack ifreeze lpstop imb clocks irq or soft_frz 15-24 mpc565/mpc566 reference manual motorola operating modes figure 15-15. stop power mode (stop bit set) figure 15-16. lpstop power mode dlcmd2 clock j1850 bus stop stop bit lpstop imb clocks irq dlcmd2 clock j1850 bus stop stop bit lpstop imb clocks clocks begin to restart (c2 message(s) lost) irq don't care motorola chapter 15. data link controller module (dlcmd2) 15-25 cpu interface 15.8 cpu interface this section covers dlcmd2 interfaces to the cpu. 15.8.1 parallel interface requirements this section defines the de-multiplexed parallel interface protocol used. the logical operations done in a dlcmd2 module service routine are as follows: 1. read status byte from dlcmd2 module 2. read received data from dlcmd2 module if required 3. write command byte to dlcmd2 module if required 4. write transmit data to dlcmd2 module these four bytes are a complete exchange of information. however, these bytes are not all necessary or required during a cpu/dlcmd2 data link controller module (dlcmd2) module transfer. all possible unique cpu/dlcmd2 module transfers are shown in table 15-5. all cpu/dlcmd2 module transfers will be made up of combinations of one or more of these building blocks. pop and push refer to automatic (without command byte) flushing and loading of data bytes out of and into the dlcmd2 module. a transmit data byte need not immediately follow the command. the transmit data byte must be the next byte transferred to the dlcmd2 but could be sent any time later. the command will not be acted upon until this next byte is sent to the dlcmd2. table 15-5. cpu/dlcmd2 transfers acceptable read/write combinations auto pop? auto push? first byte flag set? word read/write allowed? 1. read status byte from dlcmd2 1 no no no no 2. write command byte to dlcmd2 ? no no yes write transmit or dummy data to dlcmd2 module ? no maybe yes if no data accompanies, then command byte causes no action ?? ? ? 3. read status byte from dlcmd2 no ? ? yes read received data byte from dlcmd2 yes ? ? yes read status byte from dlcmd2 no ? ? yes read received data byte from dlcmd2 yes ? ? ? (until entire message received) ? ? ? ? 4.writetransmitdatabytetodlcmd2 ? yes 2 yes no write transmit data byte to dlcmd2 ? yes no no 15-26 mpc565/mpc566 reference manual motorola operational information in numbers 2-4, word reads and writes may be done to read a status byte and a received data byte, or write a command byte and a transmit data byte with one instruction. if number 2 was for loading a single byte for transmit the command byte would specify load as first and last byte (no auto push, no first byte flag set). number 3 would be for reading an entire message from the dlcmd2 module when there is no transmit data to be sent to the dlcmd2 module. number 4 is a quick way to load an entire message into the dlcmd2 module when there is no data to read from the dlcmd2 module. auto pop is the default for reading from the rxfifo. this means that a read of a data byte from the rxfifo causes the current byte in the fifo to be automatically flushed. auto pop cannot be disabled. auto push is the automatic loading of a data byte into the txfifo via a write to the dlcmd2 module. this is the default when there was no preceding command byte. there is no auto push if a command byte is sent before the data byte; and the command byte must specify what to do with the following data byte. the action(s) called out in the command byte will be acted upon the moment the transmit (or dummy) data byte is written into the dlcmd2 module. 15.8.2 reset operation when master reset is asserted, the dlcmd2 module will be held in an off state. system power should be up and stable when master reset is negated. after toggling the reset line, the cpu writes command and any configuration bits (via mcr) into the dlcmd2 module to initialize it. 15.9 operational information the following sections will be included in the dlcmd2 application document and are mostly redundant information to previous sections. write command byte to dlcmd2 (load as last byte) ? no no yes write transmit data to dlcmd2 (last byte) ? no no yes 1 minimal transfer 2 if txfifo empty table 15-5. cpu/dlcmd2 transfers (continued) acceptable read/write combinations auto pop? auto push? first byte flag set? word read/write allowed? motorola chapter 15. data link controller module (dlcmd2) 15-27 operational information 15.9.1 initialization after power up and/or reset the dlcmd2 should be configured via writes to the mcr, ilr, ivr, sdata, and sctl registers. note interrupts are disabled at power up and reset and must be enabled if a polled method of servicing the dlcmd2 is not used. 15.9.1.1 step 1 ? initialize mcr begin initialization of the configuration bits by writing the supv bit in the mcr. this will determine what types of accesses are to be allowed (user and supervisor or just supervisor) to dlcmd2 registers for the rest of the initialization process and during normal operation. care should be taken not to clear the soft_frz or frz[1:0] bits while writing the supv bit. this precaution will ensure the dlcmd2 remains in the debug mode until initialization is complete. 15.9.1.2 step 2 ? initialize ilr and ivr registers if interrupts employed 15.9.1.3 step 3 ? initialize sctl and sdata registers 15.9.1.4 step 4 ? enable dlcmd2 by exiting debug mode 15.9.2 transmitting a message the dlcmd2 is loaded with a message from the cpu for transmission. the dlcmd2 will then add a sof bit to the outgoing data, and contend for a message slot on the j1850 bus. the txfifo in the dlcmd2 is 11 bytes long, to allow complete (except block) messages to be transferred to the dlcmd2 by the cpu for transmission. information about which byte the cpu is transferring is sent to the dlcmd2 as part of the control information sent with each byte transferred and is optional with the dlcmd2 except for the last byte. when the dlcmd2 has transmitted all of the message bytes, it will automatically append a crc to the end of the outgoing message. the dlcmd2 will automatically retry a transmission if it lost arbitration or any errors were detected. the auto retry feature causes the dlcmd2 to indicate that the txfifo is full until the message is successfully sent except where no last byte was indicated. as soon as the cpu transfers a ?last byte? of a message to the dlcmd2, or fills the eleventh position of the txfifo, the dlcmd2 will indicate that the txfifo is full. in the case of filling the txfifo with no ?last byte? indicated (block mode) the status will say ?txfifo almost full? after a byte has been sent so that the next byte of the block message can be loaded by the cpu. once successfully sent, the dlcmd2 will indicate that the txfifo is empty and 15-28 mpc565/mpc566 reference manual motorola operational information hence ready for the next message. each time the message loses arbitration, the completion code for that received message will indicate to the transmitter that it attempted transmission, and lost arbitration. the auto retry feature can be terminated by the cpu through the command byte. this causes the dlcmd2 to finish its current transmit activity, and then clear the txfifo. if there had not been any transmit activity when the auto retry is disabled, the dlcmd2 will attempt to transmit the message once and then clear the txfifo. a break waveform on the bus is shaped such that it will win arbitration against any currently transmitting message. when the dlcmd2 senses that such a waveform has occurred on the bus, it will stop transmitting its current message, reset its transmitter (clear the txfifo), and set a bit in the completion code and assert an interrupt to indicate to the cpu that such a condition has occurred. since the break signal wins arbitration all of the time, any in progress messages will have simply lost arbitration, and the dlcmd2 will treat the in progress received message as complete. if a break occurs while there are no in progress messages, a completion code indicating that a break has occurred will be placed in the rxfifo and a cpu interrupt is generated. the break/reset waveform is sent by a dlcmd2 by setting a bit combination in the command byte. this waveform is sent immediately upon the command byte being latched in. if there is a current transmission, it will be stopped, and the break waveform sent. break automatically takes all nodes on the network out of 4x speed mode. note an sof from a node in regular mode will be seen as a break by any nodes in 4x mode. 15.9.3 receiving a message the status byte that the cpu reads from the dlcmd2 contains information on the status of the rxfifo, the status of the txfifo, the condition of the bus, and the type of accompanying data byte. the data accompanying the status byte can be data received off of the j1850 bus, a completion code which contains information about a received message, or nothing. all messages received off the j1850 bus will have their start bit removed and error detection code replaced with a completion code. all other bytes of the message are placed in order, msb first, in the rxfifo. receiving information off the j1850 bus occurs in much the same manner as sending data. note by definition, every message a dlcmd2 sends on the data link is also received by its own receiver as if the transmission had been initiated by a different node. motorola chapter 15. data link controller module (dlcmd2) 15-29 operational information the dlcmd2 will automatically remove the sof bit from the message, and check the crc for errors. if a crc error occurs, it is flagged in the message completion information (completion code) that takes the place of the crc byte in the rxfifo. the dlcmd2 will interrupt the cpu to signal that a complete message has been received, or when the rxfifo is approaching full. when the cpu starts the transfer process, the status byte from the dlcmd2 indicates the data?s presence, and something about the amount of data left in the rxfifo. conditions necessary for interrupting the cpu are selectable with a write to the interrupt level register (ilr). when a dlcmd2 loses arbitration to another node, it will continue to receive the remainder of the message. the completion code will indicate that the dlcmd2 contended for a transmit slot, and lost arbitration to the received message. the cpu does not need to resend the message if the auto retry feature is enabled. 15.9.4 receiving a message in block mode although not a part of the sae j1850 protocol, the dlcmd2 does allow for a special ?block mode? of operation for the receiver. as far as the dlcmd2 is concerned, a block mode message is simply a long j1850 frame that contains an indefinite number of data bytes. all of the other features of the frame remain the same, including the sof, crc, and eod symbols. data link controller module (dlcmd2) class 2 convention requires that another node wishing to send a block mode transmission must first inform all other nodes on the network that this is about to happen. this is usually accomplished by sending a special predefined message. block mode may be combined with 4x mode. 15.9.5 transmitting a message in block mode if the txfifo was filled with no last byte indicated, the dlcmd2 will start sending that message in terminate auto-retry mode; the status will indicate ?txfifo almost full? as soon as the first byte is sent, and ?txfifo contains some data bytes? as soon as the second byte is sent. as new data is written to the txfifo, the status will accurately reflect the condition of the txfifo until a ?last byte? is written. when a ?last byte? command has been sent to the dlcmd2, the txfifo will indicate ?txfifo full? until the transmission is finished. the dlcmd2 will send an infinite length message if properly handled by the cpu. block mode transmit may be combined with 4x mode. 15.9.6 receiving a message in 4x mode although not a part of the sae j1850 protocol, the dlcmd2 does allow for a special ?4x mode? of receive operation. 4x mode is entered in software by setting the 4x bit in the 15-30 mpc565/mpc566 reference manual motorola programming model mcr register. this bit is cleared automatically by a break symbol reception, or may be manually cleared in software. 15.9.7 transmitting a message in 4x mode if the 4x mode bit is set in the mcr register, the dlcmd2 will use a different set of vpw timing numbers to set the widths of the j1850 bus symbols when transmitting. this bit is cleared automatically by a break symbol reception, or it may be cleared manually. 15.10programming model the following section provides register descriptions for the dlcmd2. in the following paragraphs, the top line lists the bit number in the register. the second line contains the mnemonic for the bit. the values shown under the mnemonic are the values of those register bits after imstrstb is asserted. if isysrstb affects the bits differently than imstrstb, this fact is discussed in the paragraphs following the chart. the dlcmd2 registers hold, in some cases, bit locations marked as ?reserved?. these bits will always read as logic ?0? and writes to these bits are ignored. the register decode map is fixed and begins at the first address of the module base address. table 15-6 shows the registers associated with the dlcmd2 module and their relative offset from the base address. four of the registers are in supervisor-only data space and the remainder are in assignable data space. table 15-6. dlcmd2 memory map access offset 0 15 r/w reset s 0x30 0080 module configuration register (mcr) r/w 0x6780 s 0x30 0082 reserved ? ? s 0x30 0084 interrupt pending register (ipr) r/w 0x0000 s 0x30 0086/ 0x30 0087 interrupt level register (ilr) interrupt vector register (ivr) r/w , ro (bit2~bit0) 0x000f s/u 0x30 0088 symbol timing control and pre-scaler register (sctl) r/w 0x0000 s/u 0x30 008a symbol timing data register (sdata) wo 0x00xx s/u 0x30 008c/ 0x30 008d command register (cmd) transmit data register (tdata) r/w -wo for (tdata) 0x00xx s/u 0x30 008e/ 0x30 008f status register (stat) receive data register (rdata) ro 0x00xx motorola chapter 15. data link controller module (dlcmd2) 15-31 programming model 15.10.1module configuration register (mcr) . msb 0 1234567891011121314lsb 15 stop fr[1:0] dsae 4xmd soft not_ free supv reserved stop reserved reset: 0 0011110000000 figure 15-17. mcr? module configuration register 0x30 0080 table 15-7. mcr bit descriptions bit(s) name description 0 stop stop system clock ? the stop bit, if asserted, will stop the system clock within the dlcmd2 module except for the imb bus interface (biu). the module?s biu must continue to operate to allow the cpu access to the module?s registers (except for lpstop). the system clock is stopped on the low phase of iclock. once the bus becomes idle, the system clock will remain stopped until the stop bit is negated by the cpu, or a reset occurs, or an edge from the j1850 bus passes through the digital filter (if dsae not set). 1:2 fr[1:0] freeze ? there exists two bits in the dlcmd2 module control register to determine the action to be taken when the freeze signal of the imb is asserted. table 15-8 defines the freeze bit field. 3 dsae disable stop mode automatic exit ? when asserted, the dsae bit will prevent j1850 activity from causing the dlcmd2 to exit stop mode, and will prevent intacl2-type interrupts from being asserted. (when dsae is negated, the dlcmd2 will automatically restart its internal clocks from stop mode upon sensing any j1850 activity, and intacl2-type interrupts will be allowed (although they must still be explicitly enabled by intacl2e).) the cpu must negate the stop bit to exit dlcmd2 stop mode and restart the dlcmd2 clocks, since j1850 activity will not take the dlcmd2 out of stop mode. when cleared, any j1850 activity that passes through the digital filter will take the dlcmd2 out of stop mode and clear the stop bit (if set). 4 4xmd 4x mode ? when the 4xmd bit is asserted, the dlcmd2 will use 4x mode bit timings rather than the normal j1850 symbol timings. note that normal waveshaping by the analog transceiver (whether on-chip or off-chip) must be disabled for the dlcmd2/transceiver combination to transmit properly in 4x mode. this bit is automatically reset upon receipt of a break symbol. 5 soft_frz software freeze ? assertion of this bit has the same effect as the assertion of the ifreezeb signal on the imb3, as described in the description of ifreezeb/soft_frz mode and frze bits. however, it does not require that the ifreezbe signal be asserted in order to enter debug mode. this bit is initialized to 1 (debug mode).the cpu clears it after initializing the control registers. no transmissions or receptions are performed by the dlcmd2 before this bit is cleared. for detailed description of the debug mode, refer to section 15.7.5, ?dlcmd2 debug. 0 no dlcmd2 internal request to enter debug mode. 1 enter debug mode if (frze[ 1] || frze[ 0]) 6 not_rdy not_rdy ? this bit indicates that the dlcmd2 is either in stop or in debug states. this bit is read-only. whenever one of these two modes is asserted, this bit is set once the dlcmd2 has entered the corresponding mode. it is negated once the dlcmd2 has exited these modes. for more details refer to section 15.7.4, ?dlcmd2 stop and lpstop? and lpstop and section 15.7.5, ?dlcmd2 debug.? 15-32 mpc565/mpc566 reference manual motorola programming model read restrictions: supervisor only, bits[9:10] are reserved but can be read as zeros. write restrictions: supervisor only, bits[9:10] are reserved. 7 freez_ack dlcmd2 disabled ? dlcmd2 is in debug mode and its pre-scaler is stopped. this bit is read-only. the value of this bit is one when the dlcmd2?s pre-scaler is stopped, and 0 when debug mode is negated and the pre-scaler is running again. when the dlcmd2 enters debug mode it sets the freez_ack bit. the cpu can poll this bit to know if the dlcmd2 entered debug mode. if debug mode is negated then this bit is negated once the dlcmd2?s pre-scaler is running. 8 supv supervisor/user data space ? the supv bit affects the sctl/sdata, cmd/tdata and stat/rdata registers, the only registers in the dlcmd2 currently defined as supervisor/unrestricted access. if supv is asserted (all dlcmd2 registers are to be treated as supervisor only) bit 2 of the function code (fc2) must be asserted during module address decoding to allow the supervisor/unrestricted access registers to respond to accesses in supervisor data space. if the supv bit is cleared (sctl/sdata, cmd/tdata and stat/rdata accesses are to be treated as unrestricted) fc2 is ignored during module address decoding, allowing supervisor/unrestricted access registers to respond to accesses in supervisor data or user data space. 9:10 ? reserved 11 stop_ack dlcmd2 is stopped ? dlcmd2 is in stop mode and its main clocks are stopped. this bit is read-only. the value of this bit is ?1? when the dlcmd2 enters stop mode and its clocks are stopped, (see section 15.7.4, ?dlcmd2 stop and lpstop?) and ?0? when stop mode is negated and the dlcmd2?s clocks are running again. when the dlcmd2 enters stop mode and shuts its clocks off, it sets the stop_ack bit. the cpu can poll this bit to know if the dlcmd2 entered stop mode (e.g., stopped its clocks). if stop mode bit is negated, then this bit is negated once the dlcmd2?s clocks are running. 12:15 ? reserved. these bits are used for the iarb (interrupt arbitration id) field in dlcmd2 implementations that use hardware interrupt arbitration. table 15-8. freeze bit field description frz[1] frz[0] result 0 0 ignore freeze 0 1 freeze on dlcmd2 internal f dlc high state. (ctwo is in high state when ifreezeb is asserted, or f dlc enters its high state sometime after ifreezeb is asserted.) 1 0 freeze on receipt of next bit. (dlcmd2 internal rit signal is asserted ifreezeb is asserted, or rbit becomes asserted sometime after ifreezeb is asserted.) 1 1 freeze immediately table 15-7. mcr bit descriptions (continued) bit(s) name description motorola chapter 15. data link controller module (dlcmd2) 15-33 programming model 15.10.2interrupt pending register (ipr) .. read restrictions: supervisor only, bit [15:5] are reserved but can be read as zeros. write restrictions: supervisor only, bit [15:5] are reserved. figure 15-19. interrupt request logic path msb 0 1234567891011121314lsb 15 reserved ipr4 ipr3 ipr2 ipr1 ipr0 reset: 0 000000000000000 figure 15-18. ipr ? interrupt pending register0x30 0084 table 15-9. interrupt pending register (ipr) bit descriptions bit(s) name description 0:10 ? reserved. 11:15 ipr[0:4] interrupt pending. indicates that an interrupt service request has been made by the module interrupt logic. an interrupt request to the imb3 is generated whenever the interrupt asserting condition is met. a bit in the ip register (indicating the application logic interrupt request is detected) can be set in any order to generate the imb3 interrupt request. once set, the ip bits remain set until the ip bit is cleared by software, or reset. to clear an ip bit, the bit must be first read as a 1 and then the bit must be written to a 0. ip bits which are 0 when the ip register is read are unaffected by the write operation. also, if the ip logic detects another application logic interrupt request after the ip bit was read as a 1 and before a 0 is written to clear it, the ip bit cannot be cleared until the ip bit is again read as a 1 and then written to a 0. bits in this register are set by the application logic request and cannot be written to a one by software (writing 1 to the ip register have no effect). only writes of 0 are valid, when permitted, to clear the ip bit(s). ipr[0] : r1stbyte interrupt pending sets ipr[0]. ipr[1] : rccode interrupt pending sets ipr[1]. ipr[2] : r13byte interrupt pending sets ipr[2]. ipr[3] : thlfmty interrupt pending sets ipr[3]. ipr[4] : acl2 interrupt pending sets ipr[4]. dff interrupt pending state machine ip_q[i] int_req[i] intreq[i] to priority encoder 2 d-ffs per ip bit (application interrupt request) ip_read din[i] ip_write clock ip_d[i] dout[i] 15-34 mpc565/mpc566 reference manual motorola programming model 15.10.3interrupt level register (ilr) read restrictions: supervisor only, bit[2] is reserved but can be read as zero. write restrictions: supervisor only, bit[2] is reserved. msb 0 123456lsb 7 intmode intacl2e reserved ilbs[1:0] ilr[2:0] reset: 0 0000000 figure 15-20. ilr ? interrupt level register r0x39 0086 table 15-10. interrupt level register (ilr) bit descriptions bit(s) name description 0 intmode interrupt mode ? when the intmode bit is asserted, the dlcmd2 will assert an interrupt when a single byte is received into an empty rxfifo. when cleared, only standard interrupts are enabled. table 15-11 defines interrupt levels. 1 intac l2e interrupt any bus activity enable ? when the intacl2e bit is set, the dlcmd2 will assert an interrupt when any network activity (including noise) is detected. this bit must be set for the dlcmd2 to wake up the processor from lpstop. although the detected activity may be only noise, neither imb3 nor module clocks can run in lpstop, therefore the dlcmd2 cannot distinguish noise from valid network activity, and must wake up the processor to restart the clocks necessary for j1850 message reception. normally, this bit would be set by the cpu just before going into lpstop, and is cleared once the acl2 interrupt condition is latched. 2?reserved. 3:4 ilbs[1:0] interrupt level byte select ? these two bits indicate during which time slot the dlcmd2 should drive its interrupt. for more details, refer to section 15.7.4, ?dlcmd2 stop and lpstop? and section 15.7.5, ?dlcmd2 debug? for irq_plug=1. 5:7 ilr interrupt request level ? the interrupt request level field contains the priority level of the dlcmd2 interrupts for the cpu. level seven for this field indicates a nonmaskable interrupt, while level zero indicates that interrupts have been disabled. the interrupt request level field is initialized to zero during reset which prevents the module from generating an interrupt until this register has been initialized. note: level zero corresponds to irq[ 0] which is not recognized at the system level, hence the interrupts are treated as disabled. the interrupt request level field, therefore acts as master enable for the interrupts. table 15-11. interrupt levels ilbs [1:0] levels 00 0:7 01 8:15 10 16:23 11 24:31 motorola chapter 15. data link controller module (dlcmd2) 15-35 programming model 15.10.4interrupt vector register (ivr) read restrictions: supervisor only. write restrictions: supervisor only. 15.10.5symbol timing control and pre-scaler register (sctl) msb 0 123456 lsb 7 ivr[7:0] reset: 0000000 0 figure 15-21. ivr ? interrupt vector register 0x30 0087 table 15-12. interrupt vector register (ivr) bit descriptions bit(s) name description 0:7 ivr[7:0] interrupt vector field ? the interrupt vector register holds the offset into the exception vector table, and is what is driven by the dlcmd2 in response to an imb iack cycle. ivr[ 7:3] are programmable. ivr[ 2:0] are read-only bits and encoded from the highest priority of any currently active interrupt sources per table 15-12. the ivr is not used by the mpc565/mpc566. msb 0 1 2 34567891011121314lsb 15 reserve nbf rxpol reserved lck sel reserved ps[5:0] reset: 0 0 0 0000000000000 figure 15-22. sctl ? symbol timing control and pre-scaler register 0x30 0088 table 15-13. symbol timing control and pre-scaler bit descriptions bit(s) name description 0?reserved. 1 nbfs this bit controls the format of normalization bit (nb). sae j1850 strongly encourages the use of an active long, ?0?, for in-frame responses containing crc and active short, ?1?, for in-frame response without crc. once the lck is set, the writes to nbfs are disabled. 0 nbfs, nb that is received or transmitted is a ?1? when the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a ?0? when the response part of an in-frame response (ifr) does not end with a crc byte. 1 nbfs, nb that is received or transmitted is a ?0? when the response part of an in-frame response (ifr) ends with a crc byte. nb that is received or transmitted is a ?1? when the response part of an in-frame response (ifr) does not end with a crc byte. 15-36 mpc565/mpc566 reference manual motorola programming model read restrictions: supervisor/unrestricted access, bit[0], bits[3:5], bits[8:9] are reserved but can be read as zeroes. write restrictions: supervisor/unrestricted access, bit[0], bits[3:5], bits[8:9] are reserved. note ps[5:0] is always loaded with ?desired divisor? -1 and comes out of reset programmed for a divided by one clock rate (ps[5:0] = 0x00). 2 rxpol receive pin polarity (bit 13) ? the receive pin polarity bit is used to select the polarity of incoming signal on the receive pin. some external analog transceivers invert the receive signal from the j1850 bus before feeding back to the digital receive pin. once the lck is set, the writes to rxpol are disabled. 0 rxpol, select normal/true polarity; true non-inverted signal from j1850 bus, (i.e., the external transceiver does not invert the receive signal). 1 rxpol, select inverted polarity, where external transceiver inverts the receive signal. 3:5 ? reserved. 6 lck write lock on symbol timing parameter table (bit 9) ? lck disables writes to the symbol timing parameter table through sdata. once lck is set, only reset will clear the bit (unless in test mode). 0 lck, enables the writes to the symbol timing parameter table through sdata register. 1 lck, disables the writes to sel, nbfs, rxpol, ps5 -ps0 in sctl register and the symbol timing parameter table through sdata register. once lck is set, only reset will clear this bit (unless in test mode). 7 sel select normal or 4x bit-timing parameter table (bit 8) ? there are two sets of parameters used for dlmcd2 bit-timing. these two sets of parameters are accessible through the sdata register. there are twelve parameters for normal bit-timing (four for receiving and eight for transmitting) and twelve parameters for 4x bit-timing (four for receiving and eight for transmitting). these bits may be written only when lck is cleared. once the lck is set, the writes to sel are disabled and sel is cleared. 0 sel, allows access (write) to the normal mode parameters. 1 sel, allows access (write) to the 4x mode parameters. 8:9 ? reserved. 10:15 ps[5:0] dlcmd2 pre-scaler rate select (bit [5:0]) set the system clock divisor necessary to achieve the dlcmd2 internal bit-rate clock. the frequency should be as close to 2 mhz as possible. these bits may be written only when lck is cleared. once the lck is set, the writes to ps[5:0] are disabled. the value programmed into ps[5:0] bits is dependent on the chosen imb3 system clock frequency per table 15-14. table 15-14. dlcmd2 pre-scaler rate selection imb3 bus clock frequency ps[5:0] division f dlc f clock = 2.000 mhz 0x00 1 2.000 mhz f clock = 15.000 mhz 0x06 7 2.143 mhz table 15-13. symbol timing control and pre-scaler bit descriptions (continued) bit(s) name description motorola chapter 15. data link controller module (dlcmd2) 15-37 programming model 15.10.6symbol timing data register (sdata) refer to figure 15-24 for sdata symbol timing table access read restrictions: supervisor/unrestricted access, the entire register will be read as zeroes. write restrictions: supervisor/unrestricted access when lck in sctl register is clear. bit [0:4] are reserved. s10-s0 ? symbol timing data register controller module (dlcmd2) the parameter table lists the cycle counts for four receive symbols and eight transmit symbols in normal and 4x modes. the user must calculate the cycle counts for each symbol based on the desired value, round trip delay, digital filter delay, and bus frequency. the calculated cycle counts must be entered into the parameter table through the section 15.10.6, ?symbol timing data register (sdata).? to calculate the cycle count f clock = 16.000 mhz 0x07 8 2.0 mhz f clock = 25.000 mhz 0x0b 12 2.083 mhz f clock = 26.000 mhz 0x0c 13 2.0 mhz f clock = 40.000 mhz 0x13 20 2.0 mhz f clock = 45.000 mhz 0x15 22 2.045 mhz f clock = 56.000 mhz 0x1b 28 2.045 mhz f clock = 66.000 mhz 0x20 33 2.0 mhz f clock = 128.000 mhz 0x3f 64 2.0 mhz msb 0 1234567891011121314lsb 15 reserved sdata[10:0] reset: 000000 0 0 figure 15-23. sdata? symbol timing data register 0x30 008a table 15-15. symbol timing data register (sdata) bit descriptions bit(s) name description 0:4 ? reserved. 5:15 sdata symbol timing data register ? the bit-timing of j1850 symbols is written into the twenty-four entries of the parameter table through the sdata register. an internal pointer along with the sel bit is used to select which parameter is accessed (write) through the sdata register. this pointer is incremented when sdata is written and cleared when the sctl register is accessed. refer to figure 15-24 for a block diagram and table 15-16 for the parameter table. table 15-14. dlcmd2 pre-scaler rate selection (continued) imb3 bus clock frequency ps[5:0] division f dlc 15-38 mpc565/mpc566 reference manual motorola programming model for receive symbols, multiply f dlc by the desired symbol time (in s) and round to the nearest integer. to calculate the cycle count for transmit symbols, subtract the round trip delay for the transceiver from the desired symbol time (in s), multiply by f dlc , round to the nearest integer, and subtract the cycle count of the digital filter (16 cycles in normal mode, four cycles in 4x mode). as an example, let the transceiver round trip delay be 16 s, the desired symbol be 64 s, and f dlc be 2.083 mhz. the cycle count would be: cycle count = ((64 s ? 16 s) x 2.083 cycles / s) ? 16 cycles = 84 cycles after the cycle count has been computed, it must be converted into binary format and entered into the respective parameter through the section 15.10.6, ?symbol timing data register (sdata).? figure 15-24. dlcmd2 sdata block diagram table 15-16. timing parameter table programming sequence symbol description symbol (sel = 0) symbol timing (s) symbol (sel = 1) symbol timing 4x (s) 1 minimum receive symbol time rmin 34 rmin_4 8 2 maximum receive short pulse time rsh 96 rsh_4 24 3 maximum receive long pulse time rln 163 rln_4 41 4 minimum end-of-frame time reof 239 reof_4 60 5 target transmit short passive symbol time tshp 64 tshp_4 16 6 target transmit short active symbol time tsha 64 tsha_4 16 7 target transmit long passive symbol time tlnp 128 tlnp_4 32 8 target transmit long active symbol time tlna 128 tlna_4 32 sdata memory_array inc rst sdata_access iclock ptr sctl_access 4-bit pointer $0a 0 10 sel = 0 rmin rsh rln reof tshp tlnp tlna tsha tifr tifs tbrk tsof sel = 1 rmin_4 rsh_4 rln_4 reof_4 tshp_4 tlnp_4 tlna_4 tsha_4 tifr_4 tifs_4 tbrk_4 tsof_4 motorola chapter 15. data link controller module (dlcmd2) 15-39 programming model 15.10.7transmit command register (cmd) command and configuration of the dlcmd2 module is accomplished through a command byte that accompanies every data byte sent from the cpu to the dlcmd2 module. note the command byte is the first byte transferred to the dlcmd2 module, and must be followed by a byte (data or dummy) which causes the command to be acted on (this can be done in an aligned word write or two separate byte writes). read restrictions: reads will return 0x00. write restrictions: supervisor/unrestricted access. 9 target end-of-data time before ifr begins tifr 200 tifr_4 50 10 target transmit start-of-frame symbol time tsof 200 tsof_4 50 11 target inter-frame separation time before dlcmd2 is ready for new message tifs 320 tifs_4 80 12 target transmit break symbol time tbrk 800 tbrk_4 800 msb 0 123456lsb 7 cmd reset: 0 0000000 figure 15-25. cmd? transmit command register0x30 008c table 15-17. transmit command register (cmd) bit descriptions bit(s) name description 0:7 cmd transmit command register ? the command byte can be broken in three fields. bits 0:2 describe general commands. bits 3:5 describe the type and destination of the accompanying byte associated with the command. bits 6:7 control the receive fifo. refer to table 15-18 for general command descriptions. refer to table 15-19 for type and destination of accompanying byte descriptions. refer to table 15-20 for rxfifo command descriptions. table 15-16. timing parameter table (continued) programming sequence symbol description symbol (sel = 0) symbol timing (s) symbol (sel = 1) symbol timing 4x (s) 15-40 mpc565/mpc566 reference manual motorola programming model table 15-18. general commands cmd0 cmd1 cmd2 description 0 0 0 do nothing ? dlcmd2 will not perform any actions defined in this field. 0 0 1 reserved ? results in ?do nothing.? 0 1 0 send break signal ? when this command is latched in, the dlcmd2 will immediately send a break signal on the bus, regardless of its current transmit or receive status. 0 1 1 send on eod with crc (transmit single or multiple byte ifr with crc) 1. must be accompanied by a data byte that is flagged as ?1st byte? or ?1st and last? byte. the remaining ifr bytes may not be sent to the dlcmd2 with the ?send on eod? combination set. 2. this command causes the dlcmd2 to go into terminate auto retry (tar) mode automatically. it also causes a reset of the transmitter and txfifo before the response byte is loaded. if the dlcmd2 is transmitting and loses arbitration, an ifr can be loaded in response to the message winning arbitration. 3. if this command is latched in while the bus is idle or between eod and eof, the ifr command/data bytes will be ignored. if valid command/data bytes follow the invalid ifr command/data bytes, the dlcmd2 will attempt to transmit the bytes as a normal message once. 4. if a message is in progress and the eod symbol has not been detected when this command is latched in, the dlcmd2 will send the ifr if there were no receiver errors detected. if receiver errors were detected, the ifr will be lost and the dlcmd2 will not be in tar mode. 5. if the remaining ifr bytes, if any are required, are not placed into the txfifo before they are needed, then an underrun will occur. this will cause the crc to be inverted in the ifr. the second byte must be loaded before the falling edge of the normalization bit. the next ifr byte must be loaded before the last bit of the current byte is transmitted. since there is only one responder transmitting an ifr, the inverted crc will cause the dlcmd2 to corrupt its own message. other nodes will receive this as a crc error. 6. if this dlcmd2 is the one transmitting, send on eod will cause a bit timing or incomplete byte error and a reset of the txfifo. both the original message and the ifr will be lost. 7. cannot be sent in response to an ifr without crc. 1 0 0 terminate auto retry (tar) 1. if this command is latched in while there is not a complete message in the txfifo, then when that message is completely loaded the dlcmd2 will attempt to transmit that message only once. after this transmit attempt, the txfifo will be empty. 2. if this command is latched in while the dlc is transmitting, then the dlcmd2 will finish its transmit activity (successful transmission, or lose arbitration) and then clear the txfifo. 3. if a complete message is in the txfifo, but not yet transmitting when this command is latched in, and: a. the message has just lost arbitration and is waiting for the next slot for retransmission, the dlcmd2 will attempt transmission one more time. b. the message has not tried to transmit yet (loaded while a message was on the bus). the dlcmd2 will try to transmit once, and then reset the txfifo. c. if the txfifo is full, and there is no last byte indicated (message of more than 11 bytes), then an automatic tar is executed. 1 0 1 send on eod without crc (transmit single or multiple byte ifr w/o crc) 1. same as 0 1 1 but a crc will not be transmitted. 2. this response cannot be sent after a previous ifr without crc. motorola chapter 15. data link controller module (dlcmd2) 15-41 programming model 1 1 0 send on eod with auto re-try (transmit single byte ifr with auto re-try) 1. if a loss of arbitration occurs when the dlcmd2 attempts to transmit and after the ifr byte winning arbitration completes transmission, the dlcmd2 will again attempt to transmit. the dlcmd2 will continue transmission attempts until an error is detected on the bus. 2. the txfifo will not be empty until the message is successfully sent. 1 1 1 abort transmission now (reset transmitter) 1. this command causes the transmitter, including the txfifo to be reset immediately. if a message is in progress, it will be terminated immediately. 2. the first byte of a new message may accompany this command in the same 2-byte host-dlcmd2 transfer. table 15-19. type and destination of accompanying byte commands cmd3 cmd4 cmd5 description 0 0 0 do not load as transmit data ? the dlcmd2 will not perform any actions defined in this field. 0 0 1 load as transmit data ? if the txfifo is indicating full (complete message already in txfifo), then the byte is not loaded and is lost. 0 1 0 reserved 0 1 1 load as last byte of transmit data 1. if there is not a ?1st byte? at the head of the txfifo, the byte is not loaded and is lost unless a block transfer is in progress. 2. if the txfifo is empty, the byte is not loaded and is lost. 3. if the txfifo is indicating full (complete message already in txfifo), then the byte is not loaded and is lost. 1 0 0 reserved 1 0 1 load as first byte of message 1. if there is already a first byte in the txfifo, the byte is loaded, and will cause a transmit underrun error during transmission of this message. the first ?first byte? and subsequent bytes will transmit correctly until the second ?first byte? is encountered and this byte is not transmitted and is lost. 2. if the status of the txfifo is full (complete message already loaded, or partial message < 11 bytes), then the data byte is not loaded, and is lost. 1 1 0 reserved 1 1 1 load as first and last byte of message ? if the txfifo is full, then the byte is not loaded and is lost. table 15-18. general commands (continued) cmd0 cmd1 cmd2 description 15-42 mpc565/mpc566 reference manual motorola programming model 15.10.8transmit data register (tdata) 15.10.9txfifo command load sequences table 15-21 shows various load sequences for the cmd and tdata registers. the table indicates whether the sequence is valid or invalid and how the dlcmd2 will handle each case. table 15-20. rxfifo commands cmd6 cmd7 description 0 0 do nothing 0 1 reserved (do nothing) 10flushbyte 1. if there is nothing in the rxfifo, then no action is taken even if a byte arrives before the dlcmd2 access is complete. 2. if there are any bytes in the rxfifo, then the first byte (at the head of the rxfifo) is flushed. 3. flush byte commands will not queue up. 1 1 flush current message 1 1. if there is nothing in the rxfifo when this command is latched in, the next message received will be flushed except for the completion code. only the completion code will cause an interrupt. 2. if there is a partial message in the rxfifo (still being received off of the data link), all remaining bytes of the message will be flushed, except for the completion code, when it is formed. only the completion code will cause an interrupt. 3. if there is a complete message in the rxfifo (message bytes and completion code), all bytes of the message will be flushed except for the completion code. 4. if there is completion code at the head of the rxfifo, no action is taken when this command is latched in. 1 flush message commands cannot be queued up. only one dump command is ever active. a flush message command cannot be stopped after being issued. in cases 2 and 3, the rxfifo status may be invalid during a flush message operation. it could take a few motorola chapter 15. data link controller module (dlcmd2) 15-43 programming model note any load sequence other than sequences 1-5 will not result in dlcmd2 transmission activity. 15.10.10transmit data register (tdata) table 15-21. command load sequences load sequence dlcmd2 operation 1) write ?load as first byte? and data byte as 16-bit write. 2) write ?load as transmit data byte? and data byte as 16-bit write. 3) write ?load as last byte? and data byte as 16-bit write. all three command and data bytes are pushed into the txfifo. dlcmd2 transmits message correctly. ?load as last byte? command and last data byte can be written with two separate 8-bit writes. 1) write data bytes as 8-bit writes. 2) write ?load as last byte? and last data byte as 16-bit write. first data byte treated as ?first byte.? ?load as last byte? and last data byte is pushed into the txfifo. dlcmd2 transmits message correctly. ?load as last byte? command and last data byte can be written with two separate 8-bit writes. 1) write ?send on eod? as 8-bit write. 2) write data bytes as 8-bit writes. 3) write ?load as last byte? and last byte as 16-bit write. no ifr transmission occurs. ?send on eod? command will be ignored and first data byte will be treated as ?first byte.? if eof is received, the dlcmd2 will transmit the bytes as a normal message. 1) write ?send on eod? as 8-bit write. 2) write ?load as first byte? and data byte as 16-bit write. 3) write data bytes as 8-bit writes. 4) write ?load as last byte? and data byte as 16-bit write. no ifr transmission occurs. ?send on eod? command will be ignored and first data byte will be treated as ?first byte.? if eof is received, the dlcmd2 will transmit the bytes as a normal message. 1) write ?send on eod,? ?load as first byte,? and data byte as 16-bit write. 2) write data bytes as 8-bit writes. 3) write ?load as last byte? and last data byte as 16-bit write. command and data word is pushed into the txfifo. data bytes are pushed into the txfifo. command and data byte is pushed into the txfifo. dlcmd2 transmits an ifr correctly. 1) write ?load as first byte? as 8-bit write. 2) write ?send on eod? as 8-bit write. 3) write data bytes as 8-bit writes. 4) write ?load as last byte? and data byte as 16-bit write. no ifr transmission occurs. ?send on eod? command will be ignored and first data byte will be treated as ?first byte.? if eof is received, the dlcmd2 will transmit the bytes as a normal message. 1) write ?send on eod,? ?load as first byte,? and data byte as 16-bit write. 2) write ?send on eod,? ?load as transmit data byte,? and data byte as 16-bit write. 3) write ?send on eod,? load as last byte,? and data byte as 16-bit write. no ifr transmission occurs. data bytes other than the first byte of an ifr cannot be written with ?send on eod.? all data bytes are ignored. msb 0 123456lsb 7 tdata[0:7] reset: 0 0000000 figure 15-26. tdata? transmit data register 0x30 008d 15-44 mpc565/mpc566 reference manual motorola programming model read restrictions: reads will return 0x00. write restrictions: supervisor/unrestricted access. figure 15-27. txfifo block diagram 15.10.11receive status register (stat) each byte of data that the dlcmd2 module has received from the j1850 bus will be transferred to the cpu along with a status byte, which relays information on the condition of the dlcmd2 module and the data that has been received. note commands that are in progress may not be reflected in the status byte until sufficient time has elapsed for that command to be performed. the status must be read with each received data byte on the dlcmd2 module, either in an aligned word read, or two separate byte reads. table 15-22. transmit data register (tdata) bit descriptions bit(s) name description 0:7 tdata transmit data register ? the transmit data register (tdata[ 7:0]) is used to load data into the txfifo.dataisautomaticallypushedintothetxfifooneverywritetothetdataregister.see figure 15-27. msb 0 123456lsb 7 stat[0:7] reset: 0 0000000 figure 15-28. stat? receive status register 0x30 008e txfifo control 11 x 3 bits 11 x 8 bits tx_data_out[7:0] tx_status_flags tx_data_in[7:0] txfifo clock t_ctl[2:0] t_pop t_push t_ctl t_reset motorola chapter 15. data link controller module (dlcmd2) 15-45 programming model read restrictions: supervisor/unrestricted access. write restrictions: supervisor/unrestricted access, unaffected by writes. table 15-23. receive status register (stat) bit descriptions bit(s) name description 0:7 stat receive status register ? the status byte can be broken in five fields. bits 0:2 describe the status of the rxfifo. bit 3 indicates whether the bus is idle. bit 4 indicates whether the bus is shorted to ground. bit 5 indicates whether the txfifo is underrunning. bits 6:7 describes the status of the txfifo. refer to table 15-24 for rxfifo status descriptions. refer to table 15-25 for data link idle status descriptions. refer to table 15-26 for transmitter shorted status descriptions. refer to table 15-27 for txfifo underrunning status descriptions. refer to table 15-28 for txfifo status descriptions. table 15-24. rxfifo status stat0 stat1 stat2 description 0 0 0 rxfifo invalid or empty. 1. read of accompanying data byte is not valid. 2. rxfifo invalid (flush message command in progress). 0 0 1 rxfifo contains more than one byte ? rxfifo has between 2-12 bytes of data at the dlcmd2 access and no completion code. 0 1 0 rxfifo contains a completion code ? indicates the presence of a completion code in the rxfifo (not at head of rxfifo) at the dlcmd2 access. there is no other data also in the rsfifo. 0 1 1 receive data byte in position 13 and no completion code in rxfifo?position13intherxfifoisfilledandnocompletion code is present. 1 0 0 rxfifo contains exactly one byte ? rxfifo contains exactly one data byte (not a completion code). 1 0 1 completion code at head of rxfifo, more bytes available ? rxfifo has a completion code at the head, additional bytes from an in-progress message and no other completion codes. 1 1 0 completion code at head of rxfifo, another complete message available ? rxfifo has a completion code at the head and another completed message (completion code preset) in the rxfifo. 1 1 1 completion code on at head of fifo ? rxfifo has a completion code at the head and it is the only byte in the rxfifo. 15-46 mpc565/mpc566 reference manual motorola programming model table15-25.datalinkidlestatus stat3 description 0 data link is busy ? a high level on the bus has been detected for more than 8 s, or an eof symbol is being timed by the receive logic. once bit 4 is a zero because of message activity it will not become one until an eof symbol has been received. noise on an idle line could cause the idle bit to change state as the idle bit is unfiltered. the order of events after a transmission is: eod motorola chapter 15. data link controller module (dlcmd2) 15-47 programming model 15.10.12receive data register (rdata) read restrictions: supervisor/unrestricted access. write restrictions: supervisor/unrestricted access, unaffected by writes. figure 15-30. rxfifo block diagram 15.10.13completion code when the message that is being received is complete, that is, after eod has elapsed since the last transition on the bus, the dlcmd2 will prepare a completion code, which is a one byte descriptor with information about the message. if an error (crc error, incomplete byte, bit timing error, underrun, and loss of arbitration) has occurred, the dlcmd2 will push a completion code into the rxfifo after eod has elapsed. if a break symbol has been received, the dlcmd2 will push a completion code into the rxfifo as soon as the bus is passive. refer to figure 15-31. this byte will be queued and transferred to the host in the same manner that a data byte is. the status byte will flag its presence. msb 0 123456lsb 7 rdata[0:7] reset: 0 0000000 figure 15-29. rdata? receive data register 0x30 008f table 15-29. receive data register (rdata) bit descriptions bit(s) name description 0:7 rdata receive data register ? the receive data register is used to read data from the rxfifo. data is popped from the rxfifo on every read of the rdata register. see figure 15-30. rxfifo rxfifo control 20 x 8 bits clock r_pop r_reset rcv_data_in[7:0] rcv_data_out[7:0] rcv_status_flags r_ctl 20 x 1 bit r_ctl r_push 15-48 mpc565/mpc566 reference manual motorola programming model note any activity on the bus (i.e., noise pulses greater than eight s, messages, truncated messages, bad messages, etc.) will cause a completion code to be pushed into the rxfifo after the bus is idle for an eod length of time. in the case of noise, the completion code will not be pushed until the noise train is over for at least an eod period of time and there will be only one completion code for all of the noise. figure 15-31. completion code byte bit definitions refer to table 15-30 for receive error descriptions. refer to table 15-31 for rxfifo overrun descriptions. refer to table 15-32 for transmitter action descriptions. refer to table 15-27 for txfifo underrunning status descriptions. refer to table 15-32 for ifr bit descriptions. refer to table 15-33 for ifr with/without a crc bit descriptions. refer to table 15-34 for error code descriptions. table 15-30. receive error status bit 0 description 0 no error detected 1 error(s) detected ? when set, certain errors occurred in the reception of this message (see description for bits 1 and 0). if not set, then bits 1 and 0 are also 0. table 15-31. rxfifo overrun status bit 1 description 0 no overrun 1 overrun ? when set, a receiver rxfifo overrun has occurred. it will be set as soon as the 19th data byte has been placed in the fifo (20th position is always completion code). the host has not read out the dlcmd2 regularly enough to prevent the incoming message bytes from being lost. previously received data bytes remain in the rxfifo. the host must make a decision to disregard the partial message and perhaps transmit a request for retransmission of the message. if this bit is set no other bits in the completion code may be taken as valid. 7 6 5 43210 0 0 0 00000 reset error code ifr w/crc ifr transmitter actions rxfifo overrun errors in receive message motorola chapter 15. data link controller module (dlcmd2) 15-49 programming model i table 15-32. transmitter action status bit 2 bit 3 description 0 0 transmitter not involved ? the transmitter did not attempt to contend against this message. 0 1 transmitter underrun ? this message was not completed (not set if transmitter lost arbitration). 1 0 transmitter lost arbitration ? transmitter contended against this message unsuccessfully or a rxfifo overrun occurred (arbitration was not necessarily lost nor transmission stopped). 1 1 transmitter successful ? transmitter contended for this slot successfully (message transmitted successfully). message originated from this node. table 15-33. ifr bit status bit 4 description 0 message not an ifr. 1 ifr ? the preceding bytes that this completion code is associated with was an in-frame response. table 15-34. ifr with/without a crc bit status bit 5 description 0 ifr without crc ? this in-frame response does not contain a crc. 1 ifr with crc ? the preceding byte(s) that this completion code is associated with was an in-frame response with a crc. table 15-35. error code status 1, 2, 3 bit 6 bit 7 description 0 0 crc error ? a crc error was detected in the reception of this message or a receiver overrun occurred. 0 1 incomplete byte received ? an incorrect mod 8 count was detected in the reception of this message. a complete byte was not received. 15-50 mpc565/mpc566 reference manual motorola programming model 15.10.14bus errors the following figures describe various bit timing/ invalid symbol errors. note txp signals shown are what is expected if the error had not occurred and not necessarily what is on the bus during these error conditions. figure 15-32 shows an active symbol received during sof transmission that is greater than the 8 s digital filter and less than the minimum sof symbol time. this symbol will be flagged as an invalid symbol and the corresponding completion code will be 0x82. 1 0 bit timing error ? a bit timing error occurred in this message. will occur with a mismatch of internal clock divide relative to other nodes. the receiver immediately places this completion code after the reception of this error. may happen if a break occurs after the bus has been low for only 8 to 34 s. in this case there will be two completion codes, the first for the bit error, and the second for the break. see table 15-30 through table 15-34 for other bit timing errors. 1 1 break symbol received. 1. a break was detected on the bus, or the bus was shorted high for more than 239 s and has recovered. a. if the receive buffer has 19 bytes in it and a break is received, the completion code will indicate on overflow but no break. b. if the receive buffer has 20 bytes (full) and a break is received, there will be no new completion code pushed and no indication of the break. 1 these error codes are used in conjunction with the error flag to report detected errors. errors are reported based on the order of precedence. only the highest precedence error be reported. 2 the following list is in precedence order, highest first: 1. bread condition occurred. 2. bit timing error detected. 3. incomplete byte (incorrect mod 8 count). 4. crc error detected. 3 if any of these error conditions is noted, any pending eod response message (in-frame response) will not be sent. table 15-35. error code status 1, 2, 3 bit 6 bit 7 description motorola chapter 15. data link controller module (dlcmd2) 15-51 programming model figure 15-32. sof symbol too short figure 15-33 shows bit timing errors on short bits. this can be caused by noise, a bus short to ground (or v dd for passive bits), clock mismatches, etc. the corresponding completion code will be 0x82. if for the second case, the bus remains high for more than 239 s and then goes low, a completion code of 0x83 will follow. figure 15-33. short bit too short figure 15-34 shows bit timing errors on long bits. this can be caused by noise, a bus short to v dd (or ground for passive bits), clock mismatches, etc. for an active bit, if the bus goes low between 163 and 239 s, the corresponding completion code will be 0x82. if the bus goes low after the minimum break time, a completion code of 0x83 will follow. for a passive bit, if the bus goes high between163 and 239 s, the completion code will be 0x82. if the bus remains high for more than 239 s and then goes low, a completion code of 0x83 will follow. txp rxp 8ms < t < 163ms sof a short to ground occurred during sof. eof txp rxp bus error caused an active short pulsetobeaninvalidsymbol. eof sof ln 8ms < t < 34ms sh eof sof ln 8ms < t < 34ms bus error caused a passive short pulsetobeaninvalidsymbol. sh t < 239ms txp rxp 15-52 mpc565/mpc566 reference manual motorola programming model figure 15-34. long bit too long 15.10.15data link controller module (dlcmd2) figure 15-35 shows bit timing errors on an eod and eof. this can be caused by noise, a bus short to v dd , clock mismatches, etc. in these cases, the completion code will be 0x82. figure 15-35. eod and eof too short figure 15-36 shows a bit timing error on a normalization bit. this can be caused by noise, a bus short to ground, clock mismatches, etc. the corresponding completion code will be 0x82. figure 15-36. normalization bit too short eof sh 163ms 239ms a short to vdd, sof (163ms < t < 239ms) or brk (t > 239ms) occurred in the middle of a message. all are errors. txp rxp txp rxp eof sof ln a short to ground, eod, or eof occurred in the middle of a message. 163ms 239ms sof sof sh txp rxp 8ms < t < 163ms eod nb txp rxp 8ms < t < 239ms eof sof the eod before the nb of an ifr byte is too short. the eof before the sof of a new message is too short. txp rxp nb eod 8ms < t < 34ms a short to ground or noise > 8ms caused the normalization bit to be too short and invalid. motorola chapter 15. data link controller module (dlcmd2) 15-53 mask programmable bus error (berr) functionality figure 15-37 shows a bit timing error on a normalization bit. this can be caused by noise, a bus short to v dd , clock mismatches, etc. the corresponding completion code will be 0x82. if the bus remains high for more than 239 s and then goes low, a completion code of 0x83 will follow. figure 15-37. normalization bit too long other errors include crc, incomplete byte, and break. a crc error occurs when the received message is corrupted by noise, delays, clock mismatches, etc. an incomplete byte error occurs when a received message ends on a non-byte boundary. this error also occurs when two extra 1?s are transmitted after arbitration is lost on the last bit of a byte. reception of a break symbol is considered an error. this error occurs when the bus is held high for more than 239 s and then goes low. 15.11 mask programmable bus error (berr) functionality this dlcmd2 supports the berr behavior according to imb3 specification. 15.11.1berr_plug = 0 the dlcmd2 never asserts berr signal in the imb3. 15.11.2berr_plug = 1 the dlcmd2 will terminate the bus cycle with berr in the following cases: access to reserved 16-bit register within the dlcmd2?s memory map. user access to supervisor-only registers when other registers in the dlcmd2?s memory map are user-accessible (mcr supv bit is not set). access to test register (tcr) when not in test mode. writes to read-only registers. txp rxp eod nb 163ms 239ms a short to vdd, an sof, a brk, or noise > 8ms caused the normalization bit to be too long and invalid. 15-54 mpc565/mpc566 reference manual motorola interrupt 15.12interrupt this section describes dlcmd2 interrupt operation. 15.12.1dlcmd2 interrupts in the default mode, interrupts may be requested due to one or more of four conditions becoming true. an optionally configured mode adds one more condition which will generate an interrupt. interrupts may also be disabled. if conditions which generate an interrupt occur while the dlcmd2 is being accessed, they will not be requested until the access is complete. assuming interrupts are enabled, the default set of conditions that will cause the dlcmd2 module to request an interrupt are: 1. completion code is placed in rxfifo, dlcmd2 not accessed. a) an eod has been received on the j1850 bus. b) additional byte is received when the rxfifo is full. this condition will cause the completion code to be pushed (in position 20 of the rxfifo). the received byte and the rest of the message are ignored. c) dlcmd2 receives break. the reception of the break symbol will cause the completion code to be pushed into rxfifo. if the break is received in the middle of dlcmd2 transmitting, it will stop transmitting, reset the transmitter, and clear the txfifo. d) dlcmd2 detects a bit-timing error. the bit-timing error will cause the completion code to be pushed into rxfifo. 2. the rxfifo has 12 bytes in it and the 13th byte is received, and the dlcmd2 is not accessed. completion code may or may not be present in rxfifo. this differs from the 13th byte status indication which occurs only if there is no completion code in the rxfifo. a) the status byte will only reflect this interrupt if there are no completion codes in the rxfifo b) this interrupt generally means that the dlcmd2 is being neglected by the host. 3. a transmit operation is in progress, and there is no last byte to the message in the buffer and the buffer becomes half empty (six bytes left to transmit, five bytes in txfifo and the sixth byte is popped off to the transmit shift register), and the dlcmd2 is not accessed. 4. the dlcmd2 is waking up on the rising edge of data link activity when it was previously in sleep mode. a) any j1850 bus edge will wake up the dlcmd2. will get a bit error indication if the dlcmd2 does not see at least 34 s of the sof. motorola chapter 15. data link controller module (dlcmd2) 15-55 interrupt by setting bit 15 in the ilr register in section 15.10.3, ?interrupt level register (ilr),? one more condition capable of generating an interrupt is added: 5. a byte has been received into an empty rxfifo, and the dlcmd2 is not accessed. table 15-35 shows dlcmd2 interrupt operations. refer to table 15-12 for ivr[2:0] encoding. table 15-36. interrupt operations interrupt conditions necessary to enable/re-enable interrupts conditions for interrupt assertion conditions to clear this interrupt wake up enter low power mode dlcmd2 module is in sleep mode. positive going edge on bus > v ih is sensed on bus. read ipr with bit 3 set and write ipr[3] ?0? to clear transmitter half full (6 bytes) 1. ?load a byte into txfifo? with a fifth byte position filled, ?or? 2. load in data bytes so that the sixth position in txfifo is occupied. a transmit operation is in progress, no last byte indicated to the message in txfifo (block mode), txfifo becomes half empty, and transmit interrupt is enabled (last byte not pushed into txfifo) read ipr with bit 3 set and write ipr[3] ?0? to clear 13th byte received the only way to insure that this interrupt is re-enabled is to complete empty out the rx fifo: 1. if the 13th byte is occupied and the 14th isn?t a ?flush byte? command will re-enable. ?or? 2. if the 13th byte is occupied and the 14th is not, and there is no completion code at the head of the rxfifo, a ?flush message? command will re-enable. ?or? 3. the 13th byte becomes unoccupied. rxfifo receives 13th byte, (completion may or may not be present in rxfifo, refer to section 15.12.1, ?dlcmd2 interrupts?) read ipr with bit 2 set and write ipr[2] ?0? to clear. eod sensed on bus always enabled. a completion code is placed onto the rxfifo. read ipr with bit 1 set and write ipr[1] ?0? to clear. first byte received in an empty rxfifo 1. if the first position is filled, and the second position is empty, and a ?flush byte? command is issued. ?or? 2. the first position becomes empty. rxfifo empty, first byte received, intmode in ilr must be set, and flush interrupt enabled (flush message except completion code, completion code will cause eod interrupt) read ipr with bit 0 set and write ipr[0] ?0? to clear. 15-56 mpc565/mpc566 reference manual motorola interrupt 15.12.2interrupt structure this interrupt structure for the imb3 supports a total of 32 interrupt levels that are time multiplexed on the irqb[7:0] lines as seen in table 15-37. in this structure, all interrupt sources place their asserted level on a time multiplexed bus during four different time slots, with eight levels communicated per slot. however, each group of levels actually occur, one system clock cycle after the associated imb3 ilbs signal is asserted. the ilbs[1:0] signals indicate which group of eight are being driven on the interrupt request lines. see table 15-37 and section 12.4, ?interrupt operation? for further details. the dlcmd2 module is capable of generating one of the 32 possible interrupt levels on the imb3. the level that the dlcmd2 will drive can be programmed into the interrupt request level bits located in the interrupt level register (ilr[2:0] bit field ? bits [2:0] in the ilr register). the two bits, ilbs[1:0] in the ilr register (bits [4:3]) determine on which slot the dlcmd2 should drive its interrupt signal (one of irqb[7:1]. figure 15-38 shows the timing of slot multiplexing on the imb3. figure 15-38. interrupt request multiplex timing this interrupt generation scheme is shown in figure 15-39. even though the iack cycles are not generated in this interrupt scheme, the lower three bits of ivr register are read-only bits and will be updated immediately by the dlcmd2 to indicate the source of interrupts. table 15-37. interrupt levels ilbs[1:0] levels 00 0:7 01 8:15 10 16:23 11 24:31 ilbs irq clock 00 01 10 11 00 01 10 11 irq 7:0 irq 15:8 irq 23:16 irq 31:24 irq 7:0 irq 15:8 irq 23:16 motorola chapter 15. data link controller module (dlcmd2) 15-57 in-frame response figure 15-39. dlcmd2 interrupt vector generation (irq_plug = 1) 15.13in-frame response this section describes how the dlcmd2 uses an in-frame response (ifr) in message transmission. 15.13.1ifr operation the ifr may be sent by loading up a message for transmission with a ?send on eod? bit combination set in the command byte accompanying the first byte. the setting of the eod bit combination will automatically next byte as part of, or the complete, response. a message on the bus is determined to be ready for a response when an ?end of data? (eod) waveform has occurred on the bus. if a reply message initiates immediately following the eod, then this will be an ifr. if no response is sent when eod occurs, then an eof will appear on the bus, signifying normal end of message without response. the eof waveform is an extension of the eod waveform. the reply will start with an active ?1? or ?0?, called the normalization bit, and may also have a crc transmitted with it. the dlcmd2 is capable of arbitrating against and receiving all types of ifrs. whether or not the received ifr contains a crc or not is signalled through the use of the nbfs bit in the 80 8-bit vector irq level 9 10 6 7 ivr ilr irq mux time slot ilbs[1:0] equal 3to8 decoder sel[2:0 ] en dlcmd2 interrupts pending {@clockhi] irqb[0] clockhi d q irqb[7] driver enable driver enable unused 5to3 encoder 2 15-58 mpc565/mpc566 reference manual motorola in-frame response section 15.10.5, ?symbol timing control and pre-scaler register (sctl)?. ifrs are arbitrated just like any other message if more than one node wants to send a response. single byte ifr from multiple responders (type 2) will retransmit if arbitration is lost. if arbitration is lost on the last bit of a type 2 ifr byte, two extra ?1? bits will not be sent onto the bus since the ifr will retransmit. upon beginning transmission of a single byte ifr from a single responder (type 1) or multiple byte ifr from a single responder (type 3), the dlcmd2 will enter tar mode and not retransmit the ifr if arbitration is lost. if arbitration is lost on the last bit of a type 3 ifr byte, two extra ?1? bits will be sent onto the bus. this response message is sent only if: 1. there were no errors of any type in the original message requiring response. the only exception to this is that if an ifr is loaded after the transmitter lost arbitration to another message, the ifr will be sent at eod. 2. ifr was loaded with a command byte that indicated either: ?first byte? or ?first and last? byte of a message. 3. this ifr was loaded into the dlcmd2 after the start of the message was detected, and t resp before the eod was recognized. when the dlcmd2 receives the command byte and data byte signaling an ifr, it will start transmitting the response after eod even if there is no last byte in the txfifo. the dlcmd2 will start the response by t automatically transmitting an active phase ?0? or a ?1? depending on how the nbfs bit is programmed. it is left to the host to remember that any messages that were in the transmit buffer at the time the ifr was loaded have been flushed, and must be reloaded by the host for transmission. this is true even if the ifr was not successfully loaded or transmitted. completion code bit 3 will inform the host of whether or not an ifr has occurred. if an ifr has occurred, the rxfifo will contain the initial message, with a completion code, and the response, with its completion code. each completion code identifies the message associated with it as a normal message, or a response. the only way that the cpu can tell that such a sequence has occurred on the bus is by reading the completion code. if any errors occur during the reception of an ifr: 1. a completion code indicating an error occurred during reception is pushed into the rxfifo. 2. anything left of the ifr is not received off the bus. if bit 3 of the completion code is set, then bit 2 will indicate whether the response had a crc field or not. if bit 2 is set, then the response had a crc field. this is important for the cpu to determine the meaning of the response. adlcmd2maysendanifrtoanifrwithcrcbutnoresponsemayfollowanifr without crc. motorola chapter 15. data link controller module (dlcmd2) 15-59 in-frame response for the system to enter a mode that allows an ifr, some coordination of nodes is required. the node sending an ifr must select the appropriate interrupt configuration (interrupt on first byte), and be ready to transfer a response into the dlcmd2, signalling through the command byte that this is an ifr. 15.13.2ifr abort conditions table 15-38 shows conditions in which ifrs are aborted. 15.13.3ifr types the dlcmd2 supports types 1, 2 and 3 ifrs with arbitration and auto-retransmission. see figure 15-40 for a description of each type of ifr. the following sections describe how the dlcmd2 can be configured to transmit the three types of ifrs. table 15-38. ifr aborted conditions ifr transmission aborted if actions taken host underran transmitter (no ?last byte? indicated in the txfifo at eod, and host did not supply a last byte in time for transmission). dlcmd2 inverts the crc field on the truncated ifr. ifr loses contention to another ifr. dlcmd2 stops transmitting multiple byte ifrs, and flushes the txfifo immediately. dlcmd2 can be configured to auto-retry or stop transmission of single byte ifrs upon loss of arbitration. error detected in the received message. dlcmd2 resets the transmitter and txfifo, no ifr is sent. error in ifr during transmission. ifr is stopped, transmitter and txfifo are reset. ifr not loaded correctly. 1. bus idle when ifr was loaded (loaded before any message is on the bus). 2. ifr loaded less than t resp before eod is sensed on bus (loaded too late). 3. ifr not loaded with ?first byte? indicated. 4. ifr bit set in command byte, but no data is loaded at all. dlcmd2 resets the transmitter and txfifo, no ifr is sent. 15-60 mpc565/mpc566 reference manual motorola in-frame response figure 15-40. types of ifr 15.13.3.1 type 1 ifr a type 1 ifr is a single byte ifr without crc transmitted by a single responder. if arbitration is lost, the dlcmd2 will not attempt to re-transmit the ifr byte in the txfifo. the txfifo will be cleared and the ifr byte will be lost. the dlcmd2 can be configured to transmit a type 1 ifr by writing an ifr byte into the tdata register and a command byte of $bc indicating ?send on eod without crc? and ?load as first and last byte.? 15.13.3.2 1.type 2 ifr a type 2 ifr results from multiple responders transmitting a single byte ifr onto the bus. since only one ifr will win arbitration, the other responders will re-transmit their ifrs as soon as the ifr winning arbitration finishes. the ifr byte in the txfifo will not be cleared until transmission is successful or an error is detected on the bus. the dlcmd2 can be configured to transmit a type 2 ifr by writing an ifr byte into the tdata register and a command byte of $dc indicating ?send on eod with auto retry? and ?load as first and last byte.? 15.13.3.3 type 3 ifr a type 3 ifr is a multiple byte ifr with or without crc transmitted by a single responder. if arbitration is lost, the dlcmd2 will not attempt to re-transmit the ifr bytes in the txfifo. the txfifo will be cleared and the ifr bytes will be lost. sof header data field crc eo d type 0 ? no ifr header data field crc eo d type 3 ? multiple bytes from a single responder header data field crc eo d type 1 ? single byte from a single responder header data field crc eo d type 2 ? single byte from multiple responders id1 id n ifr data field crc nb nb nb id so f so fsof eof eod eof eod eof eod eo f motorola chapter 15. data link controller module (dlcmd2) 15-61 system overview the dlcmd2 can be configured to transmit a type 3 ifr with crc by writing the first ifr byte into the tdata register and a command byte of $74 indicating ?send on eod with crc? and ?load as first byte.? the dlcmd2 can also be configured to transmit a type 3 ifr without crc by writing the first byte into the tdata register and a command byte of $b4 indicating ?send on eod without crc? and ?load as first byte.? 15.14system overview typical usage of the dlcmd2 in a microcomputer system is shown in figure 15-41. figure 15-41. j1850 node 15.15test operation 15.15.1test configuration register (tcr) the test configuration register controls various test modes which are used during manufacturing, and are not intended to be used in a normal application. the test configuration register can be read or written only in test mode. when read from supervisor data space in non-test mode, the test register reads as 0x0000. when being written to supervisor data space in non-test mode, the test register ignores the write. dlcmd2 xcvr mcu power supply digital analog j1850 bus 15-62 mpc565/mpc566 reference manual motorola module i/o signals 15.16module i/o signals 15.16.1signal descriptions this section provides information on external signal functions. 15.16.2external connections figure 15-42 shows dlcmd2 external connections. figure 15-42. dlcmd2 external connections 15.16.3signal functions table 15-39 summarizes dlcmd2 external signals. 15.16.3.1 cl2tx this pin is a logic level output. a logic ?0? output drives the bus output to 0 vdc (external pull down resistor to ground) and a logic ?1? output produces a high voltage at the table 15-39. signal names module signal name (external) input / output description cl2tx o dlcmd2 digital output to transceiver cl2rx i dlcmd2 digital input from transceiver 4xen 1 1 this signal is not available on the mpc565/mpc566. o 4x transmit enable output to transceiver dlcmd2 transceiver imb3 cpu cl2tx cl2tx bus load motorola chapter 15. data link controller module (dlcmd2) 15-63 module i/o signals bus output. an internal 200 k ? to ground in the xcvr guarantees a logic ?0? input when this pin is open circuit (the bus output is tri-stated). 15.16.3.2 cl2rx this is a cmos compatible input used to get receiver data to the microprocessor. there is a minimum of.1 vdc of hysteresis between the bus high and low (and vice versa) transition points. 15-64 mpc565/mpc566 reference manual motorola module i/o signals motorola chapter 16. can 2.0b controller module 16-1 chapter 16 can 2.0b controller module the mpc565/mpc566 contains three can 2.0b controller modules (toucan). each toucan is a communication controller that implements the controller area network (can) protocol, an asynchronous communications protocol used in automotive and industrial control systems. it is a high speed (one mbit/sec), short distance, priority based protocol that can run over a variety of mediums (for example, fiber optic cable or an unshielded twisted pair of wires). the toucan supports both the standard and extended identifier (id) message formats specified in the can protocol specification, revision 2.0, part b. the third toucan has its pins muxed with mios14 gpio pins. these pins are configured as gpio inputs at reset and must be changed to toucan pins in the mios before enabling the toucan. each toucan module contains 16 message buffers, which are used for transmit and receive functions. it also contains message filters, which are used to qualify the received message ids when comparing them to the receive buffer identifiers. figure 16-1 shows a block diagram of a toucan module. figure 16-1. toucan block diagram control slave bus cntx0 cnrx0 interface unit 16 rx/tx message buffers transmitter receiver cntx1 cnrx1 imb 16-2 mpc565/mpc566 reference manual motorola features 16.1 features each toucan module provides these features: full implementation of can protocol specification, version 2.0 a/b ? standard data and remote frames (up to 109 bits long) ? extended data and remote frames (up to 127 bits long) ? zero to eight bytes data length ? programmable bit rate up to one mbit/sec 16 rx/tx message buffers of 0-8 bytes data length content-related addressing no read/write semaphores required three programmable mask registers: global (for message buffers 0 through 13), special for message buffer 14, and special for message buffer 15 programmable transmit-first scheme: lowest id or lowest buffer number ?time stamp?, based on 16-bit free-running timer global network time, synchronized by a specific message programmable i/o modes maskable interrupts independent of the transmission medium (external transceiver is assumed) open network architecture multimaster concept high immunity to emi short latency time for high-priority messages low power sleep mode with programmable wakeup on bus activity outputs have open drain drivers support for sae j1939 and sae j2284 support for devicenet? and smart distributed system 16.2 external pins the toucan module interface to the can bus consists of four pins: cantx0 and cantx1, which transmit serial data, and canrx0 and canrx1, which receive serial data. motorola chapter 16. can 2.0b controller module 16-3 toucan architecture figure 16-2. typical can network each can station is connected physically to the can bus through a transceiver. the transceiver provides the transmit drive, waveshaping, and receive/compare functions required for communicating on the can bus. it can also provide protection against damage to the toucan caused by a defective can bus or a defective can station. 16.3 toucan architecture the toucan module uses a flexible design that allows each of its 16 message buffers to be designated either a transmit (tx) buffer or a receive (rx) buffer. in addition, to reduce the cpu overhead required for message handling, each message buffer is assigned an interrupt flag bit to indicate that the transmission or reception completed successfully. 16.3.1 tx/rx message buffer structure figure 16-3 displays the extended (29-bit) id message buffer structure. figure 16-4 displays the standard (11-bit) id message buffer structure. oo transceiver cntx0 cnrx0 can controller (toucan) can system can station 2 can station n can station 1 transceiver transceiver 16-4 mpc565/mpc566 reference manual motorola toucan architecture figure 16-3. extended id message buffer structure figure 16-4. standard id message buffer structure 16.3.1.1 common fields for extended and standard format frames table 16-1 describes the message buffer fields that are common to both extended and standard identifier format frames. msb 07811 lsb 12 15 0x0 time stamp code length control/status 0x2 id[28-18] srr ide id[17-15] id_high 0x4 id[14-0] rtr id_low 0x6 data byte 0 data byte 1 0x8 data byte 2 data byte 3 0xa data byte 4 data byte 5 0xc data byte 6 data byte 7 0xe reserved msb 07811 lsb 12 15 0x0 time stamp code length control/status 0x2 id[28:18] rtr 0 0 0 0 id_high 0x4 16-bit time stamp id_low 0x6 data byte 0 data byte 1 0x8 data byte 2 data byte 3 0xa data byte 4 data byte 5 0xc data byte 6 data byte 7 0xe reserved table 16-1. common extended/standard format frames field description time stamp contains a copy of the high byte of the free running timer, which is captured at the beginning of the identifier field of the frame on the can bus. code refer to table 16-2 and table 16-3. length (rx) length (in bytes) of the rx data stored in offset 0x6 through 0xd of the buffer.this field is written by the toucan module, copied from the dlc (data length code) field of the received frame. motorola chapter 16. can 2.0b controller module 16-5 toucan architecture 16.3.1.2 fields for extended format frames table 16-4 describes the message buffer fields used only for extended identifier format frames. length (tx) length (in bytes) of the data to be transmitted, located in offset 0x6 through 0xd of the buffer. this field is written by the cpu and is used as the dlc field value. if rtr (remote transmission request) = 1, the frame is a remote frame and will be transmitted without data field, regardless of the value in tx length. data this field can store up to eight data bytes for a frame. for rx frames, the data is stored as it is received from the bus. for tx frames, the cpu provides the data to be transmitted within the frame. reserved the cpu controls access to this word entry field (16 bits). table 16-2. message buffer codes for receive buffers rx code before rx new frame description rx code after rx new frame comment 0b0000 not active ? message buffer is not active. ? ? 0b0100 empty ? message buffer is active and empty. 0b0010 ? 0b0010 full ? message buffer is full. 0b0110 if a cpu read occurs before the new frame, new receive code is 0010. 0b0110 overrun ? addtional frame was received into a full buffer before the cpu read the first one. 0b0xy1 1 1 for tx message buffers, upon read, the busy bit should be ignored. busy ? message buffer is now being filled with a new receive frame. this condition will be cleared within 20 cycles. 0b0010 an empty buffer was filled (xy was 10). 0b0110 a full/overrun buffer was filled (y was 1). table 16-3. message buffer codes for transmit buffers rtr initial tx code description code after successful transmission x 0b1000 message buffer not ready for transmit. ? 0 0b1100 data frame to be transmitted once, unconditionally. 0b1000 1 0b1100 remote frame to be transmitted once, and message buffer becomes an rx message buffer for data frames. 0b0100 0 0b1010 1 1 when a matching remote request frame is detected, the code for such a message buffer is changed to be 0b1110. data frame to be transmitted only as a response to a remote frame, always. 0b1010 0 0b1110 data frame to be transmitted only once, unconditionally, and then only as a response to remote frame, always. 0b1010 table 16-1. common extended/standard format frames (continued) field description 16-6 mpc565/mpc566 reference manual motorola toucan architecture 16.3.1.3 fields for standard format frames table 16-5 describes the message buffer fields used only for standard identifier format frames. 16.3.1.4 serial message buffers to allow double buffering of messages, the toucan has two shadow buffers called serial message buffers. the toucan uses these two buffers for buffering both received messages and messages to be transmitted. only one serial message buffer is active at a time, and its function depends upon the operation of the toucan at that time. these buffers are not accessible or visible to the user. table 16-4. extended format frames field description id[28:18]/[17:15] contains the 14 most significant bits of the extended identifier, located in the id_high word of the message buffer. substitute remote request (srr) contains a fixed recessive bit, used only in extended format. should be set to one for tx buffers. it will be stored as received on the can bus for rx buffers. id extended (ide) if extended format frame is used, this field should be set to one. if zero, standard format frame shouldbeused. id[14:0] bits [14:0] of the extended identifier, located in the id_low word of the message buffer. remote transmission request (rtr) this bit is located in the least significant bit of the id_low word of the message buffer; 0 = data frame, 1 = remote frame. table 16-5. standard format frames field description 16-bit time stamp the id_low word, which is not needed for standard format, is used in a standard format buffer to store the 16-bit value of the free-running timer which is captured at the beginning of the identifier field of the frame on the can bus. id[28:18] contains bits [28:18] of the identifier, located in the id_high word of the message buffer. the four least significant bits in this register (corresponding to the ide bit and id[17:15] for an extended identifier message) must all be written as logic zeros to ensure proper operation of the toucan. rtr this bit is located in the id_high word of the message buffer; 0 = data frame, 1 = remote frame. rtr/srr bit treatment if the toucan transmits this bit as a one and receives it as a zero, an ?arbitration loss? is indicated. if the toucan transmits this bit as a zero and receives it as a one, a bit error is indicated. if the toucan transmits a value and receives a matching response, a successful bit transmission is indicated. motorola chapter 16. can 2.0b controller module 16-7 toucan architecture 16.3.1.5 message buffer activation/deactivation mechanism each message buffer must be activated once it is configured for the desired operation. a buffer is activated by writing the appropriate code to the control/status word for that buffer. once the buffer is activated, it will start the normal transmit and receive processes. a buffer is deactivated by writing the appropriate deactivation code to the control/status word for that buffer. a buffer is typically deactivated to reconfigure the buffer (for example to change the buffer?s function from rx to tx or tx to rx). the buffer should also be deactivated before changing a receive buffer?s message identifier or before loading a new message to be transmitted into a transmit buffer. for more details on activation and deactivation of message buffers and the effects on message buffer operation, refer to section 16.4, ?toucan operation.? 16.3.1.6 message buffer lock/release/busy mechanism in addition to the activation/deactivation mechanism, the toucan also uses a lock/release/busy mechanism to ensure data coherency during the receive process. the mechanism includes a lock status for each message buffer and uses the two serial message buffers to facilitate frame transfers within the toucan. reading the control/status word of a receive message buffer triggers the lock for that buffer. while locked, a received message cannot be transferred into that buffer from one of the serial message buffers. if a message transfer between the message buffer and a serial message buffer is in progress when the control/status word is read, the busy status is indicated in the code field, and the lock is not activated. the user can release the lock on a message buffer in one of two ways. reading the control/status word of another message buffer locks that buffer, releasing the previously locked buffer. a global release can also be performed on any locked message buffer by reading the free-running timer. once a lock is released, any message transfers between a serial message buffer and a message buffer that were delayed due to that buffer being locked will take place. for more details on the message buffer locking mechanism, and the effects on message buffer operation, refer to section 16.4, ?toucan operation.? 16.3.2 receive mask registers the receive mask registers are used as acceptance masks for received frame ids. the following masks are defined: a global mask, used for receive buffers 0-13 two separate masks for buffers 14 and 15 16-8 mpc565/mpc566 reference manual motorola toucan architecture the value of the mask registers should not be changed during normal operation. if the mask register data is changed after the masked identifier of a received message is matched to a locked message buffer, that message will be transferred into that message buffer once it is unlocked, regardless of whether that message?s masked identifier still matches the receive buffer identifier. table 16-6 shows mask bit values. table 16-7 shows mask examples for normal and extended messages. refer to section 16.7, ?programmer?s model? for more information on rx mask registers. table 16-6. receive mask register bit values mask bit values 0 the corresponding incoming id bit is ?don?t care? 1 the corresponding id bit is checked against the incoming id bit to see if a match exists table 16-7. mask examples for normal/extended messages message buffer (mb) /mask base id id[28:18] ide extended id id[17:0] match mb2 11111111000 0 ? ? mb3 11111111000 1 010101010101010101 ? mb4 00000011111 0 ? ? mb5 00000011101 1 010101010101010101 ? mb14 11111111000 1 010101010101010101 ? rx global mask 11111111110 111111100000000001 ? rxmessagein 11111111001 1 010101010101010101 3 1 1 match for extended format (mb3). 11111111001 0 ? 2 2 2 match for standard format (mb2). 11111111001 1 010101010101010100 ? 3 3 no match for mb3 because of id0. 01111111000 0 ? ? 4 4 no match for mb2 because of id28. 01111111000 1 010101010101010101 ? 5 5 no match for mb3 because of id28, match for mb14. rx 14 mask 01111111111 111111100000000000 ? rxmessagein 10111111000 1 010101010101010101 ? 6 6 no match for mb14 because of id27. 01111111000 1 010101010101010101 14 7 7 match for mb14. motorola chapter 16. can 2.0b controller module 16-9 toucan architecture 16.3.3 bit timing the toucan module uses three 8-bit registers to set up the bit timing parameters required by the can protocol. control registers one and two (canctrl1, canctrl2) contain the propseg, pseg1, pseg2, and the rjw fields which allow configuration of the bit timing parameters. the prescaler divide register (presdiv) allows selection of the ratio used to derive the s-clock from the system clock. the time quanta clock operates at the s-clock frequency. table 16-8 provides examples of system clock, can bit rate, and s-clock bit timing parameters. refer to section 16.7, ?programmer?s model? for more information on the bit timing registers. 16.3.3.1 configuring the toucan bit timing the following considerations must be observed when programming bit timing functions. if the programmed presdiv value results in a single system clock per one time quantum, then the pseg2 field in canctrl2 register must not be programmed to zero. if the programmed presdiv value results in a single system clock per one time quantum, then the information processing time (ipt) equals three time quanta; otherwise it equals two time quanta. if pseg2 equals two, then the toucan transmits one time quantum late relative to the scheduled sync segment. table 16-8. example system clock, can bit rate and s-clock frequencies system clock frequency (mhz) can bit rate (mhz) possible s-clock frequency (mhz) possible number of time quanta/bit presdiv value + 1 56 1 56 56 1 40 1 40 40 1 25 1 25 25 1 20 1 10, 20 10, 20 2, 1 16 1 8,16 8,16 2,1 56 0.500 56 118 1 40 0.500 40 80 1 25 0.500 25 50 1 20 0.500 1, 2, 2.5 2, 4, 5 20, 10, 8 16 0.500 1, 2 2, 4 16, 8 56 0.125 1, 2 8, 16 56, 28 40 0.125 1, 2 8, 16 40, 20 25 0.125 1, 1.25, 2.5 8,10, 20 25, 20,10 20 0.125 1, 2, 2.5 8, 16, 20 20, 10, 8 16 0.125 1, 2 8,16 16, 8 16-10 mpc565/mpc566 reference manual motorola toucan architecture if the prescaler and bit timing control fields are programmed to values that result in fewer than 10 system clock periods per can bit time and the can bus loading is 100%, then any time the rising edge of a start-of-frame (sof) symbol transmitted by another node occurs during the third bit of the intermission between messages, the toucan may not be able to prepare a message buffer for transmission in time to begin its own transmission and arbitrate against the message which transmitted the early sof. the toucan bit time must be programmed to be greater than or equal to nine system clocks, or correct operation is not guaranteed. 16.3.4 error counters the toucan has two error counters, the transmit (tx) error counter and the receive (rx) error counter. refer to section 16.7, ?programmer?s model? for more information on error counters.the rules for increasing and decreasing these counters are described in the can protocol, and are fully implemented in the toucan. each counter has the following features: eight-bit up/down-counter increment by eight (rx error counter also increments by one) decrement by one avoid decrement when equal to zero rx error counter reset to a value between 119 and 127 inclusive, when the toucan transitions from error passive to error active following reset, both counters reset to zero detect values for error passive, bus off and error active transitions cascade usage of tx error counter with an additional internal counter to detect the 128 occurrences of 11 consecutive recessive bits necessary to transition from bus off into error active. both counters are read-only (except in test/freeze/halt modes). the toucan responds to any bus state as described in the can protocol, transmitting an error active or error passive flag, delaying its transmission start time (error passive) and avoiding any influence on the bus when in the bus off state. the following are the basic rules for toucan bus state transitions: if the value of the tx error counter or rx error counter increments to a value greater than or equal to 128, the fault confinement state (fcs[1:0]) field in the error status register is updated to reflect an error passive state. if the toucan is in an error passive state, and either the tx error counter or rx error counter decrements to a value less than or equal to 127 while the other error counter motorola chapter 16. can 2.0b controller module 16-11 toucan architecture already satisfies this condition, the fcs[1:0] field in the error status register is updated to reflect an error active state. if the value of the tx error counter increases to a value greater than 255, the fcs[1:0] field in the error status register is updated to reflect a bus off state, and an interrupt may be issued. the value of the tx error counter is reset to zero. if the toucan is in the bus off state, the tx error counter and an additional internal counter are cascaded to count 128 occurrences of 11 consecutive recessive bits on the bus. to do this, the tx error counter is first reset to zero, and then the internal counter begins counting consecutive recessive bits. each time the internal counter counts 11 consecutive recessive bits, the tx error counter is incremented by one and the internal counter is reset to zero. when the tx error counter reaches the value of 128, the fcs[1:0] field in the error status register is updated to be error active, and both error counters are reset to zero. any time a dominant bit is detected following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero but does not affect the tx error counter value. if only one node is operating in a system, the tx error counter is incremented with each message it attempts to transmit, due to the resulting acknowledgment errors. however, acknowledgment errors never cause the toucan to change from the error passive state to the bus off state. if the rx error counter increments to a value greater than 127, it stops incrementing, even if more errors are detected while being a receiver. after the next successful message reception, the counter is reset to a value between 119 and 127, to enable a return to the error active state. the 3 basic states and the transition behavior of the can controller are shown in figure 16-5. 16-12 mpc565/mpc566 reference manual motorola toucan operation figure 16-5. can controller state diagram 16.3.5 time stamp the value of the free-running 16-bit timer is sampled at the beginning of the identifier field on the can bus. for a message being received, the time stamp is stored in the time stamp entry of the receive message buffer at the time the message is written into that buffer. for a message being transmitted, the time stamp entry is written into the transmit message buffer once the transmission has completed successfully. the free-running timer can optionally be reset upon the reception of a frame into message buffer 0. this feature allows network time synchronization to be performed. 16.4 toucan operation the basic operation of the toucan can be divided into three areas: reset and initialization of the module transmit message handling receive message handling example sequences for performing each of these processes is given in the following paragraphs. error active error passive bus off (tx error > 127 or rx error > 127) and (tx error < 255) tx error > 255 (tx error 127 and rx error 127) normal state 128 occurences of 11 consecutive recessive bits, tx error and rx error are reset to 0. motorola chapter 16. can 2.0b controller module 16-13 toucan operation 16.4.1 toucan reset the toucan can be reset in two ways: hard reset, by the processor?s sreset. soft reset, using the softrst bit in the module configuration register following the negation of reset, the toucan is not synchronized with the can bus, and the halt, frz, and frzack bits in the module configuration register are set. in this state, the toucan does not initiate frame transmissions or receive any frames from the can bus. the contents of the message buffers are not changed following reset. any configuration change or initialization requires that the toucan be frozen by either the assertion of the halt bit in the module configuration register or by reset. 16.4.2 toucan initialization initialization of the toucan includes the initial configuration of the message buffers and configuration of the can communication parameters following a reset, as well as any reconfiguration which may be required during operation. the following is a general initialization sequence for the toucan: 1. initialize all operation modes a) initialize the transmit and receive pin modes in control register 0 (canctrl0) b) initialize the bit timing parameters propseg, psegs1, pseg2, and rjw in control registers 1 and 2 (canctrl[1:2]) c) select the s-clock rate by programming the presdiv register d) select the internal arbitration mode (lbuf bit in canctrl1) 2. initialize message buffers a) the control/status word of all message buffers must be written either as an active or inactive message buffer. b) all other entries in each message buffer should be initialized as required 3. initialize toucan interrupt handler a) initialize the interrupt configuration register (canicr) with a specific request level b) set the required mask bits in the imask register (for all message buffer interrupts), in canctrl0 (for bus off and error interrupts), and in canmcr for the wake interrupt 4. negate the halt bit in the module configuration register. at this point, the toucan attempts to synchronize with the can bus 16-14 mpc565/mpc566 reference manual motorola toucan operation note in both the transmit and receive processes, the first action in preparing a message buffer must be to deactivate the buffer by setting its code field to the proper value. this step is mandatory to ensure data coherency. 16.4.3 transmit process the transmit process includes preparation of a message buffer for transmission, as well as the internal steps performed by the toucan to decide which message to transmit. this involves loading the message and id to be transmitted into a message buffer and then activating that buffer as an active transmit buffer. once this is done, the toucan performs all additional steps necessary to transmit the message onto the can bus. the user should prepare or change a message buffer for transmission by executing the following steps. 1. write the control/status word to hold the transmit buffer inactive (code = 0b1000) 2. write the id_high and id_low words 3. write the data bytes 4. write the control/status word (active tx code, tx length) note steps 1 and 4 are mandatory to ensure data coherency. once an active transmit code is written to a transmit message buffer, that buffer begins participating in an internal arbitration process as soon as the receiver senses that the can bus is free, or at the inter-frame space. if there are multiple messages awaiting transmission, this internal arbitration process selects the message buffer from which the next frame is transmitted. when this process is over and a message buffer is selected for transmission, the frame from that message buffer is transferred to the serial message buffer for transmission. the toucan transmits no more than eight data bytes, even if the transmit length contains a value greater than eight. at the end of a successful transmission, the value of the free-running timer (which was captured at the beginning of the identifier field on the can bus), is written into the time stamp field in the message buffer. the code field in the control/status word of the message buffer is updated and a status flag is set in the iflag register. motorola chapter 16. can 2.0b controller module 16-15 toucan operation 16.4.3.1 transmit message buffer deactivation any write access to the control/status word of a transmit message buffer during the process of selecting a message buffer for transmission immediately deactivates that message buffer, removing it from the transmission process. if the transmit message buffer is deactivated while a message is being transferred from it to a serial message buffer, the message is not transmitted. if the transmit message buffer is deactivated after the message is transferred to the serial message buffer, the message is transmitted, but no interrupt is requested, and the transmit code is not updated. if a message buffer containing the lowest id is deactivated while that message is undergoing the internal arbitration process to determine which message should be sent, then that message may not be transmitted. 16.4.3.2 reception of transmitted frames the toucan receives a frame it has transmitted if an empty message buffer with a matching identifier exists. 16.4.4 receive process during the receive process, the following events occur: the user configures the message buffers for reception the toucan transfers received messages from the serial message buffers to the receive message buffers with matching ids the user retrieves these messages the user should prepare or change a message buffer for frame reception by executing the following steps. 1. write the control/status word to hold the receive buffer inactive (code = 0b0000) 2. write the id_high and id_low words 3. write the control/status word to mark the receive message buffer as active and empty note steps 1 and 3 are mandatory for data coherency. once these steps are performed, the message buffer functions as an active receive buffer and participates in the internal matching process, which takes place every time the toucan 16-16 mpc565/mpc566 reference manual motorola toucan operation receives an error-free frame. in this process, all active receive buffers compare their id value to the newly received one. if a match is detected, the following actions occur: 1. the frame is transferred to the first (lowest entry) matching receive message buffer 2. the value of the free-running timer (captured at the beginning of the identifier field on the can bus) is written into the time stamp field in the message buffer 3. the id field, data field, and rx length field are stored 4. the code field is updated 5. the status flag is set in the iflag register the user should read a received frame from its message buffer in the following order: 1. control/status word (mandatory, as it activates the internal lock for this buffer) 2. id (optional, since it is needed only if a mask was used) 3. data field word(s) 4. free-running timer (optional, as it releases the internal lock) if the free running timer is not read, that message buffer remains locked until the read process starts for another message buffer. only a single message buffer is locked at a time. when a received message is read, the only mandatory read operation is that of the control/status word. this ensures data coherency. if the busy bit is set in the message buffer code, the cpu should defer accessing that buffer until this bit is negated. refer to table 16-2. note the user should check the status of a message buffer by reading the status flag in the iflag register and not by reading the control/status word code field for that message buffer. this prevents the buffer from being locked inadvertently. because the received identifier field is always stored in the matching receive message buffer, the contents of the identifier field in a receive message buffer may change if one or more of the id bits are masked. 16.4.4.1 receive message buffer deactivation any write access to the control/status word of a receive message buffer during the process of selecting a message buffer for reception immediately deactivates that message buffer, removing it from the reception process. if a receive message buffer is deactivated while a message is being transferred into it, the transfer is halted and no interrupt is requested. if this occurs, that receive message buffer may contain mixed data from two different frames. motorola chapter 16. can 2.0b controller module 16-17 toucan operation the cpu should not write data into a receive message buffer. if this occurs while a message is being transferred from a serial message buffer, the control/status word will reflect a full or overrun condition, but no interrupt is requested. 16.4.4.2 locking and releasing message buffers the lock/release/busy mechanism is designed to guarantee data coherency during the receive process. the following examples demonstrate how the lock/release/busy mechanism affects toucan operation. 1. reading a control/status word of a message buffer triggers a lock for that message buffer. a new received message frame which matches the message buffer cannot be written into this message buffer while it is locked. 2. to release a locked message buffer, the cpu either locks another message buffer by reading its control/status word or globally releases any locked message buffer by reading the free-running timer. 3. if a receive frame with a matching id is received during the time the message buffer is locked, the receive frame is not immediately transferred into that message buffer, but remains in the serial message buffer. there is no indication when this occurs. 4. when a locked message buffer is released, if a frame with a matching identifier exists within the serial message buffer, then this frame is transferred to the matching message buffer. 5. if two or more receive frames with matching ids are received while a message buffer with a matching id is locked, the last received frame with that id is kept within the serial message buffer, while all preceding ones are lost. there is no indication when this occurs. 6. if the control/status word of a receive message buffer is read while a frame is being transferred from a serial message buffer, the busy code is indicated. the user should wait until this code is cleared before continuing to read from the message buffer to ensure data coherency. in this situation, the read of the control/status word does not lock the message buffer. polling the control/status word of a receive message buffer can lock it, preventing a message from being transferred into that buffer. if the control/status word of a receive message buffer is read, it should be followed by a read of the control/status word of another buffer, or by a read of the free-running timer, to ensure that the locked buffer is unlocked. 16.4.5 remote frames the remote frame is a message frame that is transmitted to request a data frame. the toucan can be configured to transmit a data frame automatically in response to a remote 16-18 mpc565/mpc566 reference manual motorola special operating modes frame, or to transmit a remote frame and then wait for the responding data frame to be received. to transmit a remote frame, a message buffer is initialized as a transmit message buffer with the rtr bit set to one. once this remote frame is transmitted successfully, the transmit message buffer automatically becomes a receive message buffer, with the same id as the remote frame that was transmitted. when the toucan receives a remote frame, it compares the remote frame id to the ids of all transmit message buffers programmed with a code of 1010. if there is an exact matching id, the data frame in that message buffer is transmitted. if the rtr bit in the matching transmit message buffer is set, the toucan transmits a remote frame as a response. a received remote frame is not stored in a receive message buffer. it is only used to trigger the automatic transmission of a frame in response. the mask registers are not used in remote frame id matching. all id bits (except rtr) of the incoming received frame must match for the remote frame to trigger a response transmission. 16.4.6 overload frames the toucan does not initiate overload frame transmissions unless it detects the following conditions on the can bus: a dominant bit is the first or second bit of intermission a dominant bit is the seventh (last) bit of the end-of-frame (eof) field in receive frames a dominant bit is the eighth (last) bit of the error frame delimiter or overload frame delimiter 16.5 special operating modes the toucan module has three special operating modes: debug mode low-power stop mode auto power save mode 16.5.1 debug mode debug mode is entered when the frz1 bit in canmcr is set and one of the following events occurs: the halt bit in the canmcr is set; or the imb3 freeze line is asserted motorola chapter 16. can 2.0b controller module 16-19 special operating modes once entry into debug mode is requested, the toucan waits until an intermission or idle condition exists on the can bus, or until the toucan enters the error passive or bus off state. once one of these conditions exists, the toucan waits for the completion of all internal activity. once this happens, the following events occur: the toucan stops transmitting or receiving frames the prescaler is disabled, thus halting all can bus communication the toucan ignores its rx pins and drives its tx pins as recessive the toucan loses synchronization with the can bus and the notrdy and frzack bits in canmcr are set the cpu is allowed to read and write the error counter registers after engaging one of the mechanisms to place the toucan in debug mode, the frzack bit must be set before accessing any other registers in the toucan; otherwise unpredictable operation may occur. to exit debug mode, the imb freeze line must be negated or the halt bit in canmcr must be cleared. once debug mode is exited, the toucan resynchronizes with the can bus by waiting for 11 consecutive recessive bits before beginning to participate in can bus communication. 16.5.2 low-power stop mode before entering low-power stop mode, the toucan waits for the can bus to be in an idle state, or for the third bit of intermission to be recessive. the toucan then waits for the completion of all internal activity (except in the can bus interface) to be complete. then the following events occur: the toucan shuts down its clocks, stopping most internal circuits, thus achieving maximum power savings the bus interface unit continues to operate, allowing the cpu to access the module configuration register the toucan ignores its rx pins and drives its tx pins as recessive the toucan loses synchronization with the can bus, and the stopack and notrdy bits in the module configuration register are set to exit low-power stop mode: reset the toucan either by asserting one of the imb3 reset lines or by asserting the softrst bit canmcr clear the stop bit in canmcr the toucan module can optionally exit low-power stop mode via the self wake mechanism. if the selfwake bit in canmcr was set at the time the toucan 16-20 mpc565/mpc566 reference manual motorola special operating modes entered stop mode, then upon detection of a recessive to dominant transition on the can bus, the toucan clears the stop bit in canmcr and its clocks begin running. when the toucan is in low-power stop mode, a recessive to dominant transition on the can bus causes the wakeint bit in the error and status register (estat) to be set. this event generates an interrupt if the wakemsk bit in canmcr is set. consider the following notes regarding low-power stop mode: when the self wake mechanism is activated, the toucan tries to receive the frame that woke it up. (it assumes that the dominant bit detected is a start-of-frame bit.) it will not arbitrate for the can bus at this time. if the stop bit is set while the toucan is in the bus off state, then the toucan enters low-power stop mode and stops counting recessive bit times. the count continues when stop is cleared. to place the toucan in low-power stop mode with the self wake mechanism engaged, write to canmcr with both stop and selfwake set, and then wait for the toucan to set the stopack bit. to take the toucan out of low-power stop mode when the self wake mechanism is enabled, write to canmcr with both stop and selfwake clear, and then wait for the toucan to clear the stopack bit. the selfwake bit should not be set after the toucan has already entered low-power stop mode. if both stop and selfwake are set and a recessive to dominant edge immediately occurs on the can bus, the toucan may never set the stopack bit, and the stop bit will be cleared. to prevent old frames from being sent when the toucan awakes from low-power stop mode via the self wake mechanism, disable all transmit sources, including transmit buffers configured for remote request responses, before placing the toucan in low-power stop mode. if the toucan is in debug mode when the stop bit is set, the toucan assumes that debug mode should be exited. as a result, it tries to synchronize with the can bus, and only then does it await the conditions required for entry into low-power stop mode. unlike other modules, the toucan does not come out of reset in low-power stop mode. the basic toucan initialization procedure should be executed before placing the module in low-power stop mode. (refer to section 16.4.2, ?toucan initialization.?) if the toucan is in low-power stop mode with the self wake mechanism engaged and is operating with a single system clock per time quantum, there can be extreme cases in which the toucan would wake-up on a recessive to dominant edge which motorola chapter 16. can 2.0b controller module 16-21 interrupts may not conform to the can protocol. toucan synchronization is shifted one time quantum from the wake-up event. this shift lasts until the next recessive-to-dominant edge, which resynchronizes the toucan to be in conformance with the can protocol. the same holds true when the toucan is in auto power save mode and awakens on a recessive to dominant edge. 16.5.3 auto power save mode auto power save mode enables normal operation with optimized power savings. once the auto power save (aps) bit in canmcr is set, the toucan looks for a set of conditions in which there is no need for the clocks to be running. if these conditions are met, the toucan stops its clocks, thus saving power. the following conditions activate auto power save mode. no rx/tx frame in progress no transfer of rx/tx frames to and from a serial message buffer, and no tx frame awaiting transmission in any message buffer no cpu access to the toucan module the toucan is not in debug mode, low-power stop mode, or the bus off state while its clocks are stopped, if the toucan senses that any one of the aforementioned conditions is no longer true, it restarts its clocks. the toucan then continues to monitor these conditions and stops or restarts its clocks accordingly. 16.6 interrupts the toucan can generate one interrupt level to be passed to the cpu. this level is programmed into the priority level bits in the interrupt configuration register (canicr). this value determines which interrupt signal is driven onto the bus when an interrupt is requested. each one of the 16 message buffers can be an interrupt source, if its corresponding imask bit is set. there is no distinction between transmit and receive interrupts for a particular buffer. each of the buffers is assigned a bit in the iflag register. an iflag bit is set when the corresponding buffer completes a successful transmission/reception. an iflag bit is cleared when the cpu reads iflag while the associated bit is set, and then writes it back as zero (and no new event of the same type occurs between the read and the write actions). the other three interrupt sources (bus off, error and wake up) act in the same way, and have flag bits located in the error and status register (estat). the bus off and error interrupt mask bits (boffmsk and errmsk) are located in canctrl0, and the wake up interrupt mask bit (wakemsk) is located in the module configuration register. refer to section 16.7, ?programmer?s model? for more information on these registers. 16-22 mpc565/mpc566 reference manual motorola programmer?s model the toucan module is capable of generating one of the 32 possible interrupt levels on the imb3. the 32 interrupt levels are time multiplexed on the imb3 irq[0:7] lines. all interrupt sources place their asserted level on a time multiplexed bus during four different time slots, with eight levels communicated per slot. the ilbs[0:1] signals indicate which group of eight are being driven on the interrupt request lines. the level that the toucan will drive onto internal irq[7:0] signals is programmed in the three interrupt request level (irl) bits located in the interrupt configuration register. the two ilbs bits in the icr register determine on which slot the toucan should drive its interrupt signal. under the control of ilbs, each interrupt request level is driven during the time multiplexed bus during one of four different time slots, with eight levels communicated per time slot. no hardware priority is assigned to interrupts. furthermore, if more than one source on a module requests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. figure 16-6 displays the interrupt levels on irq with ilbs. figure 16-6. interrupt levels on irq with ilbs 16.7 programmer?s model table 16-10 shows the toucan address map. the lowercase ?x? appended to each register name represents ?a?, ?b? or ?c? for the toucan_a, toucan_b or toucan_c module, respectively. refer to figure 1-2 to locate each toucan module in the mpc565/mpc566 address map. the column labeled ?access? indicates the privilege level at which the cpu must be operating to access the register. a designation of ?s? indicates that supervisor mode is table 16-9. interrupt levels ilbs[0:1] levels 00 0:7 01 8:15 10 16:23 11 24:31 imb3 clock ilbs [1:0] imb3 irq [7:0] irq 7:0 00 01 11 10 irq 15:8 irq 23:16 irq 31:24 irq 7:0 00 01 11 10 motorola chapter 16. can 2.0b controller module 16-23 programmer?s model required. a designation of ?s/u? indicates that the register can be programmed for either supervisor mode access or unrestricted access. the address space for each toucan module is split, with 128 bytes starting at the base address, and an extra 256 bytes starting at the base address +128. the upper 256 are fully used for the message buffer structures. of the lower 128 bytes, some are not used. registers with bits marked as ?reserved? should always be written as logic 0. typically, the toucan control registers are programmed during system initialization, before the toucan becomes synchronized with the can bus. the configuration registers can be changed after synchronization by halting the toucan module. this is done by setting the halt bit in the toucan module configuration register (canmcr). the toucan responds by asserting the canmcr notrdy bit. additionally, the control registers can be modified while the mcu is in background debug mode. note the toucan has no hard-wired protection against invalid bit/field programming within its registers. specifically, no protection is provided if the programming does not meet can protocol requirements. table 16-10. toucan register map access address msb 0 lsb 15 s 0x30 7080(a) 0x30 7480(b) 0x30 7880(c) toucan module configuration register (canmcr_x) see table 16-11 for bit descriptions. s 0x30 7082(a) 0x30 7482(b) 0x30 7882(c) toucan test register (cantcr_x) s 0x30 7084(a) 0x30 7484(b) 0x30 7884(c) toucan interrupt register (canicr_x) s/u 0x30 7086(a) 0x30 7486(b) 0x30 7886(c) control register 0 (canctrl0_x) see table 16-13 and table 16-16 for bit descriptions. control register 1 (canctrl1_x) s/u 0x30 7088(a) 0x30 7488(b) 0x30 7888(c) control and prescaler divider register (presdiv_x) see table 16-17 and table 16-18 for bit descriptions. control register 2 (canctrl2_x) s/u 0x30 708a(a) 0x30 748a(b) 0x30 788a(c) free-running timer register (timer_x) see table 16-19 for bit descriptions. ? 0x30 708c ? 0x30 708e(a)) 0x30 748c ? 0x30 748e(b) 0x30 788c ? 0x30 788e(c) reserved 16-24 mpc565/mpc566 reference manual motorola programmer?s model s/u 0x30 7090(a) 0x30 7490(b) 0x30 7890(c) receive global mask ? high (rxgmskhi_x) see table 16-20 for bit descriptions. s/u 0x30 7092(a) 0x30 7492(b) 0x30 7892(c) receive global mask ? low (rxgmsklo_x) see table 16-20 for bit descriptions. s/u 0x30 7094(a) 0x30 7494(b) 0x30 7894(c) receive buffer 14 mask ? high (rx14mskhi_x) see section 16.7.10, ?receive buffer 14 mask registers? for bit descriptions. s/u 0x30 7096(a) 0x30 7496(b) 0x30 7896(c) receive buffer 14 mask ? low (rx14msklo_x) see section 16.7.10, ?receive buffer 14 mask registers? for bit descriptions. s/u 0x30 7098(a) 0x30 7498(b) 0x30 7898(c) receive buffer 15 mask ? high (rx15mskhi_x) see section 16.7.11, ?receive buffer 15 mask registers? for bit descriptions. s/u 0x30 709a(a) 0x30 749a(b) 0x30 789a(c) receive buffer 15 mask ? low (rx15msklo_x) see section 16.7.11, ?receive buffer 15 mask registers? for bit descriptions. ? 0x30 709c ? 0x30 709e(a) 0x30 749c? 0x30 749e(b) 0x30 789c ? 0x30 789e(c) reserved s/u 0x30 70a0(a) 0x30 74a0(b) 0x30 78a0(c) error and status register (estat_x) see table 16-21 for bit descriptions. s/u 0x30 70a2(a) 0x30 74a2(b) 0x30 78a2(c) interrupt masks (imask_x) see table 16-24 for bit descriptions. s/u 0x30 70a4(a) 0x30 74a4(b) 0x30 78a4(c) interrupt flags (iflag_x) see table 16-25 for bit descriptions. s/u 0x30 70a6(a) 0x30 74a6(b) 0x30 78a6(c) receive error counter (rxectr_x) see table 16-26 for bit descriptions. transmit error counter (txectr_x) s/u 0x30 7100 ? 0x30 710f(a) 0x30 7500 ? 0x30 750f(b) 0x30 7500 ? 0x30 790f(c) mbuff0 1 toucan_a message buffer 0. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 7110 ? 0x30 711f(a) 0x30 7510 ? 0x30 751f(b) 0x30 7910 ? 0x30 791f(c) mbuff1 1 toucan_a message buffer 1. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 7120 ? 0x30 712f(a) 0x30 7520 ? 0x30 752f(b) 0x30 7920 ? 0x30 792f(c) mbuff2 1 toucan_a message buffer 2. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 7130 ? 0x30 713f(a) 0x30 7530 ? 0x30 753f(b) 0x30 7930 ? 0x30 793f(c) mbuff3 1 toucan_a message buffer 3. see table 16-3 and table 16-4 for message buffer definitions. table 16-10. toucan register map (continued) access address msb 0 lsb 15 motorola chapter 16. can 2.0b controller module 16-25 programmer?s model s/u 0x30 7140 ? 0x30 714f(a) 0x30 7540 ? 0x30 754f(b) 0x30 7940 ? 0x30 794f(c) mbuff4 1 toucan_a message buffer 4. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 7150 ? 0x30 715f(a) 0x30 7550 ? 0x30 755f(b) 0x30 7950 ? 0x30 795f(c) mbuff5 1 toucan_a message buffer 5. see table 16-3 and table 16-3 for message buffer definitions. s/u 0x30 7160 ? 0x30 716f(a) 0x30 7560 ? 0x30 756f(b) 0x30 7960 ? 0x30 796f(c) mbuff6 1 toucan_a message buffer 6. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x307170 ? 0x30717f(a) 0x30 7570 ? 0x30 757f(b) 0x30 7970 ? 0x30 797f(c) mbuff7 1 toucan_a message buffer 7. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 7180 ? 0x30 718f(a) 0x30 7580 ? 0x30 758f(b) 0x30 7980 ? 0x30 798f(c) mbuff8 1 toucan_a message buffer 8. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 7190 ? 0x30 719f(a) 0x30 7590 ? 0x30 759f(b) 0x30 7990 ? 0x30 799f(c) mbuff9 1 toucan_a message buffer 9. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 71a0 ? 0x30 71af(a) 0x30 75a0 ? 0x30 75af(b) 0x30 79a0 ? 0x30 79af(c) mbuff10 1 toucan_a message buffer 10. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 71b0 ? 0x30 71bf(a) 0x30 75b0 ? 0x30 75bf(b) 0x30 79b0 ? 0x30 79bf(c) mbuff11 1 toucan_a message buffer 11. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 71c0 ? 0x30 71cf(a) 0x30 75c0 ? 0x30 75cf(b) 0x30 79c0 ? 0x30 79cf(c) mbuff12 1 toucan_a message buffer 12. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 71d0 ? 0x30 71df(a) 0x30 75d0 ? 0x30 75df(b) 0x30 79d0 ? 0x30 79df(c) mbuff13 1 toucan_a message buffer 13. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 71e0 ? 0x30 71ef(a) 0x30 75e0 ? 0x30 75ef(b) 0x30 79e0 ? 0x30 79ef(c) mbuff14 1 toucan_a message buffer 14. see table 16-3 and table 16-4 for message buffer definitions. s/u 0x30 71f0 ? 0x30 71ff(a) 0x30 75f0 ? 0x30 75ff(b) 0x30 79f0 ? 0x30 79ff(c) mbuff15 1 toucan_a message buffer 15. see table 16-3 and table 16-4 for message buffer definitions. 1 the last word of each of the mbuff arrays (address 0x....e) is reserved and may cause a rcpu exception if read. table 16-10. toucan register map (continued) access address msb 0 lsb 15 16-26 mpc565/mpc566 reference manual motorola programmer?s model figure 16-7. toucan message buffer memory map 16.7.1 toucan module configuration register msb 0 1 2 3 4 5 6 7 8 9 10 11 121314lsb 15 stop frz rese rved halt not rdy wake msk soft rst frz ack supv self wake aps stop ack reserved reset: 0 1 0 1 1 0 0 1 1 0 0 0 0000 figure 16-8. canmcr ? toucan module configuration register 0x30 7080 0x30 7480 0x30 7880 0x30 7100, 0x30 7500 0x30 7102, 0x30 7502 id low message buffer 0 0x30 7104, 0x30 7504 0x30 7106, 0x30 7506 0x30 710d, 0x30 750d 0x30 710e, 0x30 750e 0x30 7110, 0x30 7510 message buffer 1 0x30 7120, 0x30 7520 0x3071ff, 0x3075ff message buffer 2 message buffer 15 control/status id high 8-byte data field reserved , 0x30 7900 , 0x30 7902 , 0x30 7904 , 0x30 7906 , 0x30 790d ,0x30790e , 0x30 7910 , 0x30 7920 ,0x3079ff motorola chapter 16. can 2.0b controller module 16-27 programmer?s model table 16-11. canmcr bit descriptions bit(s) name description 0 stop low-power stop mode enable. the stop bit may only be set by the cpu. it may be cleared either by the cpu or by the toucan, if the selfwake bit is set. 0 enable toucan clocks 1 disable toucan clocks 1 frz freeze assertion response. when frz = 1, the toucan can enter debug mode when the imb3 freeze line is asserted or the halt bit is set. clearing this bit field causes the toucan to exit debug mode. refer to section 16.5.1, ?debug mode for more information. 0 toucan ignores the imb3 freeze signal and the halt bit in the module configuration register. 1 toucan module enabled to enter debug mode. 2?reserved 3 halt halt toucan s-clock. setting the halt bit has the same effect as assertion of the imb3 freeze signal on the toucan without requiring that freeze be asserted. this bit is set to one after reset. it should be cleared after initializing the message buffers and control registers. toucan message buffer receive and transmit functions are inactive until this bit is cleared. when halt is set, write access to certain registers and bits that are normally read-only is allowed. 0 the toucan operates normally 1 toucan enters debug mode if frz = 1 4 notrdy toucan not ready. this bit indicates that the toucan is either in low-power stop mode or debug mode. this bit is read-only and is set only when the toucan enters low-power stop mode or debug mode. it is cleared once the toucan exits either mode, either by synchronization to the can bus or by the self wake mechanism. 0 toucan has exited low-power stop mode or debug mode. 1 toucan is in low-power stop mode or debug mode. 5 wakemsk wakeup interrupt mask. the wakemsk bit enables wake-up interrupt requests. 0 wake up interrupt is disabled 1 wake up interrupt is enabled 6 softrst soft reset. when this bit is asserted, the toucan resets its internal state machines (sequencer, error counters, error flags, and timer) and the host interface registers (canmcr, canicr, cantcr, imask, and iflag). the configuration registers that control the interface with the can bus are not changed (canctrl[0:2] and presdiv). message buffers and receive message masks are also not changed. this allows softrst to be used as a debug feature while the system is running. setting softrst also clears the stop bit in canmcr. after setting softrst, allow one complete bus cycle to elapse for the internal toucan circuitry to completely reset before executing another access to canmcr. the toucan clears this bit once the internal reset cycle is completed. 0 soft reset cycle completed 1 soft reset cycle initiated 7 frzack toucan disable. when the toucan enters debug mode, it sets the frzack bit. this bit should be polled to determine if the toucan has entered debug mode. when debug mode is exited, this bit is negated once the toucan prescaler is enabled. this is a read-only bit. 0 the toucan has exited debug mode and the prescaler is enabled 1 the toucan has entered debug mode, and the prescaler is disabled 16-28 mpc565/mpc566 reference manual motorola programmer?s model 16.7.2 toucan test configuration register cantcr ? toucan test configuration register0x30 7082, 0x30 7482, 0x30 7882 this register is used for factory test only. 16.7.3 toucan interrupt configuration register 8 supv supervisor/user data space. the supv bit places the toucan registers in either supervisor or user data space. 0 registers with access controlled by the supv bit are accessible in either user or supervisor privilege mode 1 registers with access controlled by the supv bit are restricted to supervisor mode 9 selfwake self wake enable. this bit allows the toucan to wake up when bus activity is detected after the stop bit is set. if this bit is set when the toucan enters low-power stop mode, the toucan will monitor the bus for a recessive to dominant transition. if a recessive to dominant transition is detected, the toucan immediately clears the stop bit and restarts its clocks. if a write to canmcr with selfwake set occurs at the same time a recessive-to-dominant edge appears on the can bus, the bit will not be set, and the module clocks will not stop. the user should verify that this bit has been set by reading canmcr. refer to section 16.5.2, ?low-power stop mode for more information on entry into and exit from low-power stop mode. 0 self wake disabled 1 self wake enabled 10 aps auto power save. the aps bit allows the toucan to automatically shut off its clocks to save power when it has no process to execute, and to automatically restart these clocks when it has a task to execute without any cpu intervention. 0 auto power save mode disabled; clocks run normally 1 auto power save mode enabled; clocks stop and restart as needed 11 stopack stop acknowledge. when the toucan is placed in low-power stop mode and shuts down its clocks, it sets the stopack bit. this bit should be polled to determine if the toucan has entered low-power stop mode. when the toucan exits low-power stop mode, the stopack bit is cleared once the toucan?s clocks are running. 0 the toucan is not in low-power stop mode and its clocks are running 1 the toucan has entered low-power stop mode and its clocks are stopped 12:15 ? reserved. these bits are used for the iarb (interrupt arbitration id) field in toucan implementations that use hardware interrupt arbitration. msb 0 1234567891011121314lsb 15 reserved irl ilbs reserved reset: 0000000000 0 01111 figure 16-9. canicr ? toucan interrupt configuration register 0x30 7084 0x30 7484 0x30 7884 table 16-11. canmcr bit descriptions (continued) bit(s) name description motorola chapter 16. can 2.0b controller module 16-29 programmer?s model 16.7.4 control register 0 table 16-12. canicr bit descriptions bit(s) name description 0:4 ? reserved 5:7 irl interrupt request level. when the toucan generates an interrupt request, this field determines which of the interrupt request signals is asserted. 8:9 ilbs interrupt level byte select. this field selects one of four time-multiplexed slots during which the interrupt request is asserted. the ilbs and irl fields together select one of 32 effective interrupt levels. 00 levels 0 to7 01 levels 8 to 15 10 levels 16 to 23 11 levels 24 to 31 10:15 ? reserved msb 0 1234567891011121314lsb 15 boff msk err msk reserved rxmod txmode canctrl1 reset: 0000000000 0 00000 figure 16-10. canctrl0 ? control register 0 0x30 7086 0x30 7486 0x30 7886 table 16-13. canctrl0 bit descriptions bit(s) name description 0 boffmsk bus off interrupt mask. the boff mask bit provides a mask for the bus off interrupt. 0 bus off interrupt disabled 1 bus off interrupt enabled 1 errmsk error interrupt mask. the errmsk bit provides a mask for the error interrupt. 0 error interrupt disabled 1 error interrupt enabled 2:3 ? 4:5 rxmode receive pin configuration control. these bits control the configuration of the canrx0 and canrx1 pins. refer to the table 16-14. 6:7 txmode transmit pin configuration control. this bit field controls the configuration of the cantx0 and cantx1 pins. refer to table 16-15. 8:15 canctrl1 see table 16-16 and section 16.7.5, ?control register 1?. 16-30 mpc565/mpc566 reference manual motorola programmer?s model 16.7.5 control register 1 table 16-14. rx mode[1:0] configuration pin rx1 rx0 receive pin configuration cnrx1 1 1 the cnrx1 signal is not available on the mpc565. 0 x a logic zero on the cnrx1 pin is interpreted as a dominant bit; a logic one on the cnrx1 pin is interpreted as a recessive bit 1 x a logic one on the cnrx1 pin is interpreted as a dominant bit; a logic zero on the cnrx1 pin is interpreted as a recessive bit cnrx0 x 0 a logic zero on the cnrx0 pin is interpreted as a dominant bit; a logic one on the cnrx0 pin is interpreted as a recessive bit x 1 a logic one on the cnrx0 pin is interpreted as a dominant bit; a logic zero on the cnrx0 pin is interpreted as a recessive bit table 16-15. transmit pin configuration txmode[1:0] transmit pin configuration 00 full cmos 1 ; positive polarity (cntx0 = 0, cntx1 = 1 is a dominant level) 2 1 full cmos drive indicates that both dominant and recessive levels are driven by the chip. 2 the cnrx1 signal is not available on the mpc565. 01 full cmos 1 ; negative polarity (cntx0 = 1, cntx1 = 0 is a dominant level) 2 1x open drain 3 ; positive polarity 3 open drain drive indicates that only a dominant level is driven by the chip. during a recessive level, the cntx0 and cntx1 pins are disabled (three stated), and the electrical level is achieved by external pull-up/pull-down devices. the assertion of both tx mode bits causes the polarity inversion to be cancelled (open drain mode forces the polarity to be positive). msb 0 12345678 9 1011121314lsb 15 canctrl0 sam p reserv ed tsyn c lbuf rese rved propseg reset: 000000000 0 0 0 0 000 figure 16-11. canctrl1 ? control register 1 0x30 7086 0x30 7486 0x30 7886 motorola chapter 16. can 2.0b controller module 16-31 programmer?s model 16.7.6 prescaler divide register table 16-16. canctrl1 bit descriptions bit(s) name description 0:7 canctrl0 see table 16-13 8 samp sampling mode. the samp bit determines whether the toucan module will sample each received bit one time or three times to determine its value. 0 one sample, taken at the end of phase buffer segment one, is used to determine the value of the received bit. 1 three samples are used to determine the value of the received bit. the samples are taken at the normal sample point and at the two preceding periods of the s-clock. 9?reserved 10 tsync timer synchronize mode. the tsync bit enables the mechanism that resets the free-running timer each time a message is received in message buffer zero. this feature provides the means to synchronize multiple toucan stations with a special ?sync? message (global network time). 0 timer synchronization disabled. 1 timer synchronization enabled. note: there can be a bit clock skew of four to five counts between different toucan modules that are using this feature on the same network. 11 lbuf lowest buffer transmitted first. the lbuf bit defines the transmit-first scheme. 0 message buffer with lowest id is transmitted first. 1 lowest numbered buffer is transmitted first. 12 ? reserved 13:15 propseg propagation segment time. propseg defines the length of the propagation segment in the bit time. the valid programmed values are zero to seven. the propagation segment time is calculated as follows: propagation segment time = (propseg + 1) time quanta where 1 time quantum = 1 serial clock (s-clock) period msb 0 1234567891011121314lsb 15 presdiv canctrl2 reset: 0000000000 0 00000 figure 16-12. presdiv ? prescaler divide register 0x30 7088 0x30 7488 0x30 7888 16-32 mpc565/mpc566 reference manual motorola programmer?s model 16.7.7 control register 2 table 16-17. presdiv bit descriptions bit(s) name description 0:7 presdiv prescaler divide factor. presdiv determines the ratio between the system clock frequency and the serial clock (s-clock). the s-clock is determined by the following calculation: the reset value of presdiv is 0x00, which forces the s-clock to default to the same frequency as the system clock. the valid programmed values are 0 through 255. 8:15 canctrl2 see table 16-18. msb 0 1234567891011121314lsb 15 presdiv rjw pseg1 pseg2 reset: 0000000000 0 00000 figure 16-13. canctrl2 ? control register 2 0x30 7088 0x30 7488 0x30 7888 table 16-18. canctrl2 bit descriptions bit(s) name description 0:7 presdiv see table 16-17. 8:9 rjw resynchronization jump width. the rjw field defines the maximum number of time quanta a bit time may be changed during resynchronization. the valid programmed values are zero through three. the resynchronization jump width is calculated as follows: resynchronizaton jump width = (rjw + 1) time quanta 10:12 pseg1 pseg1[2:0] ? phase buffer segment 1. the pseg1 field defines the length of phase buffer segment one in the bit time. the valid programmed values are zero through seven. the length of phase buffer segment 1 is calculated as follows: phase buffer segment 1 = (pseg1 + 1) time quanta 13:15 pseg2 pseg2 ? phase buffer segment 2. the pseg2 field defines the length of phase buffer segment two in the bit time. the valid programmed values are zero through seven. the length of phase buffer segment two is calculated as follows: phase buffer segment 2 = (pseg2 + 1) time quanta s-clock f sys presdiv 1 + --------------------------------- - = motorola chapter 16. can 2.0b controller module 16-33 programmer?s model 16.7.8 free running timer 16.7.9 receive global mask registers msb 0 1234567891011121314lsb 15 timer reset: 0000000000 0 00000 figure 16-14. timer ? free running timer register 0x30 708a 0x30 748a 0x30 788a table 16-19. timer bit descriptions bit(s) name description 0:15 timer the free running timer counter can be read and written by the cpu. the timer starts from zero after reset, counts linearly to 0xffff, and wraps around. the timer is clocked by the toucan bit-clock. during a message, it increments by one for each bit that is received or transmitted. when there is no message on the bus, it increments at the nominal bit rate. the timer value is captured at the beginning of the identifier field of any frame on the can bus. the captured value is written into the ?time stamp? entry in a message buffer after a successful reception or transmission of a message. msb 0 123456789101112131415 mid2 8 mid2 7 mid2 6 mid2 5 mid2 4 mid2 3 mid2 2 mid2 1 mid2 0 mid1 9 mid18 0 1 mid1 7 mid1 6 mid1 5 reset: 1111111111 1 01111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 mid1 4 mid1 3 mid1 2 mid1 1 mid1 0 mid9 mid8 mid7 mid6 mid5 mid4 mid3 mid2 mid1 mid0 0 reset: 1111111111 1 11110 figure 16-15. rxgmskhi ? receive global mask register high 0x30 7090 0x30 7490 0x30 7890 rxgmsklo ? receive global mask register low 0x30 7092 0x30 7492 0x30 7892 16-34 mpc565/mpc566 reference manual motorola programmer?s model 16.7.10receive buffer 14 mask registers rx14mskhi ? receive buffer 14 mask register high 0x30 7094, 0x30 7494, 0x30 7894 rx14msklo ? receive buffer 14 mask register low 0x30 7096, 0x30 7496, 0x30 7896 the receive buffer 14 mask registers have the same structure as the receive global mask registers and are used to mask buffer 14. 16.7.11receive buffer 15 mask registers rx15mskhi ? receive buffer 15 mask register high 0x30 7098, 0x30 7498, 0x30 7898 rx15msklo ? receive buffer 15 mask register low 0x30 709a, 0x30 749a, 0x30 789a the receive buffer 15 mask registers have the same structure as the receive global mask registers and are used to mask buffer 15. 16.7.12error and status register table 16-20. rxgmskhi, rxgmsklo bit descriptions bit(s) name description 0:31 midx the receive global mask registers use four bytes. the mask bits are applied to all receive-identifiers, excluding receive-buffers 14 and 15, which have their own specific mask registers. base id mask bits mid[28:18] are used to mask standard or extended format frames. extended id bits mid[17:0] are used to mask only extended format frames. the rtr/srr bit of a received frame is never compared to the corresponding bit in the message buffer id field. however, remote request frames (rtr = 1) once received, are never stored into the message buffers. rtr mask bit locations in the mask registers (bits 11 and 31) are always zero, regardless of any write to these bits. the ide bit of a received frame is always compared to determine if the message contains a standard or extended identifier. its location in the mask registers (bit 12) is always one, regardless of any write to this bit. msb 0 12 3 4 5 6 7 8 9101112 1314lsb 15 biter ack err crc err form err stuff err tx warn rx warn idle tx/rx fcs rese rved boff int err int wake int reset: 000 0 0 0 0 0 0 0 00 0 0 0 0 figure 16-16. estat ? error and status register 0x30 70a0 0x30 74a0 0x30 78a0 motorola chapter 16. can 2.0b controller module 16-35 programmer?s model this register reflects various error conditions, general status, and has the enable bits for three of the toucan interrupt sources. the reported error conditions are those which have occurred since the last time the register was read. a read clears these bits to zero. table 16-21. estat bit descriptions bit(s) name description 0:1 biterr transmit bit error. the biterr[1:0] field is used to indicate when a transmit bit error occurs. refer to table 16-22. note: the transmit bit error field is not modified during the arbitration field or the ack slot bit time of a message, or by a transmitter that detects dominant bits while sending a passive error frame. 2 ackerr acknowledge error. the ackerr bit indicates whether an acknowledgment has been correctly received for a transmitted message. 0 no ack error was detected since the last read of this register 1 an ack error was detected since the last read of this register 3 crcerr cyclic redundancy check error. the crcerr bit indicates whether or not the crc of the last transmitted or received message was valid. 0 no crc error was detected since the last read of this register 1 a crc error was detected since the last read of this register 4 formerr message format error. the formerr bit indicates whether or not the message format of the last transmitted or received message was correct. 0 no format error was detected since the last read of this register 1 a format error was detected since the last read of this register 5 stufferr bit stuff error. the stufferr bit indicates whether or not the bit stuffing that occurred in the last transmitted or received message was correct. 0 no bit stuffing error was detected since the last read of this register 1 a bit stuffing error was detected since the last read of this register 6 txwarn transmit error status flag. the txwarn status flag reflects the status of the toucan transmit error counter. 0 transmit error counter < < 16-36 mpc565/mpc566 reference manual motorola programmer?s model 13 boffint bus off interrupt. the boffint bit is used to request an interrupt when the toucan enters the bus off state. 0 no bus off interrupt requested 1 when the toucan state changes to bus off, this bit is set, and if the boffmsk bit in canctrl0 is set, an interrupt request is generated. this interrupt is not requested after reset. 14 errint error interrupt. the errint bit is used to request an interrupt when the toucan detects a transmit or receive error. 0 no error interrupt request 1 if an event which causes one of the error bits in the error and status register to be set occurs, the error interrupt bit is set. if the errmsk bit in canctrl0 is set, an interrupt request is generated. to clear this bit, first read it as a one, then write as a zero. writing a one has no effect. 15 wakeint wake interrupt. the wakeint bit indicates that bus activity has been detected while the toucan module is in low-power stop mode. 0 no wake interrupt requested 1 when the toucan is in low-power stop mode and a recessive to dominant transition is detected on the can bus, this bit is set. if the wakemsk bit is set in canmcr, an interrupt request is generated. table 16-22. transmit bit error status biterr[1:0] bit error status 00 no transmit bit error 01 at least one bit sent as dominant was received as recessive 10 at least one bit sent as recessive was received as dominant 11 not used table 16-23. fault confinement state encoding fcs[1:0] bus state 00 error active 01 error passive 1x bus off table 16-21. estat bit descriptions (continued) bit(s) name description motorola chapter 16. can 2.0b controller module 16-37 programmer?s model 16.7.13interrupt mask register 16.7.14interrupt flag register msb 0 1234567891011121314lsb 15 imaskh imaskl reset: 0000000000 0 00000 figure 16-17. imask ? interrupt mask register 0x30 70a2 0x30 74a2 0x30 78a2 table 16-24. imask bit descriptions bit(s) name description 0:7, 8:15 imaskh, imaskl imask contains two 8-bit fields, imaskh and imaskl. imask can be accessed with a 16-bit read or write, and imaskh and imaskl can be accessed with byte reads or writes. imask contains one interrupt mask bit per buffer. it allows the cpu to designate which buffers will generate interrupts after successful transmission/reception. setting a bit in imask enables interrupt requests for the corresponding message buffer. msb 0 1234567891011121314lsb 15 iflagh iflagl reset: 0000000000 0 00000 figure 16-18. iflag ? interrupt flag register 0x30 70a4 0x30 74a4 0x30 78a4 table 16-25. iflag bit descriptions bit(s) name description 0:7, 8:15 iflagh, iflagl iflag contains two 8-bit fields, iflagh and iflagl. iflag can be accessed with a 16-bit read or write, and iflagh and iflagl can be accessed with byte reads or writes. iflag contains one interrupt flag bit per buffer. each successful transmission/reception sets the corresponding iflag bit and, if the corresponding imask bit is set, an interrupt request will be generated. to clear an interrupt flag, first read the flag as a one, and then write it as a zero. should a new flag setting event occur between the time that the cpu reads the flag as a one and writes the flag as a zero, the flag is not cleared. this register can be written to zeros only. 16-38 mpc565/mpc566 reference manual motorola programmer?s model 16.7.15error counters msb 0 1234567891011121314lsb 15 rxectr txectr reset: 0000000000 0 00000 figure 16-19. rxectr ? receive error counter0x30 70a6 0x30 74a6 0x30 78a6 txectr ? transmit error counter table 16-26. rxectr, txectr bit descriptions bit(s) name description 0:7, 8:15 rxectr, txectr both counters are read only, except when the toucan is in test or debug mode. motorola chapter 17. modular input/output subsystem (mios14) 17-1 chapter 17 modular input/output subsystem (mios14) the modular i/o system (mios) consists of a library of flexible i/o and timer functions including i/o port, counters, input capture, output compare, pulse and period measurement, and pwm. because the mios14 is composed of submodules, it is easily configurable for different kinds of applications. mios14 is the implementation of the mios14 architecture used in the mpc565/mpc566. the mios14 is composed of the following submodules: one mios14 bus interface submodule (mbism) one mios14 counter prescaler submodule (mcpsm) six mios14 modulus counter submodules (mmcsm) 10 mios14 double action submodules (mdasm) 12 mios14 pulse-width modulation submodules (mpwmsm) one mios14 16-bit parallel port i/o submodule (mpiosm) two interrupt request submodules (mirsm) real-time clock 17.1 block diagram figure 17-1 is a block diagram of the mios14. 17-2 mpc565/mpc566 reference manual motorola mios14 key features figure 17-1. mpc565/mpc566 mios14 block diagram 17.2 mios14 key features the basic features of the mios14 are as follows: modulus counter mmcsm6 bus interface unit submodule 16-bit counter bus set modular i/o bus (miob) c l mda30 mda29 mda15 mda14 modulus counter mmcsm23 c l (to all submodules) imb3 bus mda28 mda27 submodules interrupt mda28 mda27 mda13 mda11 real-time clock mrtcsm vddrtc modulus counter mmcsm8 c l modulus counter mmcsm22 c l mda14 mda13 pwm19 modulus counter mmcsm7 c l switch power mda11 pwm17 pwm16 mda31 mda30 mda12 mdasm 11 mdasm12 mdasm13 mdasm14 mdasm15 mdasm 27 mdasm28 mdasm29 mdasm30 mdasm31 mda12 modulus counter mmcsm24 c l mda31 cb23 pwm18 cb8 cb22 cb6 cb7 extal32 xtal32 mcpsm mpwm21 pwm pwmsm21 mpwm16 pwm mpwmsm16 mpwm5 pwm pwmsm5 mpwm0 pwm pwmsm0 channel and i/o pins: 6xpwmsm 6xpwmsm double action double action double action double action double action double action double action double action double action double action counter prescaler mirsm0/1 cb24 channel and i/o pins: motorola chapter 17. modular input/output subsystem (mios14) 17-3 mios14 key features modular architecture at the silicon implementation level disable capability in each submodule to allow power saving when its function is not needed six 16-bit counter bus to allow action submodules to use counter data when not used for timing functions, every channel pin can be used as a port pin: i/o, output only or input only, depending on the channel function. submodules? pin status bits reflect the status of the pin mios14 counter prescaler submodule (mcpsm): ? centralized counter clock generator ? programmable 4-bit modulus down-counter ? wide range of possible division ratios: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and 16 ? count inhibit under software control mios14 modulus counter submodule (mmcsm): ? programmable 16-bit modulus up-counter with built-in programmable 8-bit prescaler clocked by mcpsm output. ? maximum increment frequency of the counter: ? clocked by the internal mcpsm output: f sys /2 ? clocked by the external pin: f sys /4 ? flag setting and possible interrupt generation on overflow of the up-counter ? time counter on internal clock with interrupt capability after a pre-determined time ? optional pin usable as an external event counter (pulse accumulator) with overflow and interrupt capability after a pre-determined number of external events. ? usable as a regular free-running up-counter ? capable of driving a dedicated 16-bit counter bus to provide timing information to action submodules (the value driven is the contents of the 16-bit up-counter register) ? optional pin to externally force a load to the counter with modulus value mios14 double action submodule (mdasm): ? versatile 16-bit dual action unit allowing two events to occur before software intervention is required ? six software selectable modes allowing the mdasm to perform pulse width and period measurements, pwm generation, single input capture and output compare operations as well as port functions 17-4 mpc565/mpc566 reference manual motorola mios14 key features ? software selection of one of the six possible 16-bit counter buses used for timing operations ? flag setting and possible interrupt generation after mdasm action completion ? software selection of output pulse polarity ? software selection of totem-pole or open-drain output ? software readable output pin status ? possible use of pin as i/o port when mdasm function is not needed mios14 pulse width modulation submodule (mpwmsm): ? output pulse width modulated (pwm) signal generation with no software involvement ? built-in 8-bit programmable prescaler clocked by the mcpsm ? pwm period and pulse width values provided by software: ? double-buffered for glitch-free period and pulse width changes ? two-cycle minimum output period/pulse-width increment (50 ns @ 40 mhz) ? 50% duty-cycle output maximum frequency: 10 mhz ? up to 16 bits output pulse width resolution ? wide range of periods: 16 bits of resolution: period range from 3.27 ms (with 50-ns steps) to 6.71 s (with 102.4 s steps) eight bits of resolution: period range from 12.8 s (with 50 ns steps) to 26.2 ms (with 102.4- s steps) ? wide range of frequencies: maximum output frequency at f sys = 40 mhz with 16 bits of resolution and divide-by-2 prescaler selection: 305 hz (3.27 ms) minimum output frequency at f sys = 40 mhz with 16 bits of resolution and divide-by-4096 prescaler selection: 0.15 hz (6.7 s) maximum output frequency at f sys = 40 mhz with eight bits of resolution and divide-by-2 prescaler selection: 78125 hz (12.8 s) minimum output frequency at f sys = 40 mhz with 8 bits of resolution and divide-by-4096 prescaler selection: 38.14 hz (8.2 ms) ? programmable duty cycle from 0% to 100% ? possible interrupt generation after every period motorola chapter 17. modular input/output subsystem (mios14) 17-5 mios14 key features ? software selectable output pulse polarity ? software readable output pin status ? possible use of pin as i/o port when pwm function is not needed mios14 16-bit parallel port i/o submodule (mpiosm): ? up to 16 parallel i/o pins per mpiosm ? uses four 16-bit registers in the address space, one for data and one for direction and two reserved ? simple data direction register (ddr) concept for selection of pin direction one mios real-time clock submodule (mrtcsm) ? programmable 47-bit free-running ripple counter for minimum power consumption split into a 15-bit prescaler and a 32-bit second counter ? buffering of the 47-bit free-running counter to guaranty 32-bit and 47-bit coherent accesses on the 16-bit miob bus. ? possibility of suppressing 15-bit prescaler update ? software shutdown of the dedicated low power oscillator to maintain battery shelf life ? flag setting and possible interrupt generation according to eight software selectable rates ? automatic hardware power supply selection through dedicated power switch ? customized to use low cost standard 32.768-khz crystal for internal clocking of the 32-bit counter at 1hz ? software accessible precision of 2 -15 second and unique time indication in seconds over a span of 136 years (2 32 seconds) 17.2.1 submodule numbering, naming and addressing a block is a group of four 16-bit registers. each of the blocks within the mios14 addressing range is assigned a block number. the first block is located at the base address of the mios14. the blocks are numbered sequentially starting from 0. every submodule instantiation is also assigned a number. the number of a given submodule is the block number of the first block of this submodule. a submodule is assigned a name made of its acronym followed by its submodule number. for example, if submodule number 18 were an mpwmsm, it would be named mpwmsm18. this numbering convention does not apply to the mbism, the mcpsm and the mirsms. the mbism and the mcpsm are unique in the mios14 and do not need a number. the mirsms are numbered incrementally starting from zero. 17-6 mpc565/mpc566 reference manual motorola mios14 key features the mios14 base address is defined at the chip level and is referred to as the ?mios14 base address.? the mios14 addressable range is four kbytes. the base address of a given implemented submodule within the mios14 is the sum of the base address of the mios14 and the submodule number multiplied by eight. refer to table 17-1. this does not apply to the mbism, the mcpsm and the mirsms. for these submodules, refer to the mios14 memory map in figure 17-2. 17.2.2 pin naming convention in figure 17-2, mdasm pins have a prefix mda, mpwmsm pins have a prefix of mpwm and the port pins have a prefix of mpio. the modulus counter clock and load pins are multiplexed with mdasm pins. the mios14 input and output pin names are composed of five fields according to the following convention: ?m? motorola chapter 17. modular input/output subsystem (mios14) 17-7 mios14 configuration mpwmsm: ? submodule short_prefix: ?pwm? ? pin attribute suffix: none ? for example a mpwmsm placed as submodule number n would have its corresponding channel i/o pin named mpwmn mpiosm: ? submodule short_prefix: ?pio? ? pin attribute suffix: b ? for example a mpiosm placed as submodule number n would have its corresponding i/o pins named mpionb0 to mpionb15 for bit-0 to bit-15, respectively. in the mios14, some pins are multiplexed between submodules using the same pin names for the inputs and outputs which are connected as shown in table 17-1. 17.3 mios14 configuration the complete mios14 submodule and pin configuration is shown in table 17-1. table 17-1. mios14 configuration description sub- module type block number connected to: rqsm number rqsm bi position base address offset pin function input pin name output pin name alternate pin function cba cbb cbc cbd bsl0=0 bsl1=0 bsl0=1 bsl1=0 bsl0=0 bsl1=1 bsl0=1 bsl1=1 pwmsm 0 000x30 6000 pwm, i/o mpwm0 mpwm0 pwmsm 1 010x30 6008 pwm, i/o mpwm1 mpwm1 pwmsm 2 020x30 6010 pwm, i/o mpwm2 mpwm2 pwmsm 3 030x30 6018 pwm, i/o mpwm3 mpwm3 pwmsm 4 040x30 6020 pwm, i/o mpwm4 mpwm4 pwmsm 5 050x30 6028 pwm, i/o mpwm5 mpwm5 mmcsm 6 cb6 060x30 6030 clock in mda11 load in mda12 mmcsm 7 cb7 070x30 6038 clock in mda30 load in mda31 mmcsm 8 cb8 0 8 0x30 6040 clock in mpwm16 17-8 mpc565/mpc566 reference manual motorola mios14 configuration load in mpwm17 reserved 9-9 rtcsm 10 0100x30 6050 osc. input extal32 osc. output xtal32 power supply vrtc mdasm 11 cb6 cb22 cb7 cb8 0 11 0x30 6058 channel i/o mda11 mda11 mdasm 12 cb6 cb22 cb7 cb8 0 12 0x30 6060 channel i/o mda12 mda12 mdasm 13 cb6 cb22 cb23 cb24 0 13 0x30 6068 channel i/o mda13 mda13 mdasm 14 cb6 cb22 cb23 cb24 0 14 0x30 6070 channel i/o mda14 mda14 mdasm 15 cb6 cb22 cb23 cb24 0 15 0x30 6078 channel i/o mda15 mda15 pwmsm 16 100x30 6080 pwm, i/o mpwm16 mpwm1 6 pwmsm 17 110x30 6088 pwm, i/o mpwm17 mpwm1 7 pwmsm 18 120x30 6090 pwm, i/o mpwm18 mpwm1 8 pwmsm 19 130x30 6098 pwm, i/o mpwm19 mpwm1 9 pwmsm 20 140x30 60a0 pwm, i/o mpwm20 mpwm2 0 pwmsm 21 150x30 60a8 pwm, i/o mpwm21 mpwm2 1 mmcsm 22 cb22 160x30 60b0 clock in mda13 load in mda14 mmcsm 23 cb23 170x30 60b8 clock in mda27 load in mda28 mmcsm 24 cb24 1 8 0x30 60c0 clock in mpwm18 load in mpwm19 reserved 25-26 mdasm 27 cb6 cb22 cb23 cb24 1 11 0x30 60d8 channel i/o mda27 mda27 table 17-1. mios14 configuration description (continued) sub- module type block number connected to: rqsm number rqsm bi position base address offset pin function input pin name output pin name alternate pin function cba cbb cbc cbd bsl0=0 bsl1=0 bsl0=1 bsl1=0 bsl0=0 bsl1=1 bsl0=1 bsl1=1 motorola chapter 17. modular input/output subsystem (mios14) 17-9 mios14 configuration mdasm 28 cb6 cb22 cb23 cb24 1 12 0x30 60e0 channel i/o mda28 mda28 mdasm 29 cb6 cb22 cb7 cb8 1 13 0x30 60e8 channel i/o mda29 mda29 mdasm 30 cb6 cb22 cb7 cb8 1 14 0x30 60f0 channel i/o mda30 mda30 mdasm 31 cb6 cb22 cb7 cb8 1 15 0x30 60f8 channel i/o mda31 mda31 piosm 32 0x30 6100 gpio mpio32b 0 mpio32 b0 vf[0] gpio mpio32b 1 mpio32 b1 vf[1] gpio mpio32b 2 mpio32 b2 vf[2] gpio mpio32b 3 mpio32 b3 vfls[0] gpio mpio32b 4 mpio32 b4 vfls[1] gpio mpio32b 5 mpio32 b5 mpwm4 gpio mpio32b 6 mpio32 b6 mpwm5 gpio mpio32b 7 mpio32 b7 mdo[7] gpio mpio32b 8 mpio32 b8 mdo[6] gpio mpio32b 9 mpio32 b9 mdo[5] gpio mpio32b 10 mpio32 b10 mdo[4] gpio mpio32b 11 mpio32 b11 mpwm2 0 gpio mpio32b 12 mpio32 b12 mpwm2 1 gpio mpio32b 13 mpio32 b13 c_cntx 0 gpio mpio32b 14 mpio32 b14 c_cnrx 0 gpio mpio32b 15 mpio32 b15 reserved 33-255 mbism 256 0x30 6800 table 17-1. mios14 configuration description (continued) sub- module type block number connected to: rqsm number rqsm bi position base address offset pin function input pin name output pin name alternate pin function cba cbb cbc cbd bsl0=0 bsl1=0 bsl0=1 bsl1=0 bsl0=0 bsl1=1 bsl0=1 bsl1=1 17-10 mpc565/mpc566 reference manual motorola mios14 configuration 17.3.1 mios14 signals the mios14 requires 34 pins: 10 mdasm pins, 8 dedicated mpwmsm pins, 12 dedicated mpiosm pins and 4 pins are shared between the mpwmsm and mpiosm. the required pin function on shared pins is chosen using the pdmcr2 register in the usiu. the usage of all mios14 pins is shown in the block diagram of figure 17-1 and in the configuration description of table 17-1 . 17.3.2 mios14 bus system the internal bus system within the mios14 is called the modular i/o bus (miob). the miob makes communications possible between any submodule and the imb3 bus master through the mbism. the miob is divided into three dedicated buses: the read/write and control bus the request bus the counter bus set 17.3.3 read/write and control bus the read/write and control bus (rwcb) allows read and write data transfers to and from any i/o submodule through the mbism. it includes signals for data and addresses as well as control signals. the control signals allow 16-bit simple synchronous single master accesses and supports fast or slow master accesses. reserved 257-257 mcpsm 258 0x30 6810 reserved 259-383 mirsm0 384-391 0x30 6c00 mirsm1 392-399 0x30 6c40 reserved 400-511 table 17-1. mios14 configuration description (continued) sub- module type block number connected to: rqsm number rqsm bi position base address offset pin function input pin name output pin name alternate pin function cba cbb cbc cbd bsl0=0 bsl1=0 bsl0=1 bsl1=0 bsl0=0 bsl1=1 bsl0=1 bsl1=1 motorola chapter 17. modular input/output subsystem (mios14) 17-11 mios14 programmer?s model 17.3.4 request bus the request bus (rqb) provides interrupt request signals along with i/o submodule identification and priority information to the mbism. note some submodules do not generate interrupts and are therefore independent of the rqb. 17.3.5 counter bus set the 16-bit counter bus set (cbs) is a set of two 16-bit counter buses. the cbs makes it possible to transfer information between submodules. typically, counter submodules drive the cbs, while action submodules process the data on these buses. note, however, that some submodules are self-contained and therefore independent of the counter bus set. 17.4 mios14 programmer?s model the address space of the mios14 consist of 4 kbytes starting at the base address of the module (0x306000). the overall address map organization is shown in figure 17-2. 17.4.1 bus error support a bus error signal is generated when access to an unimplemented or reserved 16-bit register is attempted, or when a priviledge violation occurs. a bus error is generated under any of the following conditions: attempted access to unimplemented 16-bit registers within the decoded register block boundary. attempted user access to supervisor registers attempted access to test registers when not in test mode (tstmod negated) attempted write to read-only registers 17.4.2 wait states the mios14 does not generate wait states. 17-12 mpc565/mpc566 reference manual motorola mios14 programmer?s model figure 17-2. mios14 memory map reserved supervisor/ mbism mcpsm base address 0x30 6c00 0x30 6fff 0x30 6800 reserved reserved unrestricted supervisor supervisor 0x30 6c00 0x30 6c04 0x30 6c06 0x30 6c30 0x30 6000 0x30 6810 reserved mios1lvl0 reserved mios1rpr0 mios1er0 reserved mios1sr0 submodules 31 to 16 submodules 15 to 0 channels 0x30 6c02 0x30 6c40 0x30 6c40 0x30 6c44 0x30 6c46 0x30 6c70 reserved mios1lvl1 reserved mios1rpr 1 mios1er1 mios1sr1 reserved 0x30 6c42 mpwmsm0 mpwmsm1 mpwmsm2 mpwmsm3 0x30 6000 0x30 6008 0x30 6010 0x30 6018 mpwmsm4 mmcsm6 mdasm11 0x30 6030 0x30 6058 mdasm12 mdasm13 mdasm14 mdasm15 0x30 6060 0x30 6068 0x30 6070 0x30 6078 mpwmsm16 mpwmsm17 mpwmsm18 mpwmsm19 0x30 6088 0x30 6098 0x30 6080 0x30 6090 mmcsm22 mdasm27 0x30 60b0 0x30 60d8 mdasm28 mdasm29 mdasm30 0x30 60e8 0x30 60f8 mdasm31 mpiosm32 0x30 6100 0x30 60e0 0x30 60f0 0x30 6020 mpwmsm5 0x30 6028 mmcsm7 0x30 6038 mmcsm8 0x30 6040 mrtcsm 0x30 6050 mmcsm23 0x30 60b8 mmcsm24 0x30 60c0 mpwmsm20 0x30 60a0 mpwmsm21 0x30 60a8 mirsm1 mirsm0 motorola chapter 17. modular input/output subsystem (mios14) 17-13 mios14 i/o ports if a supervisor privilege address space is accessed in user mode, the module returns a bus error. all mios14 unimplemented locations within the addressable range, return a logic 0 when accessed. in addition, the internal tea (transfer error acknowledge) signal is asserted. all unused bits within mios14 registers return a 0 when accessed. 17.5 mios14 i/o ports each pin of each submodule can be used as an input, output, or i/o port: 17.6 mios14 bus interface submodule (mbism) the mios14 bus interface submodule (mbism) is used as an interface between the miob (modular i/o bus) and the imb3. it allows the cpu to communicate with the mios14 submodules. 17.6.1 mios14 bus interface (mbism) registers table 17-3 is the address map for the mbism submodule. table 17-2. mios14 i/o ports submodule number type mpiosm 16 i/o mmcsm 2 i mdasm 1 i/o mpwmsm 1 i/o msb 0 1234567891011121314lsb 15 0x30 mios14 test and pin control register (mios14tpcr) 0x03 mios14 vector register (mios14vect) note: reserved for mpc565/566 0x03 mios14 module-version number register (mios14vnr) 0x03 mios14 module control register (mios14mcr) 0x03 reserved 0x03 reserved 0x03 reserved 0x03 reserved table 17-3. mbism registers 17-14 mpc565/mpc566 reference manual motorola mios14 bus interface submodule (mbism) 17.6.1.1 mios14 test and pin control register (mios14tpcr) this register is used for mios14 factory testing and to specify the pin usage. note that this register does not control the pin multiplexing of the mios gpio pins which are shared with the readi mdo function (mdo_4_mpio32b10, mdo_5_mpio32b9, mdo_6_mpio32b8, mdo_7_mpio32b7). these pins are controlled by the readi module. msb 0 1234567891011 12 1314lsb 15 test reserved vmux[7:5] pwm reserv cca vf vfls sreset: 000000000000 0 000 figure 17-3. mios14tpcr ? test and pin control register 0x30 6800 table 17-4. mios14tpcr bit descriptions bit(s) name description 0 ? test ? this bit is used for mios14 factory testing and should always be programmed to a 0. 1:7 ? reserved 8:10 vmux7 ? vmux5 pin multiplex ? these bits are unused on mpc565/mpc566. 11 pwm pwm pin multiplex ? this bit controls the function of the following pins: mpwm20_mpio32b11, mpwm21_mpio32b12, mpwm4_mpio32b5, mpwm5_mpio32b6. 1 pwm function is selected (mpwm4, mpwm5, mpwm20, mpwm21) 0 mios general purpose i/o is selected (mpio32b5, mpio32b6, mpio32b11, mpio32b12) 12 ? this bit should be set to 0. 13 ccan toucan_c pin multiplex ? this bit controls the function of the following pins: c_cntx0_mpio32b13 c_cnrx0_mpio32b14 1 toucan_c function is selected (c_cntx0, c_cnrx0) 0 mios general purpose i/o is selected (mpio32b13, mpio32b14) 14 vf vf pin multiplex ? this bit controls the function of the vf pins (vf0_mpio32b0, vf1_mpio32b3, vf2_mpio32b4) 1 vf function is selected (vf[0:2]) 0 mios general purpose i/o is selected (mpio32b0, mpio32b1, mpio32b2) 15 vfls vfls pin multiplex ? this bit controls the function of the vfls pins (vfls0_mpio32b3, vfls1_mpio32b4) 1 vfls function is selected (vfls[0:1]) 0 mios general purpose i/o is selected (vfls0_mpio32b3, vfls1_mpio32b4) motorola chapter 17. modular input/output subsystem (mios14) 17-15 mios14 bus interface submodule (mbism) 17.6.1.2 mios14 vector register (mios14vect) 17.6.1.3 mios14 module and version number register this read-only register contains the hard-coded values of the module and version number. 17.6.1.4 mios14 module configuration register (mios14mcr) the mios14mcr register is a collection of read/write stop, freeze, reset and supervisor bits, as well as interrupt arbitration number bits. these bits are detailed in table 17-7. msb 0 1234567891011121314lsb 15 reserved vect vect vect vect reserved sreset: 000000000000 0 000 figure 17-4. mios14vect ? vector register 0x30 6802 table 17-5. mios14vect bit descriptions bit(s) name description 0:7 ? reserved 8:11 vect interrupt vectors msbs ? these bits are not used on the mpc565/mpc566 12:15 ? reserved msb 0 1234567891011121314lsb 15 mn vn figure 17-5. mios14vnr ? mios14 module/version number register 0x30 6804 table 17-6. mios14vnr bit descriptions bit(s) name description 0:7 mn module number = 1 on the mpc565/mpc566. 8:15 vn version number msb 0 1234567891011121314lsb 15 stop rsvd frz rst reserved supv reserved sreset: 0000000000000000 figure 17-6. mios14mcr ? module configuration register 0x30 6806 17-16 mpc565/mpc566 reference manual motorola mios14 counter prescaler submodule (mcpsm) 17.7 mios14 counter prescaler submodule (mcpsm) the mios14 counter prescaler submodule (mcpsm) divides the mios14 clock (f sys )to generate the counter clock. it is designed to provide all the submodules with the same division of the main mios14 clock (division of f sys ). it uses a 4-bit modulus counter. the clock signal is prescaled by loading the value of the clock prescaler register into the prescaler counter every time it overflows. this allows all prescaling factors between two and 16. counting is enabled by asserting the pren bit in the control register. the counter can be stopped at any time by negating this bit, thereby stopping all submodules using the output of the mcpsm (counter clock). a block diagram of the mcpsm is given in figure 17-7. table 17-7. mios14mcr bit descriptions bit(s) name description 0 stop stop enable ? the stop bit, while asserted, activates the miob freeze signal regardless of the state of the imb3 freeze signal. the miob freeze signal is further validated in some submodules with internal freeze enable bits in order for the submodule to be stopped. the mbism continues to operate to allow the cpu access to the submodule?s registers. the miob freeze signal remains active until reset or until the stop bit is written to zero by the cpu (via the imb3). thestopbitisclearedbyreset. 0 allows mios14 operation. 1 selectively stops mios14 operation. 1?reserved 2 frz freeze enable ? the frz bit, while asserted, activates the miob freeze signal only when the imb3 freeze signal is active. the miob freeze signal is further validated in some submodules with internal freeze enable bits in order for the submodule to be frozen. the mbism continues to operate to allow the cpu access to the submodule?s registers. the miob freeze signal remains active until the frz bit is written to zero or the imb3 freeze signal is negated. the frz bit is cleared by reset. 0 ignores the freeze signal on the imb3, allows mios14 operation. 1 selectively stops mios14 operation when the freeze signal appears on the imb3. 3 rst module reset ? the rst bit is always read as 0 and can be written to 1. when the rst bit is written to 1 operation of the mios14 completely stops and resets all the values in the submodule. this completely stops the operation of the mios14 and reset all the values in the submodules registers that are affected by reset. this bit provides a way of resetting the complete mios14 module regardless of the reset state of the cpu. the rst bit is cleared by reset. 0 writing a 0 to rst has no effect. 1 reset the mios14 submodules. 4:7 ? reserved 8 supv supervisor data space selector ? the supv bit tells if the address space from (0x30 6000) to (0x30 67ff) in the mios14 is accessed at the supervisor privilege level (see the address map on table 17-3). when cleared, these addresses are accessed at the unrestricted privilege level. the supv bit is cleared by reset. 0 unrestricted data space. 1 supervisor data space. 9:15 ? reserved. these bits are used for the iarb (interrupt arbitration id) field in mios14 implementations that use hardware interrupt arbitration. these bits are not used on mpc565/mpc566. motorola chapter 17. modular input/output subsystem (mios14) 17-17 mios14 counter prescaler submodule (mcpsm) the following sections describe the mcpsm in detail. figure 17-7. mcpsm block diagram 17.7.1 mcpsm features centralized counter clock generator programmable 4-bit modulus down-counter wide range of possible division ratios: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 or 16 count inhibit under software control count inhibit under software control 17.7.1.1 mcpsm pin functions the mcpsm has no associated external pins. 17.7.1.2 modular i/o bus (miob) interface the mcpsm is connected to all the signals in the read/write and control bus, to allow data transfer from and to the mcpsm registers, and to control the mcpsm in the different possible situations. the mios14 counter prescaler submodule does not use any 16-bit counter bus. the mios14 counter prescaler submodule does not use the request bus. fsys prescaler pren cp2 cp1 cp0 decrementer clock register load cp3 enable mcpsmscr 4-bit =1? dec. counter clock 17-18 mpc565/mpc566 reference manual motorola mios14 counter prescaler submodule (mcpsm) 17.7.2 effect of reset on mcpsm when the reset signal is asserted, all the bits in the mcpsm status and control register are cleared. note the mcpsm is still disabled after the reset signal is negated and counting must be explicitly enabled by asserting the pren bit. 17.7.3 mcpsm registers the privilege level to access to the mcpsm registers is supervisor only. 17.7.3.1 mcpsm registers organization 17.7.3.2 mcpsmscr ? mcpsm status/control register table 17-8. mcpsm register address map address register 0x30 6810 reserved 0x30 6812 reserved 0x30 6814 reserved 0x30 6816 mcpsm status/control register (mcpsmscr) msb 0 1234567891011121314lsb 15 pren fren reserved psl3:0 sreset: 0000000000000000 figure 17-8. mcpsmscr ? mcpsm status/control register 0x30 6816 motorola chapter 17. modular input/output subsystem (mios14) 17-19 mios14 modulus counter submodule (mmcsm) note if the binary value 0b0001 is entered in psl[3:0], the output signal is stuck at zero, no clock is output. 17.8 mios14 modulus counter submodule (mmcsm) the mmcsm is a versatile counter submodule capable of performing complex counting and timing functions, including modulus counting, in a wide range of applications. the mmcsm may also be configured as an event counter, allowing the overflow flag to be set after a predefined number of events (internal clocks or external events), or as a time source for other submodules. table 17-9. mcpsmscr bit descriptions bit(s) name description 0 pren prescaler enable bit ? this active high read/write control bit enables the mcpsm counter. the pren bit is cleared by reset. 1 mcpsm counter enabled. 0 mcpsm counter disabled. 1 fren freeze bit ? this active high read/write control bit when set make possible a freeze of the mcpsm counter if the miob freeze line is activated. note: this line is active when the mios14mcr stop bit is set or when the mios14mcr fren bit and the imb3 freeze line are set. when the mcpsm is frozen, its stops counting. then when the fren bit is reset or when the freeze condition on the miob is negated, the counter restart from where it was before to freeze. the fren bit is cleared by reset. 1 mcpsm counter frozen if miob freeze active. 0 mcpsm counter not frozen. 2:11 ? reserved 12:15 psl[3:0] clock prescaler ? this 4-bit read/write data register stores the modulus value for loading into the clock prescaler. the new value is loaded into the counter on the next time the counter equals one or when disabled (pren =0). table 17-10. clock prescaler setting psl[3:0] value divide ratio 0x0 16 0x1 no counter clock output 0x2 2 0x3 3 ... ... 0xe 14 0xf 15 17-20 mpc565/mpc566 reference manual motorola mios14 modulus counter submodule (mmcsm) note the mmcsm can also operate as a free running counter by loading the modulus value of zero. the main components of the mmcsm are an 8-bit prescaler counter, an 8-bit prescaler register, a 16-bit up-counter register, a 16-bit modulus latch register, counter loading and interrupt flag generation logic. the contents of the modulus latch register is transferred to the counter under the following three conditions: 1. when an overflow occurs 2. when an appropriate transition occurs on the external load pin 3. when the program writes to the counter register. in this case, the value is first written into the modulus register and immediately transferred to the counter. software can also write a value to the modulus register for later loading into the counter with one of the two first criteria. a software control register selects whether the clock input to the counter is one of the prescaler outputs or the corresponding input pin. the polarity of the external input pin is also programmable. the following sections describe the mmcsm in detail. a block diagram of the mmcsm is shown in figure 17-9. motorola chapter 17. modular input/output subsystem (mios14) 17-21 mios14 modulus counter submodule (mmcsm) figure 17-9. mmcsm block diagram figure 17-10. mmcsm modulus up-counter 16-bit up-counter reg. edge 16-bit counter bus clock input overflow miob detect load control 16-bit modulus pin (mmcnc) edge modulus load detect pin (mmcnl) counter clock clock select load clock mmcsmml mmcsmcnt flag 8-bit clock prescaler 8-bit prescale mod.register clock enable request bus fren cls1 cls0 cp7 - cp0 pinc pinl edgn edgp latch reg. pinc 0xffff modulus value two?s complement counter reload 17-22 mpc565/mpc566 reference manual motorola mios14 modulus counter submodule (mmcsm) 17.8.1 mmcsm features programmable 16-bit modulus up-counter with a built-in programmable 8-bit prescaler clocked by mcpsm maximum increment frequency of the counter: ? clocked by the internal mcpsm output: f sys /2 ? clocked by the external pin: f sys /4 flag setting and possible interrupt generation on overflow of the up-counter register time counter on internal clock with interrupt capability after a pre-determined time external event counter (pulse accumulator) with overflow and interrupt capability after a pre-determined number of external events usable as a regular free-running up-counter capable of driving a dedicated 16-bit counter bus to provide timing information to action submodules (the value driven is the contents of the 16-bit up-counter register) optional pin for counting external events optional pin to externally force a load of the modulus counter 17.8.1.1 mmcsm pin functions the mmcsm has two dedicated external pins. an external modulus load pin (mmcnl) allows the modulus value stored in the modulus latch register (mmcsmml) to be loaded into the up-counter register (mmcsmcnt) at any time. both rising and falling edges of the load signal may be used, according to the edgep and edgen bit settings in the mmcsmscr. an external event clock pin (mmcnc) can be selected as the clock source for the up-counter register (mmcsmcnt) by setting the appropriate value in the cls bit field of the status/control register (mmcsmscr). either rising or falling edge may be used according to the setting of these bits. when the external clock source is selected, the mmcsm is in the event counter mode. the counter can simply counts the number of events occurring on the input pin. alternatively, the mmcsm can be programmed to generate an interrupt when a predefined number of events have been counted; this is done by presetting the counter with the two?s complement value of the desired number of events. 17.8.2 mmcsm prescaler the built-in prescaler consists of a 8-bit modulus counter, clocked by the mcpsm output. it is loaded with an 8-bit value every time the counter overflows or whenever the prescaler output is selected as the clock source. this 8-bit value is stored in the mmcsmscr bit motorola chapter 17. modular input/output subsystem (mios14) 17-23 mios14 modulus counter submodule (mmcsm) field cp. the prescaler overflow signal is used to clock the mmcsm up-counter. this allows the mmcsmcnt to be incremented at the mcpsm output frequency divided by a value between one and 256. 17.8.3 modular i/o bus (miob) interface the mmcsm is connected to all the signals in the read/write and control bus, to allow data transfer from and to the mmcsm registers, and to control the mmcsm in the different possible situations. the mmcsm drives a dedicated 16-bit counter bus with the value currently in the up-counter register the mmcsm uses the request bus to transmit the flag line to the interrupt request submodule (mirsm). a flag is set when an overflow has occurred in the up-counter register. 17.8.4 effect of reset on mmcsm when the reset signal is asserted, only the fren, edgp, edgn, and cls bits in the mmcsmscr are cleared. the clock prescaler cp, pinc and pinl bits in the same register are not cleared. the pinc and pinl bits in the mmcsmscr always reflect the state of the appropriate external pins. the mmcsm is disabled after reset and must be explicitly enabled by selecting a clock source using the cls bits. the mmcsmcnt and the mmcsmml, together with the clock prescaler register bits, must be initialized by software, since they are undefined after a hardware reset. a modulus value must be written to the mmcsmcnt (which also writes into the mmcsmml) before the mmcsmscr is written to. the latter access initializes the clock prescaler. 17.8.5 mmcsm registers the privilege level to access to the mmcsm registers depends on the mios14mcr supv bit. the privilege level is unrestricted after reset and can be change to supervisor by software. 17-24 mpc565/mpc566 reference manual motorola mios14 modulus counter submodule (mmcsm) 17.8.5.1 mmcsm register organization table 17-11. mmcsm address map address register mmcsm6 0x30 6030 mmcsm6 up-counter register (mmcsmcnt) see table 17-12 for bit descriptions. 0x30 6032 mmcsm6 modulus latch register (mmcsmml) see table 17-13 for bit descriptions. 0x30 6034 mmcsm6 status/control register duplicated (mmcsmscrd) see section 17.8.5.5, ?mmcsm status/control register (mmcsmscr)? for bit descriptions. 0x30 6036 mmcsm6 status/control register (mmcsmscr). see table 17-14 for bit descriptions. mmcsm7 0x30 6038 mmcsm7 up-counter register (mmcsmcnt) 0x30 603a mmcsm7 modulus latch register (mmcsmml) 0x30 603c mmcsm7 status/control register duplicated (mmcsmscrd) 0x30 603e mmcsm7 status/control register (mmcsmscr) mmcsm8 0x30 6040 mmcsm8 up-counter register (mmcsmcnt) 0x30 6042 mmcsm8 modulus latch register (mmcsmml) 0x30 6044 mmcsm8 status/control register duplicated (mmcsmscrd) 0x30 6046 mmcsm8 status/control register (mmcsmscr) mmcsm22 0x30 60b0 mmcsm22 up-counter register (mmcsmcnt) 0x30 60b2 mmcsm22 modulus latch register (mmcsmml) 0x30 60b4 mmcsm22 status/control register duplicated (mmcsmscrd) 0x30 60b6 mmcsm22 status/control register (mmcsmscr) mmcsm23 0x30 60b8 mmcsm23 up-counter register (mmcsmcnt) 0x30 60ba mmcsm23 modulus latch register (mmcsmml) 0x30 60bc mmcsm23 status/control register duplicated (mmcsmscrd) 0x30 60be mmcsm23 status/control register (mmcsmscr) mmcsm24 0x30 60c0 mmcsm24 up-counter register (mmcsmcnt) 0x30 60c2 mmcsm24 modulus latch register (mmcsmml) motorola chapter 17. modular input/output subsystem (mios14) 17-25 mios14 modulus counter submodule (mmcsm) 17.8.5.2 mmcsm up-counter register (mmcsmcnt) 17.8.5.3 mmcsm modulus latch register (mmcsmml) 0x30 60c4 mmcsm24 status/control register duplicated (mmcsmscrd) 0x30 60c6 mmcsm24 status/control register (mmcsmscr) msb 0 1234567891011121314lsb 15 cnt sreset: uuuuuuuuuuuuuuuu figure 17-11. mmcsmcnt ? mmcsm up-counter register 0x30 6030 0x30 6038 0x30 6040 0x30 60b0 0x30 60b8 0x30 60c0 table 17-12. mmcsmcnt bit descriptions bit(s) name description 0:15 cnt counter value ? these bits are read/write data bits representing the 16-bit value of the up-counter. it contains the value that is driven onto the 16-bit counter bus. note: writing to mmcsmcnt simultaneously writes to mmcsmml. msb 0 1234567891011121314lsb 15 ml sreset: uuuuuuuuuuuuuuuu figure 17-12. mmcsmml ? mmcsm modulus latch register 0x30 6032 0x30 603a 0x30 6042 0x30 60b2 0x30 60ba 0x30 60c2 table 17-11. mmcsm address map (continued) address register 17-26 mpc565/mpc566 reference manual motorola mios14 modulus counter submodule (mmcsm) 17.8.5.4 mmcsmscrd ? mmcsm status/control register (duplicated) the mmcsmscrd and the mmcsmscr are the same registers accessed at two different addresses. reading or writing to one of these two addresses has exactly the same effect. the duplication of the scr register allows coherent 32-bit accesses when using a rcpu. warning the user should not write directly to the address of the mmcsmscrd. this register?s address may be reserved for future use and should not be accessed by the software to ensure future software compatibility. 17.8.5.5 mmcsm status/control register (mmcsmscr) the status/control register (scr) is a collection of read-only pin status bits, read/write control bits and an 8-bit read/write data register, as detailed below. table 17-13. mmcsmml bit descriptions bit(s) name description 0:15 ml modulus latches ? these bits are read/write data bits containing the 16-bit modulus value to be loaded into the up-counter. the value loaded in this register must be the one?s complement of the desired modulus count. the up-counter increments from this one?s complement value up to 0xffff to get the correct number of steps before an overflow is generated to reload the modulus value into the up-counter. msb 0 1234567891011121314lsb 15 pinc pinl fren edg edg cls rsvd cp sreset: uu00000uuu uuuuuu figure 17-13. mmcsmscr ? mmcsm status/control register 0x30 6036 0x30 603e 0x30 6046 0x30 60b6 0x30 60be 0x30 60c6 motorola chapter 17. modular input/output subsystem (mios14) 17-27 mios14 modulus counter submodule (mmcsm) table 17-14. mmcsmscr bit descriptions bit(s) name description 0 pinc clock input pin status bit ? this read-only status bit reflects the logic state of the clock input pin mmcnc (mda[11], mda[13], mda[27], mda[30], pwm[16], and pwm[18]). 1 pinl modulus load input pin status bit ? this read-only status bit reflects the logic state of the modulus load pin mmcnl (mda[12], mda[14], mda[28], mda[31], pwm[17], and pwm[19]). 2 fren freeze enable ? this active high read/write control bit enables the mmcsm to recognize the miob freeze signal. 3 edgn modulus load falling-edge sensitivity ? this active high read/write control bit sets falling-edge sensitivity for the mmcnl pin, such that a high-to-low transition causes a load of the mmcsmcnt. 4 edgp modulus load rising-edge sensitivity this active high read/write control bit sets rising-edge sensitivity for the mmcnl pin, such that a low-to-high transition causes a load of the mmcsmcnt. see table 17-15 for details about edge sensitivity. 5:6 cls clock select ? these read/write control bits select the clock source for the modulus counter. either the rising edge or falling edge of the clock signal on the mmcnc pin may be selected, as well as, the internal mmcsm prescaler output or disable mode (no clock source). see table 17-16 for details about the clock selection. 7?reserved 8:15 cp clock prescaler ? this 8-bit data field is also accessible as an 8-bit data register. it stores the two?s complement of the modulus value to be loaded into the built-in 8-bit clock prescaler. the new value is loaded into the prescaler counter on the next counter overflow, or upon setting the cls1 ? cls0 bits for selecting the clock prescaler as the clock source. table 17-17 gives the clock divide ratio according to the value of cp. table 17-15. mmcsmcnt edge sensitivity edgn edgp edge sensitivity 1 1 mmcsmcnt load on rising and falling edges 1 0 mmcsmcnt load on falling edges 0 1 mmcsmcnt load on rising edges 0 0 none (disabled) table 17-16. mmcsmcnt clock signal cls clocking selected 11 mmcsm clock prescaler 10 clock pin rising-edge 01 clock pin falling-edge 00 none (disable) 17-28 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) fl 17.9 mios14 double action submodule (mdasm) the mios14 double action submodule (mdasm) is a function included in the mios14 library. it is a versatile 16-bit dual action submodule capable of performing two event operations before software intervention is required. it can perform two event operations such as pwm generation and measurement, input capture, output compare, etc. the mdasm is composed of two timing channels (a and b), an output flip-flop, an input edge detector and some control logic. all control and status bits are contained in the mdasm status and control register. the following sections describe the mdasm in detail. a block diagram of the mdasm is shown in figure 17-14. table 17-17. prescaler values prescaler value (cp in hex) mios14 prescaler clock divided by ff 1 fe 2 fd 3 fc 4 fb 5 fa 6 f9 7 f8 8 ...... ........ 02 254 (2^8 -2) 01 255 (2^8 -1) 00 256 (2^8) motorola chapter 17. modular input/output subsystem (mios14) 17-29 mios14 double action submodule (mdasm) figure 17-14. mdasm block diagram 17.9.1 mdasm features versatile 16-bit dual action unit allowing up to two events to occur before software intervention is required six software selectable modes allowing the mdasm to perform pulse width and period measurements, pwm generation, single input capture and output compare operations as well as port functions software selection of one of the four possible 16-bit counter buses used for timing operations flag setting and possible interrupt generation after mdasm action completion software selection of output pulse polarity software selection of totem-pole or open-drain output software readable output pin status 16-bitcomparator a 4x16-bit counter bus control register bits mio bus select output flip-flop i/o pin edge detect 16-bit register a output buffer 16-bit register b1 16-bit registerb2 16-bitcomparator b edpo l register b bsl1 bsl0 forca forcb flag mode [0] mode [1] mode mode [3] wor pin counter buses request bus counter bus set [2] 17-30 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) 17.9.1.1 mdasm pin functions the mdasm has one dedicated external pin. this pin is used in input or in output depending on the selected mode. when in input, it allows the mdasm to perform input capture, input pulse width measurement and input period measurement. when in output, it allows output compare, single shot output pulse, single output compare and output port bit operations as well as output pulse width modulation. note in disable mode, the pin becomes a high impedance input and the input level on this pin is reflected by the state of the pin bit in the mdasmscr register. 17.9.2 mdasm description the mdasm contains two timing channels a and b associated with the same input/output pin. the dual action submodule is so called because its timing channel configuration allows two events (input capture or output compare) to occur before software intervention is required. six operating modes allow the software to use the mdasm?s input capture and output compare functions to perform pulse width measurement, period measurement, single pulse generation and continuous pulse width generation, as well as standard input capture and output compare. the mdasm can also work as a single i/o pin. see table 17-18 for details. channel a comprises one 16-bit data register and one 16-bit comparator. channel b also consists of one 16-bit data register and one 16-bit comparator, however, internally, channel b has two data registers b1 and b2, and the operating mode determines which register is accessed by the software: intheinputmodes(ipwm,ipmandic),registersaandb2areusedtoholdthe captured values; in these modes, the b1 register is used as a temporary latch for channel b. in the output compare modes (ocb and ocab), registers a and b2 are used to define the output pulse; register b1 is not used in these modes. in the output pulse width modulation mode (opwm), registers a and b1 are used as primary registers and hidden register b2 is used as a double buffer for channel b. register contents are always transferred automatically at the correct time so that the minimum pulse (measurement or generation) is just one 16-bit counter bus count. the a and b data registers are always read/write registers, accessible via the miob. in the input modes, the edge detect circuitry triggers a capture whenever a rising or falling edge (as defined by the edpol bit) is applied to the input pin. the signal on the input pin is schmitt triggered and synchronized with the mios14 clock. motorola chapter 17. modular input/output subsystem (mios14) 17-31 mios14 double action submodule (mdasm) in the disable mode (dis) and in the input modes, the pin bit reflects the state present on the input pin (after being schmitt triggered and synchronized). in the output modes the pin bit reflects the value present on the output flip-flop. the output flip-flop is used in output modes to hold the logic level applied to the output pin. the 16-bit counter bus selector is common to all input and output functions; it connects the mdasm to one of the four 16-bit counter buses available to that submodule instance and is controlled in software by the 16-bit counter bus selector bits bsl0 and bsl1 in the mdasmscr register. 17.9.3 mdasm modes of operation the mode of operation of the mdasm is determined by the mode select bits mode[0:3] in the mdasmscr register (see table 17-18). to avoid spurious interrupts, and to make sure that the flag line is activated according to the newly selected mode, the following sequence of operations should be adopted when changing mode: 1. disable mdasm interrupts (by resetting the enable bit in the relevant mirsm) 2. change mode (via disable mode) 3. reset the corresponding flag bit in the relevant mirsm 4. re-enable mdasm interrupts (if desired) table 17-18. mdasm modes of operation mode[0:3] mode description of mode 0000 dis disabled ? input pin is high impedance; pin gives state of the input pin. 0001 ipwm input pulse width measurement ? capture on the leading edge and the trailing edge of an input pulse. 0010 ipm input period measurement ? capture two consecutive rising/falling edges. 0011 ic input capture ? capture when the designated edge is detected. 0100 ocb output compare, flag line activated on b compare ? generate leading and trailing edges of an output pulse. 0101 ocab output compare, flag line activated on a and b compare ? generate leading and trailing edges of an output pulse. 1xxx opwm output pulse width modulation ? generate continuous pwm output with 7, 9, 11, 12, 13, 14, 15 or 16 bits of resolution. 17-32 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) note when changing between output modes, it is not necessary to follow this procedure, as in these modes the flag bit merely indicates to the software that the compare value can be updated. however changing modes without passing via the disable mode does not guarantee the subsequent functionality. 17.9.3.1 disable (dis) mode the disable mode is selected by setting mode[0:3] to 0000. in this mode, all input capture and output compare functions of the mdasm are disabled and the flag line is maintained inactive, but the input port pin function remains available. the associated pin becomes a high impedance input and the input level on this pin is reflected by the state of the pin bit in the mdasmscr register. all control bits remain accessible, allowing the software to prepare for future mode selection. data registers a and b are accessible at consecutive addresses. writing to data register b stores the same value in registers b1 and b2. warning when changing modes, it is imperative to go through the dis mode in order to reset the mdasm?s internal functions properly. failure to do this could lead to invalid and unexpected output compare or input capture results, and to flags being set incorrectly. 17.9.3.2 input pulse width measurement (ipwm) mode ipwm mode is selected by setting mode[0:3] to 0001. this mode allows the width of a positive or negative pulse to be determined by capturing the leading edge of the pulse on channel b and the trailing edge of the pulse on channel a; successive captures are done on consecutive edges of opposite polarity. the edge sensitivity is selected by the edpol bit in the mdasmscr register. this mode also allows the software to determine the logic level on the input pin at any time by reading the pin bit in the mdasmscr register. the channel a input capture function remains disabled until the first leading edge triggers the first input capture on channel b. when this leading edge is detected, the count value of the 16-bit counter bus selected by the bsl[1:0] bits is latched in the 16-bit data register b1; the flag line is not activated. when the next trailing edge is detected, the count value of the 16-bit counter bus is latched into the 16-bit data register a and, at the same time, the flag line is activated and the contents of register b1 are transferred to register b2. reading data register b returns the value in register b2. if subsequent input capture events motorola chapter 17. modular input/output subsystem (mios14) 17-33 mios14 double action submodule (mdasm) occur while the flag bit is set in the corresponding mirsm, data registers a and b will be updated with the latest captured values and the flag line will remain active. if a 32-bit coherent operation is in progress when the trailing edge is detected, the transfer from b1 to b2 is deferred until the coherent operation is completed. operation of the mdasm then continues on channels b and a as previously described. the input pulse width is calculated by subtracting the value in data register b from the value in data register a. figure 17-15 provides an example of how the mdasm can be used for input pulse width measurement. figure 17-15. input pulse width measurement example 17.9.4 input period measurement (ipm) mode ipm mode is selected by setting mode[0:3] to 0010. this mode allows the period of an input signal to be determined by capturing two consecutive rising edges or two consecutive falling edges; successive input captures are done on consecutive edges of the same polarity. the edge polarity is defined by the edpol bit in the mdasmscr register. this mode also allows the software to determine the logic level on the input pin at any time by reading the pin bit in the mdasmscr register. when the first edge having the selected polarity is detected, the 16-bit counter bus value is latched into the 16-bit data register a, the data in register b1 is transferred to data register b2 and finally the data in register a is transferred to register b1. on this first capture the flag reset by software mode selection; edpol = 1 (channel a capture on falling edge, channel b capture on rising edge) input signal -bit counter bus flag bit 0xxxxx 0xxxxx 0xxxxx 0x1000 register b1 register b2 0x1000 0x1000 0x1100 0x1100 0x1400 0x1000 0x1400 0x1525 0x1400 0x1525 0x1400 0x16a0 edge trigger 0x0500 0x1000 0x1100 0x1400 0x1525 0x16a0 register a 0xxxxx 0xxxxx edge trigger rising falling edge trigger edge trigger rising falling edge trigger rising flag set flag set internal register, not accessible to software flag reset by software pulse 1 pulse 2 pulse 1 = reg a- reg b =0x0100 pulse 2 = reg a- reg b =0x0125 17-34 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) flag line is not activated, and the value in register b2 is meaningless. on the second and subsequent captures, the flag line is activated when the data in register a is transferred to register b1. when the second edge of the same polarity is detected, the counter bus value is latched into data register a, the data in register b1 is transferred to data register b2, the flag line is activated to signify that the beginning and end points of a complete period have been captured, and finally the data in register a is transferred to register b1. this sequence of events is repeated for each subsequent capture. reading data register b returns the value in register b2. if a 32-bit coherent operation is in progress when an edge (except for the first edge) is detected, the transfer of data from b1 to b2 is deferred until the coherent operation is completed. at any time, the input level present on the input pin can be read on the pin bit. the input pulse period is calculated by subtracting the value in data register b from the value in data register a. figure 17-16 provides an example of how the mdasm can be used for input period measurement. figure 17-16. input period measurement example flag reset by software mode selection; edpol = 0 (channel a capture on rising edge) input signal it counter bus flag bit 0xxxxx 0x1000 0xxxxx 0x1000 register b1 register b2 0x1000 0xxxxx 0x1000 0x1400 0x1400 0x1000 0x1400 0x1400 0x1000 0x16a0 0x1400 0x16a0 edge trigger 0x0500 0x1000 0x1100 0x1400 0x1525 0x16a0 register a 0xxxxx 0xxxxx rising edge trigger rising flag set flag set internal register, not accessible to software flag reset b y softwa re edge trigger rising 1 2 3 2 1 3 flag set period = reg a -reg b =0x300 2 1 3 flag set period = reg a -r =0x2a0 motorola chapter 17. modular input/output subsystem (mios14) 17-35 mios14 double action submodule (mdasm) 17.9.5 input capture (ic) mode ic mode is selected by setting mode[0:3] to 0011. this mode is identical to the input period measurement mode (ipm) described above, with the exception that the flag line is also activated at the occurrence of the first detected edge of the selected polarity. in this mode the mdasm functions as a standard input capture function. in this case the value latched in channel b can be ignored. figure 17-17 provides an example of how the mdasm can be used for input capture. figure 17-17. mdasm input capture example 17.9.5.1 output compare (ocb and ocab) modes output compare mode (either oca or ocb) is selected by setting mode[0:3] to 010x. the mode[0] bit controls the activation criteria for the flag line, (i.e., when a compare occurs only on channel b or when a compare occurs on either channel). this mode allows the mdasm to perform four different output functions: single-shot output pulse (two edges), with flag line activated on the second edge single-shot output pulse (two edges), with flag line activated on both edges single-shot output transition (one edge) output port pin, with output compare function disabled in this mode the leading and trailing edges of variable width output pulses are generated by calculated output compare events occurring on channels a and b, respectively. oc mode may also be used to perform a single output compare function, or may be used as an output port bit. flag reset by software mode selection; edpol = 0 (channel a capture on rising edge) input signal it counter bus flag bit 0xxxxx 0x1000 0xxxxx 0x1000 register b1 register b2 0x1000 0xxxxx 0x1000 0x1400 0x1400 0x1000 0x1400 0x1400 0x1000 0x16a0 0x1400 0x16a0 edge trigger 0x0500 0x1000 0x1100 0x1400 0x1525 0x16a0 register a 0xxxxx 0xxxxx rising edge trigger rising flag set flag set internal register, not accessible to software flag reset by software edge trigger rising flag reset by software (ignored) flag set 17-36 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) in this mode, channel b is accessed via register b2. a write to register b2 writes the same value to register b1 even though the contents of b1 are not used in this mode. both channels work together to generate one ?single shot? output pulse signal. channel a defines the leading edge of the output pulse, while channel b defines the trailing edge of the pulse. flag line activation can be done when a match occurs on channel b only or when a compare occurs on either channel (as defined by the mode[0] bit in the mdasmscr register). when this mode is first selected, (i.e., coming from disable mode, both comparators are disabled). each comparator is enabled by writing to its data register; it remains enabled until the next successful comparison is made on that channel, whereupon it is disabled. the values stored in registers a and b are compared with the count value on the selected 16-bit counter bus when their corresponding comparators are enabled. the output flip-flop is set when a match occurs on channel a. the output flip-flop is reset when a match occurs on channel b. the polarity of the output signal is selected by the edpol bit. the output flip-flop level can be obtained at any time by reading the pin bit. if subsequent enabled output compares occur on channels a and b, the output pulses continue to be output, regardless of the state of the flag bit. at any time, the forca and forcb bits allow the software to force the output flip-flop to the level corresponding to a comparison on channel a or b, respectively. note the flag line is not affected by these ?force? operations. totem pole or open-drain output circuit configurations can be selected using the wor bit in the mdasmscr register. note if both channels are loaded with the same value, the output flip-flop provides a logic zero level output and the flag bit is still set on the match. note 16-bit counter bus compare only occurs when the 16-bit counter bus is updated. 17.9.5.2 single shot output pulse operation the single shot output pulse operation is selected by writing the leading edge value of the desired pulse to data register a and the trailing edge value to data register b. a single pulse will be output at the desired time, thereby disabling the comparators until new values are written to the data registers. to generate a single shot output pulse, the ocb mode should be used to only generate a flag on the b match. motorola chapter 17. modular input/output subsystem (mios14) 17-37 mios14 double action submodule (mdasm) in this mode, registers a and b2 are accessible to the user software (at consecutive addresses). figure 17-18 provides an example of how the mdasm can be used to generate a single output pulse. figure 17-18. single shot output pulse example 17.9.5.3 single output compare operation the single output compare operation is selected by writing to only one of the two data registers (a or b), thus enabling only one of the comparators. following the first successful match on the enabled channel, the output level is fixed and remains at the same level indefinitely with no further software intervention being required. to generate a single output compare, the ocab mode should be used to generate a flag on both the a and the b match. note in this mode, registers a and b2 are accessible to the user software (at consecutive addresses). figure 17-19 provides an example of how the mdasm can be used to perform a single output compare. flag reset by software mode selection; mode[0] = 0 output signal it counter bus flag bit 0x1000 0x1000 0x1100 0xxxxx register b1 register b2 0xxxxx 0x1100 0x1000 0x1000 0xxxxx 0x1100 0xxxxx 0x1000 0x1100 0x1000 0x1100 0xxxxx 0x0500 0x1000 0x1100 0x0000 0x1000 0x1100 register a 0x1100 0xxxxx internal register, not accessible to software a event bevent writetoaandb reoccurrences of the timer count do not trigger the output pulse unless r esistors a and b have been written again. 17-38 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) figure 17-19. single shot output transition example 17.9.5.4 output port bit operation the output port bit operation is selected by leaving both channels disabled, (i.e., by writing to neither register a nor b). the edpol bit alone controls the output value. the same result can be achieved by keeping edpol at zero and using the forca and forcb bits to obtain the desired output level. 17.9.5.5 output pulse width modulation (opwm) mode opwm mode is selected by setting mode[0:3] to 1xxx. the mode[1:3] bits allow some of the comparator bits to be masked. this mode allows pulse width modulated output waveforms to be generated, with eight selectable frequencies. frequencies are only relevant as such if the counter bus is driven by a counter as a time reference. both channels (a and b) are used to generate one pwm output signal on the mdasm pin. channel b is accessed via register b1. register b2 is not accessible. channels a and b define respectively the leading and trailing edges of the pwm output pulse. the value in register b1 is transferred to register b2 each time a match occurs on either channel a or b. note a forca or forcb does not cause a transfer from b1 to b2. the value loaded in register a is compared with the value on the 16-bit counter bus each time the counter bus is updated. when a match on a occurs, the flag line is activated and the output flip-flop is set. the value loaded in register b2 is compared with the value on the flag reset by software mode selection; mode[0] = 1 output signal 6-bit counter bus flag bit 0x1000 0x1000 0xxxxx 0xxxxx register b1 register b2 0xxxxx 0xxxxx 0x1000 0x1000 0xxxxx 0x1100 0xxxxx 0x1000 0x1100 0x1000 0x1100 0xxxxx 0x0500 0x1000 0x1100 0x1000 0x1100 0x1000 register a 0xxxxx 0xxxxx internal register, not accessible to software a event b event write to a writetob flag reset by software reoccurences of the timer count do not trigger a response unless registers a or b have been written again. motorola chapter 17. modular input/output subsystem (mios14) 17-39 mios14 double action submodule (mdasm) 16-bit counter bus each time the counter bus is updated. when a match occurs on b, the output flip-flop is reset. note if both channels are loaded with the same value, when a simultaneous match on a and b occurs, the submodule behaves as if a simple match on b had occurred except for the flag line which is activated. the output flip-flop is reset and the value in register b1 is transferred to register b2 on the match. the polarity of the pwm output signal is selected by the edpol bit. the output flip-flop level can be obtained at any time by reading the pin bit. if subsequent compares occur on channels a and b, the pwm pulses continue to be output, regardless of the state of the flag bit. at any time, the forca and forcb bits allow the software to force the output flip-flop to the level corresponding to a comparison on a or b respectively. note that the flag line is not activated by the forca and forcb operations. warning data registers a and b must be loaded with the values needed to produce the desired pwm output pulse. note 16-bit counter bus compare only occurs when the 16-bit counter bus is updated. figure 17-20 provides an example of how the mdasm can be used for pulse width modulation. 17-40 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) figure 17-20. mdasm output pulse width modulation example to generate pwm output pulses of different frequencies, the 16-bit comparator can have some of its bits masked. this is controlled by bits mode[2], mode[1] and mode[0]. the frequency of the pwm output (f pwm ) is given by the following equation (assuming the mdasm is connected to a 16-bit counter bus used as time reference and f sys is the frequency of the mios14 clock): where: n mcpsm is the overall mcpsm clock divide ratio (2, 3, 4,...,16). n counter is the divide ratio of the prescaler of the counter (used as a time reference) that drives the 16-bit counter bus. n mdasm is the maximum count reachable by the counter when using n bits of resolution (this count is equal to 2 n ). a few examples of frequencies and resolutions that can be obtained are shown in table 17-19. table 17-19. mdasm pwm example output frequencies/resolutions at f sys =40mhz resolution (bits) n mcpsm n counter n mdasm pwm output frequency (hz) 1 16 16 256 65536 0.15 16 2 1 65536 305.17 edpol = 0 output signal 6-bit counter bus flag bit 0x1000 0x1000 0x1800 0x1500 register b1 0x1500 0x1500 0x1000 0x1000 0x1700 0x1500 0x1700 0x1000 0x1700 0x1000 0x1700 0x1700 0x1000 0x1100 0x1800 0x0000 0x1000 0x1700 register a 0x1800 0x1800 internal register, not accessible to software a compare b compare write 0x1000 to a writetob1 register b2 writetob1 a compare b compare write 0x1800 to b1 flag reset by software flag reset by software f pwm = f sys n mcpsm n counter n mdasm motorola chapter 17. modular input/output subsystem (mios14) 17-41 mios14 double action submodule (mdasm) when using 16 bits of resolution on the comparator (mode[2:0] = 000), the output can vary from a 0% duty cycle up to a duty cycle of 65535/65536. in this case it is not possible to have a 100% duty cycle. in cases where 16-bit resolution is not needed, it is possible to have a duty cycle ranging from 0% to 100%. setting bit 15 of the value stored in register b to one results in the output being ?always set?. clearing bit 15 (to zero) allows normal comparisons to occur and the normal output waveform is obtained. changes to and from the 100% duty cycle are done synchronously on an a or b match, as are all other width changes. in the opwm mode, the wor bit selects whether the output is totem pole driven or open-drain. 17.9.6 modular i/o bus (miob) interface the mdasm is connected to all the signals in the read/write and control bus, to allow data transfer from and to the mdasm registers, and to control the mdasm in the different possible situations. the mdasm is connected to four 16-bit counter buses available to that submodule instance, so that the mdasm can select by software which one to use. 15 16 256 32768 0.29 15 2 1 32768 610.35 14 16 256 16384 0.59 14 2 1 16384 1 220.70 13 16 256 8192 1.19 13 2 1 8192 2 441.41 12 16 256 4096 2.38 12 2 1 4096 4 882.81 11 16 256 2048 4.77 11 2 1 2048 9 765.63 9 16 256 512 19.07 9 2 1 512 39 062.50 7 16 256 128 76.29 7 2 1 128 156 250 1 this information is valid only if the mdasm is connected to an mmcsm operating as a free-running counter. table 17-19. mdasm pwm example output frequencies/resolutions at f sys = 40 mhz (continued) resolution (bits) n mcpsm n counter n mdasm pwm output frequency (hz) 1 17-42 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) the mdasm uses the request bus to transmit the flag line to the interrupt request submodule (mirsm). 17.9.7 effect of reset on mdasm when the reset signal is asserted, the mdasm registers are reset according to the values specified in section 17.9.8, ?mdasm registers.? 17.9.8 mdasm registers the privilege level to access the mdasm registers depends on the mios14mcr supv bit. the privilege level is unrestricted after reset and can be changed to supervisor by software. 17.9.8.1 mdasm registers organization the mdasm register map comprises four 16-bit register locations. as shown in below, the register block contains four mdasm registers. note that the mdasmscrd is the duplication of the mdasmscr. this is done to allow 32-bit aligned accesses. warning the user should not write directly to the address of the mdasmscrd. this register?s address may be reserved for future use and should not be accessed by the software to ensure future software compatibility. all unused bits return zero when read by the software. all register addresses in this section are specified as offsets from the base address of the mdasm. table 17-20. mdasm address map address register mdasm11 0x30 6058 mdasm11 data a register (mdasmar) see section 17.9.8.2, ?mdasm dataa (mdasmar) register bits? for bit descriptions. 0x30 605a mdasm11 data b register (mdasmbr) see section 17.9.8.3, ?mdasm datab (mdasmbr) register bits? for bit descriptions. 0x30 605c mdasm11 status/control register duplicated (mdasmscrd) see table 17-23 for bit descriptions. 0x30 605e mdasm11 status/control register (mdasmscr) see table 17-23 for bit descriptions. mdasm12 0x30 6060 mdasm12 data a register (mdasmar) 0x30 6062 mdasm12 data b register (mdasmbr) motorola chapter 17. modular input/output subsystem (mios14) 17-43 mios14 double action submodule (mdasm) 0x30 6064 mdasm12 status/control register duplicated (mdasmscrd) 0x30 6066 mdasm12 status/control register (mdasmscr) mdasm13 0x30 6068 mdasm13 data a register (mdasmar) 0x30 606a mdasm13 data b register (mdasmbr) 0x30 606c mdasm13 status/control register duplicated (mdasmscrd) 0x30 606e mdasm13 status/control register (mdasmscr) mdasm14 0x30 6070 mdasm14 data a register (mdasmar) 0x30 6072 mdasm14 data b register (mdasmbr) 0x30 6074 mdasm14 status/control register duplicated (mdasmscrd) 0x30 6076 mdasm14 status/control register (mdasmscr) mdasm15 0x30 6078 mdasm15 data a register (mdasmar) 0x30 607a mdasm15 data b register (mdasmbr) 0x30 607c mdasm15 status/control register duplicated (mdasmscrd) 0x30 607e mdasm15 status/control register (mdasmscr) mdasm27 0x30 60d8 mdasm27 data a register (mdasmar) 0x30 60da mdasm27 data b register (mdasmbr) 0x30 60dc mdasm27 status/control register duplicated (mdasmscrd) 0x30 60de mdasm27 status/control register (mdasmscr) mdasm28 0x30 60e0 mdasm28 data a register (mdasmar) 0x30 60e2 mdasm28 data b register (mdasmbr) 0x30 60e4 mdasm28 status/control register duplicated (mdasmscrd) 0x30 60e6 mdasm28 status/control register (mdasmscr) mdasm29 0x30 60e8 mdasm29 data a register (mdasmar) 0x30 60ea mdasm29 data b register (mdasmbr) 0x30 60ec mdasm29 status/control register duplicated (mdasmscrd) 0x30 60ee mdasm29 status/control register (mdasmscr) mdasm30 0x30 60f0 mdasm30 data a register (mdasmar) 0x30 60f2 mdasm30 data b register (mdasmbr) 0x30 60f4 mdasm30 status/control register duplicated (mdasmscrd) 0x30 60f6 mdasm30 status/control register (mdasmscr) mdasm31 0x30 60f8 mdasm31 data a register (mdasmar) 0x30 60fa mdasm31 data b register (mdasmbr) table 17-20. mdasm address map (continued) address register 17-44 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) 17.9.8.2 mdasm dataa (mdasmar) register bits 0x30 60fc mdasm31 status/control register duplicated (mdasmscrd) 0x30 60fe mdasm31 status/control register (mdasmscr) msb 0 1234567891011121314lsb 15 ar sreset: uuuuuuuuuuuuuuuu figure 17-21. mdasmar ? mdasm dataa register 0x30 6058 0x30 6060 0x30 6068 0x30 6070 0x30 6078 0x30 60d8 0x30 60e0 0x30 60e8 0x30 60f0 0x30 60f8 table 17-21. mdasmar bit descriptions bit(s) name description 0:15 ar mdasmar is the data register associated with channel a; its use varies with the different modes of operation: in the dis mode, mdasmar can be accessed to prepare a value for a subsequent mode selection. in the ipwm mode, mdasmar contains the captured value corresponding to the trailing edge of the measured pulse. in the ipm and ic modes, mdasmar contains the captured value corresponding to the most recently detected dedicated edge (rising or falling edge). in the ocb and ocab modes, mdasmar is loaded with the value corresponding to the leading edge of the pulse to be generated. writing to mdasmar in the ocb and ocab modes also enables the corresponding channel a comparator until the next successful comparison. in the opwm mode, mdasmar is loaded with the value corresponding to the leading edge of the pwm pulse to be generated. note: in ic, ipm, or ipwm mode, when a read to register a or b occurs at the same time as a counter bus capture into that register and the counter bus is changing value, then the counter bus capture to that register is delayed. table 17-20. mdasm address map (continued) address register motorola chapter 17. modular input/output subsystem (mios14) 17-45 mios14 double action submodule (mdasm) 17.9.8.3 mdasm datab (mdasmbr) register bits msb 0 1234567891011121314lsb 15 br sreset: uuuuuuuuuuuuuuuu figure 17-22. mdasmbr ? mdasm datab register 0x30 605a 0x30 6062 0x30 606a 0x30 6072 0x30 607a 0x30 60da 0x30 60e2 0x30 60ea 0x30 60f2 0x30 60fa table 17-22. mdasmbr bit descriptions bit(s) name description 0:15 br mdasmbr is the data register associated with channel b; its use varies with the different modes of operation. writing to register b always writes to b1 and, depending on the mode selected, sometimes to b2. reading register b either reads b1 or b2 depending on the mode selected. in the dis mode, mdasmbr can be accessed to prepare a value for a subsequent mode selection. in this mode, register b1 is accessed in order to prepare a value for the opwm mode. unused register b2 is hidden and cannot be read, but is written with the same value when register b1 is written. in the ipwm mode, mdasmbr contains the captured value corresponding to the leading edge of the measured pulse. in this mode, register b2 is accessed; buffer register b1 is hidden and is not readable. in the ipm and ic modes, mdasmbr contains the captured value corresponding to the previously dedicated edge (rising or falling edge). in this mode, register b2 is accessed; buffer register b1 is hidden and is not readable. in the ocb and ocab modes, mdasmbr is loaded with the value corresponding to the trailing edge of the pulse to be generated. writing to mdasmbr in the ocb and ocab modes also enables the corresponding channel b comparator until the next successful comparison. in this mode, register b2 is accessed; buffer register b1 is hidden and is not readable. in the opwm mode, mdasmbr is loaded with the value corresponding to the trailing edge of the pwm pulse to be generated. in this mode, register b1 is accessed; buffer register b2 is hidden and cannot be accessed. note: in ic, ipm, or ipwm mode, when a read to register a or b occurs at the same time as a counter bus capture into that register and the counter bus is changing value, then the counter bus capture to that register is delayed. 17-46 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) 17.9.9 mdasmscrd ? mdasm status/control register (duplicated) the mdasmscrd and the mdasmscr are the same registers accessed at two different addresses. reading or writing to one of these two addresses has exactly the same effect. warning the user should not write directly to the address of the mdasmscrd. this register?s address may be reserved for future use and should not be accessed by the software to ensure future software compatibility. the duplication of the scr register allows coherent 32-bit accesses when using an rcpu. 17.9.10mdasmscr ? mdasm status/control register the status and control register gathers a read only bit reflecting the status of the mdasm pin as well as read/write bits related to its control and configuration. the pin input status bit reflects the status of the corresponding pin when in input mode. when in output mode, the pin bit only reflects the status of the output flip-flop . msb 0 1234567891011121314lsb 15 pin wor fren rsvd edp for for reserved bsl rsvd mode sreset: ?000000000000000 figure 17-23. mdasmscr ? mdasm status/control register 0x30 605e 0x30 6066 0x30 606e 0x30 6076 0x30 607e 0x30 60de 0x30 60e6 0x30 60ee 0x30 60f6 0x30 60fe motorola chapter 17. modular input/output subsystem (mios14) 17-47 mios14 double action submodule (mdasm) table 17-23. mdasmscr bit descriptions bit(s) name description 0 pin pin input status ? the pin input status bit reflects the status of the corresponding bit. 1 wor wired-or bit ? in the dis, ipwm, ipm and ic modes, the wor bit is not used; reading this bit returns the value that was previously written. in the ocb, ocab and opwm modes, the wor bit selects whether the output buffer is configured for open-drain or totem pole operation. 1 output buffer is open-drain. 0 output buffer is totem pole. the wor bit is cleared by reset. 2 fren freeze enable bit ? this active high read/write control bit enables the mdasm to recognize the miob freeze signal. 1 = the mdasm is frozen if the miob freeze line is active. 0=themdasmisnotfrozenevenifthemiobfreezelineisactive. the fren is cleared by reset. 3?reserved 4 edpol polarity bit ? in the dis mode, this bit is not used; reading it returns the last value written. in the ipwm mode, this bit is used to select the capture edge sensitivity of channels a and b. 1 channel a captures on a falling edge. channel b captures on a rising edge. 0 channel a captures on a rising edge. channel b captures on a falling edge. in the ipm and ic modes, the edpol bit is used to select the input capture edge sensitivity of channel a. 1 channel a captures on a falling edge. 0 channel a captures on a rising edge. in the ocb, ocab and opwm modes, the edpol bit is used to select the voltage level on the output pin. 1 the complement of the output flip-flop logic level appears on the output pin: a match on channel a resets the output pin; a match on channel b sets the output pin. 0 the output flip-flop logic level appears on the output pin: a match on channel a sets the output pin, a match on channel b resets the output pin. the edpol bit is cleared by reset. 5 forca force a bit ? in the ocb, ocab and opwm modes, the forca bit allows the software to force the output flip-flop to behave as if a successful comparison had occurred on channel a (except that the flag line is not activated). writing a one to forca sets the output flip-flop; writing a zero to it has no effect. in the dis, ipwm, ipm and ic modes, the forca bit is not used and writing to it has no effect. forca is cleared by reset and is always read as zero. writing a one to both forca and forcb simultaneously resets the output flip-flop. 6 forcb force b bit ? in the ocb, ocab and opwm modes, the forcb bit allows the software to force the output flip-flop to behave as if a successful comparison had occurred on channel b (except that the flag line is not activated). writing a one to forcb resets the output flip-flop; writing a zero to it has no effect. in the dis, ipwm, ipm and ic modes, the forcb bit is not used and writing to it has no effect. forcb is cleared by reset and is always read as zero. writing a one to both forca and forcb simultaneously resets the output flip-flop. 7:8 ? reserved 9:10 bsl bus select bits ? these bits are used to select which of the six 16-bit counter buses is used by the mdasm. each mdasm instance has four possible counter buses that may be connected. see table 17-25 for more information. note: unconnected counter buses inputs are grounded. 17-48 mpc565/mpc566 reference manual motorola mios14 double action submodule (mdasm) mdas 11 ? reserved 12:15 mode mode select bits ? the four mode select bits select the mode of operation of the mdasm. to avoid spurious interrupts, it is recommended that mdasm interrupts are disabled before changing the operating mode. the mode select bits are cleared by reset. note: the reserved modes should not be set; if these modes are set, the mdasm behavior is undefined. table 17-24. mdasm mode selects mdasm control register bits bits of resolution counter bus bits ignored mdasm mode of operation mode 0000 ? ? dis ? disabled 0001 16 ? ipwm ? input pulse width measurement 0010 16 ? ipm ? input period measurement 0011 16 ? ic ? input capture 0100 16 ? ocb ? output compare, flag on b compare 0101 16 ? ocab ? output compare, flag on a and b compare 0110 ? ? reserved 0111 ? ? reserved 1000 16 ? opwm ? output pulse width modulation 1001 15 0 opwm ? output pulse width modulation 1010 14 0,1 opwm ? output pulse width modulation 1011 13 0-2 opwm ? output pulse width modulation 1100 12 0-3 opwm ? output pulse width modulation 1101 11 0-4 opwm ? output pulse width modulation 1110 9 0-6 opwm ? output pulse width modulation 1111 7 0-8 opwm ? output pulse width modulation table 17-25. mdasm counter bus selection sub- module type block number connected to: cba cbb cbc cbd bsl0=0 bsl1=0 bsl0=1 bsl1=0 bsl0=0 bsl1=1 bsl0=1 bsl1=1 mdasm 11 cb6 cb22 cb7 cb8 mdasm 12 cb6 cb22 cb7 cb8 table 17-23. mdasmscr bit descriptions (continued) bit(s) name description motorola chapter 17. modular input/output subsystem (mios14) 17-49 mios14 pulse width modulation submodule (mpwmsm) 17.10mios14 pulse width modulation submodule (mpwmsm) the mios14 pulse width modulation submodule (mpwmsm) is a function included in the mios14 library. it allows pulse width modulated signals to be generated over a wide range of frequencies, independently of other mios14 output signals and with no software intervention. the output pulse width can vary from 0% to 100%. the minimum pulse width is twice the minimum mios14 clock period (i.e., the minimum pulse width is 50 ns when f sys is 40 mhz). the mwpmsm can run in a double-buffered mode, to avoid spurious update. the following sections describe the mpwmsm in detail. a block diagram of the mpwmsm is shown in figure 17-24. mdasm 13 cb6 cb22 cb23 cb24 mdasm 14 cb6 cb22 cb23 cb24 mdasm 15 cb6 cb22 cb23 cb24 mdasm 27 cb6 cb22 cb23 cb24 mdasm 28 cb6 cb22 cb23 cb24 mdasm 29 cb6 cb22 cb7 cb8 mdasm 30 cb6 cb22 cb7 cb8 mdasm 31 cb6 cb22 cb7 cb8 table 17-25. mdasm counter bus selection (continued) sub- module type block number connected to: cba cbb cbc cbd bsl0=0 bsl1=0 bsl0=1 bsl1=0 bsl0=0 bsl1=1 bsl0=1 bsl1=1 17-50 mpc565/mpc566 reference manual motorola mios14 pulse width modulation submodule (mpwmsm) figure 17-24. mpwmsm block diagram 17.10.1mpwmsm terminology bits of resolution ? the mpwmsm contains a 16-bit modulus down-counter that counts from the desired loaded value to 0x0001. the term ?bits of resolution? is used in this document to indicate the size of the equivalent free running binary counter. to cover the worst case, the number of bits is rounded to the lower number. for example, if the counter is preset with a value between 128 and 255, it is said to have seven bits of resolution. if it is preset with a value between 256 and 511, it is said to have eight bits of resolution, and so on. resolution ? the term ?resolution? is used in this document to define the minimum mpwmsm output increment in time units. 17.10.2mpwmsm features ? output pulse width modulated (pwm) signal generation with no software intervention ? built-in 8-bit programmable prescaler clocked by the mcpsm 16-bit down counter 8- bit prescaler ps7 - ps0 output submodule bus buffer (ncount) = 0x0001 pol next period register mpwmperr 16-bit pulse width register next pulse width register mpwmpulr2 output flip-flop pin trsp en counter output pin mpwmcntr request bus <= comparator load fren clock flag en ddr output logic output logic mpwmpulr1 motorola chapter 17. modular input/output subsystem (mios14) 17-51 mios14 pulse width modulation submodule (mpwmsm) ? pwm period and pulse width values provided by software: ? double-buffered for glitch-free period and pulse width changes ? minimum output period/pulse-width increment: 50 ns (assuming f sys =40 mhz) ? maximum 50% duty-cycle output frequency: 10 mhz (assuming f sys =40 mhz) ? up to 16 bits of resolution for the output pulse width ? wide range of periods 16 bits of resolution: period range from 3.27 ms (with 50-ns steps) to 6.71 s (with 102.4 s steps) eight bits of resolution: period range from 12.8 s(with 50-ns steps) to 26.2 ms (with 102.4- s steps) ? wide range of frequencies maximum output frequency at f sys = 40 mhz with 16 bits of resolution and divide-by-2 prescaler selection: 305 hz (3.27 ms.) minimum output frequency at f sys = 40 mhz with 16 bits of resolution and divide-by-4096 prescaler selection: 0.15 hz (6.7 s.) maximum output frequency at f sys = 40 mhz with 8 bits of resolution and divide-by-2 prescaler selection: 78125 hz (12.8 s.) minimum output frequency at f sys = 40 mhz with 8 bits of resolution and divide-by-4096 prescaler selection: 38.15 hz (26.2 ms.) ? programmable duty cycle from 0% to 100% ? possible interrupt generation at start of every period ? software selectable output pulse polarity ? software readable output pin status ? possible use of pin as i/o port when pwm function is not needed 17.10.3mpwmsm description the purpose of the mpwmsm is to create a variable pulse width output signal at a wide range of frequencies, independently of other mios14 output signals. the mpwmsm includes its own counter, and thus does not use the mios14 counter bus set. however the mpwmsm uses the prescaled clock bus that originates in the mios14 counter prescaler submodule (mcpsm). the mpwmsm pulse width can vary from 0.0 percent to 100.0 17-52 mpc565/mpc566 reference manual motorola mios14 pulse width modulation submodule (mpwmsm) percent, with up to 16 bits of resolution. the finest output resolution is the mios14 clock period multiplied by two (for a mios14 clock with f sys = 40 mhz, the finest output pulse width resolution is 50 ns). with the full 16 bits of resolution and the mcpsm set to divide by two, the period of the output signal can range from 3.276 ms to 6.71 s (assuming f sys =40mhz). by reducing the amount of bits of resolution, the output signal period can be reduced. for example, the period can be as fast as 204.8 s (4882 hz) with 12 bits of resolution, as fast as 12.8 s (78.125 khz) with eight bits of resolution, and as fast as 3.2 s (312.5 khz) with six bits of resolution (still assuming a f sys = 40 mhz and the mcpsm set to divide by two). the mpwmsm is composed of: an output flip-flop with output buffer and polarity control an input/output pin with data direction control an 8-bit prescaler and clock selection logic a 16-bit down-counter (mpwmcntr) a register to hold the next period values (mpwmperr) two registers to hold the current and next pulse width values (mpwmpulr) a less-than or equal comparator a status and control register (mpwmscr) 17.10.3.1 clock selection the mpwmsm contains an 8-bit prescaler clocked by the output signal from the mios14 counter prescaler submodule (f sys /2 to f sys /16). the mpwmsm clock selector allows the choice, by software, of one of 256 divide ratios which give to the mpwmsm a large choice of frequencies available for the down-counter. the mpwmsm down-counter is thus capable of counting with a clock frequency ranging from f sys /2 to f sys /4096. switching the mpwmsm from disable to enable will reload the value of mpwmscr[cp] into the 8-bit prescaler counter. 17.10.3.2 counter a 16-bit down-counter in the mpwmsm provides the time reference for the output signal. the counter is software writable. when writing to the counter (i.e., at the mpwmcntr address), it also writes to the mpwmperr register. when in transparent mode (trsp = 1), writing to the mpwmperr will also write to the counter. the down-counter is readable at anytime. the value loaded in the down-counter corresponds to the period of the output signal. motorola chapter 17. modular input/output subsystem (mios14) 17-53 mios14 pulse width modulation submodule (mpwmsm) when the mpwmsm is enabled, the counter begins counting. as long as it is enabled, the counter counts down freely. the counter counts at the rate established by the prescaler. when the count down reaches 0x0001, the load operation is executed and the value in the mpwmperr register is loaded in the mpwmcntr register, (i.e., the counter). then the counter restarts to count down from that value. 17.10.3.3 period register the period section is composed of a 16-bit data register (mpwmperr). the software establishes the period of the output signal in register mpwmperr. when the mpwmsm is running in transparent mode, the period value in register mpwmperr is immediately transferred to the counter on a write to the mpwmperr. when the mpwmsm is running in double-buffered mode, the period value in register mpwmperr can be changed at any time without affecting the current period of the output signal. the new value mpwmperr will be transferred to the counter only when the counter reaches the value of 0x0001 and generates a load signal. period values of 0x0000, 0x0001 and 0x0002 are mpwmsm special cases: the value 0x0000 in the period register, causes the counter to act like a free running counter. this condition creates a period of 65536 pwm clock periods. the value 0x0001 in the period register will always cause a period match to occur and the counter will never decrement below 0x0001. this condition is defined as a period of ?1? pwm clock count. the output flip-flop is always set unless the value in the mpwmpulr = 0x0000, when the output flip-flop is always reset. refer to section 17.10.3.5, ?0% and 100% duty cycles? for details about 0% and 100% duty cycles. writing value 0x0002 in the period register causes a period match to occur every two clock periods. the counter decrements from 0x0002 to 0x0001, and then it is initialized back to 0x0002. this condition is defined as a period of ?2? clock count. note that the value 0x0002 loaded in the period register and a value of 0x0001 in the pulse width register is the condition to obtain the maximum possible output frequency for a given clock period. the relationship between the output frequency obtained (f pwmo ) and the mios14 clock frequency (f sys ), the mcpsm clock divide ratio (n mcpsm ), the counter divide ratio (n mpwmsm ) and the value loaded in the counter (v counter ) is given by the following equation: f pwmo = f sys n mcpsm n mpwmsm v counter 17-54 mpc565/mpc566 reference manual motorola mios14 pulse width modulation submodule (mpwmsm) 17.10.3.4 pulse width registers the pulse width section is composed of two 16-bit data registers (mpwmpulr1 and mpwmpulr2). only register mpwmpulr1 is accessible by software. the software establishes the pulse width of the mpwmsm output signal in register mpwmpulr1. register mpwmpulr2 is used as a double buffer of register mpwmpulr1. when the mpwmsm is running in transparent mode, the pulse width value in register mpwmpulr1 is immediately transferred in the register mpwmpulr2 so that the new value takes effect immediately. note when the mpwmsm is in disable mode, writing to mpwmpulr1 will write automatically to mpwmpulr2. when the mpwmsm is not running in double-buffered mode, the pulse width value in register mpwmpulr1 can be changed at any time without affecting the current pulse width of the output signal. the new value mpwmpulr1 will be transferred to mpwmpulr2 only when the down-counter reaches the value of 0x0001. when the counter first reaches the value in register mpwmpulr2, the output flip-flop is set. the output is reset when the counter reaches 0x0001. the pulse width match starts the width of the output signal, it does not affect the counter. register mpwmpulr1 is software readable and writable at any time. the mpwmsm does not modify the content of register mpwmpulr1. the pwm output pulse width can be as wide as one period minus one mpwmsm clock count: (i.e., mpwmpulr2 = mpwmperr ? [one mpwmsm clock count]). at the other end of the pulse width range, register mpwmpulr2 can contain 0x0001 to create a pulse width of one pwm clock count. for example, with 0x00ff in the counter and 0x0002 in mpwmpulr2, the period is 255 pwm clock count and the pulse width is 2 pwm clock counts. for a given system clock frequency, with a given counter divide ratio and clock selection divide ratio, the output pulse width is given by the following equation: where v mpwmb2 is the value in the register b2 in such conditions, the minimum output pulse width that can be obtained is given by: pulse_width n mcpsm n mpwmsm ? v mpwmb2 ? f sys ------------------------------------------------------------------------------------ - = minimum_pulse_width n mcpsm n mpwmsm ? f sys ----------------------------------------------------- = motorola chapter 17. modular input/output subsystem (mios14) 17-55 mios14 pulse width modulation submodule (mpwmsm) and the maximum pulse width by: 17.10.3.5 0% and 100% duty cycles the 0% and 100% duty cycles are special cases to give flexibility to the software to create a full range of outputs. the ?always set? and ?always clear? conditions of the output flip-flop are established by the value in register mpwmpulr2. these boundary conditions are generated by software, just like another pulse. when the pwm output is being used to generate an analog level, the 0% and 100% represent the full scale values. the 0% output is created with a 0x0000 in register mpwmpulr2, which prevents the output flip-flop from ever being set. the 100% output is created when the content of register mpwmpulr2 is equal to or greater than the content of register mpwmperr. thus, the width register match occurs on counter reload. the state sequencer provides the timing to ensure that the first appearance of a 100% value in register mpwmpulr2 causes a glitchless always-set condition of the output flip-flop when trsp = ?0?. note even if the output is forced to 100%, the 16-bit up counter continues its counting and that output changes to or from the 100% value are done synchronously to the selected period. note when a pwm output period is selected to be 65536 pwm clocks by loading 0x0000 in the period register, it is not possible to have an 100% duty cycle output signal. in this case, the maximum duty cycle available is of 65535/65536. 17.10.3.6 pulse/frequency range table table 17-26 summarizes the frequency and minimum pulse width values that can be obtained respectively with divide-by-1 and divide-by-256 mpwmsm clock prescaler options, while using a mios14 clock frequency of 40 mhz, and for each mcpsm clock divide ratios. maximum_pulse_width n mcpsm n mpwmsm ? 2 bit_of_resolution 1 ? () ? f sys ------------------------------------------------------------------------------------------------------------- = 17-56 mpc565/mpc566 reference manual motorola mios14 pulse width modulation submodule (mpwmsm) table 17-26. pwm pulse/frequency ranges (in hz) using /1 or /256 option (40 mhz) minimum pulse width bits of resolution 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 with /1 option 50 ns/2 305 610 1220 2441 4882 9765 19.5k 39k 78k 156k 312k 625k 1250 k 2500k 5000k 10000k 75 ns/3 203 407 814 1628 3255 6510 13k 26k 52k 104k 208k 416k 833 k 1666k 3333k 6666k 100 ns/4 152 305 610 1220 2441 4882 9765 19.5k 39k 78k 156k 312k 625 k 1250k 2500k 5000k 125 ns/5 122 244 488 976 1953 3906 7812 15.6k 31.3k 62.5k 125k 250k 500 k 1000k 2000k 4000k 150 ns/6 101 203 407 814 1628 3255 6510 13k 26k 52k 104k 208k 416 k 833k 1666k 3333k 175 ns/7 87.2 174 348 697 1395 2790 5580 11.1k 22.3k 44.6k 89.3k 178k 357k 714k 1428k 2857k 200 ns/8 76.3 152 305 610 1220 2441 4882 9765 19.5k 39k 78k 156 k 312 k 625k 1250k 2500k 225 ns/9 67.8 135 271 542 1085 2170 4340 8680 17.3k 34.7k 69.4k 138k 277k 555k 1111k 2222k 250 ns/10 61 122 244 488 976 1953 3906 7812 15.k 31.3k 62.5k 125k 250 k 500 k 1000k 2000k 275 ns/11 55.5 111 222 443 887 1775 3551 7102 14.2k 28.4k 56.8k 113k 227 k 454k 909 k 1818 k 300 ns/12 50.8 101 203 407 814 1628 3255 6510 13k 26k 52k 104k 208 k 416k 833 k 1666 k 325 ns/13 46.9 93.9 187 375 751 1502 3004 6009 12k 24k 48k 96.1k 192 k 384k 769 k 1538 k 350 ns/14 43.6 87.2 174 348 697 1395 2790 5580 11.1k 22.3 k 44.6k 89.3k 178 k 357k 714 k 1428k 375 ns/15 40.7 81.4 162 325 651 1302 2604 5208 10.4k 20.8 k 41.6k 83.3k 166 k 333k 666 k 1333 k 400 ns/16 38.1 76.3 152 305 610 1220 2441 4882 9765 19.5k 39k 78k 156k 312k 625k 1250k with /256 option 12.8 motorola chapter 17. modular input/output subsystem (mios14) 17-57 mios14 pulse width modulation submodule (mpwmsm) 17.10.3.7 mpwmsm status and control register (scr) one register is used to initialize the mpwmsm and monitor its operation. control bits are included to allow the software to enable the pwm generator, establish the output signal polarity, select the counter clock rate and set the glitch-free mode. a status bit is included to allow the software to read the state of the output pin. 17.10.3.8 mpwmsm interrupt a valid mpwmsm interrupt is recognized when a pulse occurs on the flag line to set the flag bit and the interrupt enable bit is set for the corresponding level in the mirsm (refer to section 17.12, ?mios14 interrupts,? section 17.12.1, ?mios14 interrupt structure? and section 17.12.2, ?mios14 interrupt request submodule (mirsm)? for details about interrupts). a set flag pulse is generated at the start of every period. the flag bit is a status bit which indicates, when set, that the output period has started and that registers mpwmperr and mpwmpulr1 are available for updates when in double-buffered mode. the level of the resulting interrupt is determined in the mirsm. 17.10.3.9 mpwmsm port functions the mpwmsm has one dedicated i/o external pin. the output flip-flop is the basic output of the mpwmsm. except when the pulse width is at 100% or 0%, the output flip-flop is reset at the beginning of each period and is set at the beginning of the designated pulse width until the end of the period. as a software option, the polarity of the signal presented to the output pin may be the state of the output flip-flop or the inverse of the output flip-flop. the mpwmsm is connected to an external, input/output pin. when in the disabled mode, the pol bit (polarity) and the ddr bit (data direction) in the scr register allow the mpwmsm to be used as an i/o port. 17.10.3.10mpwmsm data coherency byte accesses to mpwmpulr and mpwmperr are supported, but are not recommended as the transfer from the primary registers to the secondary registers are done as a 16-bit word transfer. for most mpwmsm operations, 16-bit accesses are sufficient and long word accesses (32-bit) are treated as two 16-bit accesses, with one exception ? a long word write to the period/pulse width registers. in this case, if the long word write takes place within the pwm period, there is no visible effect on the output signal and the new values stored in mpwmperr and mpwmpulr are ready to be loaded into the buffer registers at the start of the next period. if, however, the long word write coincides with the end of the period, then the transfer of values from the primary to the secondary registers is delayed until the 17-58 mpc565/mpc566 reference manual motorola mios14 pulse width modulation submodule (mpwmsm) end of the next period; during this period the previous values are used for the period and width this feature enables updates of the period and pulse-width values without getting erroneous pulses. 17.10.4modular input/output bus (mios14) interface the mpwmsm is connected to all the signals in the read/write and control bus, to allow data transfer from and to the mpwmsm registers, and to control the mpwmsm in the different possible situations. the mpwmsm is not using any of the 16-bit counter buses the mpwmsm uses the request bus to transmit to the request submodule 17.10.5effect of reset on mpwmsm the mpwmsm is affected by reset according to what is described in the section related to register description. the mpwmperr, mpwmpulr, and mpwmcntr registers, together with the clock prescaler register bits, must be initialized by software, since they are undefined after hardware reset. a value must be written to the mpwmcntr (which writes the same value into the mpwmperr) and a pulse width value written to mpwmpulr, before the mpwmscr is written to. the latter access initializes the clock prescaler. 17.10.6mpwmsm registers the privilege level to access to the mpwmsm registers depends on the mios14mcr supv bit. the privilege level is unrestricted after reset and can be change to supervisor by software. 17.10.6.1 mpwmsm registers organization the mpwmsm register map comprises four 16-bit register locations, as shown below. all unused bits return zero when read by the software. all register addresses in this section are specified as offsets from the base address of the mpwmsm. table 17-27. mpwmsm address map address register mpwmsm0 0x30 6000 mpwmsm0 period register (mpwmperr) see table 17-28 for bit descriptions. 0x30 6002 mpwmsm0 pulse register (mpwmpulr) see table 17-29 for bit descriptions. motorola chapter 17. modular input/output subsystem (mios14) 17-59 mios14 pulse width modulation submodule (mpwmsm) 0x30 6004 mpwmsm0 count register (mpwmcntr) see table 17-30 for bit descriptions. 0x30 6006 mpwmsm0 status/control register (mpwmscr) see table 17-31 for bit descriptions. mpwmsm1 0x30 6008 mpwmsm1 period register (mpwmperr) 0x30 600a mpwmsm1 pulse register (mpwmpulr) 0x30 600c mpwmsm1 count register (mpwmcntr) 0x30 600e mpwmsm1 status/control register (mpwmscr) mpwmsm2 0x30 6010 mpwmsm2 period register (mpwmperr) 0x30 6012 mpwmsm2 pulse register (mpwmpulr) 0x30 6014 mpwmsm2 count register (mpwmcntr) 0x30 6016 mpwmsm2 status/control register (mpwmscr) mpwmsm3 0x30 6018 mpwmsm3 period register (mpwmperr) 0x30 601a mpwmsm3 pulse register (mpwmpulr) 0x30 601c mpwmsm3 count register (mpwmcntr) 0x30 601e mpwmsm3 status/control register (mpwmscr) mpwmsm4 0x30 6020 mpwmsm4 period register (mpwmperr) 0x30 6022 mpwmsm4 pulse register (mpwmpulr) 0x30 6024 mpwmsm4 count register (mpwmcntr) 0x30 6026 mpwmsm4 status/control register (mpwmscr) mpwmsm5 0x30 6028 mpwmsm5 period register (mpwmperr) 0x30 602a mpwmsm5 pulse register (mpwmpulr) 0x30 602c mpwmsm5 count register (mpwmcntr) 0x30 602e mpwmsm5 status/control register (mpwmscr) mpwmsm16 0x30 6080 mpwmsm16 period register (mpwmperr) 0x30 6082 mpwmsm16 pulse register (mpwmpulr) 0x30 6084 mpwmsm16 count register (mpwmcntr) 0x30 6086 mpwmsm16 status/control register (mpwmscr) table 17-27. mpwmsm address map (continued) address register 17-60 mpc565/mpc566 reference manual motorola mios14 pulse width modulation submodule (mpwmsm) 17.10.6.2 mpwmperr ? mpwmsm period register mpwmperr address: mpwmsm base address the period register contains the binary value corresponding to the period to be generated. mpwmsm17 0x30 6088 mpwmsm17 period register (mpwmperr) 0x30 608a mpwmsm17 pulse register (mpwmpulr) 0x30 608c mpwmsm17 count register (mpwmcntr) 0x30 608e mpwmsm17 status/control register (mpwmscr) mpwmsm18 0x30 6090 mpwmsm18 period register (mpwmperr) 0x30 6092 mpwmsm18 pulse register (mpwmpulr) 0x30 6094 mpwmsm18 count register (mpwmcntr) 0x30 6096 mpwmsm18 status/control register (mpwmscr) mpwmsm19 0x30 6098 mpwmsm19 period register (mpwmperr) 0x30 609a mpwmsm19 pulse register (mpwmpulr) 0x30 609c mpwmsm19 count register (mpwmcntr) 0x30 609e mpwmsm19 status/control register (mpwmscr) mpwmsm20 0x30 60a0 mpwmsm20 period register (mpwmperr) 0x30 60a2 mpwmsm20 pulse register (mpwmpulr) 0x30 60a4 mpwmsm20 count register (mpwmcntr) 0x30 60a6 mpwmsm20 status/control register (mpwmscr) mpwmsm21 0x30 60a8 mpwmsm21 period register (mpwmperr) 0x30 60aa mpwmsm21 pulse register (mpwmpulr) 0x30 60ac mpwmsm21 count register (mpwmcntr) 0x30 60ae mpwmsm21 status/control register (mpwmscr) table 17-27. mpwmsm address map (continued) address register motorola chapter 17. modular input/output subsystem (mios14) 17-61 mios14 pulse width modulation submodule (mpwmsm) 17.10.6.3 mpwmpulr ? mpwmsm pulse width register the pulse width register contains the binary value of the pulse width to be generated. msb 0 1234567891011121314lsb 15 per sreset: uuuuuuuuuuuuuuuu figure 17-25. mpwmperr ? mpwmsm period register 0x30 6000 0x30 6008 0x30 6010 0x30 6018 0x30 6020 0x30 6028 0x30 6080 0x30 6088 0x30 6090 0x30 6098 0x30 60a0 0x30 60a8 table 17-28. mpwmperr bit descriptions bit(s) name description 0:15 per period. these bits contain the binary value corresponding to the period to be generated. 17-62 mpc565/mpc566 reference manual motorola mios14 pulse width modulation submodule (mpwmsm) 17.10.6.4 mpwmcntr ? mpwmsm counter register the counter register reflects the actual value of the mpwmsm counter. this register is writable only through the period register (pwmperr). writes to the counter register will write the same value to the period register. msb 0 1234567891011121314lsb 15 pul sreset: uuuuuuuuuuuuuuuu figure 17-26. mpwmpulr ? mpwmsm pulse width register 0x30 6002 0x30 600a 0x30 6012 0x30 601a 0x30 6022 0x30 602a 0x30 6082 0x30 608a 0x30 6092 0x30 609a 0x30 60a2 0x30 60aa table 17-29. mpwmpulr bit descriptions bit(s) name description 0:15 pul pulse width. these bits contain the binary value of the pulse width to be generated. motorola chapter 17. modular input/output subsystem (mios14) 17-63 mios14 pulse width modulation submodule (mpwmsm) 17.10.6.5 mpwmscr ? mpwmsm status/control register the status and control register gathers read only bits reflecting the status of the mpwmsm pin as well as read/write bits related to its control and configuration. msb 0 1234567891011121314lsb 15 cnt sreset: uuuuuuuuuuuuuuuu figure 17-27. mpwmcntr ? mpwmsm counter register 0x30 6004 0x30 600c 0x30 6014 0x30 601c 0x30 6024 0x30 602c 0x30 6084 0x30 608c 0x30 6094 0x30 609c 0x30 60a4 0x30 60ac table 17-30. mpwmcntr bit descriptions bit(s) name description 0:15 cnt counter. these bits reflect the actual value of the mpwmsm counter. 17-64 mpc565/mpc566 reference manual motorola mios14 pulse width modulation submodule (mpwmsm) msb 0 1234567891011121314lsb 15 pin ddr fren trsp pol en reserved cp sreset: u00000 uuuuuuuuuu figure 17-28. mpwmcntr ? mpwmsm counter register 0x30 6004 0x30 600c 0x30 6014 0x30 601c 0x30 6024 0x30 602c 0x30 6084 0x30 608c 0x30 6094 0x30 609c 0x30 60a4 0x30 60ac table 17-31. mpwmscr bit descriptions bit(s) name description 0 pin pin input status bit ? the pin bit reflects the state present on the mpwmsm pin. the software can thus monitor the signal on the pin. the pin bit is a read-only bit. writing to the pin bit has no effect. 1 ddr data direction register ? the ddr bit indicates the direction for the pin when the pwm function is not used (disable mode). 0 pin is in input. 1 pin is in output. the ddr bit is cleared by reset. table 17-32 lists the different uses for the polarity (pol) bit, the enable (en) bit and the data direction register (ddr) bit. 2 fren freeze enable bit ? this active high read/write control bit enables the mpwmsm to recognize thefreezesignalonthemiob. 0 mpwmsm not frozen even if the miob freeze line is active. 1 mpwmsm frozen if the miob freeze line is active. the fren is cleared by reset. 3 trsp transparent mode ? the trsp bit indicates that the mpwmsm is in transparent mode. in transparent mode, when the software writes to either the mpwmperr or mpwmpulr1 register the value written is immediately transferred to the counter or register mpwmpulr2 respectively. 0 double-buffered mode. 1 transparent mode. the trsp bit is cleared by reset. 4 pol output polarity control bit ? the pol bit works in conjunction with the en bit and controls whether the mpwmsm drives the pin with the direct or the inverted value of the output flip-flop. table 17-32 lists the different uses for the polarity (pol) bit, the enable (en) bit and the data direction register (ddr) bit. motorola chapter 17. modular input/output subsystem (mios14) 17-65 mios14 pulse width modulation submodule (mpwmsm) . 5 en enable pwm signal generation ? the en bit defines whether the mpwmsm generates a pwm signal or is used as an i/o channel: 0 pwm generation disabled (pin can be used as i/o). 1 pwm generation enabled (the pin is in output mode). each time the submodule is enabled, the value of cp is loaded into the prescaler. the en bit is cleared by reset. 6:7 ? reserved 8:15 cp clock prescaler ? this 8-bit read/write data register stores the modulus value for loading into the built-in 8-bit clock prescaler. the value loaded defines the divide ratio for the signal that clocks the mpwmsm. the new value is loaded into the prescaler counter on the prescaler counter overflow, or upon the en bit of the mpwmscr being set. table 17-33 gives the clock divide ratio according to the value of cp. table 17-32. pwmsm output pin polarity selection control bits pin direction pin state periodic edge variable edge optional interrupt on pol en ddr 0 0 0 input input ? ? ? 0 0 1 output always low ? ? ? 0 1 ? output high pulse rising edge falling edge rising edge 1 0 0 input input ? ? ? 1 0 1 output always high ? ? ? 1 1 ? output low pulse falling edge rising edge falling edge table 17-33. prescaler values prescaler value (cp in hex) mcpsm divide ratio: ff 1 fe 2 fd 3 fc 4 fb 5 fa 6 f9 7 f8 8 ...... ........ 02 254 (2^8 -2) 01 255 (2^8 -1) 00 256 (2^8) table 17-31. mpwmscr bit descriptions (continued) bit(s) name description 17-66 mpc565/mpc566 reference manual motorola mios14 16-bit parallel port i/o submodule (mpiosm) 17.11 mios14 16-bit parallel port i/o submodule (mpiosm) the mios14 parallel port i/o submodule (mpiosm) is a function included in the mios14 library in order to provide the required port i/o capability. the mpiosm can operate without the involvement of other mios14 submodules. each implemented mpiosm provides i/o capability for up to 16 pins. the following sections describe the mpiosm in detail. a block diagram of one bit of the mpiosm is shown in figure 17-29. the mpiosm contains 16 such blocks. figure 17-29. mpiosm 1-bit block diagram 17.11.1mpiosm features a submodule of the mios14 library uses two 16-bit registers in the address space up to 16 bidirectional parallel input/output pins simple ddr (data direction register) concept for pin direction selection 17.11.2mpiosm pin functions table 17-34 shows the mpiosm i/o pin functions according to the setting of the ddr when writing to or reading from the dr. i/o pin data register data register output input driver mios14 bus (miob) direction motorola chapter 17. modular input/output subsystem (mios14) 17-67 mios14 16-bit parallel port i/o submodule (mpiosm) 17.11.3mpiosm description 17.11.3.1 mpiosm port function a mios14 parallel port i/o submodule can handle up to 16 input/output pins. the number of i/o pins is determined at the time of silicon implementation. the mpiosm has two 16-bit registers: the data register (dr) and the data direction register (ddr). each pin of the mpiosm may be programmed as an input or an output, determined by the state of the corresponding bit in the ddr. the data direction register can be written to or read by the processor. during the programmed output state, a read of the data register reads the value of the output data latch and not the i/o pin. see figure 17-29 and table 17-34. during reset, all mpiosm pins are configured as inputs. the contents of the data register are undefined after reset. as a general practice, it is recommended to write a value in the data register before configuring its corresponding i/o pin as an output. 17.11.3.2 non-bonded mpiosm pads a non-bonded mpiosm pad reads ?0? when it is configured as an input. when configured as an output, it indicates the current state of the output data latch. 17.11.4modular i/o bus (miob) interface the mpiosm is connected to all the signals in the read/write and control bus, to allow data transfer from and to the mpiosm registers, and to control the mpiosm in the different possible situations. the mpiosm does not use the counter bus set and is therefore not connected to it. the mpiosm does not generate any interrupts and is therefore not connected to this bus. table 17-34. mpiosm i/o pin function operation performed ddr i/o pin function write 0 the i/o pin is in input mode. data is written into the dr. write 1 data is written into the dr and output to the i/o pin. read 0 the i/o pin is in input mode. the state of the i/o pin is read. read 1 the i/o pin is in an output mode. the dr is read. 17-68 mpc565/mpc566 reference manual motorola mios14 16-bit parallel port i/o submodule (mpiosm) 17.11.5effect of reset on mpiosm when the reset signal is asserted, all the ddr bits are cleared. the data bits are undefined after reset. 17.11.6mpiosm testing no special test logic has been implemented in this submodule. to be flexible while selecting the number of implemented pins, the test patterns are implemented in a bit per bit modular fashion. 17.11.7mpiosm registers the privilege level to access to the mpiosm registers depends on the mios14mcr supv bit. the privilege level is unrestricted after reset and can be change to supervisor by software. 17.11.8mpiosm register organization 17.11.8.1 mpiosmdr ? mpiosm data register msb 0 1234567891011121314lsb 15 0x30 6100 mpiosm data register (mpiosmdr) 0x30 6102 mpiosm data direction register (mpiosmddr) 0x30 6104 reserved 0x30 6106 reserved figure 17-30. mpiosm ? register organization msb 0 1234567891011121314lsb 15 data1 data1 data1 data1 data1 data1 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 sreset: uuuuuuuuuuuuuuuu figure 17-31. mpiosmdr ? mpiosm data register 0x30 6100 table 17-35. mpiosmdr bit descriptions bit(s) name description 0:15 data15 ?data0 these bits are read/write data bits that define the value to be driven to the pad in output mode, for each implemented i/o pin of the mpiosm motorola chapter 17. modular input/output subsystem (mios14) 17-69 mios14 interrupts 17.11.8.2 mpiosmddr ? mpiosm data direction register 17.12mios14 interrupts this section describes the interrupt functions of the mios14 and its submodules and how these interrupts are passed to the cpu via the peripheral bus. interrupt requests from the mios14 are treated as exceptions by the cpu and are dealt with by the cpu?s exception processing routines. for a more detailed description of exception processing in the relevant microprocessors, please refer chapter 3, ?central processing unit? and to the rcpu reference manual (rcpurm/ad) 17.12.1mios14 interrupt structure the mios14 and its submodules are capable of generating interrupts on different levels to be transmitted to the cpu via the peripheral bus. inside the mios14, all the information required for requesting and servicing the interrupts are treated in two different sections: the interrupt request submodules (mirsm) the interrupt control section (ics) of the mbism the mirsm gathers in service request flags from each group of up to 16 submodules and transfers those requests to the mios14 interrupt control section (ics). figure 17-33 shows a block diagram of the whole interrupt architecture. msb 0 1234567891011121314lsb 15 ddr1 ddr1 ddr1 ddr1 ddr1 ddr1 ddr9 ddr8 ddr7 ddr6 ddr5 ddr4 ddr3 ddr2 ddr1 ddr0 sreset: 0000000000000000 figure 17-32. mpiosmddr ? mpiosm data direction register 0x30 6102 table 17-36. mpiosmddr bit descriptions bit(s) name description 0:15 ddr15 ? ddr0 these bits are read/write data bits that define the data direction status for each implemented i/o pin of the mpiosm 0 = corresponding pin is input. 1 = corresponding pin is output. 17-70 mpc565/mpc566 reference manual motorola mios14 interrupts figure 17-33. mios14 interrupt structure 17.12.2mios14 interrupt request submodule (mirsm) each submodule that is capable of generating an interrupt can assert a flag line when an event occurs. on mpc565/mpc566 each mirsm serves 14 submodules. submodule 15 status register enable register irq pend. register mirsm0 level n enable register level m irq pend. register (flags) submodule 0 submodule 20 mirsm1 imb3 mbism interrupt control motorola chapter 17. modular input/output subsystem (mios14) 17-71 mios14 interrupts each mirsm includes: one 16-bit status register (for the flags) one 16-bit enable register for each implemented level one 16-bit irq pending register for each implemented level one bit position in each of the above registers is associated with one submodule. note if a submodule in a group of 16 cannot generate interrupts, then its corresponding flag bit in the status register is inactive and is read as zero. when an event occurs in a submodule that activates a flag line, the corresponding flag bit in the status register is set. the status register is read/write, but a flag bit can be reset only if it has previously been read as a one. writing a ?one? to a flag bit has no effect. when the software intends to clear only one flag bit within a status register, the software must write an all-ones 16-bit value except for the bit position to be cleared which is a zero. the enable register is initialized by the software to indicate whether each interrupt request is enabled for the levels defined in the ics. note in the case of multiple requests levels implementation in the same mios14, it is possible to enable interrupts at more than one different levels for the same submodule. it is the responsibility of the software to manage this. each bit in the irq pending register is the result of a logical ?and? between the corresponding bits in the status and in the enable registers. if a flag bit is set and the level enable bit is also set, then the irq pending bit is set, and the information is transferred to the interrupt control section that is in charge of sending the corresponding level to the cpu. the irq pending register is read only. note when the enable bit is not set for a particular submodule, the corresponding status register bit is still set when the corresponding flag is set. this allows the traditional software approach of polling the flag bits to see which ones are set. the status register makes flag polling easy, since up to 16 flag bits are contained in one register. 17-72 mpc565/mpc566 reference manual motorola mios14 interrupts the submodule number of an interrupting source defines the corresponding mirsm number and the bit position in the status registers. to find the mirsm number and bit position of an interrupting source, proceed as follow: 1. divide the interrupting submodule number by 16 2. the integer result of the division gives the mirsm number 3. the reminder of the division gives the bit position 17.12.3mirsm0 interrupt registers 17.12.3.1 mios14sr0 interrupt status register this register contains the flag bits that are raised when the submodules generate an interrupt. each bit corresponds to a given submodule. 17.12.3.2 mios14er0 interrupt enable register this register contains the interrupt enable bits for the submodules. each bit corresponds to a given submodule. msb 0 1234567891011121314lsb 15 flg1 flg1 flg1 flg1 flg1 reserved flg8 flg7 flg6 flg5 flg4 flg3 flg2 flg1 flg0 sreset: uuuuuuuuuuuuuuuu figure 17-34. mios14sr0 ? interrupt status register 0x30 6c00 table 17-37. mios14sr0 bit description bit(s) name description 0:4 flg15:11 flag bits ? mdasm flag bits [15:11] 5:6 ? reserved 7:9 flg8:6 flag bits ? mmcsm flag bits [8:6] 10:15 flg5:0 flag bits ? pwmsm flag bits [5:0] msb 0 1234567891011121314lsb 15 en15 en14 en13 en12 en11 reserved en8 en7 en6 en5 en4 en3 en2 en1 en0 sreset: 0000000000000000 figure 17-35. mios14er0 ? interrupt enable register 0x30 6c04 motorola chapter 17. modular input/output subsystem (mios14) 17-73 mios14 interrupts 17.12.3.3 mios14rpr0 interrupt request pending register this register is a read only register that contains the interrupt pending bits for the submodules. each bit corresponds to a given submodule. when one of these bits is set, it means that a submodule raised its flag and the corresponding enable was set. as this register is read only, a write to this register has no other effect than generating a bus error if the bus error option is selected. 17.12.4mirsm1 interrupt registers 17.12.4.1 mios14sr1 interrupt status register this register contains the flag bits that are raised when the submodules generate an interrupt. each bit corresponds to a given submodule. table 17-38. mios14er0 bit descriptions bit(s) name description 0:4 en15:11 enable bits ? mdasm enable bits [15:11] 5:6 ? reserved 7:9 en8:6 enable bits ? mmcsm enable bits [8:6] 10:15 en5:0 enable bits ? pwmsm enable bits [5:0] msb 0 1234567891011121314lsb 15 irp15 irp14 irp13 irp12 irp11 reserved irp8 irp7 irp6 irp5 irp4 irp3 irp2 irp1 irp0 sreset: 0000000000000000 figure 17-36. mios14rpr0 ? interrupt request pending register 0x30 6c06 table 17-39. mios14pr0 bit descriptions bit(s) name description 0:4 irp15:11 pending bits ? mdasm pending bits [15:11] 5:6 ? reserved 7:9 irp8:6 pending bits ? mmcsm pending bits [8:6] 10:15 irp5:0 pending bits ? pwmsm pending bits [5:0] 17-74 mpc565/mpc566 reference manual motorola mios14 interrupts 17.12.4.2 mios14er1 interrupt enable register this register contains the interrupt enable bits for the submodules. each bit corresponds to a given submodule. 17.12.4.3 mios14rpr1 interrupt request pending register this register is a read only register that contains the interrupt pending bits for the submodules. each bit corresponds to a given submodule. when one of these bits is set, it means that a submodule raised its flag and the corresponding enable was set. as this register is read only, a write to this register has no other effect than generating a bus error if the bus error option is selected. msb 0 1234567891011121314lsb 15 flg3 flg3 flg2 flg2 flg2 reserved flg2 flg2 flg2 flg2 flg2 flg1 flg1 flg1 flg1 sreset: 0000000000000000 figure 17-37. mios14sr1 ? interrupt status register 0x30 6c40 table 17-40. mios14sr1 bit descriptions bit(s) name description 0:4 flg31:27 flag bits ? mdasm flag bits [31:27] 5:6 ? reserved 7:9 flgl24:22 flag bit ? mmcsm flag bit [24:22] 10:15 flg21:16 flag bits ? pwmsm flag bits [21:16] msb 0 1234567891011121314lsb 15 en31 en30 en29 en28 en27 reserved en24 en23 en22 en21 en20 en19 en18 en17 en16 sreset: 0000000000000000 figure 17-38. mios14er1 ? interrupt enable register 0x30 6c44 table 17-41. mios14er1 bit descriptions bit(s) name description 0:4 en31:27 enable bits ? mdasm enable bits [31:27] 5:6 ? reserved 7:9 en24:22 enable bits ? mmcsm enable bits [24:22] 10:15 en21:16 enable bits ? pwmsm enable bits [21:16] motorola chapter 17. modular input/output subsystem (mios14) 17-75 mios14 interrupts 17.12.5interrupt control section (ics) the interrupt control section delivers the interrupt level to the cpu. the interrupt control section adapts the characteristics of the miob request bus to the characteristics of the interrupt structure of the imb3. when at least one of the flags is set on an enabled level, the ics receives a signal from the corresponding irq pending register. this signal is the result of a logical ?or? between all the bits of the irq pending register. the signal received from the irq pending register is associated with the interrupt level register within the ics. this level is coded on five bits in this register: three bits represent one of eight levels and the two other represent the four time multiplex slots. according to this level, the ics sets the correct irq [7:0] lines with the correct ilbs[1:0] time multiplex lines on the peripheral bus. the cpu is then informed as to which of the thirty-two interrupt levels is requested. based on the interrupt level requested, the software must determine which submodule requested the interrupt. the software may use a find-first-one type of instruction to determine, in the concerned mirsm, which of the bits is set. the cpu can then serve the requested interrupt. msb 0 1234567891011121314lsb 15 irp31 irp30 irp29 irp28 irp27 reserved irp24 irp23 irp22 irp21 irp20 irp19 irp18 irp17 irp16 sreset: 0000000000000000 figure 17-39. mios14rpr1 ? interrupt request pending register 0x30 6c46 table 17-42. mios14pr1 bit descriptions bit(s) name description 0:4 irp31:27 pending bits ? mdasm pending bits [31:27] 5:6 ? reserved 7:9 irp24:22 pending bits ? mmcsm pending bits [24:22] 10:15 irp21:16 pending bits ? pwmsm pending bits [21:16] 17-76 mpc565/mpc566 reference manual motorola mios14 interrupts 17.12.6mbism interrupt registers table 17-43 shows the mbism interrupt registers. 17.12.6.1 mios14 interrupt level register 0 (mios14lvl0) this register contains the interrupt level that applies to the submodules number 15 to zero. 17.12.6.2 mios14 interrupt level register 1 (mios14lvl1) this register contains the interrupt level that applies to the submodules number 15 to zero. table 17-43. mbism interrupt registers address map address register 0x30 6c30 mios14 interrupt level register 0 (mios14lvl0) see table 17-44 for bit descriptions. 0x30 6c70 mios14 interrupt level register 1 (mios14lvl1) see table 17-45 for bit descriptions. msb 0 1234567891011121314lsb 15 reserved lvl tm reserved reset: 0000000000 0 00000 figure 17-40. mios14lvl0 ? mios14 interrupt level register 0 0x30 6c30 table 17-44. mios14lvl0 bit descriptions bit(s) name description 0:4 ? reserved 5:7 lvl interrupt request level. this field represents one of eight possible levels. 8:9 tm time multiplexing. this field determines the multiplexed time slot 10:15 ? reserved msb 0 1234567891011121314lsb 15 reserved lvl tm reserved reset: 0000000000 0 00000 figure 17-41. mios14lvl1 ? mios14 interrupt level register 1 0x30 6c70 motorola chapter 17. modular input/output subsystem (mios14) 17-77 mios14 function examples 17.13mios14 function examples the versatility of the mios14 timer architecture is based on multiple counters and capture/compare channel units interconnected on 16-bit counter buses. this section includes some typical application examples to show how the submodules can be interconnected to form timing functions. the diagrams used to illustrate these examples show only the blocks utilized for that function. to illustrate the timing range of the mios14 in different applications, many of the following paragraphs include time intervals quoted in microseconds and seconds. the assumptions used are that f sys is at 40 mhz with minimum overall prescaling (50 ns cycle) and with the maximum overall prescaling (32 s cycle). for other f sys clock cycle rates and prescaler choices, the times mentioned in these paragraphs scale appropriately. 17.13.1mios14 input double edge pulse width measurement to measure the width of an input pulse, the mios14 double action submodule (mdasm) has two capture registers so that only one interrupt is needed after the second edge. the software can read both edge samples and subtract them to get the pulse width. the leading edge sample is double latched so that the software has the time of one full period of the input signal to read the samples to be sure that nothing is lost. depending on the prescaler divide ratio, pulse width from 50 ns to 6.7 s can be measured. note that a software option is provided to also generate an interrupt after the first edge. in the example shown in figure 17-42, a counter submodule is used as the time-base for a mdasm configured in the input pulse width measurement mode. when the leading edge (programmed for being either rising or falling) of the input signal occurs, the state of the 16-bit counter bus is saved in register b1. when the trailing edge occurs, the 16-bit counter bus is latched into register a and the content of register b1 is transferred to register b2. this operation leaves register b1 free for the next leading edge to occur on the next clock cycle. when enabled, an interrupt is provided after the trailing edge, to notify the software that pulse width measurement data is available for a new pulse. after the trailing edge, the software has one cycle time of the input signal to obtain the values for each edge. when software attention is not needed for every pulse, the interrupt can be disabled. the software can read registers a and b2 coherently (using a 32-bit read instruction) at any time, to get table 17-45. mios14lvl1 bit descriptions bit(s) name description 0:4 ? reserved 5:7 lvl interrupt request level. this field represents one of eight possible levels. 8:9 tm time multiplexing. this field determines the multiplexed time slot. 10:15 ? reserved 17-78 mpc565/mpc566 reference manual motorola mios14 function examples the latest edge measurements. the software work is less than half that needed with a timer that requires the software to read one edge and save the value and then wait for the second edge. figure 17-42. mios14 example: double capture pulse width measurement 17.13.2mios14 input double edge period measurement two samples are available to the software from an mios14 double action submodule for period measurement. the software can read the previous and the current edge samples and subtract them. as with pulse width measurement, the software can be sure not to miss samples by ensuring that the interrupt response time is faster than the fastest input period. alternately, when the software is just interested in the latest period measurement, one 32-bit coherent read instruction can get both the current and the previous samples. depending on the prescaler divide ratio, period times can be measured from 50 ns to 6.7 s. figure 17-43 shows a counter submodule and a dasm combination as an example of period measurement. the software designates whether the rising or falling edge of the input signal is to be used for the measurements. when the edge is detected, the state of the 16-bit counter bus is stored in register a and the content of register b1 is transferred to register b2. after register b2 is safely latched, the content of register a is transferred to register b1. this procedure gives the software coherent current and previous samples in registers a and b2 at all times. an interrupt is available for the cases where the software needs to be aware of each new sample. note that a software option is provided to also generate an interrupt after the first edge. 16-bit up-counter submodule bus clock select 16-bit register b1 edge detect input pin 16-bit register a input capture interrupt on from prescaler or pin trailing bus select edge two 16-bit counter buses 16-bit register b2 mios14 modulus counter submodule mios14 double action submodule in ipwm mode (mod3-mod0 = 0b0001) motorola chapter 17. modular input/output subsystem (mios14) 17-79 mios14 function examples figure 17-43. mios14 example: double capture period measurement 17.13.3mios14 double edge single output pulse generation software can initialize the mios14 to generate both the rising and the falling edge of an output pulse. with a mdasm, pulses as narrow as 50 ns can be generated since software action is not needed between the edges. pulses as long as 2.1 s can be generated. when an interrupt is desired, it can be selected to occur on every edge or only after the second edge. figure 17-44 shows how a counter submodule and a mdasm can be used to generate both edges of a single output pulse. the software puts the compare value for one edge in register a and the other one in register b2. the mdasm automatically creates both edges and the pulse can be selected by software to be a high-going or a low-going. after the trailing edge, the mdasm stops to await further commands from the software. note that a single edge output can be generated by writing to only one register. 16-bit up-counter submodule bus clock select 16-bit register b1 edge detect input pin 16-bit register b2 input capture interrupt on from prescaler or pin designated bus select edge 16-bit register a two 16-bit counter buses mios14 modulus counter submodule mios14 double action submodule in ipm mode (mod3-mod0 = 0b0010) 17-80 mpc565/mpc566 reference manual motorola mios14 function examples figure 17-44. mios14 example: double edge output compare 17.13.4mios14 output pulse width modulation with mdasm output waveforms can be generated with any duty cycle without software involvement. the software sets up a mdasm with the compare times for the rising and falling edges and they are automatically repeated. the software does not need to respond to interrupts to generate continuous pulses. the frequency may be selected as the frequency of a free-running counter time-base, times a binary multiplier selected in the mdasm. multiple pwm outputs can be created from multiple mdasms and share one counter submodule, provided that the frequencies of all of the output signals are a binary multiple of the time-base and that the counter submodule is operating in a free-running mode. each mdasm has a software selectable ?don?t care? on high-order bits of the time-base comparison so that the frequency of one output can be a binary multiple of another signal. masking the time-base serves to multiply the frequency of the time-base by a binary number to form the frequency of the output waveform. the duty cycle can vary from one cycle to 64-kbyte cycles. the frequency can range from 0.48 hz to 156 khz, though the resolution decreases at the higher frequencies to as low as seven bits. the generation of output square wave signals is of course the special case where the high and low times are equal. when an mmcsm is used to drive the time-base, the modulus value is the period of the output pwm signal. figure 17-45 shows such an example. the polarity of the leading edge 16-bit up-counter submodule bus clock select 16-bit compare b output flip-flop output pin 16-bit compare a 16-bit register b2 16-bit register a output compare interrupt on from prescaler or pin trailing bus select edge two 16-bit counter buses mios14 double action submodule in ocb mode (mod3 - mod0 = 0b0100) mios14 modulus counter submodule motorola chapter 17. modular input/output subsystem (mios14) 17-81 mios14 function examples of an output waveform is programmable for a rising or a falling edge. the software selects the period of the output signal by programming the mmcsm with a modulus value. the leading edge compare value is written into register a by software and the trailing edge time is written into register b1. when the leading edge value is reached, the content of register b1 is transferred to register b2, to form the next trailing edge value. subsequent changes to the output pulse width are made by writing a new time into register b1. updates to the pulse width are always synchronized to the leading edge of the waveform. it is typical to use the pulse width modulation mode of the mdasm without interrupts, although an interrupt can be enabled to occur on the leading edge. when the output is an unchanging repetitive waveform, the mdasm continuously generates the signal without any software intervention. when the software needs to change the pulse width, a new trailing edge time is written to the mdasm. the output is changed on the next full pulse. when the software needs to change the output at a regular rate, such as an acceleration curve, the leading edge interrupt gives the software one period time to update the new trailing edge time. figure 17-45. mios14 example: pulse width modulation output 16-bit up-counter submodule bus 16-bit compare b output flip-flop output pin 16-bit compare a 16-bit register b2 16-bit register a output compare interrupt on bus from prescaler or pin leading 16-bit register b1 edge modulus register modulus control clock select load select two 16-bit counter buses mios14 double action submodule in ocab mode (mod3 ? mod0 = 0b0101) mios14 modulus counter submodule 17-82 mpc565/mpc566 reference manual motorola real-time clock submodule (mrtcsm) 17.13.5mios14 input pulse accumulation counting the number of pulses on an input signal is another capability of the mios14. pulse accumulation uses an mmcsm. since the counters in the counter submodules are software accessible, pulse accumulation does not require the use of an action submodule. the pulse accumulation can operate continuously, interrupting only on binary overflow of the 16-bit counter. when an mmcsm is used, an interrupt can instead be created when the pulse accumulation reaches a preprogrammed value. to do that, the two?s complement of the value is put in the modulus register and the interrupt occurs when the counter overflows. 17.14real-time clock submodule (mrtcsm) in this section the values taken by the bits in the registers are given according to the following rule: 0 reset (negated) 1 set (asserted) u undefined - unaffected 17.14.1mrtcsm overview description the mios real-time clock submodule (mrtcsm) is a function included in the mios library. it is a software-programmable counter suitable for keeping track of the time of the day, maintaining calendar information or timestamping incoming system events. the purpose of the mrtcsm is to provide a real time function independently of other mios submodules, which may be sustained on a separate standby power supply. the mrtcsm was designed to minimize current drained from battery when in standby. this time counter is driven by a dedicated 32.768-khz low-power oscillator. the core of the mrtcsm is a 47-bit counter chain, split as a 15-bit prescaler and a 32-bit free-running counter. seconds, minutes, hours and days can be derived by software from the 32-bit counter. the mrtcsm can maintain a unique one-second count over a period of approximately 136 years. the prescaler provides additional sub-second information for precise timestamping. the mrtcsm has interrupt generation capability for one of eight delays ranging from one second to 2 23 seconds (approximately three months). 17.14.1.1 mrtcsm terminology in this section, the following terminology is used: motorola chapter 17. modular input/output subsystem (mios14) 17-83 real-time clock submodule (mrtcsm) update ? the term ?update? indicates the buffers are updated from the counter and/or prescaler. transfer ? the term ?transfer? is used to indicate a data transfer from the buffer to the counter and prescaler. 17.14.1.2 mrtcsm features programmable 47-bit free-running ripple counter for minimum power consumption split into a 15-bit prescaler and a 32-bit second counter buffering of the 47-bit free-running counter to guaranty 32-bit and 47-bit coherent accesses on the 16-bit miob bus possibility of suppressing 15-bit prescaler update software shutdown of the dedicated low power oscillator to maintain battery shelf life figure 17-46. mrtcsm block diagram 15-bit prescaler extal32 xtal32 vdd vrtc power switch vt_frc_clk en vt_osc_en interrupt rate 3 wen write enable miob bus request bus 7 vt_stbyb vt_vddrtc vt_osc_clk counter chain 8 stb test vt_osc_test 1hz pwr 32.768 khz rtc oscillator wip 32-bit free-running counter buffer 15-bit prescaler buffer mrtcfrc mrtcpr 32-bit free-running counter wake-up signal control logic 17-84 mpc565/mpc566 reference manual motorola real-time clock submodule (mrtcsm) flag setting and possible interrupt generation according to eight software selectable rates wake-up signal generation for chip level usage automatic hardware power supply selection through dedicated power switch customized to use low cost standard 32.768-khz crystal for internal clocking of the 32-bit counter at one hz software accessible precision of 2 -15 second and unique time indication in seconds over a span of 136 years (2 32 seconds) eliminates risk of time inaccuracy due to interrupt overruns appearing in systems with software accumulated time 17.14.1.3 mrtcsm pad functions the mrtcsm has no dedicated pads. however its dedicated power switch needs two pads for the 32.768-khz crystal while its dedicated power switch needs one. 17.14.2mrtcsm description this section describes the mrctsm and its dedicated oscillator and power switch. refer to the specifications of these two external modules for more information. refer to figure 17-46 for a block diagram of the mrtcsm. 17.14.2.1 oscillator the basic time base for the mrtcsm is a 32.768-khz dedicated low power oscillator. this oscillator uses an external crystal connected between the xtal32 and extal32 pads as a reference frequency source. the dedicated 32.768-khz oscillator is in the chip periphery with the pads for the 32.768-khz crystal. having a dedicated oscillator with its uninterruptable power supply allows the counter chain (15-bit prescaler and 32-bit free-running counter) to run while the rest of the chip is powered down. the 32.768-khz clock signal which is output by the oscillator is called vt_osc_clk. the frequency of the oscillator is called osc_freq. the extal32 pin has an internal load capacitor, therefore an external load capacitor is not required on extal32. the c l on the xtal32 side of the crystal should be according to the crystal manufacturer, typically 12 pf. the mios rtc oscillator circuit is shown in figure 17-47. the enable bit (en) in the mrtcsm control register (mrtcscr) can disable the oscillator and counter chain for maximum power saving. when enabled, the oscillator supplies the clock to the counter chain. motorola chapter 17. modular input/output subsystem (mios14) 17-85 real-time clock submodule (mrtcsm) note: resistor is not currently required on the board but room should be left on the board for its addition in the future. figure 17-47. mios rtc oscillator circuit 17.14.2.2 standby supply and power switch the mrtcsm power switch selects either the main power v dd or dedicated standby power v rtc as power supply (vt_vddrtc) for the mrtcsm. the power switch also generates the internal vt_stbyb signal which indicates in the mrtcsm which of the two supplies is selected: vt_stbyb = 0, standby mode, v rtc supply selected vt_stbyb = 1, normal mode, v dd supply selected normal mode is selected when v dd is greater than v rtc . the mrtcsm is supplied by v dd and all the mrtcsm functions are allowed. read and write operations to the mrtcsm registers comply to the description given in section 17.14.1, ?mrtcsm overview description.? the standby mode is selected automatically by hardware when the main v dd supply becomes lower than the vrtc supply. while in standby mode, the mrtcsm is supplied by the vrtc supply. the counter chain continues to count the time from the dedicated 32.768-khz oscillator. however, the buffers of the counter chain are no longer updated. if, despite being in standby mode, a buffer read or write operation occurs, a bus error is returned. write operations to any of the mrtcsm registers have no effect. the loss of primary power v dd does not cause the counter chain to be affected as long as the vrtc power pad is above its minimum operating voltage. only the loss of primary and standby power cause the content of the counter chain to be lost. figure 17-48. selection of vt_vddrtc extal32 xtal32 cl r1 * 32.7 khz t vt_vddrtc vdd vrtc 17-86 mpc565/mpc566 reference manual motorola real-time clock submodule (mrtcsm) 17.14.2.3 counter chain the mrtcsm avoids the software burden of servicing periodic interrupts to count time of day and calendar information. the software needs an initialization procedure that determines the preset state of the counter chain. after initialization, the software can calculate the current time and the current date from the contents of the counter chain. the software fetches the contents of the counter chain either regularly, with a periodic interrupt or as a low priority task in the application?s software loop, or whenever needed. in any case, software response time problems during intensive cpu usage will not affect the counter chain accuracy. when the en bit in mrtcscr is set, the mrtcsm oscillator and the counter chain are running. the counter chain is clocked with every rising edge of vt_osc_clk. refer to figure 17-49 for timing details. 17.14.2.4 15-bit prescaler the prescaler is a 15-bit presetable ripple counter designed to require minimum power consumption. the input clock is vt_osc_clk. the output is the vt_frc_clk clock signal used by the 32-bit free-running counter and runs at one hz. the 15-bit prescaler is double buffered in order to synchronize the available data and to allow easy coherent register accesses. the 15-bit prescaler can only be accessed through the 15-bit prescaler buffer (mrtcpr) 17.14.2.5 32-bit free-running counter the mrtcsm has a 32-bit presetable binary free-running counter that increments every second. the input to this counter is vt_frc_clk which comes directly from the 15-bit prescaler. the counter chain overflows approximately every 136 years. the 32-bit free-running counter is double buffered in order to synchronize the available data and to allow easy coherent register accesses. the 32-bit free-running counter can only be accessed through the 32-bit free-running counter buffer (mrtcfrc). 17.14.2.6 15-bit prescaler and 32-bit free-running counter buffers the 15-bit prescaler buffer (mrtcpr) and 32-bit free-running counter buffer (mrtcfrc) shown in figure 17-46 serve two purposes: synchronize the counter chain signals (vt_osc_clk and vt_frc_clk) to the peripheral bus system clock provide coherent access to 47-bit or 32-bit data on a 16-bit data bus motorola chapter 17. modular input/output subsystem (mios14) 17-87 real-time clock submodule (mrtcsm) mrtcfrc and mrtcpr can be read at any time. they must be written in conjunction and can only be written if the write enable bit (wen) is set. refer to section 17.14.1.2, ?mrtcsm features? for details concerning write operations to the buffers. when doing regular byte or word read operations, the coherency of subsequent accesses is not guaranteed. specific hardware is implemented that allows coherent accesses by using long word operations. refer to section 17.9.10, ?mdasmscr ? mdasm status/control register? for the description of coherent accesses. 17.14.3modes of operation the following subsections describe how mrtcpr and mrtcfrc are updated and how they should be accessed by software. 17.14.3.1 enabling the mrtcsm the en enable bit of the mrtcscr register selects whether the oscillator and counter chain are running or not. the mrtcsm can be disabled (en = 0) by software for maximum power saving (e.g., to maintain battery shelf life). when the mrtcsm is disabled, writing to mrtcpr and mrtcfrc may give unpredictable results. 17.14.3.2 15-bit prescaler and 32-bit free-running counter buffer updates when the mrtcsm is enabled (en = 1), mrtcpr and mrtcfrc are updated at the osc_freq rate. the timing for updating the buffers is shown in figure 17-49. the 47-bit counter chain is incremented at every rising edge of vt_osc_clk. a pulse is generated after the falling edge of vt_osc_clk to synchronize transfers and updates of the buffers to/from the counter chain. in this document, this synchronized pulse is called vt_sync. figure 17-49. 15-bit prescaler and 32-bit free-running counter buffer updates in standby mode (vt_stbyb = 0), the update of mrtcpr and mrtcfrc is stopped to reduce power consumption. access to all the mrtcsm registers is then inhibited. when exiting standby mode, the update of mrtcpr and mrtcfrc is reestablished at the regular osc_freq rate starting on the next vt_sync. in some particular conditions, the update of mrtcpr can be disabled. refer to section 17.14.2.2, ?standby supply and power switch? for more details. 17-88 mpc565/mpc566 reference manual motorola real-time clock submodule (mrtcsm) 17.14.3.3 read of 15-bit prescaler and 32-bit free-running counter buffers the addresses of the different mrtcsm registers are given in section 17.14.9, ?mrtcsm registers.? byte or word accesses to mrtcpr, mrtcfrch and mrtcfrcl can be performed at any time. however, the coherency between reads is not guaranteed when using byte or word accesses since these buffers may be updated in between read operations. in order to guarantee coherent reads, the following procedure should be followed: 1. execute a long word read of mrtcfrc (at address mrtcfrch) 2. execute a word read of mrtcpr (optional) if vt_sync occurs while a long word read operation of mrtcfrc is in progress, the update of the buffer is deferred until the end of the long word read. long word reads to mrtcfrc disable the update of mrtcpr until the next word read of mrtcpr. once a 15-bit prescaler buffer read operation is performed, mrtcpr updates resume at the osc_freq rate, starting with the next vt_sync. system 32-bit vt_osc_clk 12 cleared by software prescaler vt_frc_clk every 32.768-khz clock: counter (32.768khz) clock rate dependant: vt_sync (1hz) mrtcpr motorola chapter 17. modular input/output subsystem (mios14) 17-89 real-time clock submodule (mrtcsm) 17.14.3.4 write to 15-bit prescaler and 32-bit free-running counter buffers write operations to the buffers have no effect if wen is reset. in order to write a new value coherently to the complete counter chain, the following sequence must be performed: 1. set the wen bit in the mrtcscr register 2. execute a long word write to mrtcfrc (at address mrtcfrch), or two word writes to mrtcfrch and mrtcfrcl 3. execute a word write to mrtcpr when the wen bit is set, the update of mrtcpr and mrtcfrc is stopped. when mrtcpr is written to, the wen bit is reset and the buffers become read only. the written values will then be transferred to the counter chain at the next vt_sync pulse. following this sequence, the buffers will be updated from the counter chain at their regular osc_freq rate, as described in section 17.14.3.2, ?15-bit prescaler and 32-bit free-running counter buffer updates.? the option of disabling the update of mrtcpr from the counter chain is not affected by the write operation. once wen is set, write mrtcfrc before mrtcpr. not doing so transfers an old value of mrtcfrc to the counter chain. when a word write to mrtcpr happens after setting the wen bit, the wip read only bit in the mrtcscr register is set. this bit is reset once the transfer has occurred. the wip bit indicates to the programmer that a write procedure is in progress while doing a coherent write, once the prescaler buffer has been written to, the wen bit cannot be set again until the full contents of mrtcpr and mrtcfrc have been transferred to the counter chain. trying to set the wen bit before this operation is completed has no effect. if a reset appears while doing a coherent write or after a coherent write before the next vt_sync, the write operation is aborted and the buffers are updated as usual from the counter chain at the next vt_sync pulse. 17.14.4mrtcsm interrupt the mrtcsm is capable of generating interrupts at a fixed time interval. the value of the interrupt rate is determined by the mrtcscr bits ir2, ir1 and ir0. these three bits control which bit in the counter chain will be monitored for a positive edge. therefore, the interrupt rates are powers of two of the vt_frc_clk period. the interrupt flag is updated synchronously with vt_sync. the possible rates which can be selected are shown in table 17-50. 17-90 mpc565/mpc566 reference manual motorola real-time clock submodule (mrtcsm) interrupts are not generated when writing a new value to the counter chain. when exiting low power mode with the peripheral bus clock stopped or standby mode, buffers contain unpredictable values until the next vt_sync and the periodic interrupt flag is undetermined until the second vt_sync. the programmer should consider clearing the corresponding rqsm interrupt enable bit before entering these low power or standby modes to avoid possible interrupts when exiting these modes. 17.14.5chip wake-up feature in the case of main power supply shut-down, the chip clocks are stopped. a wake-up signal is available at the mios14 periphery that allows the mrtcsm to wake up the chip periodically. this signal reflects the status of one of the bits of the counter chain. the period is programmable by setting ir2, ir1 and ir0 appropriately, and is the same as the interrupt signal period (refer to table 17-50). this feature can be used to get the chip out of the low power mode. refer to the chip specification for details about the use of the wake-up signal. 17.14.6modular i/o bus (miob) interface the mrtcsm is connected to all the signals in the read/write and control bus, to allow data transfer from and to the mrtcsm registers, and to control the mrtcsm the mrtcsm does not use the counter bus set the mrtcsm uses the request bus to transmit the flag line to its request submodule (rqsm) 17.14.6.1 low power mode ? peripheral bus clock running as long as the peripheral bus clock is running, the mrtcsm is running normally. 17.14.6.2 low power mode ? peripheral bus clock stopped if the peripheral bus clock is stopped, the update of the prescaler and counter buffers is not possible. the interrupt flag is also not updated and consequently cannot be used to exit this low power mode. however, the operation of the wake-up signal, the dedicated 32.768-khz oscillator and the counter chain are not disturbed by this mode. the wake-up signal can still be used to exit this mode. as soon as this low power mode is exited, the update of mrtcpr and mrtcfrc is done at their regular osc_freq rate, starting on the next vt_sync. until this update occurs, the buffers contain unpredictable values. refer to section 17.14.4, ?mrtcsm interrupt? for a description of the effect of this mode on the interrupt flag. motorola chapter 17. modular input/output subsystem (mios14) 17-91 real-time clock submodule (mrtcsm) when a coherent write operation is performed, it is mandatory to wait for the vt_sync following the completion of this operation before entering this low power mode. 17.14.7effect of standby mode on mrtcsm when in standby mode, the mrtcsm is supplied by the vrtc power supply. the counter chain continues to count clocked by the 32.768-khz oscillator. however, the update of mrtcpr and mrtcfrc is stopped. the interrupt flag is also not updated and consequently cannot be used to exit this mode. in order to prevent loss of data in a run away situation during power-up and power-down sequences, the access to all the mrtcsm registers is inhibited. it is recommended to use an external lvi circuit asserting the reset pin when the main v dd supply is below the minimum specified value. when exiting the standby mode, the update of mrtcpr and mrtcfrc is done at the regular osc_freq rate, starting on the next vt_sync. until this update occurs, the buffers contain unpredictable values. refer to section 17.14.4, ?mrtcsm interrupt? for a description of the effect of this mode on the interrupt flag. the standby mode should not be entered during a coherent write operation or while wip is set. if this happens, the correct transfer to the counter chain is not guaranteed. the prescaler update power saving feature described in section 17.14.3.3, ?read of 15-bit prescaler and 32-bit free-running counter buffers? is not affected by standby mode. 17.14.8effect of reset on mrtcsm when the miob reset is asserted, the access to all the mrtcsm registers is blocked. the operation of the mrtcsm oscillator, counter chain and buffer updates is not affected by reset. the interrupt rate selection and the prescaler update power saving feature are not affected by reset. only the wen, test, stb and wip bits of the mrtcscr register are affected by reset. refer to section 17.14.9, ?mrtcsm registers? for more details. reset should not occur during a coherent write operation or while wip is set. if this happens, the transfer operation is not guaranteed. since the interrupt rate and the power saving feature are not affected by the reset, initialize these options when the device is powered for the first time. on a power-on reset, after a standby mode, buffers contain unpredictable values and the periodic interrupt flag is undetermined until the second vt_sync. however, the interrupt enable will have been cleared by reset in the corresponding rqsm. 17-92 mpc565/mpc566 reference manual motorola real-time clock submodule (mrtcsm) 17.14.9mrtcsm registers the privilege level to access the mrtcsm registers depends on the mios14mcr supv bit. this privilege level is reset to user and can be changed to supervisor by software. 17.14.10mrtcsm register organization the mrtcsm register map comprises four 16-bit register locations. all unused bits return zero when read by the software. all register addresses in this section are specified as offsets from the base address of the mrtcsm. 17.14.10.1mrtcsm free-running counter high buffer (mrtcfrch) register bits msb 0 1234567891011121314lsb 15 0x30 6050 mrtcsm free-running counter buffer high register (mrtcfrch) 0x30 6052 mrtcsm free-running counter buffer low register (mrtcfrcl) 0x30 6054 mrtcsm prescaler buffer register (mrtcpr) 0x30 6056 mrtcsm status and control register (mrtcscr) figure 17-50. mrtcsm ? register organization msb 0 1234567891011121314lsb 15 ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 sreset: ???????????????? figure 17-51. mrtcsmfrch ? mrtcsm 32-bit counter high buffer register 0x30 6050 table 17-46. mrtcsmfrch bit descriptions bit(s) name description 0:15 ch15 ? ch0 mrtcfrch is the data register associated with the 32-bit free-running counter high buffer. it contains the synchronized high word value of the 32-bit free-running counter or the value to be loaded into the high word 32-bit free-running counter. the mrtcfrch register is not affected by reset. motorola chapter 17. modular input/output subsystem (mios14) 17-93 real-time clock submodule (mrtcsm) 17.14.10.2mrtcsm free-running counter low buffer (mrtcfrcl) register bits 17.14.10.3mrtcsm prescaler counter buffer (mrtcpr) register bits 17.14.10.4mrtcsmscr ? mrtcsm status/control register the status and control register gathers read/write bits related to its control and configuration. msb 0 1234567891011121314lsb 15 cl15 cl14 cl13 cl12 cl11 cl10 cl9 cl8 cl7 cl6 cl5 cl4 cl3 cl2 cl1 cl0 sreset: ???????????????? figure 17-52. mrtcsmfrcl ? mrtcsm 32-bit counter low buffer register 0x30 6052 table 17-47. mrtcsmfrcl bit descriptions bit(s) name description 0:15 cl15 ? cl0 mrtcfrcl is the data register associated with the 32-bit free-running counter low buffer. it contains the synchronized low word value of the 32-bit free-running counter or the value to be loaded into the low word 32-bit free-running counter. the mrtcfrcl register is not affected by reset. msb 0 1234567891011121314lsb 15 pr15 pr14 pr13 pr12 pr11 pr10 pr9 pr8 pr7 pr6 pr5 pr4 pr3 pr2 pr1 0 sreset: ???????????????? figure 17-53. mrtcpr ? mrtcsm prescaler counter buffer register 0x30 6054 table 17-48. mrtcpr bit descriptions bit(s) name description 0:15 pr15 ? pr0 mrtcpr is the data register associated with the prescaler buffer. it contains the synchronized value of the 15-bit prescaler or the value to be loaded into the 15-bit prescaler. the mrtcpr register is not affected by reset. msb 0 1234567891011121314lsb 15 wip reserved wen en reserved test stb reserved ir2 ir1 ir0 sreset: 00000?0000000??? figure 17-54. mrtcsmscr ? mrtcsm status/control register 0x30 6056 17-94 mpc565/mpc566 reference manual motorola real-time clock submodule (mrtcsm) table 17-49. mrtcsmscr bit descriptions bit(s) name description 0 wip write in progress status bit ? this read only bit indicates that a transfer from the buffers to the counter chain is in progress. this bit is set when writing to mrtcpr during the coherent write procedure and is reset once the transfer to the counter chain has occurred. 0 no transfer from buffers to counter chain in progress. 1 transfer from buffers to counter chain in progress. the wip bit is cleared by reset. 1:3 ? reserved 4 wen write enable control bit ? this active high control bit allows the counter chain to be written to. mrtcpr and mrtcfrc are read only registers and regular write operations to these registers have no effect. when the wen bit is set, it enables writing to the counter chain buffers. section 17.14.3.4, ?write to 15-bit prescaler and 32-bit free-running counter buffers? describes the coherent write procedure to be used. note: the wen bit cannot be set while the wip bit is set. the wen bit is cleared by reset. 5 en enable control bit ? this active high bit enables real time clock operation. it selects whether the mrtcsm is running or not. 0 mrtcsm is not running. oscillator, counter chain and associated logic is not running, thus completely disabling the mrtcsm for maximum power saving. 1 mrtcsm is running, all mrtcsm functions are enabled. the en bit is not affected by reset and is undefined after the first power-up of the mrtcsm. section 17.14.3.1, ?enabling the mrtcsm? describes the enabling of the mrtcsm. note: the en bit cannot be modified while the wip bit is set. 6:7 ? reserved 9 test this bit is reserved for factory testing only and should never be write to one. the test bit is cleared by reset. 10 stb this bit is reserved for factory testing only and must always be zero. the stb bit is cleared by reset. 10:12 ? reserved 13:15 ir[2:0] interrupt rate control bits ? the three interrupt rate control bits select the rate of the timer interrupt. refer to table 17-50 to determine the rate of the real time clock interrupt. table 17-50. interrupt rate selection mrtcsm control register bits monitored counter chain bit #n mrtcsm interrupt rate when vt_osc_clk = 32.768khz (2n/32768) ir2 ir1 ir0 0 0 0 15 (output of prescaler) 1 second 0 0 1 21 64 seconds = 1.1 minutes 0 1 0 25 1024 seconds = 17.1 minutes 0 1 1 27 4096 seconds = 1.1 hours 1 0 0 31 65536 second = 18.2 hours 1 0 1 34 524288 seconds = 6.1 days motorola chapter 17. modular input/output subsystem (mios14) 17-95 real-time clock submodule (mrtcsm) the interrupt rate control bits are unaffected by reset and unknown after the first power-up of the mrtcsm. 1 1 0 36 2097152 seconds = 24.3 days 1 1 1 38 8388608 seconds = 3.2 months table 17-50. interrupt rate selection (continued) mrtcsm control register bits monitored counter chain bit #n mrtcsm interrupt rate when vt_osc_clk = 32.768khz (2n/32768) ir2 ir1 ir0 17-96 mpc565/mpc566 reference manual motorola real-time clock submodule (mrtcsm) motorola chapter 18. time processor unit 3 18-1 chapter 18 time processor unit 3 the time processor unit 3 (tpu3), an enhanced version of the original tpu, is an intelligent, semi-autonomous microcontroller designed for timing control. the tpu3 is fully compatible to the tpu2. operating simultaneously with the cpu, the three tpu3 modules process micro-instructions, schedule and process real-time hardware events, perform input and output, and access shared data without cpu intervention. consequently, for each timer event, the cpu setup and service times are minimized or eliminated. the mpc565/mpc566 contains three independent tpu3s, tpu_a, tpu_b, and tpu_c. these three tpu3 modules are memory mapped as shown in table 18-1 . figure 18-1 is a simplified block diagram of a single tpu3. table 18-1. tpu memory map tpu address tpu_a 0x304000?0x3043ff tpu_b 0x304400?0x3047ff tpu_c 0x305c00?0x305fff 18-2 mpc565/mpc566 reference manual motorola overview figure 18-1. tpu3 block diagram 18.1 overview the tpu3 can be viewed as a special-purpose microcomputer that performs a programmable series of two operations, match and capture. each occurrence of either operation is called an event. a programmed series of events is called a function. tpu functions replace software functions that would require cpu interrupt service and bandwidth. the microcode rom tpu3 functions that are available in the mpc565/mpc566 are described in appendix c, ?tpu3 rom functions.? 18.2 tpu3 components the tpu3 consists of two 16-bit time bases, 16 independent timer channels, a task scheduler, a microengine, and a host interface. in addition, a dual-ported parameter ram is used to pass parameters between the module and the cpu. 18.2.1 time bases two 16-bit counters provide reference time bases for all output-compare and input-capture events. prescalers for both time bases are controlled by the cpu via bit fields in the tpu3 module configuration register (tpumcr) and tpu module configuration register two (tpumcr2). timer count registers tcr1 and tcr2 provide access to the current counter values. tcr1 and tcr2 can be read by tpu microcode but are not directly available to the cpu. the tcr1 clock is always derived from the system clock. the tcr2 clock can be pins service requests data tcr1 tcr2 microengine control store execution unit imb3 host interface parameter ram channel control development support and system config scheduler control and data control timer channels channel 0 channel 1 channel 15 channel data t2clk pin te s t motorola chapter 18. time processor unit 3 18-3 tpu3 components derived from the system clock or from an external input via thet2clk clock pin. the duration between active edges on the t2clk clock pin must be at least nine system clocks. 18.2.2 timer channels the tpu3 has 16 independent channels, each connected to an mcu pin. the channels have identical hardware and are functionally equivalent in operation. each channel consists of an event register and pin control logic. the event register contains a 16-bit capture register, a 16-bit compare/match register, and a 16-bit greater-than-or-equal-to comparator. the direction of each pin, either output or input, is determined by the tpu microengine. each channel can either use the same time base for match and capture, or can use one time base for match and the other for capture. 18.2.3 scheduler when a service request is received, the scheduler determines which tpu3 channel is serviced by the microengine. a channel can request service for one of four reasons: for host service, for a link to another channel, for a match event, or for a capture event. the host system assigns each active channel one of three priorities: high, middle, or low. when multiple service requests are received simultaneously, a priority-scheduling mechanism grants service based on channel number and assigned priority. 18.2.4 microengine the microengine is composed of a control store and an execution unit. control-store rom holds the microcode for each factory-masked time function. when assigned to a channel by the scheduler, the execution unit executes microcode for a function assigned to that channel by the cpu. microcode can also be executed from the dual-port ram (dptram) module instead of the control store. the dptram allows emulation and development of custom tpu microcode without the generation of a microcode rom mask. refer to section 18.3.6, ?emulation support? for more information. 18.2.5 host interface the host interface registers allow communication between the cpu and the tpu3, both before and during execution of a time function. the registers are accessible from the imb through the tpu3 bus interface unit. refer to section 18.4, ?programming model? for register bit/field definitions and address mapping. 18.2.6 parameter ram parameter ram occupies 256 bytes at the top of the system address map. channel parameters are organized as 128 16-bit words. channels zero through 15 each have eight 18-4 mpc565/mpc566 reference manual motorola tpu operation parameters. the parameter ram address map in section 18.4.18, ?tpu3 parameter ram? shows how parameter words are organized in memory. the cpu specifies function parameters by writing to the appropriate ram address. the tpu3 reads the ram to determine channel operation. the tpu3 can also store information to be read by the cpu in the parameter ram. detailed descriptions of the parameters required by each time function are beyond the scope of this manual. refer to the tpu reference manual (tpurm/ad), included in the tpu literature package (tpulitpak/d) for more information. 18.3 tpu operation all tpu3 functions are related to one of the two 16-bit time bases. functions are synthesized by combining sequences of match events and capture events. because the primitives are implemented in hardware, the tpu3 can determine precisely when a match or capture event occurs, and respond rapidly. an event register for each channel provides for simultaneous match/capture event occurrences on all channels. when a match or input capture event requiring service occurs, the affected channel generates a service request to the scheduler. the scheduler determines the priority of the request and assigns the channel to the microengine at the first available time. the microengine performs the function defined by the content of the control store or emulation ram, using parameters from the parameter ram. 18.3.1 event timing match and capture events are handled by independent channel hardware. this provides an event accuracy of one time-base clock period, regardless of the number of channels that are active. an event normally causes a channel to request service. the time needed to respond to and service an event is determined by which channels and the number of channels requesting service, the relative priorities of the channels requesting service, and the microcode execution time of the active functions. worst-case event service time (latency) determines tpu3 performance in a given application. latency can be closely estimated. for more information, refer to the tpu reference manual (tpurm/ad). 18.3.2 channel orthogonality most timer systems are limited by the fixed number of functions assigned to each pin. all tpu3 channels contain identical hardware and are functionally equivalent in operation, so that any channel can be configured to perform any time function. any function can operate on the calling channel, and, under program control, on another channel determined by the program or by a parameter. the user controls the combination of time functions. motorola chapter 18. time processor unit 3 18-5 tpu operation 18.3.3 interchannel communication the autonomy of the tpu3 is enhanced by the ability of a channel to affect the operation of one or more other channels without cpu intervention. interchannel communication can be accomplished by issuing a link service request to another channel, by controlling another channel directly, or by accessing the parameter ram of another channel. 18.3.4 programmable channel service priority the tpu3 provides a programmable service priority level to each channel. three priority levels are available. when more than one channel of a given priority requests service at the same time, arbitration is accomplished according to channel number. to prevent a single high-priority channel from permanently blocking other functions, other service requests of the same priority are performed in channel order after the lowest-numbered, highest-priority channel is serviced (i.e. round-robin). 18.3.5 coherency for data to be coherent, all available portions of the data must be identical in age, or must be logically related. as an example, consider a 32-bit counter value that is read and written as two 16-bit words. the 32-bit value is read-coherent only if both 16-bit portions are updated at the same time, and write-coherent only if both portions take effect at the same time. parameter ram hardware supports coherent access of two adjacent 16-bit parameters. the host cpu must use a long-word operation to guarantee coherency. 18.3.6 emulation support although factory-programmed time functions can perform a wide variety of control tasks, they may not be ideal for all applications. the tpu3 provides emulation capability that allows the development of new time functions. emulation mode is entered by setting the emu bit in tpumcr. in emulation mode, an auxiliary bus connection is made between the dptram and the tpu3, and access to dptram via the intermodule bus is disabled. a 9-bit address bus, a 32-bit data bus, and control lines transfer information between the modules. to ensure exact emulation, dptflash module access timing remains consistent with access timing of the tpu microcode rom control store. to support changing tpu application requirements, motorola has established a tpu function library. the function library is a collection of tpu functions written for easy assembly in combination with each other or with custom functions. refer to motorola programming note, using the tpu function library and tpu emulation mode (tpupn00/d) for information about developing custom functions and accessing the tpu function library. refer to the motorola tpu literature package (tpulitpak/d) for more information about specific functions. 18-6 mpc565/mpc566 reference manual motorola tpu operation 18.3.7 tpu3 interrupts each of the tpu3 channels can generate an interrupt service request. interrupts for each channel must be enabled by writing to the appropriate control bit in the channel interrupt enable register (cier). the channel interrupt status register (cisr) contains one interrupt status flag per channel. time functions set the flags. setting a flag bit causes the tpu3 to make an interrupt service request if the corresponding channel interrupt enable bit is set. the tpu3 can generate one of 32 possible interrupt request levels on the imb3. the value driven onto irq [7:0] represents the interrupt level programmed in the irl field of the tpu interrupt configuration register (ticr). under the control of the ilbs bits in the icr, each interrupt request level is driven during one of four different time-multiplexed time slots, with eight levels communicated per time slot. no hardware priority is assigned to interrupts. furthermore, if more than one source on a module requests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. figure 18-2 displays the interrupt level scheme. figure 18-2. tpu3 interrupt levels 18.3.8 prescaler control for tcr1 timer count register 1 (tcr1) is clocked from the output of a prescaler. the following fields control tcr1: the psck and tcr1p fields in tpumcr the div2 field in tpumcr2 the epscke and epsck fields in tpumcr3. imb3 clock ilbs[1:0] imb3 irq [7:0] irq 7:0 00 01 11 10 irq 15:8 irq 23:16 irq 31:24 irq 7:0 00 01 11 10 motorola chapter 18. time processor unit 3 18-7 tpu operation the rate at which tcr1 is incremented is determined as follows: the user selects either the standard prescaler (by clearing the enhanced prescaler enable bit, epscke, in tpumcr3) or the enhanced prescaler (by setting epscke). ? if the standard prescaler is selected (epscke = 0), then the psck bit determines whether the standard prescaler divides the system clock input by 32 (psck = 0) or 4 (psck = 1) ? if the enhanced prescaler is selected (epscke = 1), the epsck bits select a value by which the system clock is divided. the lowest frequency for tcr1 clock is system clock divided by 64x8. the highest frequency for tcr1 clock is system clock divided by two (2x1). see table 18-2 and table 18-3. ? the output of either the standard prescaler or the enhanced prescaler is then divided by 1, 2, 4, or 8, depending on the value of the tcr1p field in the tpumcr. ? if the tpumcr2[div2] bit is one, the tcr1 counter increments at a rate of the internal clock divided by two. if div2 is zero, the tcr1 increment rate is defined by the output of the tcr1 prescaler (which, in turn, takes as input the output of either the standard or enhanced prescaler). figure 18-3 shows a diagram of the tcr1 prescaler control block. table 18-2. enhanced tcr1 prescaler divide values epsck value divide system clock by 0x00 2 0x01 4 0x02 6 0x03 8 0x04, 0x05,...0x1d 10,12,...60 0x1e 62 0x1f 64 table 18-3. tcr1 prescaler values tcr1p value divide by 0b00 1 0b01 2 0b10 4 0b11 8 18-8 mpc565/mpc566 reference manual motorola tpu operation figure 18-3. tcr1 prescaler control 18.3.9 prescaler control for tcr2 timer count register 2 (tcr2), like tcr1, is clocked from the output of a prescaler. the t2cg (tcr2 clock/gate control) bit and the t2csl (tcr2 counter clock edge) bit in tpumcr determine t2cr2 pin functions. refer to table 18-4. the function of the t2cg bit is shown in figure 18-4. when t2cg is set, the external t2clk pin functions as a gate of the div8 clock (the tpu3 system clock divided by eight). in this case, when the external tcr2 pin is low, the div8clockisblocked,preventingitfromincrementingtcr2.whentheexternaltcr2 pin is high, tcr2 is incremented at the frequency of the div8 clock. when t2cg is cleared, an external clock from the tcr2 pin, which has been synchronized and fed through a digital filter, increments tcr2. the duration between active edges on the t2clk clock pin must be at least nine system clocks. the tcr2psck2 bit in tpumcr3 determines whether the clock source is divided by two before it is fed into the tcr2 prescaler. the tcr2 field in tpumcr specifies the value of table 18-4. tcr2 counter clock source t2csl t2cg tcr2 clock 0 0 rise transition t2clk 0 1 gated system clock 1 0 fall transition t2clk 1 1 rise and fall transition t2clk system prescaler psck mux tcr1 prescaler tcr1 div2 2,4,6,...64 prescaler 32 / 4 1,2,4,8 epscke enhanced clock motorola chapter 18. time processor unit 3 18-9 programming model the prescaler: 1, 2, 4, or 8. channels using tcr2 have the capability to resolve down to the tpu3 system clock divided by eight. figure 18-4 illustrates the tcr2 pre-divider and pre-scaler control. figure 18-4. tcr2 prescaler control table 18-5 is a summary of prescaler output (assuming a divide-by-one value for the pre-divider prescaler. 18.4 programming model the tpu3 memory map contains three groups of registers: system configuration registers channel control and status registers development support and test verification registers all registers except the channel interrupt status register (cisr) must be read or written by means of half-word (16-bit) or word (32-bit) accesses. the address space of the tpu3 memory map occupies 512 bytes. unused registers within the 512-byte address space return zeros when read. table 18-6 shows the tpu3 address map. table 18-5. tcr2 prescaler control tcr2 value internal clock divide ratio external clock divide ratio tcr2psck2 = 0 tcr2psck2 = 1 tcr2psck2 = 0 tcr2psck2 = 1 0b008811 0b01 16 24 2 3 0b10 32 56 4 7 0b11 64 120 8 15 tcr2 prescaler tcr2 1,2,4,8 tcr2psck2 pre-divider 1,2 clock source mux control tcr2 pin clock div8 prescaler 18-10 mpc565/mpc566 reference manual motorola programming model table 18-6. tpu3 register map msb 0 address register 0x30 4000(tpu_a) 0x30 4400(tpu_b) 0x30 5c00(tpu_c) tpu3 module configuration register (tpumcr) see table 18-7 for bit descriptions. 0x30 4002(tpu_a) 0x30 4402(tpu_b) 0x30 5c02(tpu_c) tpu3 test configuration register (tcr) 0x30 4004(tpu_a) 0x30 4404(tpu_b) 0x30 5c04(tpu_c) development support control register (dscr) see table 18-8 for bit descriptions. 0x30 4006(tpu_a) 0x30 4406(tpu_b) 0x30 5c06(tpu_c) development support status register (dssr) see table 18-9 for bit descriptions. 0x30 4008(tpu_a) 0x30 4408(tpu_b) 0x30 5c08(tpu_c) tpu3 interrupt configuration register (ticr) see table 18-10 for bit descriptions. 0x30 400a(tpu_a) 0x30 440a(tpu_b) 0x30 5c0a(tpu_c) channel interrupt enable register (cier) see table 18-11 for bit descriptions. 0x30 400c(tpu_a) 0x30 440c(tpu_b) 0x30 5c0c(tpu_c) channel function selection register 0 (cfsr0) see table 18-12 for bit descriptions. 0x30 400e(tpu_a) 0x30 440e(tpu_b) 0x30 5c0e(tpu_c) channel function selection register 1 (cfsr1) see table 18-12 for bit descriptions. 0x30 4010(tpu_a) 0x30 4410(tpu_b) 0x30 5c10(tpu_c) channel function selection register 2 (cfsr2) see table 18-12 for bit descriptions. 0x30 4012(tpu_a) 0x30 4412(tpu_b) 0x30 5c12(tpu_c) channel function selection register 3 (cfsr3) see table 18-12 for bit descriptions. 0x30 4014(tpu_a) 0x30 4414(tpu_b) 0x30 5c14(tpu_c) host sequence register 0 (hsqr0) see table 18-13 for bit descriptions. 0x30 4016(tpu_a) 0x30 4416(tpu_b) 0x30 5c16(tpu_c) host sequence register 1 (hsqr1) see table 18-13 for bit descriptions. 0x30 4018(tpu_a) 0x30 4418(tpu_b) 0x30 5c18(tpu_c) host service request register 0 (hsrr0) see table 18-14 for bit descriptions. 0x30 401a(tpu_a) 0x30 441a(tpu_b) 0x30 5c1a(tpu_c) host service request register 1 (hsrr1) see table 18-14 for bit descriptions. motorola chapter 18. time processor unit 3 18-11 programming model 0x30 401c(tpu_a) 0x30 441c(tpu_b) 0x30 5c1c(tpu_c) channel priority register 0 (cpr0) see table 18-15 for bit descriptions. 0x30 401e(tpu_a) 0x30 441e(tpu_b) 0x30 5c1e(tpu_c) channel priority register 1 (cpr1) see table 18-15 for bit descriptions. 0x30 4020(tpu_a) 0x30 4420(tpu_b) 0x30 5c20(tpu_c) channel interrupt status register (cisr) see table 18-17 for bit descriptions. 0x30 4022(tpu_a) 0x30 4422(tpu_b) 0x30 5c22(tpu_c) link register (lr) 0x30 4024(tpu_a) 0x30 4424(tpu_b) 0x30 5c24(tpu_c) service grant latch register (sglr) 0x30 4026(tpu_a) 0x30 4426(tpu_b) 0x30 5c26(tpu_c) decoded channel number register (dcnr) 0x30 4028(tpu_a) 0x30 4428(tpu_b) 0x30 5c28(tpu_c) tpu module configuration register 2 (tpumcr2) see table 18-18 for bit descriptions. 0x30 402a(tpu_a) 0x30 442a(tpu_b) 0x30 5c2a(tpu_c) tpu module configuration 3 (tpumcr3) see table 18-21 for bit descriptions. 0x30 402c(tpu_a) 0x30 442c(tpu_b) 0x30 5c2c(tpu_c) internal scan data register (isdr) 0x30 402e(tpu_a) 0x30 442e(tpu_b) 0x30 5c2e(tpu_c) internal scan control register (iscr) 0x30 4100 ? 0x30 410f(tpu_a) 0x30 4500 ? 0x30 450f(tpu_b) 0x30 5d00? 0x30 5d0f(tpu_c) channel 0 parameter registers 0x30 4110 ? 0x30 411f(tpu_a) 0x30 4510 ? 0x30 451f(tpu_b) 0x30 5d10 ? 0x30 5d1f(tpu_c) channel 1 parameter registers 0x30 4120 ? 0x30 412f(tpu_a) 0x30 4520 ? 0x30 452f(tpu_b) 0x30 5d20 ? 0x30 5d2f(tpu_c) channel 2 parameter registers 0x30 4130 ? 0x30 413f(tpu_a) 0x30 4530 ? 0x30 453f(tpu_b) 0x30 5d30 ? 0x30 5d3f(tpu_c) channel 3 parameter registers table 18-6. tpu3 register map (continued) msb 0 address register 18-12 mpc565/mpc566 reference manual motorola programming model 0x30 4140 ? 0x30 414f(tpu_a) 0x30 4540 ? 0x30 454f(tpu_b) 0x30 5d40 ? 0x30 5d4f(tpu_c) channel 4 parameter registers 0x30 4150 ? 0x30 415f(tpu_a) 0x30 4550 ? 0x30 455f(tpu_b) 0x30 5d50 ? 0x30 5d5f(tpu_c) channel 5 parameter registers 0x30 4160 ? 0x30 416f(tpu_a) 0x30 4560 ? 0x30 456f(tpu_b) 0x30 5d60 ? 0x30 5d6f(tpu_c) channel 6 parameter registers 0x30 4170 ? 0x30 417f(tpu_a) 0x30 4570 ? 0x30 457f(tpu_b) 0x30 5d70 ? 0x30 5d7f(tpu_c) channel 7 parameter registers 0x30 4180 ? 0x30 418f(tpu_a) 0x30 4580 ? 0x30 458f(tpu_b) 0x30 5d80 ? 0x30 5d8f(tpu_c) channel 8 parameter registers 0x30 4190 ? 0x30 419f(tpu_a) 0x30 4590 ? 0x30 459f(tpu_b) 0x30 5d90 ? 0x30 5d9f(tpu_c) channel 9 parameter registers 0x30 41a0 ? 0x30 41af(tpu_a) 0x30 45a0 ? 0x30 45af(tpu_b) 0x30 5da0 ? 0x30 5daf(tpu_c) channel 10 parameter registers 0x30 41b0 ? 0x30 41bf(tpu_a) 0x30 45b0 ? 0x30 45bf(tpu_b) 0x30 5db0 ? 0x30 5dbf(tpu_c) channel 11 parameter registers 0x30 41c0 ? 0x30 41cf(tpu_a) 0x30 45c0 ? 0x30 45cf(tpu_b) 0x30 5cc0 ? 0x30 5ccf(tpu_c) channel 12 parameter registers 0x30 41d0 ? 0x30 41df(tpu_a) 0x30 45d0 ? 0x30 45df(tpu_b) 0x30 5dd0 ? 0x30 5ddf(tpu_c) channel 13 parameter registers 0x30 41e0 ? 0x30 41ef(tpu_a) 0x30 45e0 ? 0x30 45ef(tpu_b) 0x30 5cd0 ? 0x30 5def(tpu_c) channel 14 parameter registers 0x30 41f0 ? 0x30 41ff(tpu_a) 0x30 45f0 ? 0x30 45ff(tpu_b) 0x30 5df0 ? 0x30 5dff(tpu_c) channel 15 parameter registers table 18-6. tpu3 register map (continued) msb 0 address register motorola chapter 18. time processor unit 3 18-13 programming model 18.4.1 tpu module configuration register msb 0 1234567891011121314lsb 15 stop tcr1p tcr2p emu t2cg stf supv psck tpu3 t2csl reserved reset: 00000000101 0 0000 figure 18-5. tpumcr ? tpu module configuration register 0x30 4000 0x30 4400 0x30 5c00 table 18-7. tpumcr bit description bit(s) name description 0 stop low-power stop mode enable. if the stop bit in tpumcr is set, the tpu3 shuts down its internal clocks, shutting down the internal microengine. tcr1 and tcr2 cease to increment and retain the last value before the stop condition was entered. the tpu3 asserts the stop flag (stf) in tpumcr to indicate that it has stopped. 0 enable tpu3 clocks 1 disable tpu3 clocks 1:2 tcr1p timer count register 1 prescaler control. tcr1 is clocked from the output of a prescaler. the prescaler divides its input by 1, 2, 4, or 8. this is a write-once field unless the pwod bit in tpumcr3 is set. 00 divide by 1 01 divide by 2 10 divide by 4 11 divide by 8 refer to section 18.3.8, ?prescaler control for tcr1? for more information. 3:4 tcr2p timer count register 2 prescaler control. tcr2 is clocked from the output of a prescaler. the prescaler divides this input by 1, 2, 4, or 8. this is a write-once field unless the pwod bit in tpumcr3 is set. 00 divide by 1 01 divide by 2 10 divide by 4 11 divide by 8 refer to section 18.3.9, ?prescaler control for tcr2? for more information. 5 emu emulation control. in emulation mode, the tpu3 executes microinstructions from dptram exclusively. access to the dptram via the imb3 is blocked, and the dptram is dedicated for use by the tpu3. after reset, this bit can be written only once. 0 tpu3 and dptram operate normally 1 tpu3 and dptram operate in emulation mode 1 6 t2cg tcr2 clock/gate control 0 tcr2 pin used as clock source for tcr2 1 tcr2pinusedasgateofdiv8clockfortcr2 refer to section 18.3.9, ?prescaler control for tcr2? for more information. 7 stf stop flag. 0 tpu3 is operating normally 1 tpu3 is stopped (stop bit has been set) 18-14 mpc565/mpc566 reference manual motorola programming model 18.4.2 tpu3 test configuration register tcr ? tpu3 test configuration register0x30 4002, 0x30 4402, 0x30 5c02 used for factory test only. 18.4.3 development support control register 8 supv supervisor data space 0 assignable registers are accessible from user or supervisor privilege level 1 assignable registers are accessible from supervisor privilege level only 9 psck standard prescaler clock. note that this bit has no effect if the extended prescaler is selected (epscke = 1). 0f sys motorola chapter 18. time processor unit 3 18-15 programming model table 18-8. dscr bit descriptions bit(s) name description 0 hot4 hangont4 0 exit wait on t4 state caused by assertion of hot4 1 enter wait on t4 state 1:4 ? reserved 5 blc branch latch control 0 latch conditions into branch condition register before exiting halted state 1 do not latch conditions into branch condition register before exiting the halted state or during the time-slot transition period 6 clks stop clocks (to tcrs) 0 do not stop tcrs 1 stop tcrs during the halted state 7:8 frz freeze assertion response. the frz bits specify the tpu microengine response to the imb3 freeze signal 00 ignore freeze 01 reserved 10 freeze at end of current microcycle 11 freeze at next time-slot boundary 9 ccl channel conditions latch. ccl controls the latching of channel conditions (mrl and tdl) when the chan register is written. 0 only the pin state condition of the new channel is latched as a result of the write chan register microinstruction 1 pin state, mrl, and tdl conditions of the new channel are latched as a result of a write chan register microinstruction 10 bp 18-16 mpc565/mpc566 reference manual motorola programming model 18.4.4 development support status register 18.4.5 tpu3 interrupt configuration register msb 0 1 2 3 4567891011121314lsb 15 reserved bkpt pcbk chbk srbk tpuf reserved reset: 0 0 0 0 000000000000 figure 18-7. dssr ? development support status register 0x30 4006 0x30 4406 0x30 5c04 table 18-9. dssr bit descriptions bit(s) name description 0:7 ? reserved 8 bkpt breakpoint asserted flag. if an internal breakpoint caused the tpu3 to enter the halted state, the tpu3 asserts the bkpt signal on the imb and sets the bkpt flag. bkpt remains set until the tpu3 recognizes a breakpoint acknowledge cycle, or until the imb freeze signal is asserted. 9pcbk motorola chapter 18. time processor unit 3 18-17 programming model 18.4.6 channel interrupt enable register the channel interrupt enable register (cier) allows the cpu to enable or disable the ability of individual tpu3 channels to request interrupt service. setting the appropriate bit in the register enables a channel to make an interrupt service request; clearing a bit disables the interrupt. table 18-10. ticr bit description bit(s) name description 0:4 ? reserved 5:7 cirl channel interrupt request level. this three-bit field specifies the interrupt request level for all channels. this field is used in conjunction with the ilbs field to determine the request level of tpu3 interrupts. 8:9 ilbs interrupt level byte select. this field and the cirl field determine the level of tpu3 interrupt requests. 00 irq [0:7] selected 01 irq [8:15] selected 10 irq [16:23] selected 11 irq [24:31] selected 10:15 ? reserved. note that bits 10:11 represent channel interrupt base vector (cibv) bits in some tpu3 implementations. msb 0 1234567891011121314lsb 15 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0000000000000000 figure 18-9. cier ? channel interrupt enable register 0x30 400a 0x30 440a 0x30 5c0a table 18-11. cier bit descriptions bit(s) name description 0:15 ch[15:0] channel interrupt enable/disable 0 channel interrupts disabled 1 channel interrupts enabled note: the msb (bit 0 in big-endian mode) represents ch15, and the lsb (bit 15 in big-endian mode) represents ch0. 18-18 mpc565/mpc566 reference manual motorola programming model 18.4.7 channel function select registers encoded 4-bit fields within the channel function select registers specify one of 16 time functions to be executed on the corresponding channel. encodings for predefined functions are found in table c-1 and table c-2. msb 0 1234567891011121314lsb 15 ch 15 ch 14 ch 13 ch 12 reset: 0000000000000000 figure 18-10. cfsr0 ? channel function select register 0 0x30 400c 0x30 440c 0x30 5c0c msb 0 1234567891011121314lsb 15 ch 11 ch 10 ch 9 ch 8 reset: 0000000000000000 figure 18-11. cfsr1 ? channel function select register 1 0x30 400e 0x30 440e 0x30 5c0e msb 0 1234567891011121314lsb 15 ch 7 ch 6 ch 5 ch 4 reset: 0000000000000000 figure 18-12. cfsr2 ? channel function select register 2 0x30 4010 0x30 4410 0x30 5c10 motorola chapter 18. time processor unit 3 18-19 programming model 18.4.8 host sequence registers the host sequence field selects the mode of operation for the time function selected on a given channel. the meaning of the host sequence bits depends on the time function specified. see appendix c, ?tpu3 rom functions? for definitions of the host sequence bits and host service request bits for the predefined tpu rom function. msb 0 1234567891011121314lsb 15 ch 3 ch 2 ch 1 ch 0 reset: 0000000000000000 figure 18-13. cfsr3 ? channel function select register 3 0x30 4012 0x30 4412 0x30 5c12 table 18-12. cfsrx bit descriptions name description ch[15:0] encoded time function for each channel. encoded four-bit fields in the channel function select registers specify one of 16 time functions to be executed on the corresponding channel. msb 0 1234567891011121314lsb 15 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 reset: 0000000000000000 figure 18-14. hsqr0 ? host sequence register 0 0x30 4014 0x30 4414 0x30 5c14 msb 0 1234567891011121314lsb 15 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0000000000000000 figure 18-15. hsqr1 ? host sequence register 1 0x30 4016 0x30 4416 0x30 5c16 18-20 mpc565/mpc566 reference manual motorola programming model 18.4.9 host service request registers the host service request field selects the type of host service request for the time function selected on a given channel. the meaning of the host service request bits is determined by time function microcode. refer to the tpu reference manual (tpurm/ad) and the motorola tpu literature package (tpulitpak/d) for more information. table 18-13. hsqrx bit descriptions name description ch[15:0] encoded host sequence. the host sequence field selects the mode of operation for the time function selected on a given channel. the meaning of the host sequence bits depends on the time function specified. msb 0 1234567891011121314lsb 15 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 reset: 0000000000000000 figure 18-16. hsrr0 ? host service request register 0 0x30 4018 0x30 4418 0x30 5c18 msb 0 1234567891011121314lsb 15 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0000000000000000 figure 18-17. hsrr1 ? host service request register 1 0x30 401a 0x30 441a 0x30 5c1a table 18-14. hssrx bit descriptions name description ch[15:0] encoded type of host service. the host service request field selects the type of host service request for the time function selected on a given channel. the meaning of the host service request bits depends on the time function specified. a host service request field cleared to 0b00 signals the host that service is completed by the microengine on that channel. the host can request service on a channel by writing the corresponding host service request field to one of three non-zero states. the cpu must monitor the host service request register until the tpu3 clears the service request to 0b00 before any parameters are changed or a new service request is issued to the channel. motorola chapter 18. time processor unit 3 18-21 programming model 18.4.10channel priority registers the channel priority registers (cpr1, cpr2) assign one of three priority levels to a channel or disable the channel. 18.4.11channel interrupt status register the channel interrupt status register (cisr) contains one interrupt status flag per channel. time functions specify via microcode when an interrupt flag is set. setting a flag causes the msb 0 1234567891011121314lsb 15 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 reset: 0000000000000000 figure 18-18. cpr0 ? channel priority register 0 0x30 401c 0x30 441c 0x30 5c1c msb 0 1234567891011121314lsb 15 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0000000000000000 figure 18-19. cpr1 ? channel priority register 1 0x30 401e 0x30 441e 0x30 5c1e table 18-15. cprx bit description name description ch[15:0] encoded channel priority levels. table 18-16 indicates the number of time slots guaranteed for each channel priority encoding. table 18-16. channel priorities chx[1:0] service guaranteed time slots 00 disabled ? 01 low 1 out of 7 10 middle 2 out of 7 11 high 4 out of 7 18-22 mpc565/mpc566 reference manual motorola programming model tpu3 to make an interrupt service request if the corresponding cier bit is set. to clear a status flag, read cisr, then write a zero to the appropriate bit. note cisr is the only tpu3 register that can be accessed on a byte basis. 18.4.12link register lr ? link register0x30 4022, 0x30 4422, 0x30 5c22 used for factory test only. 18.4.13service grant latch register sglr ? service grant latch register0x30 4024, 0x30 4424, 0x30 5c24 used for factory test only. 18.4.14decoded channel number register dcnr ? decoded channel number register0x30 4026, 0x30 4426, 0x30 5c26 used for factory test only. msb 0 1234567891011121314lsb 15 ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 reset: 0000000000000000 figure 18-20. cisr ? channel interrupt status register 0x30 4020 0x30 4420 0x30 5c20 table 18-17. cisr bit descriptions bit(s) name description 0:15 ch[15:0] channel interrupt status 0 channel interrupt not asserted 1 channel interrupt asserted motorola chapter 18. time processor unit 3 18-23 programming model 18.4.15tpu3 module configuration register 2 msb 0 1234567891011121314lsb 15 reserved div2 soft rst etbank fpsck t2cf dtpu reset: 0000000000000000 figure 18-21. tpumcr2 ? tpu module configuration register 2 0x30 4028 0x30 4428 0x30 5c28 table 18-18. tpumcr2 bit descriptions bit(s) name description 0:6 ? reserved 7 div2 divide by 2 control. when asserted, the div2 bit, along with the tcr1p bit and the psck bit in the tpumcr, determines the rate of the tcr1 counter in the tpu3. if set, the tcr1 counter increments at a rate of two system clocks. if negated, tcr1 increments at the rate determined by control bits in the tcr1p and psck fields. 0 tcr1 increments at rate determined by control bits in the tcr1p and psck fields of the tpumcr register 1 causes tcr1 counter to increment at a rate of the system clock divided by two 8 soft rst soft reset. the tpu3 performs an internal reset when both the soft rst bit in the tpumcr2 and the stop bit in tpumcr are set. the cpu must write zero to the soft rst bit to bring the tpu3 out of reset. the soft rst bit must be asserted for at least nine clocks. 0 normal operation 1 puts tpu3 in reset until bit is cleared note: do not attempt to access any other tpu3 registers when this bit is asserted. when this bit is asserted, it is the only accessible bit in the register. 9:10 etbank entry table bank select. this field determines the bank where the microcoded entry table is situated. after reset, this field is 0b00. this control bit field is write once after reset. etbank is used when the microcode contains entry tables not located in the default bank 0. to execute the rom functions on this mcu, etbank[1:0] must be 00. refer to table 18-19. note: this field should not be modified by the programmer unless necessary because of custom microcode. 11:13 fpsck filter prescaler clock. the filter prescaler clock control bit field determines the ratio between system clock frequency and minimum detectable pulses. the reset value of these bits is zero, defining the filter clock as four system clocks. refer to table 18-20. 18-24 mpc565/mpc566 reference manual motorola programming model 14 t2cf t2clk pin filter control. when asserted, the t2clk input pin is filtered with the same filter clock that is supplied to the channels. this control bit is write once after reset. 0 uses fixed four-clock filter 1 t2clk input pin filtered with same filter clock that is supplied to the channels 15 dtpu disable tpu3 pins. when the disable tpu3 control pin is asserted, pin tp15 is configured as an input disable pin. when the tp15 pin value is zero, all tpu3 output pins are three-stated, regardless of the pins function. the input is not synchronized. this control bit is write once after reset. 0 tp15 functions as normal tpu3 channel 1 tp15 pin configured as output disable pin. when tp15 pin is low, all tpu3 output pins are in a high-impedance state, regardless of the pin function. table 18-19. entry table bank location etbank bank 00 0 01 1 10 2 11 3 table 18-20. system clock frequency/minimum guaranteed detected pulse filter control divide by 20 mhz 33 mhz 40 mhz 000 4 200 ns 121 ns 100 ns 001 8 400 ns 242 ns 200 ns 010 16 800 ns 485 ns 400 ns 011 32 1.6 motorola chapter 18. time processor unit 3 18-25 programming model 18.4.16tpu module configuration register 3 18.4.17tpu3 test registers the following tpu3 registers are used for factory test only: internal scan data register (isdr, address offset 0x30 402c, 0x30 442c, and 0x30 5c2c) internal scan control register (iscr, address offset 0x30 402e, 0x30 442e, 0x30 5c2e) msb 0 123456 7 8 9 1011121314lsb 15 reserved pwod tcr2 pck2 epscke rsvd epsck reset: 00 0 0 0 0 0 figure 18-22. tpumcr3 ? tpu module configuration register 3 0x30 402a 0x30 442a 0x30 5c2a table 18-21. tpumcr3 bit descriptions bit(s) name description 0:6 ? reserved 7 pwod prescaler write-once disable bit. the pwod bit does not lock the epsck field and the epscke bit. 0 prescaler fields in mcr are write-once 1 prescaler fields in mcr can be written anytime 8 tcr2psc k2 tcr2 prescaler 2 0 prescaler clock source is divided by one. 1 prescaler clock is divided. see divider definitions in table 18-5. 9 epscke enhanced pre-scaler enable 0 disable enhanced prescaler (use standard prescaler) 1 enable enhanced prescaler. system clock will be divided by the value in epsck field. 10 ? reserved 11:15 epsck enhanced prescaler value that will be loaded into the enhanced prescaler counter. prescaler value(epsck + 1) x 2. refer to section 18.3.8, ?prescaler control for tcr1? for details. 18-26 mpc565/mpc566 reference manual motorola programming model 18.4.18tpu3 parameter ram the channel parameter registers are organized as one hundred 16-bit words of ram. channels 0 to 15 have eight parameters. the parameter registers constitute a shared work space for communication between the cpu and the tpu3. the tpu3 can only access data in the parameter ram. refer to table 18-22. table 18-22. parameter ram address offset map channel parameter number01234567 00x30 4100(a) 0x30 4500(b) 0x30 5d00(c) 0x30 4102a(a) 0x30 4502(b) 0x30 5d02(c) 0x30 4104(a) 0x30 4504(b) 0x30 5d04(c) 0x30 4106(a) 0x30 4506(b) 0x30 5d06(c) 0x30 4108(a) 0x30 4508(b) 0x30 5d08(c) 0x30 410a(a) 0x30 450a(b) 0x30 5d0a(c) 0x30 410c(a) 0x30 450c(b) 0x30 5d0c(c) 0x30 410e(a) 0x30 450e(b) 0x30 5d0e(c) 10x30 4110(a) 0x30 4510(b) 0x30 5d10(c) 0x30 4112(a) 0x30 4512(b) 0x30 5d12(c) 0x30 4114(a) 0x30 4514(b) 0x30 5d14(c) 0x30 4116(a) 0x30 4516(b) 0x30 5d16(c) 0x30 4118(a) 0x30 4518(b) 0x30 5d18(c) 0x30 411a(a) 0x30 451a(b) 0x30 5d1a(c) 0x30 411c(a) 0x30 451c(b) 0x30 5d1c(c) 0x30 411e(a) 0x30 451e(b) 0x30 5d1e(c) 20x30 4120(a) 0x30 4520(b) 0x30 5d20(c) 0x30 4122(a) 0x30 4522(b) 0x30 5d23(c) 0x30 4124(a) 0x30 4524(b) 0x30 5d24(c) 0x30 4126(a) 0x30 4526(b) 0x30 5d26(c) 0x30 4128(a) 0x30 4528(b) 0x30 5d28(c) 0x30 412a(a) 0x30 452a(b) 0x30 5d2a(c) 0x30 412c(a) 0x30 452c(b) 0x30 5d2c(c) 0x30 412e(a) 0x30 452e(b) 0x30 5d2e(c) 30x30 4130(a) 0x30 4530(b) 0x30 5d30(c) 0x30 4132(a) 0x30 4532(b) 0x30 5d32(c) 0x30 4134(a) 0x30 4534(b) 0x30 5d34(c) 0x30 4136(a) 0x30 4536(b) 0x30 5d36(c) 0x30 4138(a) 0x30 4538(b) 0x30 5d38(c) 0x30 413a(a) 0x30 453a(b) 0x30 5d3a(c) 0x30 413c(a) 0x30 453c(b) 0x30 5d3c(c) 0x30 413e(a) 0x30 453e(b) 0x30 5d3e(c) 40x30 4140(a) 0x30 4540(b) 0x30 5d40(c) 0x30 4142(a) 0x30 4542(b) 0x30 5d42(c) 0x30 4144(a) 0x30 4544(b) 0x30 5d44(c) 0x30 4146(a) 0x30 4546(b) 0x30 5d46(c) 0x30 4148(a) 0x30 4548(b) 0x30 5d48(c) 0x30 414a(a) 0x30 454a(b) 0x30 5d4a(c) 0x30 414c(a) 0x30 454c(b) 0x30 5d4c(c) 0x30 414e(a) 0x30 454e(b) 0x30 5d4e(c) 50x30 4150(a) 0x30 4550(b) 0x30 5d50(c) 0x30 4152(a) 0x30 4552(b) 0x30 5d52(c) 0x30 4154(a) 0x30 4554(b) 0x30 5d54(c) 0x30 4156(a) 0x30 4556(b) 0x30 5d56(c) 0x30 4158(a) 0x30 4558(b) 0x30 5d58(c) 0x30 415a(a) 0x30 455a(b) 0x30 5d5a(c) 0x30 415c(a) 0x30 455c(b) 0x30 5d5c(c) 0x30 415e(a) 0x30 455e(b) 0x30 5d5e(c) motorola chapter 18. time processor unit 3 18-27 programming model 60x30 4160(a) 0x30 4560(b) 0x30 5d60(c) 0x30 4162(a) 0x30 4562(b) 0x30 5d62(c) 0x30 4164(a) 0x30 4564(b) 0x30 5d64(c) 0x30 4166(a) 0x30 4566(b) 0x30 5d66(c) 0x30 4168(a) 0x30 4568(b) 0x30 5d68(c) 0x30 416a(a) 0x30 456a(b) 0x30 5d6a(c) 0x30 416c(a) 0x30 456c(b) 0x30 5d6c(c) 0x30 416e(a) 0x30 456e(b) 0x30 5d6e(c) 70x30 4170(a) 0x30 4570(b) 0x30 5d70(c) 0x30 4172(a) 0x30 4572(b) 0x30 5d72(c) 0x30 4174(a) 0x30 4574(b) 0x30 5d74(c) 0x30 4176(a) 0x30 4576(b) 0x30 5d76(c) 0x30 4178(a) 0x30 4578(b) 0x30 5d78(c) 0x30 417a(a) 0x30 457a(b) 0x30 5d7a(c) 0x30 417c(a) 0x30 457c(b) 0x30 5d7c(c) 0x30 417e(a) 0x30 457e(b) 0x30 5d7e(c) 80x30 4180(a) 0x30 4580(b) 0x30 5d80(c) 0x30 4182(a) 0x30 4582(b) 0x30 5d82(c) 0x30 4184(a) 0x30 4585(b) 0x30 5d84(c) 0x30 4186(a) 0x30 4586(b) 0x30 5d86(c) 0x30 4188(a) 0x30 4588(b) 0x30 5d88(c) 0x30 418a(a) 0x30 458a(b) 0x30 5d8a(c) 0x30 418c(a) 0x30 458c(b) 0x30 5d8c(c) 0x30 418e(a) 0x30 458e(b) 0x30 5d8e(c) 90x30 4190(a) 0x30 4590(b) 0x30 5d90(c) 0x30 4192(a) 0x30 4592(b) 0x30 5d92(c) 0x30 4194(a) 0x30 4594(b) 0x30 5d94(c) 0x30 4196(a) 0x30 4596(b) 0x30 5d96(c) 0x30 4198(a) 0x30 4598(b) 0x30 5d98(c) 0x30 419a(a) 0x30 459a(b) 0x30 5d9a(c) 0x30 419c(a) 0x30 459c(b) 0x30 5d9c(c) 0x30 419e(a) 0x30 459e(b) 0x30 5d9e(c) 10 0x30 41a0(a) 0x30 45a0(b) 0x30 5da0(c) 0x30 41a2(a) 0x30 45a2(b) 0x30 5da2(c) 0x30 41a4(a) 0x30 45a4(b) 0x30 5da4(c) 0x30 41a6(a) 0x30 45a6(b) 0x30 5da6(c) 0x30 41a8(a) 0x30 45a8(b) 0x30 5da8(c) 0x30 41aa(a) 0x30 45aa(b) 0x30 5daa(c) 0x30 41ac(a) 0x30 45ac(b) 0x30 5dac(c) 0x30 41ae(a) 0x30 45ae(b) 0x30 5dae(c) 11 0x30 41b0(a) 0x30 45b0(b) 0x30 5db0(c) 0x30 41b2(a) 0x30 45b2(b) 0x30 5db2(c) 0x30 41b4(a) 0x30 45b4(b) 0x30 5db4(c) 0x30 41b6(a) 0x30 45b6(b) 0x30 5db6(c) 0x30 41b8(a) 0x30 45b8(b) 0x30 5db8(c) 0x30 41ba(a) 0x30 45ba(b) 0x30 5dba(c) 0x30 41bc(a) 0x30 45bc(b) 0x30 5dbc(c) 0x30 41be(a) 0x30 45be(b) 0x30 5dbe(c) 12 0x30 41c0(a) 0x30 45c0(b) 0x30 5dc0(c) 0x30 41c2(a) 0x30 45c2(b) 0x30 5dc2(c) 0x30 41c4(a) 0x30 45c4(b) 0x30 5dc4(c) 0x30 41c6(a) 0x30 45c6(b) 0x30 5dc6(c) 0x30 41c8(a) 0x30 45c8(b) 0x30 5dc8(c) 0x30 41ca(a) 0x30 45ca(b) 0x30 5dca(c) 0x30 41cc(a) 0x30 45cc(b) 0x30 5dcc(c) 0x30 41ce(a) 0x30 45ce(b) 0x30 5dce(c) 13 0x30 41d0(a) 0x30 45d0(b) 0x30 5dd0(c) 0x30 41d2(a) 0x30 45d2(b) 0x30 5dd2(c) 0x30 41d4(a) 0x30 45d4(b) 0x30 5dd4(c) 0x30 41d6(a) 0x30 45d6(b) 0x30 5dd6(c) 0x30 41d8(a) 0x30 45d8(b) 0x30 5dd8(c) 0x30 41da(a) 0x30 45da(b) 0x30 5dda(c) 0x30 41dc(a) 0x30 45dc(b) 0x30 5ddc(c) 0x30 41de(a) 0x30 45de(b) 0x30 5dde(c) table 18-22. parameter ram address offset map (continued) 18-28 mpc565/mpc566 reference manual motorola time functions 18.5 time functions descriptions of the mpc565/mpc566 pre-programmed time functions are shown in appendix c, ?tpu3 rom functions.? 14 0x30 41e0(a) 0x30 45e0(b) 0x30 5de0(c) 0x30 41e2(a) 0x30 45e2(b) 0x30 5de2(c) 0x30 41e4(a) 0x30 45e4(b) 0x30 5de4(c) 0x30 41e6(a) 0x30 45e6(b) 0x30 5de6(c) 0x30 41e8(a) 0x30 45e8(b) 0x30 5de8(c) 0x30 41ea(a) 0x30 45ea(b) 0x30 5dea(c) 0x30 41ec(a) 0x30 45ec(b) 0x30 5dec(c) 0x30 41ee(a) 0x30 45ee(b) 0x30 5dee(c) 15 0x30 41f0(a) 0x30 45f0(b) 0x30 5df0(c) 0x30 41f2(a) 0x30 45f2(b) 0x30 5df2(c) 0x30 41f4(a) 0x30 45f4(b) 0x30 5df4(c) 0x30 41f6(a) 0x30 45f6(b) 0x30 5df6(c) 0x30 41f8(a) 0x30 45f8(b) 0x30 5df8(c) 0x30 41fa(a) 0x30 45fa(b) 0x30 5dfa(c) 0x30 41fc(a) 0x30 45fc(b) 0x30 5dfc(c) 0x30 41fe(a) 0x30 45fe(b) 0x30 5dfe(c) table 18-22. parameter ram address offset map (continued) motorola chapter 19. dual-port tpu3 ram (dptram) 19-1 chapter 19 dual-port tpu3 ram (dptram) the dual-port ram (dptram) module with tpu3 microcode storage support consists of a control register block and a 4- or 6-kbyte array of static ram, which can be used either as a microcode storage for tpu3 or as a general-purpose memory. the mpc565/mpc566 has two dptram modules. one module (dptram_ab) has a 6-kbyte array and serves two tpu3 modules (a and b). the other module (dptram_c) has a 4-kbyte array and serves a third tpu3 module (c). each dptram module acts as a common memory on the imb3 and allows the transfer of data to the two tpu3 modules. therefore, the dptram interface includes an imb3 bus interface and two tpu3 interfaces. the dptram_c, however, connects to only one tpu3. when the ram is being used in microcode mode, the array is only accessible to the tpu3 via a separate local bus, and not via the imb3. in the mpc565/mpc566, the dptram base address register (rambar) for each dptram must be set to a particular value to fit into the imb memory map of the part. the dptram_ab rambar must be programmed to 0xffa0 and the dptram_c rambar must be programmed to 0xff90 in order to put them in the proper memory location for the mpc565. the dual-port tpu3 ram (dptram) is intended to serve as fast, two-clock access, general-purpose ram memory for the mcu. when used as general-purpose ram, this module is accessed via the mcu?s internal bus. the dptram module is powered by v ddl in normal operation. the entire array may be used as standby ram if standby power is supplied via the v ddsram3 pin of the mcu. v ddsram3 must be supplied by an external source. the dptram powers the array both during run and in standby operation. the dptram may also be used as the microcode control store for up to two tpu3 modules when placed in a special emulation mode. in this mode the dptram array may only be accessed by either or both of the tpu3 units simultaneously via separate emulation buses, and not via the imb3. the dptram contains a multiple input signature calculator (misc) in order to provide ram data corruption checking. the misc reads each ram address and generates a 32-bit data-dependent signature. this signature can then be checked by the host. 19-2 mpc565/mpc566 reference manual motorola features the dptram supports soft defects detection (sdd). note the rcpu cannot perform instruction fetches from any module on the imb (including the dptram). only data accesses are permitted. 19.1 features six kbytes of static ram and four kbytes of static ram accessible by the cpu only if neither tpu3 (connected to the dptram) is in emulation mode low-power stop operation ? entered by setting the stop bit in the dptmcr ? applies only to imb3 accesses and not to accesses from either tpu3 interface tpu3 microcode mode ? the dptram array acts as a microcode storage for the tpu3 module. this provides a means of executing tpu3 code out of dptram instead of tpu3 rom. includes built in check logic which scans the array contents and calculates the ram signature imb3 bus interface two tpu3 interface units byte, half-word, or word accessible motorola chapter 19. dual-port tpu3 ram (dptram) 19-3 dptram configuration and block diagram 19.2 dptram configuration and block diagram figure 19-1. dptram configuration 19.3 programming model the dptram module consists of two separately addressable sections. the first is a set of memory-mapped control and status registers used for configuration (dptmcr, rambar, misrh, misrl, miscnt) and testing (dpttcr) of the dptram array. the second section is the array itself. all dptram module control and status registers are located in supervisor data space. user read or write attempts will result in a bus error. when the tpu3 is using the ram array for microcode control storage, none of these control registers has any effect on the operation of the ram array. all addresses within the 64-byte control block will respond when accessed properly. unimplemented addresses will return zeros for read accesses. likewise, unimplemented bits within registers will return zero when read and will not be affected by write operations. table 19-1 shows the dptram control and status registers. the addresses shown are offsets from the base address for the module. refer to figure 1-2 to locate the dptram control block in the mpc565/mpc566 address map. imb3 tpu3 emulation mode imb3 tpu3 tpu3 local bus local bus ram mode ram tpu3 tpu3 ram imb3 19-4 mpc565/mpc566 reference manual motorola programming model note: (ab) = six kbytes and (c) = four kbytes the dptram_ab array occupies a 6-kbyte block. in the mpc565/mpc566, the array must be located at the address 0x30 2000. the dptram_c array occupies a 4-kbyte block and the array must be located at the address 0x30 1000. refer to figure 1-2 and figure 19-2. figure 19-2. dptram memory map 19.3.1 dptram module configuration register (dptmcr) this register defines the basic configuration of the dptram module. the dptmcr contains bits to configure the dptram module for stop operation and for proper access privileges to the array. the register also contains the misc control bits. table 19-1. dptram register map r/w access address register reset value supervisor r/w 0x30 0000(ab) 0x30 0040(c) dpt ram module configuration register (dptrmcr) see table 19-2 for bit descriptions. 0x0100 test 0x30 0002(ab) 0x30 0042(c) test configuration register (dpttcr) 0x0000 supervisor r/w 0x30 0004(ab) 0x30 0044(c) ram base address register (rambar) see table 19-3 for bit descriptions. 0x0001 supervisor read only 0x30 0006(ab) 0x30 0046(c) multiple input signature register high (misrh) see section 19.3.4, ?misr high (misrh) and misr low (misrl)? for bit descriptions. 0x0000 supervisor read only 0x30 0008(ab) 0x30 0048(c) multiple input signature register low (misrl) see section 19.3.4, ?misr high (misrh) and misr low (misrl)? for bit descriptions. 0x0000 supervisor read only 0x30 000a(ab) 0x30 004a(c) multiple input signature counter (miscnt) see section 19.3.5, ?misc counter (miscnt)? for bit descriptions. last memory address dptram array (ab) 0x30 1fff 0x30 2000 0x30 37ff 0x30 1000 dptram array (c) (4 kbytes) (6 kbytes) motorola chapter 19. dual-port tpu3 ram (dptram) 19-5 programming model msb 0 1234567891011121314lsb 15 stop reserved misf mise n rasp reserved reset: 0 00100000000 figure 19-3. dptmcr ? dpt module configuration register 0x30 0000 0x30 0040 table 19-2. dptmcr bit settings bit(s) name description 0 stop low power stop (sleep) mode 0 dptram clocks running 1 dptram clocks shut down only the stop bit in the dptmcr may be accessed while the stop bit is asserted. accesses to other dptram registers may result in unpredictable behavior. note also that the stop bit should be set and cleared independently of the other control bits in this register to guarantee proper operation. changing the state of other bits while changing the state of the stop bit may result in unpredictable behavior. refer to section 19.4.4, ?stop operation? for more information. 1:4 ? reserved 5 misf multiple input signature flag. misf is readable at any time. this flag bit should be polled by the host to determine if the misc has completed reading the ram. if misf is set, the host should read the misrh and misrl registers to obtain the ram signature. 0 first signature not ready 1 misc has read entire ram. signature is latched in misrh and misrl and is ready to be read. 6 misen multiple input signature enable. misen is readable and writable at any time. the misc will only operate when this bit is set and the mpc565/mpc566 is in tpu3 emulation mode. when enabled, the misc will continuously cycle through the ram addresses, reading each and adding thecontentstothemisr.inordertosavepower,themisccanbedisabledbyclearingthe misen bit. 0miscdisabled 1 misc enabled 7 rasp ram area supervisor/user program/data. the ram array may be placed in supervisor or unrestricted space. when placed in supervisor space, (rasp = 1), only a supervisor may access the array. if a supervisor program is accessing the array, normal read/write operation will occur. if a user program is attempting to access the array, the access will be ignored and the address may be decoded externally. 0 both supervisor and user access to ram allowed 1 supervisor access only to ram allowed 8:15 ? reserved. these bits are used for the iarb (interrupt arbitration id) field in tpu3 implementations that use hardware interrupt arbitration. 19-6 mpc565/mpc566 reference manual motorola programming model 19.3.2 dptram test register ramtst (test register 0x30 0002, 0x30 0042) is used only during factory testing of the mcu, and, if written, will generate a bus error. 19.3.3 ram base address register (rambar) therambarregisterisusedtospecifythe16msbsofthestartingdptramarray location in the memory map. in order to be accessible in the mpc565/mpc566 memory map, this register must be programed to 0xffa0 for the dptram_ab and 0xff90 for the dptram_c. this register can be written only once after a reset. this prevents runaway software from inadvertently re-mapping the array. since the locking mechanism is triggered by the first write after reset, the base address of the array should be written in a single operation. writing only one half of the register will prevent the other half from being written. soft reset has no effect on this register. msb 0 1234567891011121314lsb 15 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 reserved ramd s reset: 0 00000000000000 1 figure 19-4. rambar ? ram array base address register 0x30 0004 0x30 0044 table 19-3. rambar bit settings bit(s) name description 0:11 a[8:19] ram array base address. these bits specify the 11 high-order bits (address lines addr[8:19] in little-endian notation) of the 24-bit base address of the ram array. this allows the array to be placed on a 8-kbyte boundary anywhere in the memory map. do not overlap the ram array memory map with other modules on the chip. on the mpc565/mpc566 the value 0xffa0 must be used for dptram_6 kbyte and 0xff90 must be used for dptram_4 kbyte. 12:14 ? reserved. (bit 12 represents a[20] in dptram implementations that require it.) 15 ramds ram disabled. ramds is a read-only status bit. the ram array is disabled after a master reset since the rambar register may be incorrect. when the array is disabled, it will not respond to any addresses on the imb3. access to the ram control register block is not affected when the array is disabled. ramds is cleared by the dptram module when a base address is written to the array address field of rambar. ramds = 0: ram enabled ramds = 1: ram disabled motorola chapter 19. dual-port tpu3 ram (dptram) 19-7 programming model 19.3.4 misr high (misrh) and misr low (misrl) the misrh and misrl together contain the 32-bit ram signature calculated by the misc. these registers are read-only and should be read by the host when the misf bit in the mcr is set. note that the naming of the d[31:0] bits represents little-endian bit encoding. exiting tpu3 emulation mode results in the reset of both misrh and misrl. 19.3.5 misc counter (miscnt) the miscnt contains the address of the current misc memory access. this register is read-only. note that the naming of the a[31:0] bits represents little-endian bit encoding. exiting tpu3 emulation mode or clearing the misen bit in the dptmcr results in the reset of this register. msb 0 1234567891011121314lsb 15 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 reset: 0 00000000000000 0 figure 19-5. misrh ? multiple input signature register high 0x30 0006 0x30 0046 msb 0 1234567891011121314lsb 15 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reset: 0 00000000000000 0 figure 19-6. misrl ? multiple input signature register low 0x30 0008 0x30 0048 msb 0 1234567891011121314lsb 15 reserved a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 reset: last memory address figure 19-7. miscnt ? misc counter 0x30 000a 0x30 004a 19-8 mpc565/mpc566 reference manual motorola operation 19.4 operation the dptram module has several modes of operation. the following sections describe dptram operation in each of these modes. 19.4.1 normal operation in normal operation, read or write data accesses of 8, 16, or 32 bits are supported. also, in normal operation, neither tpu3 accesses the array, nor do they have any effect on the operation of the dptram module. 19.4.2 standby operation the dptram array uses a separate power supply v ddsram3 to provide power to the dptram array during a power-down phase. in order to guarantee valid dptram data during power-down, external low voltage inhibit circuitry (external to the mcu) must be designed to force the reset pin of the mcu into the active state before v ddl drops below its normal limit. this is necessary to inhibit spurious writes to the dptram during power-down. 19.4.3 reset operation when a synchronous reset occurs, a bus master is allowed to complete the current access. thus a write bus cycle (byte or half word) that is in progress when a synchronous reset occurs will be completed without error. once a write already in progress has been completed, further writes to the ram array are inhibited. note a word (32-bit) write will be completed coherently only if the reset occurs during the second (16-bit) write bus cycle. if reset occurs during the first write bus cycle, only the first half word will be written to the ram array and the second write will not be allowed to occur. in this case, the word data contained in the dptram will not be coherent. the first half word will contain the most significant half of the new word information and the second half word will contain the least significant half of the old word information. if a reset is generated by an asynchronous reset such as the loss of clocks or software watchdog time-out, the contents of the ram array are not guaranteed. (refer to chapter 7, ?reset? for a description of mpc565/mpc566 reset sources, operation, control, and status.) motorola chapter 19. dual-port tpu3 ram (dptram) 19-9 operation reset will also reconfigure some of the fields and bits in the dptram control registers to their default reset state. see the description of the control registers to determine the effect of reset on these registers. 19.4.4 stop operation setting the stop control bit in the dptmcr causes the module to enter its lowest power-consuming state. the dptmcr can still be written to allow the stop control bit to be cleared. in stop mode, the dptram array cannot be read or written. all data in the array is retained. the biu continues to operate to allow the cpu to access the stop bit in the dptmcr. the system clock remains stopped until the stop bit is cleared or the dptram module is reset. the stop bit is initialized to logical zero during reset. only the stop bit in the dptmcr can be accessed while the stop bit is asserted. accesses to other dptram registers may result in unpredictable behavior. note the stop bit should be set and cleared independently of the other control bits in this register to guarantee proper operation. changing the state of other bits while changing the state of the stop bit may result in unpredictable behavior. switching to vddsram3 occurs if v ddl drops below its specified value when the ram module is in stop mode. the dptram_ab and the dptram_c 1will not enter stop mode if either or both of the tp1emm or tp2emm signals are asserted, indicating tpu3 emulation mode. 19.4.5 freeze operation the freeze line on the imb3 has no effect on the dptram module. when the freeze line is set, the dptram module will operate in its current mode of operation. if the dptram module is not disabled, (ramds = 0), it may be accessed via the imb3. if the dptram array is being used by the tpu3 in emulation mode, the dptram will still be able to be accessed by the tpu3 microengine. 19.4.6 tpu3 emulation mode operation to emulate tpu3 time functions, store the microinstructions required for all time functions to be used, in the ram array. this must be done with the dptram in its normal operating mode and accessible from the imb3. after the time functions are stored in the array, place 19-10 mpc565/mpc566 reference manual motorola multiple input signature calculator (misc) one or both of the tpu3 units in emulation mode. the ram array is then controlled by the tpu3 units and disconnected from the imb3. to use the dptram for microcode accesses, set the emu bit in the corresponding tpu3 module configuration register. through the auxiliary buses, the tpu3 units can access word instructions simultaneously at a rate of up to 56 mhz. when a ram array is being used by one or two of the tpu3 units, all accesses via the imb3 are disabled. the control registers have no effect on the ram array. the contents of the ram are validated using a multiple input signature calculator (misc). misc reads of the ram are performed only when the mpc565/mpc566 is in emulation mode and the misc is enabled (misen = 1 in the dptmcr). refer to section 18.3.6, ?emulation support? for more information in tpu3 and dptram operation in emulation mode. 19.5 multiple input signature calculator (misc) the integrity of the ram data is ensured through the use of a misc. the ram data is read in reverse address order and a unique 32-bit signature is generated based on the output of these reads. misc reads are performed when one of the tpu3 modules does not request back-to-back accesses to the ram provided that the misen bit in the dptmcr is set. the misc generates the dptram signature based on the following polynomial: after the entire ram has been read and a signature has been calculated, the misc sets the misf bit in the mpc565/mpc566 mcr. the host should poll this bit and enter a handling routine when the bit is found to be set. the signature should then be read from the misrh and misrl registers and the host determines if it matches the predetermined signature. the misrh and misrl registers are updated each time the misc completes reading the entire ram regardless of whether or not the previous signature has been read or not. this ensures that the host reads the most recently generated signature. the misc can be disabled by clearing the misen bit in the dptmcr. note the reset state of the dptmcr misen is disabled. gx () motorola chapter 20. cdr3 flash (uc3f) eeprom 20-1 chapter 20 cdr3 flash (uc3f) eeprom 20.1 introduction the u-bus cdr3 (uc3f) eeprom module is designed for use in embedded microcontroller (mcu) applications targeted for high-speed read performance and high-density byte count requirements. the mpc565/mpc566 has 1 mbyte of flash divided between two of these modules. the uc3f array uses a single transistor flash bit cell and is configured for a module of 512 kbytes (524,288 bytes) of non-volatile memory (nvm). each uc3f module is divided into eight 64-kbyte (65,536-byte) array blocks. two blocks of the uc3f module memory map may be subdivided into two smaller blocks: a 16-kbyte (16,384-byte) block and a 16-kbyte block, or a 16-kbyte block and a 48-kbyte (49,152-byte) block. the primary function of the uc3f eeprom module is to serve as electrically programmable and erasable nvm to store program instructions and/or data. it is a class of non-volatile solid state silicon memory device consisting of an array of isolated elements, an electrical means for selectively adding and removing charge to the elements, and a means of selectively sensing the stored charge in the elements. when power is removed from the device, the stored charge of the isolated elements will be retained. the uc3f eeprom module is arranged into two major sections as shown in figure 20-1. the first section is the uc3f array used to store system program and data. the second section is the memory interface (mi) that controls operation of the uc3f array. the mi also serves as the interface between the uc3f array and a bus interface unit (biu) which connects the uc3f array to the u-bus. note if the flash arrays are disabled in the immr register (flen=0), then neither the uc3f array or the uc3f control registers are accessible. 20-2 mpc565/mpc566 reference manual motorola introduction figure 20-1. block diagram for a 512-kbyte uc3f module configuration the uc3f eeprom module array is divided into array blocks to allow for independent erase, address attributes restrictions, and protection from program and erase for each array block. the size of a large array block in the uc3f module is fixed at 64 kbytes. the size of a subdivided large block becomes the original large array block size minus 16 kbytes, (64 kbytes ? 16 kbytes = 48 kbytes. the size of the small block, which is the remainder of the large block, is always 16 kbytes. the total uc3f eeprom array is distributed into eight large blocks, two of which contain small blocks. information is transferred to the uc3f eeprom by long-word (64 bits), word (32 bits), half-word (16 bits), or byte (8 bits). to improve system performance, each array read access retrieves 32 bytes of information. these 32 bytes may be copied into one of two read page buffers aligned to the low order addresses. the two read page buffers are independently updated by page management logic contained in the biu which interfaces to the uc3f eeprom module. to prevent unnecessary page accesses from the array, the uc3f memory interface (mi) shall monitor the incoming address to determine if the required information is in one of the two read page buffers. this strategy allows the uc3f array to have an off page access and an on page access. in normal operation, write accesses to the uc3f array are not recognized except during program and erase operations. block 0 (64 kbytes) block 1 (64 kbytes) block 2 (64 kbytes) block 3 (64 kbytes) block 4 (64 kbytes) block 5 (64 kbytes) block 6 (64 kbytes) block 7 (64 kbytes) column decode row decode pgm data latch address latch read page buffer 0 read page buffer 1 data mux program/erase control program/erase voltage generation uc3f_rdwr uc3f_din uc3f_dout uc3f_ccmcreiwren uc3f_rst uc3f_addr uc3f_mem_en uc3f_stopin uc3f_epee uc3f_b0epee register read control internal timer register block memory interface (mi) uc3f array core outputs vssf vddf vflash motorola chapter 20. cdr3 flash (uc3f) eeprom 20-3 introduction the uc3f eeprom uses an embedded hardware algorithm to program and erase the uc3f array. special control logic is included to guard against accidental program or erase by requiring a specific series of read and write accesses to the uc3f control registers. external inputs provide a hardware protection mechanism to prevent accidental program and erase of uc3f array blocks. the hardware algorithm automatically performs all necessary applications of high voltage pulses and verify reads of the uc3f array to ensure that all bits are programmed and erased with sufficient margin to guarantee data integrity and reliability. 20.1.1 features of the cdr3 flash eeprom (uc3f) high density single transistor flash bit cell -40 to 125 c ambient temperature operating range 2.5-v to 2.7-v v ddf operating range and 4.75-v to 5.25-v v flash operating range shadow information stored in special flash nvm shadow locations two 16-kbyte small blocks per module 512 kbytes per module using 64-kbyte blocks ? one mbyte total array block restriction control for small and large blocks ? erase by array block(s) ? array protection for program and erase operations ? array block assignment of supervisor or supervisor/user space ? array block assignment of data or instruction/data space internal 64-bit data path architecture page mode read ? retains two independent read page buffers ? read page size of 32 bytes (8 words). word (32-bit) programming embedded hardware program and erase algorithm ? uses internal oscillator to time program and erase pulses. pulses are timed independently of system clock frequency ? automatically performs margin reads external flash program or erase enable inputs for block 0 or entire flash array (b0epee and epee) low power disable via an external signal or uc3f register bit censor mode for flash memory array access restriction with a user bypass for unrestricted array access 20-4 mpc565/mpc566 reference manual motorola introduction 20.1.2 glossary of terms used array block ? a 64-kbyte uc3f array subdivision. array small block ? the independently erasable 16-kbyte subdivision of a 64-kbyte array block. array host block ? an array block containing a small block. array residual block ? the 16-kbyte or 48-kbyte portion of a host block not contained in the small block. biu ? bus interface unit which controls access of the uc3f module through a standard system bus interface. uc3f ? the cdr3 flash eeprom module. cam ? non-volatile content addressable memory cell used as a nonvolatile storage bit. cams are used for censor bits. erase interlock write ? a write to any uc3f array address after initializing the erase sequence. im ? integration module is a bus master which serves as the system bus arbitration unit on the microcontroller. initialize program/erase sequence ? the write to the high voltage control register that changes the ses bit from a 0 to a 1. mask option ? a customer configurable option that is specified during the design process. mcu ? microcontroller unit. mi ? memory interface controls operation of the uc3f array. off page read ? array read operation that retrieves 32 bytes of information from the flash memory array and transfers the address selected eight bytes of the 32 bytes to the data out port. on page read ? array read operation that accesses eight bytes of information stored in one of the read page buffers. programming write ? a word write to a uc3f array address to transfer information into a program data latch. the uc3f eeprom accepts programming writes after initializing the program sequence until the ehv bit is changed from a 0 to a 1. read page buffer ? 32-byte block of information that is read from the uc3f array. this information is aligned to a 32-byte boundary within the uc3f array. each uc3f module has two read page buffers. motorola chapter 20. cdr3 flash (uc3f) eeprom 20-5 uc3f interface shadow information ? the shadow provides 512 bytes of additional uc3f storage that is used for the reset configuration word and for additional user data. these locations may be accessed by setting the sie bit in the module configuration register and accessing the uc3f array. the shadow information is always in the lowest numbered array block of the uc3f module. siu ? system integration unit. 20.2 uc3f interface the uc3f module contains a memory interface (mi) and an array core. the mi controls access of the array core and register block in the uc3f module. the interface signals to the uc3f module consist of address inputs, data inputs, data outputs, a simple set of control signals for read and write operations, a set of register selects, and a set of register outputs which are used by the biu. three required supply pins power the module: v ddf ,v ssf , and v flash . the uc3f module is a fully asynchronous module and does not require a clock input for operation. all required clocks are generated internally using an internal oscillator, external test clock input, or internal delay circuits. 20.2.1 external interface the uc3f eeprom module uses external pins to provide power supplies. these pins are listed in table 20-1. . table 20-1. uc3f external interface signals mnemonic i/o type description comments v ddf power pin uc3f power supply to reduce noise in the read path no other circuits should be connected to the uc3f v ddf supply pin.this v dd pin must be isolated from all other v dd pins inside the device. the specified voltage range during operation is 2.6 v 20-6 mpc565/mpc566 reference manual motorola programmer?s model 20.3 programmer?s model the uc3f eeprom module consists of a control register block, an addressable shadow row implemented in flash, and an addressable main flash memory array. the control registers are used to configure, program, erase and exercise the uc3f shadow row and flash array. 20.3.0.1 uc3f eeprom module control register addressing the uc3f module control registers are selected with individual register selects generated from the biu. as such, each flash module that is designed using the uc3f eeprom module may uniquely define the addressing of the control register block. epee external program/erase epee pin status the epee bit monitors the state of the external program/erase enable (epee) input. the uc3f module samples the epee input when ehv is asserted and holds that sampled state until ehv is negated. b0epee block 0 external program/erase block 0 epee pin status the b0em bit monitors the state of the block 0 epee, b0epee, input. the uc3f module samples the b0epee input when ehv is asserted and holds that sampled value until ehv is negated.if b0em = 1 when ehv is asserted, high voltage operations such as program or erase are enabled for either small block 0 or the lowest numbered block of the uc3f array regardless of the state of epee. if b0em = 0 when ehv is asserted, high voltage operations are disabled for small block 0 or the lowest numbered block of the uc3f array regardless of the state of epee. table 20-2. uc3f register programmer?s mode address register 0x2f c800 module a configuration (uc3fmcr_a) 0x2f c804 extended module configuration (uc3fmcre_a) 0x2f c808 high voltage control (uc3fctl_a) 0x2f c80c reserved 0x2f c840 module b configuration (uc3fmcr_b) 0x2f c844 extended module configuration (uc3fmcre_b 0x2f c848 high voltage control (uc3fctl_b) 0x2f c84c reserved table 20-1. uc3f external interface signals (continued) mnemonic i/o type description comments motorola chapter 20. cdr3 flash (uc3f) eeprom 20-7 programmer?s model 20.3.1 uc3f eeprom control registers the control registers are used to control uc3f eeprom module operation. on reset, the registers are loaded with default reset information. several bits of the uc3f control registers are special flash nvm registers which retain their state when power is removed from the uc3f eeprom. these special nvm registers are identified in the individual register field and control bit descriptions. 20.3.2 uc3f eeprom configuration register (uc3fmcr) the uc3f module configuration register is used to configure the operation and access restrictions of the uc3f array and shadow row. msb 0 1 2 3 4 5 6 7 8 9 101112131415 stop lock reserved fic sie access censor supv hreset: 01 0 00 0 11111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 data protect hreset: 0 0 0 0 0 0 0 0 11111111 note: reset state determined by nvm registers figure 20-2. uc3fmcr ? uc3f eeprom configuration register 0x2f c800 0x2f c840 20-8 mpc565/mpc566 reference manual motorola programmer?s model table 20-3. uc3fmcr bit descriptions bit(s) name description 0 stop array stop control. when uc3f_stopin = 1 during the negation of uc3f_rst_b, the reset state of stop is 1 and the c3f array wakes up in a disabled low power mode. likewise, when uc3f_stopin = 0, the reset state of stop is 0 and the uc3f array wakes up in a read mode. writes to the stop bit have no effect while in program or erase operation (ses = 1). the stop bit is always readable whenever the registers are enabled. when stop is set to 1, the uc3f array is disabled, and internal circuits are switched into a low power state. the stop bit may be used to implement low power standby modes or power management schemes. at least the uc3fmcr remains readable and writable when stop = 1 so that the stop bit may be deasserted. attempts to program or erase the array while stop = 1 have no effect. ses cannot be set to 1 when stop = 1. when stop = 0, the uc3f array is enabled for accesses. in addition, all registers which were disabled with stop = 1 are now enabled. a stop recovery time of 1 motorola chapter 20. cdr3 flash (uc3f) eeprom 20-9 programmer?s model 5 access enable uncensored access. a censored access to the uc3f eeprom is any access where the device is in the censored mode (uc3f_censor_b = 0). the default reset state is access is a 0 so that fic and censor[0:1] control the level of censorship to the uc3f eeprom array. all accesses to the uc3f eeprom array shall be allowed if access = 1. access can be read whenever the registers are enabled. access provides a method to bypass the uc3f eeprom module censorship. 0 censored uc3f array access allowed only if the c3f censorship is no censorship 1 allows all uc3f array access 6:7 censor censor accesses. the censor[0:1] bits are implemented using nonvolatile register bits or cam cells. the reset state of censor[0:1] is user defined by the contents stored in the nvm register bits. censor is not writable but the nvm register?s data can be set or cleared to the desired reset state. reading censor while setting or clearing with the high voltage applied (csc = 1 and hvs = 1) will return 0?s. 00 cleared censorship, uc3f array access allowed only if device is in uncensored mode 01 no censorship, all uc3f array accesses allowed 10 no censorship, all uc3f array accesses allowed 11 information censorship, uc3f array access allowed only if device is in uncensored mode 8:15 supv supervisor space. the supv bits are used to assign supervisor space restrictions for each block of the uc3f array. the index for the supv bit field is used to determine block assignment. for example, supv[0] is used for the supervisor space assignment of array block 0, while supv[4] is used for array block 4 supervisor space assignment. array block m is mapped into supervisor address space when supv[m] = 1, and only supervisor accesses are allowed to array block m. if supv[m] = 0, then array block m is mapped into unrestricted address space which allows both supervisor and user accesses to array block m. the supv bits are not actually used in the uc3f eeprom module but are used by the biu to determine access restrictions to uc3f array on a blockwise basis. the block addresses are decoded in the biu to determine which array block is selected, and the selected block?s supv bit is compared with the address space attributes to determine validity of an array access. when the small block function is enabled, the enabled small block portion of an array block is not controlled by the supv bit corresponding to the array block containing that small block. this particular small block is controlled by the appropriate sbsupv bit while the remainder of that array block is controlled by its supv bit. 0 array block m is placed in unrestricted address space 1 array block m is placed in supervisor address space table 20-3. uc3fmcr bit descriptions (continued) bit(s) name description 20-10 mpc565/mpc566 reference manual motorola programmer?s model 20.3.3 uc3f eeprom extended configuration register (uc3fmcre) the uc3fmcre is an extended module configuration register used for configuring the small block functions. in addition, 16 bits of the uc3fmcre are used to provide a source for module identification. 16:23 data data space. the data bits are write protected by lock and csc. writes to data have no effect if lock = 0 or csc = 1. the data bits may be read whenever the registers are enabled. each array block of the uc3f eeprom may be mapped into data or data and instruction address space. when array block m is mapped into data address space (data[m] = 1), only data accesses will be allowed. when array block m is mapped into both data and instruction address space (data[m] = 0), both data and instruction accesses will be allowed. the data bits are not actually used in the uc3f eeprom module but are used by the biu to determine access restrictions to uc3f array on a blockwise basis. the block addresses are decoded in the biu to determine which array block is selected, and the selected block?s data bit is compared with the address space attributes to determine validity of an array access. when the small block function is enabled, the enabled small block portion of an array block is not controlled by the data bit corresponding to the array block containing that small block. this particular small block is controlled by the appropriate sbdata bit while the remainder of that array block is controlled by its data bit. 0 array block m is placed in both data and instruction address spaces 1 array block m is placed in data address space 24:31 protect block protect. each array block of the uc3f eeprom can be individually protected from program or erase operation. the contents of array block m are protected from program or erase by setting protect[m] = 1. the uc3f will perform all program and erase interlocks and complete the program or erase sequence, but the program and erase voltages are not applied to locations within the protected array block(s), blocks whose corresponding protect bit is set to 1. by setting protect[m] = 0, array block m is enabled for program and erase operation, and its contents may be altered by programming or erasing. when the small block function is enabled, the enabled small block portion of an array block is not controlled by the protect bit corresponding to the array block containing that small block. this particular small block is controlled by the appropriate sbprotect bit while the remainder of that array block is controlled by its protect bit. 0 array block m is unprotected 1 array block m is protected 1 note that the lock bit is in a different bit location on the mpc565/mpc566 than in the mpc555/556. table 20-3. uc3fmcr bit descriptions (continued) bit(s) name description motorola chapter 20. cdr3 flash (uc3f) eeprom 20-11 programmer?s model msb 0 12345 6 7 89101112131415 sben sbsupv sbdata sbprotect reserved biu hreset: 001100 1 1 11 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 memsiz blk map sblkl flashid hreset: 10110x 1 x 0 00000000 1 blkl = 0b10 for module a and sblkl = 0b01 for module b. figure 20-3. uc3fmcre? uc3f eeprom extended configuration register 0x2f c804 0x2f c844 20-12 mpc565/mpc566 reference manual motorola programmer?s model table 20-4. uc3fmcre bit descriptions bit(s) name description 0:1 sben small block enable. when sben[m]=0, the corresponding small block m behaves logically as if the small block is still part of the larger host block. in addition, the small block protect bit (sbprotect[m]), the small block supervisor bit (sbsupv[m]), the small block data bit (sbdata[m]), and the small block block bit (sbblock[m]) corresponding to small block m have no effect. the corresponding small block is controlled by the same protect, supervisor, data, and block bits that control its host block. when sben[m] = 1, the corresponding small block m can be programmed and erased independently of its host block. the corresponding small block protect bit, the small block supervisor bit, the small block data bit, and the small block bit are enabled by sben. for example: when sben[0] = 0, small block 0 (16 kbytes) and the residual block (16 kbytes or 48 kbytes) contained in the host block of small block 0 are programmed and erased as if the two blocks are one large array block (32 kbytes or 64 kbytes). when sben[0] = 1, small block 0 and the residual block contained in the host block of small block 0 behave as two separate blocks, i.e. small block 0 and the residual block in small block 0?s host block can be programmed and erased independently of each other. 0 small block m behaves as part of the host block 1 small block m functions independent of host block 2:3 sbsupv small block supervisor space. each small array block of the uc3f eeprom may be mapped into supervisor or unrestricted address space. when small array block m is mapped into supervisor address space, sbsupv[m] = 1, only supervisor accesses are allowed. when small block m is mapped to unrestricted address space, sbsupv[m] = 0, both supervisor and user accesses are allowed. if sben[m] = 0, the corresponding small block m is logically part of the host block and sbsupv[m] has no effect. instead, the corresponding supv[m] bit will be used to determine if the small block is mapped to supervisor or unrestricted address space. like the supv[0:7] bits, sbsupv are not actually used in the uc3f eeprom module but are used by the biu to determine access restrictions to the uc3f array. block addresses are decoded in the biu to determine which small array block is selected, and the selected small block?s sbsupv bit is compared with the address space attributes to determine validity of an array access. 0 small block m is placed in unrestricted address space 1 small block m is placed in supervisor address space 4:5 sbdata small block data space. each small array block of the uc3f eeprom may be mapped into data or both data and instruction address space. when a small array block is mapped into data address space, sbdata[m] = 1, only data accesses will be allowed. when a small array block is mapped into both data and instruction address space, sbdata[m] = 0, both data and instruction accesses will be allowed. if sben[m] = 0, the corresponding small block m is logically part of the host block and sbdata[m] has no effect. instead, the corresponding data[m] bit will be used to determine if the small block is mapped to data or to both data and instruction address space. like the data bits, sbdata are not actually used in the uc3f eeprom module but are used by the biu to determine access restrictions to the uc3f array. block addresses are decoded in the biu to determine which small array block is selected, and the selected small block?s sbdata bit is compared with the address space attributes to determine validity of an array access. 0 small block m is placed in both data and instruction address spaces 1 small block m is placed in data address space 6:7 sbpro tect small block protect. each small block of the uc3f eeprom can be individually protected from program or erase operation. the uc3f will perform all program and erase interlocks and even complete the program or erase sequence, but the program and erase voltages are not applied to locations within the protected small block(s). 0 small block m is unprotected 1 small block m is protected motorola chapter 20. cdr3 flash (uc3f) eeprom 20-13 programmer?s model 8:9 ? reserved 10:15 biu biu configuration bits. these register bits are reserved for biu functionality and are strictly outputs from the uc3f eeprom. 16:18 memsiz memory size. the memsiz field is used to indicate the uc3f array size. the memsiz bits are read only and writes have no effect. 0b000uc3f array is 64 kbytes 0b001uc3f array is 128 kbytes 0b010uc3f array is 192 kbytes 0b011uc3f array is 256 kbytes 0b100unused 0b101uc3f array is 512 kbytes 0b110unused 0b111 unused both modules on the mpc565/mpc566 are 512 kbytes. 19 blk block size. the blk bit is used to indicate the array block size used in the uc3f array. the blk bit is read only and writes have no effect. 0 array block size is 32 kbytes 1 block size is 64 kbytes 20 map array address mapping. the map bit is used to indicate the uc3f array address mapping within a2 n address space. the map bit is read only and writes have no effect. the map bit is more useful when the uc3f array is a non-2 n size. when map = 0, the uc3f array is mapped to the bottom (starting at address 0) of the 2 n space in which the array resides. for modules with 2 n array sizes, the map bit is always set to 0. when map = 1, the uc3f array is mapped to the top (ending at address all $f?s) of the 2 n space in which the array resides. the 192kb and 384kb modules are the only two allowed configurations of the uc3f module which have non-2 n array sizes. if map = 1 for a 192-kbyte or 384-kbyte array, the uc3f array is mapped starting at the respective 64kb offset from the beginning of a 256-kbyte address space or 128-kbyte offset from the beginning of a 512-kbyte address space. 0 uc3f array is mapped to top of 2 n address space 1 uc3f array is mapped to bottom of 2 n address space 21:22 sblkl small block location code. there are three possible locations for the small blocks: 1) a small block may be placed in the lowest numbered host block and the highest numbered host blocks, 2) a small block may be placed in the lowest numbered host block and the second lowest numbered host block, and 3) a small block may be placed in the second highest numbered host block and the highest numbered host block. 00 unused 01 small blocks are part of the two highest numbered blocks of the uc3f array 10 small blocks are part of the two lowest numbered blocks of the uc3f array 11 small blocks are part of the lowest and highest numbered blocks of the uc3f array 23:31 flashid flash module identification code. the flashid value is assigned by motorola and used internally for tracking purposes. the flashid field is read only and writes have no effect. table 20-4. uc3fmcre bit descriptions (continued) bit(s) name description 20-14 mpc565/mpc566 reference manual motorola programmer?s model 20.3.4 uc3f eeprom high voltage control register (uc3fctl) the uc3f eeprom high voltage control register is used to control the program and erase operations of the uc3f eeprom module. msb 0 1 2 3 4 567891011121314 15 hvs pegood pefi epee b0em reserved sbblock hreset: 0 0 0 0 0 0000000 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 block 0 csc reser ved hsus pe ses ehv hreset: 0 0 0 0 0 0000000 0 0 0 0 figure 20-4. uc3fctl? uc3f eeprom high voltage control register 0x2f c808 0x2f c848 table 20-5. uc3fctl bit descriptions bit(s) name description 0 hvs high voltage status. the hvs bit is for status only, and writes to hvs have no effect. during a program or erase operation, hvs is set (hvs = 1) to indicate when high voltage operations are in progress. the hvs bit will negate itself when the program or erase operation completes successfully, ehv negates during program or erase to terminate the program/erase operation, hsus is asserted to suspend the program/erase operation, resetting the module, or the internal hardware program/erase controller times out. 0 no program or erase of the uc3f array or shadow information or censor bits in progress 1 program or erase of the uc3f array or shadow information or censor bits in progress 1 pegood program/erase operation result. the pegood bit is for status only. at the completion of a program or erase operation using the embedded hardware algorithm, the hardware algorithm will change the state of the pegood bit to reflect whether or not the program or erase operation was successful. note: pegood will be set under the following conditions: no failure occurred no program or erase operation was requested the pegood bit is only valid after the hardware program/erase algorithm has cleared hvs. pegood is reset when either ehv is asserted or ses is cleared. see figure 20-5 for a timing diagram of when pegood is valid. 0 program or erase operation failed 1 program or erase operation was successful motorola chapter 20. cdr3 flash (uc3f) eeprom 20-15 programmer?s model 2 pefi program/erase fail indicator. the pefi bit is a status qualifier for the pegood bit and is valid for the same times that pegood is valid. in the event of an erase failure which returns pegood = 0, the pefi bit provides diagnostic information for the cause of the erase failure. if pefi = 0, the erase failure occurred during the preprogramming step of the erase operation. if pefi = 1, the erase failure occurred during the actual erase or apde steps of the erase operation. in the event of a program failure which returns pegood = 0, the pefi bit indicates a program failure by reading as a 0. the pefi bit should never return a 1 for a program failure. note: the pefi bit is meaningful only while pegood is valid and pegood = 0. pefi is valid after hvs negates and prior to the assertion of ehv or negation of ses. 0 program operation failed if pegood = 0 1 erase operation failed if pegood = 0 3 epee epee pin status. the epee bit monitors the state of the external program/erase enable (epee) input. the uc3f module samples the epee input when ehv is asserted and holds that sampled state until ehv is negated. 0 high voltage operations are not possible 1 high voltage operations are possible 4 b0em block 0 epee pin status. the b0em bit monitors the state of the block 0 epee, b0epee, input. the uc3f module samples the b0epee input when ehv is asserted and holds that sampled value until ehv is negated.if b0em = 1 when ehv is asserted, high voltage operations such as program or erase are enabled for either small block 0 or the lowest numbered block of the uc3f array regardless of the state of epee. if b0em = 0 when ehv is asserted, high voltage operations are disabled for small block 0 or the lowest numbered block of the uc3f array regardless of the state of epee. 0 high voltage operations are not possible for block 0 or lowest numbered block 1 high voltage operations are possible for block 0 or lowest numbered block. 5:13 ? reserved 14:15 sbblock small block program and erase select. the sbblock bits are write-protected by the ses bit. sbblock selects the uc3f eeprom small array blocks for program and erase operation. when programming, only those blocks intended to be enabled for programming should have their corresponding block[m] or sbblock[m] bit set. 0 small block m is not selected for program or erase 1 small block m is selected for program or erase 16:23 block block program and erase select. the block bits are write protected by the ses bit. block selects the uc3f eeprom array blocks for program and erase operation. all the blocks may be selected for program or erase operation at once. the uc3f eeprom configuration along with block determine which array blocks that may be programmed. the uc3f eeprom array blocks that are enabled to be programmed by the program operation are the blocks whose corresponding block bit is set to 1. for example, if array blocks 2 and 5 are enabled for programming, block[2] and block[5] must be set to 1 while block[0], block[1], block[3], block[4], block[6], and block[7] are set to 0. the uc3f eeprom configuration along with block determine the blocks that will be erased simultaneously. all array blocks whose corresponding block bits are set will be erased during the erase operation. for example, if block = 00100111, then array blocks 2, 5, 6, and 7 get erased when an erase operation is performed. 0 array block m is not selected for program or erase 1 array block m is selected for program or erase 24 ? reserved table 20-5. uc3fctl bit descriptions (continued) bit(s) name description 20-16 mpc565/mpc566 reference manual motorola programmer?s model 25 csc censor set or clear. the csc bit is write protected by the ses bit. csc configures the uc3f eeprom for setting or clearing censor. if csc = 1 then censor is configured for setting if pe = 0 or clearing if pe = 1. when the csc bit is set, the following bits in the uc3fmcr register are write-locked: lock ,fic, access, supv, data, and protect. 0 configure for normal operation 1 configure to set or clear the censor bits 26:27 ? reserved 28 hsus program/erase suspend. setting the hsus bit during an embedded hardware algorithm program or erase operation will force the uc3f eeprom to suspend the current program or erase. the uc3f eeprom will maintain all information necessary to resume the suspended operation. array reads are possible while hsus = 1. however, array reads must be done to locations that are not being affected by the program/erase operation that is currently being suspended. the uc3f eeprom will not prevent read accesses to those locations. reads to those locations will result in unknown data. writes to the hsus bit only have effect while ehv = 1. the hsus bit is write locked by ehv = 0. 0 hardware program/erase behaves normally 1 any current hardware program/erase is suspended 29 pe program or erase select. the pe bit is write protected by the ses bit. pe configures the uc3f eeprom for programming or erasing. when pe = 0, the array is configured for programming and if ses = 1 the sie bit will be write locked. when pe = 1, the array is configured for erasing and ses will not write lock the sie bit. 0 configure for program operation 1 configure for erase operation table 20-5. uc3fctl bit descriptions (continued) bit(s) name description motorola chapter 20. cdr3 flash (uc3f) eeprom 20-17 programmer?s model figure 20-5. pegood valid time 30 ses start-end program or erase sequence. the ses bit is write protected by the stop, hvs, and ehv bits. the ses bit is used to signal the start and end of a program or erase sequence. at the start of a program or erase sequence, ses is set (written to a 1). this will lock stop, protec, sbprotect, block, sbblock, sben, csc, and pe. if pe = 0 and ses = 1, sie will be write locked. at this point, the uc3f eeprom is ready to receive either the programming writes or the erase interlock write. note: the erase interlock write is a write to any uc3f eeprom array location after ses is set and pe = 1. if pe = 0 and ses = 1, writes to the uc3f array are programming writes. the first programming write sets the address of the location to be programmed, and the data written is captured into the program data latch for programming into the uc3f array. all programming writes after the first programming write update the program data latch but do not change the address to be programmed. at the end of the program or erase operation, the ses bit must be cleared (written to a 0) to return to normal operation and release the stop, protect, sbprotect, block, sbblock, csc, sben, and pe bits. 0 uc3f eeprom not configured for program or erase operation 1 configure uc3f eeprom for program or erase operation 31 ehv enable high voltage. ehv can be asserted only after the ses bit has been asserted and a valid programming write(s) or erase hardware interlock write has occurred. if an attempt is made to assert ehv when ses is negated, or if a valid programming write or erase hardware interlock write has not occurred since ses was asserted, ehv will remain negated. the external program or erase enable pin (epee) and ehv are used to control the application of the program or erase voltage to the uc3f eeprom module. high voltage operations to the uc3f eeprom array, special shadow locations or flash nvm registers can occur only if ehv = 1 and epee = 1. only after the correct hardware and software interlocks have been applied to the uc3f eeprom can ehv be set. once ehv is set, ses cannot be changed and attempts to read the array will not be acknowledged. clearing ehv during a program or erase operation will safely terminate the high voltage operation. if ehv is cleared while using the embedded hardware program/erase algorithm, the program/erase routine will abort the operation and exit normally. 0 program or erase pulse disabled 1 program or erase pulse enabled table 20-5. uc3fctl bit descriptions (continued) bit(s) name description ses ehv hvs pegood valid time pegood valid time pegood 20-18 mpc565/mpc566 reference manual motorola programmer?s model 20.3.5 uc3f eeprom array addressing the mapping of the array in the mcu is determined by the address decoder in the biu. the uc3f array is divided into a maximum of eight blocks, 64 kbytes in size, which may be independently erased. two blocks are host to a 16-kbyte small block. seventeen bits of address are used to decode locations in the uc3f array. the read control logic in the uc3f eeprom module decodes the upper 14 bits of that address to determine if the desired data is currently stored in one of the two read page buffers. if the data is already present in one of the two read page buffers, a read operation is not completed to the uc3f array core, and 64 bits of data are transferred from the appropriate read page buffer to the biu. this type of array read access is an on-page read. in the event that the read control logic determines that the desired data is not contained within one of the read page buffers, a read access to the uc3f array core is completed and 32 bytes of data are transferred from the array core. only the addressed 64 bits of data will be transferred to the biu. this type of array read access is an off-page read. the biu contains logic to implement the read page buffer update and replacement scheme to transfer the 32 bytes of data into the appropriate read page buffer. if the read page update and replacement scheme contains a random access mode that does not update the read page buffers, the 32 bytes of data retrieved from the uc3f array core will not be transferred into either read page buffer. the biu is expected to contain page update logic for controlling the updating of the read page buffers. write accesses to the uc3f array have no effect except during program and erase operation. 20.3.6 uc3f eeprom shadow row the uc3f eeprom module contains a special shadow row that is used to hold reset configuration data and user data. see figure 20-6. the shadow row is accessed by setting sie = 1 and performing normal array accesses. upon transitioning sie (a 1-to-0 or 0-to-1 transition), the read page match decode circuit is reset so that the next array access is an off-page access. the shadow row contains 512 bytes which are addressed for read accesses using the low order row and read page addresses. the shadow row is implemented in the lowest numbered block of the array. in the case of a uc3f array configuration which also has a small block in the lowest numbered block of the array, the shadow row is contained in the small block. if sben[0] = 1 in this array configuration, the shadow row is treated as part of small block 0. sbprotect[0] and sbblock[0] are used to control program and erase operation of the shadow row. if sben[0] = 0 in this array configuration, the shadow row is treated as part of the host block. the corresponding protect and block bits are used to control program and erase operation of the shadow row. motorola chapter 20. cdr3 flash (uc3f) eeprom 20-19 programmer?s model note a shadow row cannot be read if the program code is executing from the same module of the mpc565/mpc566. (i.e., if a program is executing from one flash module), it can only read the shadow row of the other flash module, for example a program running from module uc3f_a can read the shadow row of the uc3f_b module. figure 20-6. shadow information 20.3.6.1 reset configuration word (uc3fcfig) the uc3f eeprom reset configuration word is implemented in the first word (addr[23:29] = 0x00) of the special shadow locations. the reset configuration word along with the rest of the shadow information words is located in supervisor data address space. the purpose of the reset configuration word is to provide the system with an alternative internal source for the reset configuration. note that with the exception of bit 20, the bits in the uc3fcfig are identical to those in the usiu hard reset configuration word. 0x00 0x1ff 0x10 0x0f reset configuration word general-use shadow information reserved for future applications 0x04 0x03 20-20 mpc565/mpc566 reference manual motorola programmer?s model msb 0 1 2 3 4 5 6 7 8 9 10 11 12 131415 earb ip bdrv bdis bps[0:1] reserved dbgc[0:1] rese rved 2 atwc ebdf[0:1] iws reset 000 00 0 0 0000 0 0 000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 prpm sc etre hc en_ comp 1 exc_ comp 1 res erv ed oerc reserved isb dme reset 000 00 0 0 0000 0 0 000 1 available only on the mpc566. 2 reserved on all mask sets after k16y. this bit was dbpc on mask set 1k85h. figure 20-7. uc3fcfig ? hard reset configuration word table 20-6. rcw bit descriptions bit(s) name description 0 earb external arbitration ? refer to section 9.5.7, ?arbitration phase? for a detailed description of bus arbitration. the default value is that internal arbitration hardware is used. 0 internal arbitration is performed 1 external arbitration is assumed 1 ip initial interrupt prefix ? this bit defines the initial value of the msr ip immediately after reset. the msr ip bit defines the interrupt table location. if ip is zero then the msr ip initial value is zero, if the ip is one, then the msr ip initial value is one. default value is zero. see table 3-12 for more information. 0 msr[ip] = 0 after reset 1 msr[ip] = 1 after reset 2 bdrv bus pins drive strength ? this bit determines the bus pins? (address, data, and control) driving capability to be either full or reduced drive. the bus default drive strength is full; upon default, it also causes the clkout drive strength to be full. see table 6-7 for more information. bdrv controls the default state of com[1] in the siumcr. 0fulldrive 1 reduced drive 3 bdis boot disable ? if the bdis bit is set, then memory controller is not activated after reset. if it is cleared then the memory controller bank 0 is active immediately after reset such that it matches any addresses. if a write to the or0 register occurs after reset this bit definition is ignored. the default value is that the memory controller is enabled to control the boot with the cs 0pin.see section 10.7, ?global (boot) chip-select operation? for more information. 0 memory controller bank 0 is active and matches all addresses immediately after reset 1 memory controller is not activated after reset. motorola chapter 20. cdr3 flash (uc3f) eeprom 20-21 programmer?s model 4:5 bps boot port size ? this field defines the port size of the boot device on reset (br0[ps]). if a write to the or0 register occurs after reset this field definition is ignored. see table 10-5 and table 10-8 for more information. 00 32-bit port (default) 01 8-bit port 10 16-bit port 11 reserved 6:8 ? reserved. these bits must not be high in the reset configuration word. 9:10 dbgc[0:1] debug pins configuration ? see section 6.14.1.1, ?siu module configuration register (siumcr)? for this field definition. the default value is that these pins function as: vfls[0:1], bi , br ,bg and bb .seetable6-8. 11 ? reserved. 1 12 atwc address type write enable configuration ? the default value is that these pins function as we pins. 0we [0:3]/be [0:3] /at[0:3] functions as we [0:3]/be [0:3] 1we [0:3]/be [0:3]/at[0:3] functions as at[0:3] see table 6-7. 13:14 ebdf external bus division factor ? this field defines the initial value of the external bus frequency. the default value is that clkout frequency is equal to that of the internal clock (no division). see ta bl e 8 - 9 . 15 iws interlock write select ? this bit determines which interlock write operation should be used during the clear censorship operation. 0 interlock write is a write to any uc3f array location 1 interlock write is a write to the uc3fmcr register. 16 prpm peripheral mode enable ? this bit determines if the chip is in peripheral mode. a detailed description is in table 6-13 the default value is no peripheral mode enabled. 17:18 sc single chip select ? this field defines the mode of the mpc565/mpc566. 00 extended chip, 32 bits data 01 extended chip, 16 bits data 10 single chip and show cycles (address) 11 single chip see table 6-10. 19 etre exception table relocation enable ? this field defines whether the exception table relocation feature in the bbc is enabled or disabled; the default state for this field is disabled. for more details, see table 4-4. 20 hc has configuration ? this bit determines if the flash reset configuration word is valid. 0 the flash shadow row contains a valid reset configuration word 1 the flash shadow row does not contain a valid reset configuration word 21 en_ comp 2 enable compression ? this bit enables the operation of the mpc566 with compressed code. the default state is disabled. see table 4-4. 22 exc_ comp 2 exception compression ? this bit determines the operation of the mpc566 with exceptions. if this bit is set, than the mpc566 assumes that all the exception routines are in compressed code. the default indicates the exceptions are all non-compressed. see table 4-4. 23 ? reserved. this bit must not be high in the reset configuration word. table 20-6. rcw bit descriptions (continued) bit(s) name description 20-22 mpc565/mpc566 reference manual motorola programmer?s model during reset the hc bit (?has configuration? bit 20) and the usiu configure the uc3f eeprom module to provide uc3fcfig. if hc = 0 and the usiu requests internal configuration during reset the reset configuration word will be provided by uc3fcfig. the default reset state of the uc3fcfig after an erase operation of the uc3f module is no configuration word available (hc =1). note the reset configuration word can be stored in either uc3f_a or uc3f_b. 20.3.7 uc3f eeprom 512-kbyte array configuration figure 20-8 shows the uc3f configuration for the mpc565/mpc566 512-kbyte arrays. the blue shaded blocks in the array configuration diagram indicate the location of the shadow row. 24:25 oerc other exceptions relocation control ? these bits effect only if etre was enabled. relocation offset: 00 offset 0 01 offset 64 kb 10 offset 512 kb 11 offset to 0x003 fe000 (sram start address) see table 4-2. 26:27 ? reserved 28:30 isb internal space base select ? this field defines the initial value of the isb field in the immr register. a detailed description is in table 6-12. the default state is that the internal memory map is mapped to start at address 0x0000_0000 hex. this bit must not be high in the reset configuration word. 31 dme dual mapping enable ? this bit determines whether dual mapping of the internal flash is enabled. for a detailed description refer to table 10-11. the default state is that dual mapping is disabled. 0 dual mapping disabled 1 dual mapping enabled 1 reserved on all mask sets k16y and later. this bit was dbpc on mask set 1k85h. dbpc definition was 0=dsck, dsdi, dsdo selected; 1 = tck, tdi, tdo selected. 2 this bit is available only on the mpc566. table 20-6. rcw bit descriptions (continued) bit(s) name description motorola chapter 20. cdr3 flash (uc3f) eeprom 20-23 operation figure 20-8. 512-kbyte array configurations 20.4 operation the following sections describe the operation of the uc3f eeprom during various operational modes. the primary function of the uc3f eeprom module is to serve as electrically erasable and programmable non-volatile memory for embedded application in microcontrollers. 20.4.1 reset the device shall signal a reset to the uc3f eeprom by asserting the reset signal. a reset is the highest priority operation for the uc3f eeprom and terminates all other operations. the uc3f eeprom module uses reset to initialize register bits to their default reset value. if the uc3f eeprom is in program or erase operation (ehv = 1 and ses = 1) and a reset is issued, the module will perform the needed interlocks to disable the high voltage without damage to the high voltage circuits. reset terminates any other mode of operation and forces the uc3f eeprom module to a state ready to receive accesses. upon power up and power down periods, it is assumed that the reset signal is asserted to prevent accidental program/erase disturb of the uc3f array. 16 kbytes small blk 0 48 kbytes blk 4 16 kbytes small blk 1 48 kbytes blk 7 64 kbytes blk 6 blk 5 blk 0 64 kbytes blk 1 64 kbytes blk 2 64 kbytes blk 3 64 kbytes small blk 0 blk 4 16 kbytes small blk 1 48 kbytes blk 7 64 kbytes blk 6 blk 5 blk 0 64 kbytes blk 1 64 kbytes blk 2 64 kbytes blk 3 64 kbytes 48 kbytes 64 kbytes uc3f_a uc3f_b 16 kbytes 64 kbytes 20-24 mpc565/mpc566 reference manual motorola operation 20.4.2 register read and write operation the uc3f eeprom control registers are accessible for read or write operation at all times while the device is powered up and enabled except during reset. 20.4.3 array read operation the uc3f eeprom array is available for read operation under most conditions while the device is powered up. reads of the array are not allowed during reset, when in information or cleared censorship with access = 0, while the uc3f eeprom is disabled (see section section 20.4.10, ?disabled? for more information on disabling the uc3f eeprom), while the uc3f eeprom is in stop mode (see section section 20.4.9, ?stop operation? for more information on stop mode), or while high voltage is applied to the array during program and erase operation (hvs = 1 or ehv = 1 and not suspended). the uc3f array may be configured into a page mode access memory by setting the bpb bit in the uc3fmcr register, see section 20.3.2, ?uc3f eeprom configuration register (uc3fmcr).? when in page mode operation, the address of an incoming read access is compared to the address for which data is currently held in the read page buffers. if the data corresponding to the read address is currently held in one of the two read page buffers, the data is fetched from the appropriate read page buffer. a data fetch from a read page buffer is an on-page read operation section 20.4.3.1, ?array on-page read operation.? if the data is not contained in one of the read page buffers, 32 bytes of information is fetched from the uc3f array, and the addressed data is driven onto the data bus. a data fetch from the uc3f array is an off-page read operation. note after setting/clearing hsus, reset, programming writes, erase interlock write, setting ehv, clearing ses or setting/clearing sie, the page buffers may not contain valid information and the uc3f page match logic negates uc3f_onpage[0:1] to force an off page read before an on page read can be accomplished to ensure data coherency. for information regarding how the two read page buffers in the uc3f eeprom are associated to array blocks, refer to section 20.3.5, ?uc3f eeprom array addressing.? the uc3f module is configured as a page mode memory. the uc3f module uses an internal address comparator to monitor incoming addresses to determine if the addressed information is stored in a read page buffer. when the address comparator determines that the requested information is not stored in a read page buffer, an array off-page read operation retrieves 32 bytes of data from the flash array and transfers the addressed data to thedatabus. motorola chapter 20. cdr3 flash (uc3f) eeprom 20-25 operation in the mpc565/mpc566, each uc3f module contains two 32-byte read page buffers. in each module, one buffer is dedicated to the most recently accessed instruction fetches and the other read page buffer is dedicated to the most recently loaded data access. 20.4.3.1 array on-page read operation an internal address comparator is used to determine if addressed information is stored in a read page buffer. if the address of a read access matches data contained in a read page buffer, that addressed data is transferred from the read page buffer to the data bus. an off-page read access to transfer data from the flash array to the data bus is not performed in this case. 20.4.4 shadow row select read operation the normal array is accessed when the sie register bit in the uc3fmcr = 0. when sie = 1, reads to the array access the shadow information row. 20.4.5 array program/erase interlock write operation the only valid writes to the uc3f array are program or erase interlock writes. in the case of program interlock writes, the address of the write determines the location to be programmed while the data written is transferred to the program data latches to be programmed into the array. address and data written during an erase interlock write is a ?don?t care? and is not stored anywhere. 20.4.6 high voltage operations there are two fundamental high voltage operations, program and erase. program changes a uc3f array bitcell from a logic 1 state to a logic 0 state and is a selective operation performed on up to 32 bits at a time. erase changes a uc3f array bitcell from a logic 0 state to a logic 1 state and is a bulk operation performed on one block or multiple blocks of the uc3f array. 20.4.6.1 overview of program/erase operation the embedded hardware program/erase algorithm relies on an internal state controller to perform the program and erase sequences. the embedded hardware algorithm uses an internal oscillator to control the high voltage pulse duration and hardware control logic. the embedded hardware algorithm is also responsible for performing all margin reads and applying high voltage pulses to ensure each bit is programmed or erased with sufficient margin. upon successful program or erase operation, the program/erase hardware control logic terminates the program or erase operation with a pass status (pegood = 1). the program/erase control logic will time out in the event that the maximum program or erase time is exceeded and return a fail status (pegood = 0). 20-26 mpc565/mpc566 reference manual motorola operation 20.4.7 programming to modify the charge stored in an isolated element of the uc3f bit from a logic 1 state to a logic 0 state, a programming operation is required. this programming operation shall apply the required voltages to change the charge state of the selected bits without changing the logic state of any other bits in the uc3f array. the program operation cannot change the logic 0 state to a logic 1 state; this transition must be done by the erase operation. programming uses a program data latch to store the data to be programmed and an address latch to store the word address to be programmed. the uc3f array may be programmed by byte (8 bits), half-word (16 bits), or word (32 bits). blocks of the uc3f eeprom that are protected (protect[m] = 1, sben[n] = 1 and sbprotect[n] = 1) will not be programmed. also, if epee = 0, no programming voltages will be applied to the array. if b0epee = 0, no programming voltages will be applied to block 0 or small block 0 depending on the state of sben[0] and the configuration of the array. in the event of uc3f module configurations which do not contain a block 0, the lowest numbered block is protected by b0epee. also, if the lowest numbered block does not host small block 0, then no small blocks can be protected by b0epee. 20.4.7.1 program sequence the uc3f eeprom module requires a sequence of writes to the high voltage control register (uc3fctl) and to the program data latch in order to enable the high voltage to the array or shadow information for program operation. the required hardware program sequence follows. 1. write protect[0:7] and sbprotect[0:1] to disable protection on blocks to be programmed. 2. write block[0:7] and sbblock[0:1] to select the array blocks to be programmed, ses = 1 and pe = 0 in the uc3fctl register. note block[0:7] and sbblock[0:1] in conjunction with sben[0:1] determine which blocks/small blocks in the array are enabled for programming operation. just because a block or sbblock bit is enabled (set to 1), no programming can occur in the corresponding block/small block unless the programming operation specifically targets an address location within that block/small block to program. if block or sbblock is not set to 1, no address locations in that corresponding block or small block can be programmed. motorola chapter 20. cdr3 flash (uc3f) eeprom 20-27 operation 3. programming write ? a successful write to the array location to be programmed. this write shall update the program data latch with the information to be programmed. in addition, the address, uc3f_addr[0:16], of the first programming write is latched in the uc3f memory interface block. all access of the array after the first write shall be to the same address regardless of the address provided. thus the locations accessed after the first programming write are limited to the location to be programmed. the last write to the program data latch shall be saved for programming. note if a byte of the program data latch has not received a programming write, no programming voltages will be applied to the corresponding byte in the array. once ehv has been set, writes to the program data latch are disabled until ehv is cleared to 0. 4. write ehv = 1 in the uc3fctl register. note the values of the epee and b0epee inputs are latched with the assertion of ehv to determine the array protection state for the program operation. it is assumed that the epee and b0epee inputs are setup prior to the assertion of ehv. 5. read the uc3fctl register until hvs = 0. 6. read the uc3fctl, confirm pegood = 1. 7. write ehv = 0. warning writing ehv = 0 before hvs = 0 causes the current program sequence to abort. the location for which the program sequence was aborted may not have been programmed with sufficient margins. the block containing that location must be erased and reprogrammed before that block of the uc3f array may be used reliably. 8. if more information needs to be programmed go to step 3. 9. write ses = 0 in the uc3fctl register. 20-28 mpc565/mpc566 reference manual motorola operation figure 20-9. program state diagram table 20-7. program interlock state descriptions state mode next state transition requirement s1 normal operation: normal array reads and register accesses. the block protect information can be modified. s2 t2 write pe = 0, ses = 1. s2 first program hardware interlock write: normal read operation still occurs. the array will accept programming writes. accesses to the registers are normal register accesses. a write to uc3fctl cannot change ehv at this time.if the writeistoaregisternodatawillbestoredinthe program data latch and the uc3f shall remain in state s2. s1 t1 write ses = 0 or a reset. s3 t3 hardware interlock a successful write to any uc3f array location. this programming write will latch the selected word of data into the program data latch and the address shall be latched to select the location that will be programmed. once a bit has been written then it shall remain in the program data latch until another write over-writes that data or a write of ses=0.ifthewriteistoaregisterno data will be stored in the program data latch and the uc3f shall remain in state s2. s1 t1 t2 t3 s2 s4 t4 s3 t5 t6 reset t7 s5 t8 t9 t10 motorola chapter 20. cdr3 flash (uc3f) eeprom 20-29 operation 20.4.7.2 program shadow information programming the shadow information uses the same procedure as programming the array except that sie must be set to a 1 prior to initiating the programming sequence. only the lowermost addresses are used to encode words that get programmed in the shadow row. the shadow information is physically located in lowest numbered block and will also be located in small block 0 if the lowest numbered block hosts a small block in the implemented configuration. 20.4.7.3 program suspend the program operation may be suspended to allow read accesses to the array. setting the hsus bit in the uc3fctl to a 1 while pe = 0, ehv = 1, and hvs = 1 forces the array into a program suspend state. the deassertion of the hvs bit (hvs = 0) signifies that the s3 expanded program hardware interlock operation: programming writes are accepted so that data may be programmed. these writes may be to any uc3f array location. the location to be programmed is determined from the address initially written to on the first program interlock write. the program data latch may be updated on any program interlock writes which occur in this state. accesses to the registers are normal register accesses. a write to uc3fctl can change ehv. if thewriteistoaregisternodatawillbestoredinthe program data latch. s1 t6 write ses = 0 or a reset. s4 t4 write ehv = 1. s4 program operation: high voltage is applied to the array or shadow information to program the uc3f bit cells, and program margin reads are automatically performed by the internal program control logic. no further programming writes will be accepted. during programming, the array will not respond to any access. accesses to the registers are allowed. a write to uc3fctl can change ehv or hsus only. s1 t5 reset. s2 t7 write ehv = 0. s5 t8 write hsus = 1 or disable the uc3f module. s5 program suspend operation: the program operation is suspended to either read the array or disable the module. once hvs reads as a 0, the program operation is suspended. normal reads to the array can be performed if the module is enabled; read accesses to the location being programmed returns indeterminate data. s1 t10 reset. s4 t9 write hsus = 0 or re-enable the uc3f module. table 20-7. program interlock state descriptions (continued) state mode next state transition requirement 20-30 mpc565/mpc566 reference manual motorola operation program operation has been successfully suspended. the hvs bit should negate within 10 s of asserting the hsus bit. while in program suspend mode, normal read accesses may be performed to the uc3f array or shadow information words. reads to the array location targeted for program return indeterminate data since only a partial programming operation may have been performed. the program operation may be resumed by setting hsus = 0. note repeated suspending of a program operation to fetch array contents may extend the program operation. the internal program hardware may only resume the program operation at predefined steps of the internal program hardware sequence; interrupting the program operation on a high frequency basis may cause the internal program hardware to delay completion of the current step and delay advancement to the next step of the internal program hardware sequence. 20.4.8 erasing to modify the charge stored in an isolated element of the uc3f bit from a logic 0 state to a logic 1 state, an erase operation is required. in the uc3f eeprom, erase is a bulk operation that shall affect the stored charge of all the isolated elements in an array block. to make the uc3f module block-erasable, the array is divided into blocks that are physically isolated from each other. each of the array blocks may be erased in isolation or in any combination. the uc3f array block size is fixed for all blocks in the module at 64 kbytes and the module is comprised of eight blocks. two of these blocks may be further subdivided into two small blocks. array blocks of the uc3f eeprom that are protected (protect[m] = 1 or (sben[m] = 1 & sbprotect[m] = 1)) will not be erased. also, if epee = 0 or b0epee = 0, no erase voltages will be applied to the array or the block corresponding to block 0 (or lowest numbered block if no block 0 exists) or small block 0 (assuming that the lowest numbered block contains small block 0) if sben[0] = 1. the embedded program/erase algorithm first preprograms all bits in blocks selected for erase prior to actually erasing the selected blocks. the array blocks selected for erase operation are determined by block[0:7], sbblock[0:1] in conjunction with sben[0:1], and the array configuration. if multiple blocks are selected for erase, the embedded erase hardware algorithm serially erases each array block until all of the selected blocks are erased. for instance, if block[0:7] = 0x78 and sben[0:1] = 0b00, then blocks 1, 2, 3, and 4 are selected for erase. the embedded erase hardware algorithm first erases block 1 and then erases block 2 followed by blocks 3 and 4. the total erase time for this example is the block erase time, t erase , multiplied by four since four blocks are erased. in addition, the preprogramming time to program all motorola chapter 20. cdr3 flash (uc3f) eeprom 20-31 operation locations in blocks 1, 2, 3, and 4 to a ?0? state needs to be considered when determining the total erase time. the preprogramming time is dependent on the data already stored in the flash array before beginning the erase operation. 20.4.8.1 erase sequence the uc3f eeprom module requires a sequence of writes to the high voltage control register (uc3fctl) and an erase interlock write in order to enable high voltage to the array and shadow information for erase operation. the required hardware algorithm erase sequence follows. 1. write protect[0:7] and sbprotect[0:1] to disable protect for the blocks to be erased. 2. write block[0:7] and sbblock[0:1] to select the blocks to be erased, pe = 1 and ses = 1 in the uc3fctl register. note block[0:7] and sbblock[0:1] in conjunction with sben[0:1] determine which blocks are selected for erase. blocks whose block bits or enabled small blocks whose sbblock bits are set (equal to 1) get erased when an erase operation is performed. 3. execute an erase interlock write to any uc3f array location. 4. write ehv = 1 in the uc3fctl register. note the values of the epee and b0epee inputs are latched with the assertion of ehv to determine the array protection state for the erase operation. it is assumed that the epee and b0epee inputs are setup prior to the assertion of ehv. 5. read the uc3fctl register until hvs = 0. warning writing ehv = 0 before hvs = 0 causes the current erase sequence to abort. all blocks being erased must go through another erase sequence before the uc3f eeprom can be used reliably. 6. read the uc3fctl register. confirm pegood =1. 7. write ehv = 0 in the uc3fctl register. 8. write ses =0 in the uc3fctl register. 20-32 mpc565/mpc566 reference manual motorola operation figure 20-10. erase state diagram table 20-8. erase interlock state descriptions state mode next state transition requirement s1 normal operation: normal array reads and register accesses. the block protect information can be modified. s2 t2 write pe = 1, ses = 1. s2 erase hardware interlock write: normal read operation still occurs. the uc3f will accept the erase hardware interlock write. this write may be to any uc3f array location. accesses to the registers are normal register accesses. a write to uc3fctl cannot set ehv at this time. a write to the register is not an erase hardware interlock write and the uc3f shall remain in state s2. s1 t1 write ses = 0 or a reset. s3 t3 hardware interlock a successful write to any uc3f array location is the erase interlock write. if the write is to a register the erase hardware interlock write has not been done and the uc3f shall remain in state s2. s3 high voltage write enable accesses to the registers are normal register accesses. a write to uc3fctl can change ses or ehv. s1 t6 write ses = 0 or a reset. s4 t4 write ehv = 1. s1 t1 t2 t3 s2 s4 t4 s3 t5 t6 reset s5 t8 t9 t10 t7 motorola chapter 20. cdr3 flash (uc3f) eeprom 20-33 operation 20.4.8.2 erasing shadow information words the shadow information words are erased with either the lowest numbered block or small block 0, depending on the array configuration and the state of sben[0]. if the lowest numbered block in the array does not host a small block, then the shadow information words are erased with the lowest numbered block. if the lowest numbered block hosts a small block, then the shadow information words may get erased with small block 0. if sben[0] = 0 for this array configuration, then the shadow information words get erased with the lowest numbered block. if sben[0] = 1 for this same array configuration, then the shadow information words get erased with small block 0 only. 20.4.8.3 erase suspend the erase operation may be suspended to allow read accesses to the array. setting the hsus bitintheuc3fctltoa1whileehv=1andhvs=1forcesthearrayintoanerasesuspend state. the deassertion of the hvs bit (hvs = 0) signifies that the erase operation has been successfully suspended. the hvs bit should negate within 10 ms of asserting the hsus bit. while in erase suspend mode, normal read accesses may be performed to the uc3f array or shadow information words. reads to the array block or blocks targeted for erase return indeterminate data since only a partial erase operation has been performed. the erase operation may be resumed by setting hsus = 0. s4 erase operation: highvoltageisappliedtothearrayblockstoerase the uc3f bit cells, and erase margin reads are automatically performed by the embedded erase control logic. during erase the array will not respond to any address. accesses to the registers are allowed. a write to uc3fctl can change ehv or hsus only. s1 t5 reset. s2 t7 write ehv = 0. s5 t8 write hsus = 1 or disable the uc3f module. s5 erase suspend operation: the erase operation is suspended to either read the array or disable the module. once hvs reads as a 0, the erase operation is suspended. normal reads to the array can be performed if the module is enabled; read accesses to locations in blocks being erased return indeterminate data. s1 t10 reset. s4 t9 write hsus = 0 or re-enable the uc3f module. table 20-8. erase interlock state descriptions (continued) state mode next state transition requirement 20-34 mpc565/mpc566 reference manual motorola operation note repeated suspending of an erase operation to fetch array contents may severely extend the erase operation. the internal erase hardware may only resume the erase operation at predefined steps of the internal erase hardware sequence; interrupting the erase operation on a high frequency basis may cause the internal erase hardware to delay completion of the current step and delay advancement to the next step of the internal erase hardware sequence. 20.4.9 stop operation the uc3f eeprom goes into a low power operation, or stop operation, while stop = 1. when the stop bit is set, only the control registers can be accessed on the uc3f eeprom module. the uc3f eeprom array may not be programmed, erased or read while stop =1. with stop = 1, the uc3f module enters a low power state by shutting down internal timers and bias generators. a stop recovery time of 1 s is required when clearing the stop bit to exit stop operation. the biu should allow 1 s following the negation of the stop bit so that internal bias generators used by the array may recover to normal levels prior to initiating any uc3f array accesses. note the uc3f cannot be stopped while the array is being programmed or erased since the stop bit is write locked by ses = 1. 20.4.10disabled both uc3f modules can be disabled by clearing the flen bit in the immr register (see section 6.14, ?system configuration and protection registers?). while disabled, the uc3f module is completely shut down. the register block and array are not accessible in this mode, and all circuits which draw any dc power are disabled to eliminate power consumption. in addition, each individual module can be disabled by setting the stop bit in the uc3fmcr register (see section 20.3.2, ?uc3f eeprom configuration register (uc3fmcr)?). if the uc3f module is disabled while programming or erasing, the hsus bit in the uc3fctl register is asserted (hsus = 1) to suspend the current program or erase operation. when the uc3f module is re-enabled, the suspended program or erase operation may be resumed by writing the hsus bit to a 0. motorola chapter 20. cdr3 flash (uc3f) eeprom 20-35 operation note while there should be no harmful side effects resulting from disabling the uc3f module while in program or erase operation, it is not recommended that program or erase operation be suspended in this manner. when disabled, the power used by the uc3f is reduced to leakage levels, see power supplies section. when not disabled, the uc3f module is enabled for accesses. like recovering from stop operation (stop = 1), there is a recovery time of one s for internal biases to recover to operating levels. 20.4.11censored accesses and non-censored accesses the uc3f eeprom has a censorship mechanism which provides for several censorship levels. the censorship mechanism is used to increase restrictions in accessing flash data. four bits in uc3fmcr are used to configure the uc3f censorship level. these bits are: access?enables a uc3f eeprom to bypass the censorship. fic?overrides censor[0:1] to force information censorship. censor[0:1]?determine the censorship level of the uc3f. the device has two relevant modes used by the uc3f eeprom to select the type of censorship. the first mode, which is uncensored mode, provides no censorship. in uncensored mode the access and censor[0:1] bits are irrelevant. the second mode, censored mode, enables the uc3f eeprom to exercise censorship based on the state of access, fic, and censor[0:1]. the device shall authenticate between uncensored mode and censored mode. in censored mode, a uc3f eeprom may disallow accesses to the array. if censored mode is entered by any means then the uc3f eeprom will exercise censorship according to the following table. . while the device remains in the uncensored mode, access may be set to allow the device to enter censored mode and still access the uc3f array. access may not be set while the device is in censored mode but may be cleared. table 20-9. levels of censorship access fic censor[0:1] 0 0 11 information censorship, no uc3f array accesses allowed. 0 0 01 or 10 no censorship, uc3f array accesses allowed. 0 0 00 cleared censorship, no uc3f array accesses allowed. 0 1 xx emulated censorship, uc3f array accesses not allowed. 1 x xx no censorship, uc3f array accesses allowed. 20-36 mpc565/mpc566 reference manual motorola operation . the only way censor[0:1] can be changed is by setting or clearing the flash nvm fuses. in the information censorship state, censor[0:1] must be cleared to the cleared censorship state before censor[0:1] can be put into the no censorship state. while clearing censor[0:1] the entire uc3f array is erased. thus the information stored in the uc3f array is made invalid while clearing censor[0:1]. 20.4.11.1 setting and clearing censor the value of each bit in censor[0:1] is determined by the state of an nvm cam cell. the nvm cam cell is not writable but instead may be set or cleared. reading censor[0:1] while setting or clearing with the high voltage applied (csc = 1 and ehv = 1) will return 0?s. table 20-10. eeprom modes and censorship status device mode censored uncensored access 0 1 0 1 fic 0 1 010101 censor[0:1] 00 01 or 10 11 00, 01 or 10 11 00, 01, 10 or 11 uc3f eeprom status #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 indicates that the uc3f array cannot be accessed. 1. access cannot be changed. fic can be set. uc3f array cannot be accessed. censor[0:1] can be set. censor[0:1] cannot be cleared. 2. access cannot be changed. fic can be set. uc3f array can be accessed. censor[0:1] can be set. censor[0:1] can be cleared. 3. access cannot be changed. fic can be set. uc3f array cannot be accessed. censor[0:1] cannot be cleared unless iws = 1. 4. access cannot be changed. fic cannot be changed. uc3f array cannot be accessed. censor[0:1] can be set. censor[0:1] cannot be cleared unless iws = 1. 5. access cannot be changed. fic cannot be changed. uc3f array cannot be accessed. censor[0:1] cannot be cleared unless iws = 1. 6. access can be cleared. fic can be set. uc3f array can be accessed. censor[0:1] can be changed. 7. access can be cleared. fic cannot be changed. uc3f array can be accessed. censor[0:1] can be changed. 8. access can be changed. fic can be set. uc3f array can be accessed. censor[0:1] can be changed. 9. access can be changed. fic cannot be changed. uc3f array can be accessed. censor[0:1] cannot be changed unless iws = 1. 10. access can be changed. fic can be set. uc3f array can be accessed. censor[0:1] can be changed. 11. access can be changed. fic cannot be changed. uc3f array can be accessed. censor[0:1] can be changed. motorola chapter 20. cdr3 flash (uc3f) eeprom 20-37 operation 20.4.11.2 setting censor the set operation changes the state in an nvm cam cell from a zero to a one. this set operation can be done without changing the contents of the uc3f array. the required sequence to set one or both of the bits in censor[0:1] follows. 1. write csc = 1, pe = 0 and ses = 1 in the uc3fctl register 2. write a 1 to the censor bit(s) to be set 3. write ehv = 1 in the uc3fctl register 4. read the uc3fctl register until hvs = 0 5. read the uc3fctl register. confirm pegood = 1 6. write ehv = 0 in the uc3fctl register 7. write ses = 0 and csc = 0 20.4.11.3 clearing censor the clear operation changes the state of the censor[0:1] bits from a one to a zero by erasing the cam cells. this clear operation can be done only while erasing the entire uc3f array and shadow information. the required sequence to clear censor follows. clear censor[0:1] 1. write protect[0:7] = 0x00 to enable the entire array for erase. if sben[m] = 1, then sbprotect[m] must also be set to 0. 2. write block[0:7] = 0xff, csc = 1, pe = 1 and ses = 1 in the uc3fctl register. if sben[m] = 1, then sbblock[m] must also be set to 1. 3. do an erase interlock write. the erase interlock write is normally defined as a write to any valid array location and is subject to any censorship conditions which might apply. when the uc3f module interface signal, iws, is maintained in a logic 1 state, a write to the uc3fmcr also serves as an erase interlock write for the clear censor operation, in addition to a write to any valid array location. when iws = 1, the censor[0:1] bits may always be cleared in the uc3f eeprom status states #3, #4, #5, #9, and #11, from the above table, in addition to those states (state #1 is already cleared) where writes to the array are valid interlock writes. when iws = 0, only a write to any valid array location serves as the erase interlock write for the clear censor operation. the erase interlock write is only valid if all blocks of the array are selected for erase and not protected. block[0:7] and sbblock[0:1] set to 1 in addition to protect[0:7] and sbprotect[0:1] set to 0 are required to validate the erase interlock write during the clear censor operation. 20-38 mpc565/mpc566 reference manual motorola operation 4.write ehv = 1 in the uc3fctl register. note the values of the epee and b0epee inputs are latched with the assertion of ehv to determine the array protection state for the clear censor operation. it is assumed that the epee and b0epee inputs are setup prior to the assertion of ehv. if epee and b0epee are not enabled for erase, the censor[0:1] bits may not be cleared. 5. read the uc3fctl register until hvs = 0. 6. read the uc3fctl register. confirm pegood = 1. 7. write ehv = 0 in the uc3fctl register. 8. write ses = 0 and csc = 0. 20.4.11.4 switching the uc3f eeprom censorship there are three levels of censorship that censor[0:1] can select. these are: cleared censorship, no censorship (two states) and information censorship. these three levels, state values, transitions and level of censorship are shown in the following diagram. motorola chapter 20. cdr3 flash (uc3f) eeprom 20-39 operation figure 20-11. censorship states and transitions censor[0:1] transitions are listed as follows: 1. cleared censorship to no censorship, t1 set censor[0] or censor[1]. 2. no censorship to information censorship, t2 set censor[0] and censor[1]. 3. information censorship, no censorship or unknown to cleared censorship, t3 clear censor[0:1]. this is done only while the entire uc3f array is erased. 4. cleared censorship to information censorship, t4 set both censor[0] and censor[1]. 20.4.12background debug mode or freeze operation while in background debug mode, the uc3f should respond normally to accesses except that lock is writable. censor[0:1] = 10 censor[0:1] = 00 t1 t2 t3 no censorship cleared censorship information censorship censor[0:1] = 11 data data data data data data data unknown t3 t4 t3 censor[0:1] = 01 20-40 mpc565/mpc566 reference manual motorola operation motorola chapter 21. calram operation 21-1 chapter 21 calram operation 21.1 definitions and acronyms calram ? the module name for the calibration ram l2u ? the module name for the l-bus to u-bus interface unit usiu / siu ? unified system integration unit / system integration unit readi ? the module name for real-time embedded application development interface (readi) biu ? bus interface unit array ? array indicates the ram array; this is sometimes used to distinguish from calram internal registers. reserved ? memory locations and register bit fields that are unimplemented. this term is used interchangeably with unimplemented register bit fields. bus access ? synonymous with bus cycle and bus transaction. refers to the sequence of events on a bus and are defined by a bus protocol. rcpu ? risc cpu msr ? machine status register is a register which defines the state of the processor. this register resides in the rcpu core. ppc register ? special-purpose register (spr) defined by the mpc500 architecture (powerpc uisa compliant). byte ? eight bits of data form a byte half-word ? 16 bits of data form a half-word word ?32 bits of data form a word calibration ? calibration tuning in engine control is a means of optimization of parameters in real time. the parameters reside in the flash. ram overlay ? during calibration mode, it is necessary to change the data within the calibration data region. the calibration data resides in the flash, which makes it very difficult to change this data in normal operation. the concept of ram overlay is that the portion(s) of calram map to calibration data regions of the flash 21-2 mpc565/mpc566 reference manual motorola definitions and acronyms address space. hence, when overlay is enabled, data for these regions are driven by the calram rather than by the flash. one-cycle ? equivalent to one clock period (1/system clock frequency) two-cycle ? equivalent to two clock periods (2/system clock frequency) freeze mode ? special mode used during debug supervisor/user ? l-bus signal indicating whether an access is a supervisor (privileged access) or user access data/instruction ? l-bus signal indicating whether data read or instruction fetch machine check/data storage interrupt ? type of exceptions that can be generated due to an access causing an error. see the rcpu reference manual (rcpurm/ad) for details. hex address ? addresses in hexadecimal numbers unless otherwise stated 21.1.1 key feature list standard ram features are listed below: one-clock accesses byte, half-word (16-bits), or word (32-bit) read/write accesses each 8-kbyte block has individual protection control bits. two-cycle access for power savings low power standby operation for data retention special overlay features are: eight overlay regions; each can be programmed to be four, 16, 32, 64, 128, 256, or 512 bytes long each overlay region size can be forced to 4 bytes long data driven from the calram module for overlay access has the same timing as the data that would have come from the u-bus flash overlay is for data read from the u-bus flash space and does not affect instruction fetches from the flash overlay block is naturally aligned ? for example, 128-byte block is 128-byte aligned normal access to overlaid portion of calram array can be made to generate an error (machine check) if so configured motorola chapter 21. calram operation 21-3 calram introduction 21.2 calram introduction the calibration static random access memory (calram) module provides the microcontroller unit (mcu) with a general purpose memory which may be read from or written to as either bytes, half-words, or words. in addition to this, a portion of the calram, called the overlay region, can be used for calibration. calibration in this context is defined as overlaying portions of the u-bus flash with a portion of the calram array. during normal flash access, the mpc500 core reads data from u-bus flash (through l-bus and l2u) as shown in figure 21-1. during calibration access, instead of flash providing the data, the overlay regions of calram provide the data to the mpc500 core. figure 21-1. system block diagram the mpc565/mpc566 chip internal memory map is shown in figure 21-2. the internal memory block can reside in one of eight possible 4-mbyte memory spaces. this 32-mbyte (8 x 4-mbyte) memory block starts at address 0x0000 0000. there is a user-programmable register (internal memory space (isb) bits in internal memory map register (immr)) to configure the internal memory map to one of the eight possible e-bus mpc500 core l-bus u-bus + fp usiu flash int. burst 32-kbytes calram int. l2u int. uimb readi jtag 4-kbyte overlay 28-kbyte sram (no overlay) 4-kbytes calram 4-kbyte overlay 21-4 mpc565/mpc566 reference manual motorola calram introduction locations. all addresses shown in this chapter are the default 4-mbyte address from 0x00 0000 to 0x3f ffff. the calram module is divided into two sections. control section: ? includes all the registers in the calram module array sub-region: ? contains memory arrays the mpc565/mpc566 contains two calram modules ? one is a 32-kbyte memory (at address 0x3f 8000 ? 0x3f ffff) and another is a 4-kbyte memory (at address 0x3f 7000 ? 0x3f 7fff) as shown in figure 21-1 and figure 21-2. in addition, each module is assigned 16 32-bit register address spaces: 12 implemented and four unimplemented registers. the 12 implemented registers are: one module configuration register (crammcr), one register reserved for factory test, eight region base address (cram_rbax) registers, one overlay configuration register (cramovlcr), and one ownership trace register (calram_otr) to support a separate module called readi. refer to chapter 23, ?readi module.? figure 21-2. mpc565/mpc566 memory map with calram address ranges 0x38 0000 0x0f ffff uc3f_a flash 512 kbytes 0x37 ffff uc3f_b flash 512 kbytes 0x07 ffff calram_a (32 kbytes a) calram_b (4 kbytes) 0x3f ffff 0x3f 7fff 0x3f 8000 0x3f 6fff 0x3f 7000 0x08 0000 0x00 0000 0x38 007f 0x38 0040 0x38 003f calram_a registers calram_b registers motorola chapter 21. calram operation 21-5 calram introduction when the normal chip power (vdd) is off, portions of the calram array can be powered by separate power supply sources (vddsram1/vddsram2) as shown in figure 21-3, thus allowing the data to be retained. 21-6 mpc565/mpc566 reference manual motorola calram introduction figure 21-3. standby power supply configuration for calram array 0x3f 7000 0x3f 8000 0x3f 9000 0x3f a000 0x3f b000 0x3f c000 0x3f d000 0x3f e000 0x3f f000 0x3f ffff ram 4k b1 ram 4k a8 ram 4k a7 ram 4k a6 ram 4k a5 ram 4k a4 ram 4k a3 ram 4k a2 ram 4k a1 vddsram2 calram_b calram_a vddsram1 vddsram2 standby ram/overlay vddsram1 standby ram/non-overlay vddsram1 standby ram/overlay motorola chapter 21. calram operation 21-7 modes of operation 21.3 modes of operation the calram module has the following modes of operation: reset one-cycle two-cycle standby stop overlay 21.3.1 reset reset configures the calram module and resets some of the bits in the calram registers to their default reset state. some register bits are unaffected by reset. see section section 21.4, ?register definitions.? 21.3.2 one-cycle mode the calram registers and array may be accessed for reads or writes as byte, (aligned) half-word, or word. this mode is the default mode of operation and, as the name suggests, the access time to the array and the internal registers for reads and writes is one cycle.thus the one-cycle mode is used for high performance although it consumes more power than the two cycle mode. 21.3.2.1 calram access/privilege violations each 8-kbyte calram array can be assigned read-only, data-only, or supervisor-only privilege if data relocate (dr) bit in the msr is set. all calram registers are assigned supervisor-only and data-only privilege. a privilege violation causes an error. see section section 21.4.1, ?calram module configuration register (crammcr).? each calram module can have up to 32 kbytes of the array. if less than 32 kbytes of the array are implemented in a calram module, attempts to access an unimplemented portion of the array causes an error. for example, if only 4 kbytes of calram_b are implemented in mpc565/mpc566, accesses to the remaining 28-kbyte region of calram_b cause an error; that is, any accesses to the array from 0x3f 0000 to 0x3f 6fff end in an error. each calram module is allocated 16 register spaces among which only twelve registers are implemented. an attempt to access any of the four unimplemented reserved registers causes an error and returns 0?s on the data bus for a read access. if an error condition occurs due to privilege violation or an attempt to access unimplemented portions of array or register space, then the type of the error generated depends on whether the access generating the error was initiated by the rcpu core or by a 21-8 mpc565/mpc566 reference manual motorola modes of operation non-rcpu bus master. if the error causing access was initiated by the rcpu core, a data storage interrupt (dsi) is generated. if the access was initiated by a non-rcpu bus master, a machine check exception is generated. also, a write access that generates an error does not corrupt the data in an array or a register. similarly, a read access that generates an error does not drive the data on the l-bus from the array or the register, instead it drives 0?s. also, aborted accesses maintain data integrity. aborted writes do not corrupt data in register/array, and aborted reads do not drive the requested data on l-bus. 21.3.3 two-cycle mode in this mode, the calram module takes two cycles to complete an access and consumes less power than in one-cycle mode. it follows the normal one-cycle mode operation except that the accesses are completed one cycle later. this mode is selected by setting the 2cy bit in the crammcr register. 21.3.4 standby operation/keep-alive power the registers and control logic for the calram module are powered by vdd . the memory array(s) is also supplied by vdd during normal operation; however, when the vdd is off, the calram array is backed up by switched sources (vddsram1 or vddsram2) that are also known as standby power. in the mpc565/mpc566, when the vdd is off, the calram arrays from 0x3f 8000 to 0x3f ffff (32 kbytes of calram module a) and from 0x3f 7000 to 0x3f 7fff (all four kbytes of calram module b) are powered by vddsram1 and vddsram2 respectively as shown in figure 21-3. 21.3.5 stop operation the low power stop mode for this module is entered by setting the disable bit (dis) in the crammcr register. reads from and writes to the array during this mode will generate an error. when the disable bit (dis) is cleared, the module returns to normal function. 21.3.6 overlay mode operation for a microcontroller used as a controller for an engine (or other electromechanical device), various parameters stored in the flash memory may need to be changed in order to properly tune (calibrate) the engine. since flash memory may not be readily programmed during normal operation of an embedded controller, portions of the calram array can be overlayed onto the u-bus flash memory. by allowing the calram module to overlay portions of flash memory, parameters normally stored in the flash may be tweaked and motorola chapter 21. calram operation 21-9 modes of operation changed (during normal operation and prior to programming a final, more precise version of the flash memory) with a development tool. the overlay is for read-only data and does not affect instruction fetches from the flash. the data for any l-bus address which falls in the overlay region of the u-bus flash will be driven by the calram on the l-bus. the calram also indicates to the l2u to block the data from the flash to be driven onto the l-bus. as far as the rcpu core is concerned, the timing of data coming from the calram appears to be the same as that from the flash. 21.3.6.1 overlay mode configuration each calram module contains eight overlay regions, each of which is 512 bytes long as shown in figure 21-4. all overlay regions of a module are contiguous and each starts at the least significant address of the region and can increment all the way up to 512 bytes as shown in figure 21-5. as described in section section 21.4.2, ?calram region base address registers (cram_rbax)?, cram_rbax registers allow the programming of the base addresses rba[11:29] of the u-bus flash regions and the rgn_size[0:4] to be overlaid. note that each region can also be individually disabled by writing 0000 to rgn_size[0:3]. if the programmed base address is not naturally aligned with respect to the rgn_size field, the least significant bits of the base address fields can be considered 0?s in order to make the starting address naturally aligned. in an rba register, rgn_size[0:3] ={0101} select the size to be 128 bytes, and even if cram_rbax [25:29] are not all 0?s, they will be considered as 0?s so that the address becomes 128-byte naturally aligned. figure 21-4. calram_a array when programming the cram_rbax registers, the calram can be put in overlay mode by setting the ovl bit in the calram overlay configuration register (cramovl) as described in section section 21.4.3, ?calram overlay configuration register 0x3f 8000 0x3f f000 0x3f f400 0x3f fc00 0x3f f800 0x3f ffff overlay 0 overlay 6 overlay 4 overlay 2 overlay 7 overlay 5 overlay 3 overlay 1 overlay region 4-kbyte 28 kbytes 21-10 mpc565/mpc566 reference manual motorola modes of operation (cramovlcr)?. for example, figure 21-5 shows that overlay regions 0, 4, and 5 have their entire region of 512 bytes mapped to regions in the flash as specified by cram_rba0, cram_rba4, and cram_rba5. overlay region 1 is partially mapped to a region in flash as specified by the cram_rba1. for example, if the region size of 256 bytes is selected for overlay region 1, then the enabled portion of the overlay region 1 occupies array from 0x3f f200 to 0x3f f2ff. the rest of overlay region 1 from 0x3f f300 to 0x3f f3ff is available for normal (non-overlay) array access. overlay regions 2, 3, 6, and 7 are disabled for overlay and hence can be used, in their entirety, for normal (non-overlay) array accesses. figure 21-5. calram_a module overlay map of flash (clps = 0) figure 21-6 illustrates the address spaces occupied by the two calram modules available in mpc565/mpc566. 0x3f 8000 0x3f f000 0x3f f400 0x3f fc00 0x3f f800 0x3f ffff overlay 6 overlay 2 overlay 7 overlay 3 overlay region 4-kbyte 0x0f ffff 0x07 ffff 0x08 0000 0x00 0000 u-bus flash 1-mbyte overlay 4 overlay 5 overla y1 cmf_a flash 512 kbytes cmf_b flash 512 kbytes 28 kbytes calram normal array access calram overlay access u-bus flash overlay 0 motorola chapter 21. calram operation 21-11 modes of operation figure 21-6. calram_b and calram_a address map (when clps = 0) if the clps bit in ovlcr register is set, then each of the eight region sizes is forced to be 4 bytes long as shown in figure 21-7,regardless of the value programmed in the rgn_size field. these 32 bytes occupy contiguous address space in calram_a, for example, from 0x3f ffe0 to 0x3f ffff. the remainder (4 kbytes ? 32 bytes) is not only available for normal array access but also contiguous with a 28-kbyte non-overlay array. 0x3f ffff 0x3f 7000 0x3f 8000 calram_a calram_b 4-kbyte overlay area 0x3f 7fff 0x3f f000 (4-kbyte overlay area) (28-kbyte non-overlay area) 4-kbyte 32-kbyte calram_a calram_b calram_a 21-12 mpc565/mpc566 reference manual motorola modes of operation figure 21-7. calram module overlay map of flash (clps = 1) figure 21-8 shows the overlay regions when the clps bit is set for both calram_a and calram_b in mpc565/mpc566. overlay 7 overlay 32 bytes overlay 0 calram array l-bus u-bus flash non-overlay calram normal array access calram overlay access u-bus flash (each = 4 eachoverlayis4byteslong (must be 4-byte aligned) (4 kbytes ? 32 bytes) available for non-overlay use 4-kbyte bytes long) block region (28 kbytes) motorola chapter 21. calram operation 21-13 modes of operation figure 21-8. calram_b and calram_a address map (when clps = 1 for both calram_a and calram_b) note the values programmed in the rbax registers are unaffected by reset. see section 21.4.2, ?calram region base address registers (cram_rbax)? for details. on reset, it is not necessary to reprogram the rabx registers. in such cases, the calibration mode can be re-entered simply by setting the ovl bit. 0x3f ffff 0x3f 7000 0x3f 8000 calram_a calram_b 32-byte overlay area 32-byte overlay area 0x3f 7fff 0x3f f000 (4kbytes?32bytes)availablefor (28-kbyte non-overlay area) 32-kbyte (0x3f ffe0 ? 0x3f ffff) non-overlay use (0x3f 7fe0 ? 0x3f 7fff) (4kbytes?32bytes)availablefor non-overlay use) calram_a 21-14 mpc565/mpc566 reference manual motorola modes of operation 21.3.6.2 priority of overlay regions when the address matches to more than one enabled portion of the overlay region, the effective region is the region with the highest priority. priority is determined by the region number; the highest priority assigned to the lowest region number. in an mcu with multiple calram modules, the highest priority is assigned to the one in lowest address space (highest address). region 0 of calram_a has the highest priority and region 7 of calram_b has the lowest priority as shown in table 21-1. also, region 7 of calram_a has higher priority than region 0 of calram_b. the benefit from this priority feature is that by storing the parameters in eight overlay regions, it overlays all eight regions onto the same 512-byte flash region, and enables the overlay feature. upon observing system performance with a set of parameters, the next set of parameters can be selected by simply disabling the highest priority region. this ?observing and disabling the highest priority region? loop can continue until all regions are disabled. this allows moving from one set of parameters to another with minimal amount of reprogramming efforts. if there are two calram modules in a chip, as in the mpc565/mpc566, then 16 sets of parameters can be run using this technique. table 21-1. priorities of overlay regions module/region number priority calram_a/region 0 highest calram_a/region 1 . calram_a/region 2 . calram_a/region 3 . calram_a/region 4 . calram_a/region 5 . calram_a/region 6 . calram_a/region 7 . calram_b/region 0 . calram_b/region 1 . calram_b/region 2 . calram_b/region 3 . calram_b/region 4 . calram_b/region 5 . calram_b/region 6 . calram_b/region 7 lowest motorola chapter 21. calram operation 21-15 register definitions 21.3.6.3 normal (non-overlay) access to overlay regions if overlay is enabled and the derr bit in the cramovlcr register is set, then any normal l-bus array access that falls within any of the eight enabled overlay regions generates a machine-check exception; otherwise the access terminates normally without asserting data error. the l-bus write accesses cause the data to be written regardless of whether the derr bit is set or not. for example, if overlay region 1 is programmed such that it is enabled and its region size is 256 bytes, then any l-bus access to address in the range of 0x3f f200 ? 0x3f f2ff generates machine check exception if the derr bit is set in cramovlcr register. the other portion of region 1 from 0x3f f300 to 0x3f f3ff can be used as normal (non-overlay) array. 21.3.6.4 calibration write cycle flow write accesses to the overlaid u-bus flash regions are ignored completely by the calram module. 21.4 register definitions the following section describes the calram programmer?s model. the calram has one register for configuring the calram array and one register dedicated to factory test. in addition, there are eight 32-bit region base address registers for calibration purposes and a 32-bit overlay configuration register. the region base address registers hold the base address for the flash region and region size that need to be overlaid by the calram. the overlay configuration register provides three bits (ovl, derr, and clsp) that are needed for overlay configuration. the calram ownership trace register (cram_otr) is provided to support a separate module called a readi module. access to all calram registers requires the bus master to be in supervisor data mode.on a privilege violation, the register is not accessed and the access generates an error. table 21-2 shows the register address map for mpc565/mpc566. table 21-2. calram a and b control registers address register calram_a 0x38 0000 crammcr_a 0x38 0004 for factory test 0x38 0008 cram_rba0_a 0x38 000c cram_rba1_a 0x38 0010 cram_rba2_a 0x38 0014 cram_rba3_a 21-16 mpc565/mpc566 reference manual motorola register definitions any unimplemented bits in calram registers return 0?s on a read and writes to these bits are ignored. 21.4.1 calram module configuration register (crammcr) the module configuration register (crammcr) contains bits that allow the calram to be configured for normal ram accesses. 0x38 0018 cram_rba4_a 0x38 001c cram_rba5_a 0x38 0020 cram_rba6_a 0x38 0024 cram_rba7_a 0x38 0028 cramovlcr_a 0x38 002c readi_otr 0x38 0030 reserved 0x38 0034 reserved 0x38 0038 reserved 0x38 003c reserved calram_b 0x38 0040 crammcr_b 0x38 0044 for factory test 0x38 0048 cram_rba0_b 0x38 004c cram_rba1_b 0x38 0050 cram_rba2_b 0x38 0054 cram_rba3_b 0x38 0058 cram_rba4_b 0x38 005c cram_rba5_b 0x38 0060 cram_rba6_b 0x38 0064 cram_rba7_b 0x38 0068 cramovlcr_b 0x38 006c cramotr_b 0x38 0070 reserved 0x38 0074 reserved 0x38 0078 reserved 0x38 007c reserved table 21-2. calram a and b control registers address register motorola chapter 21. calram operation 21-17 register definitions a brief description of each bit is provided in table 21-3 msb 0 123456789101112131415 lck dis 2cy reserved hard reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved r0 d0 s0 r1 d1 s1 r2 d2 s2 r3 d3 s3 hard reset: 0000000000000000 figure 21-9. crammcr ? calram module configuration register 0x38 0000 0x38 0040 table 21-3. crammcr bit descriptions bit(s) name description 0 lck write protection ? this bit is designed to lock out writes to the crammcr. while lck = 0 the register can be written repeatedly without restriction. if lck = 1, the register does not accept writes (i.e., the value of the register remains unchanged, but the cycle terminates normally.) in normal mode, this bit can only be set once and can only be cleared by reset. 0 writes to the crammcr are unrestricted 1 writes to the crammcr are ignored in freeze mode, only the lck bit may be written to zero if it was previously set. 1 dis array disable ? when set, this bit disables the calram array. in this mode, all reads and writes to the calram array are ignored and a bus error is generated. the calram responds to register access while dis = 1. this is a low power mode for the module, since all internal functions will be disabled. the module can be re-enabled by writing the dis bit back to a zero. reset will also re-enable the module. 0 calram module array access is enabled 1 calram module array access is disabled 2 2cy two cycle mode ? when set, this bit puts the calram into a two cycle access mode operation for calram register accesses as well as array accesses. this mode provides power savings by using the first cycle to decode any l-bus access for an address match to where the array resides. 0 calram module in one-cycle operation 1 calram module in two-cycle operation 3:19 ? reserved 21-18 mpc565/mpc566 reference manual motorola register definitions 20 r0 read-only/read-write privilege ? if the data relocate (dr) bit is set in machine status register (msrinrcpu)andr0isalsoset,thenwriteaccessesareterminatedwithanerror.ifdrbitis 0, both reads and writes to the array block is allowed regardless of the value programmed in r0. this bit controls the highest 8-kbyte block (lowest address) of calram in the associated array. likewise, r1, r2, and r3 control three other 8-kbyte blocks in the same manner. see table 21-4 for control bit address ranges. r0 = 0 and dr = 0 readable and writable (array 8-kbyte block) r0 = 0 and dr = 1 readable and writable (array 8-kbyte block) r0 = 1and dr = 0 readable and writable (array 8-kbyte block) r0 = 1 and dr = 1 read only (array 8-kbyte block) 21 d0 data-only/data-instruction privilege (data type assignment) ? if the data relocate (dr) bit is set in machine status register (msr) and d0 is also set, then any access attempting to fetch an instruction from the array block generates an error. if dr bit is 0, both data read and instruction fetch from the array block is allowed, regardless of the value programmed in d0. this bit controls the highest 8-kbyte block (lowest address) of calram in the associated array. likewise, d1, d2, and d3 control three other 8-kbyte blocks in the same manner. see table 21-4 for control bit address ranges. d0 = 0 and dr = 0 data and/or instruction (array 8-kbyte block) d0 = 0 and dr = 1 data and/or instruction (array 8-kbyte block) d0 = 1 and dr = 0 data and/or instruction (array 8-kbyte block) d0 = 1 and dr = 1 data only (array 8-kbyte block) 22 s0 supervisor-only/supervisor-user privilege (space assignment) ? if the data relocate (dr) bit is set in machine status register (msr) and s0 is also set, then any access to the array block by a user program generates an error. if dr bit is 0, both user and supervisor program can access the array block, regardless of the value programmed in s0. the calram array may be placed in supervisor or unrestricted space. this bit controls the highest 8-kbyte block (lowest address) of calram in the associated array. likewise, s1, s2, and s3 control other three blocks in the same manner.see table 21-4 for control bit address ranges. s0 = 0 and dr = 0 both user and supervisor access allowed (array 8-kbyte block) s0 = 0 and dr = 1 both user and supervisor access allowed (array 8-kbyte block) s0 = 1 and dr = 0 both user and supervisor access allowed (array 8-kbyte block) s0 = 1 and dr = 1 only supervisor access allowed (array 8-kbyte block) 23 r1 same as r0 except for address ranges shown on table 21-4. 1 24 d1 same as d0 except for address ranges shown on table 21-4. 1 25 s1 same as s0 except for address ranges shown on table 21-4. 1 26 r2 same as r0 except for address ranges shown on table 21-4 1 . 27 d2 same as d0 except for address ranges shown on table 21-4. 1 28 s2 same as s0 except for address ranges shown on table 21-4. 1 29 r3 same as r0 except for address ranges shown on table 21-4. 30 d3 same as d0 except for address ranges shown on table 21-4. 31 s3 same as s0 except for address ranges shown on table 21-4. 1 this bit has no effect in crammcr_b. table 21-3. crammcr bit descriptions (continued) bit(s) name description motorola chapter 21. calram operation 21-19 register definitions since only a 4-kbyte array is implemented in calram_b module in the mpc565/mpc566, note that r3, d3, and s3 provide the privilege bits for the array from 0x3f 7000 to 0x3f 7fff. 21.4.2 calram region base address registers (cram_rbax) the region base address register defines the base address of a region on the u-bus flash memory space that will be overlaid by a portion of the calram memory space and the region size. since eight such regions in the flash can be overlaid by the calram, eight such registers (x = 0, 1, 2, ., 7) are provided. the cram_rbax[11:29] provides the base address (starting address) of the of the u-bus flash region to be overlaid and the cram_rbax[0:3] provides size corresponding to the region. see table 21-6 for details. the rgn_size[0] is reserved and should never be programmed to a one. since mpc565/mpc566 has only one mbyte of flash, cram_rbax[11] should never be programmed to a one. also, note that if clps bit in cramovlcr is set, each of the eight sizes are forced to be four bytes, regardless of the value programmed in rgn_size[0:3] field. see section 21.4.3, ?calram overlay configuration register (cramovlcr)? for details. the implemented bits of cram_rbax bits are unaffected by reset (hard reset). the diagram below shows one such register, cram_rba0, which provides the base address of overlay region 0. table 21-4. crammcr privilege bit assignment for 8-kbyte array blocks bit selection address block (relative) r0, d0, and s0 0xxxxx 0000 ? 0xxxxx 1fff r1, d1, and s1 0xxxxx 2000 ? 0xxxxx 3fff r2, d2, and s2 0xxxxx 4000 ? 0xxxxx 5fff r3, d3, and s3 0xxxxx 6000 ? 0xxxxx 7fff 21-20 mpc565/mpc566 reference manual motorola register definitions 1. reset (hard reset) does not affect the values of these bits. note the overlay size of eight bytes cannot be selected. msb 0 123456789101112131415 rgn_size reserved rba hard reset: x 1 xxx0000000xxxxx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 rba reserved hard reset: xxxxxxxxxxxxxx00 figure 21-10. cram_rba0-7 ? calram region base address register 0x38 0008 ? 0x38 0024 0x38 0048 ? 0x38 0064 table 21-5. crammcr bit descriptions bit(s) name description 0:3 rgn_ size these bits define the size of the overlay region. see table 21-6 for sizes. 4:10 ? reserved 11:29 rba the region base address defines the starting address of the memory to be overlayed. 30:31 ? reserved table 21-6. rgn_size encoding rgn_size number of overlay bytes 0000 overlay block disabled 0001 overlay block is 4 bytes 0010 overlay block is 16 bytes 0011 overlay block is 32 bytes 0100 overlay block is 64 bytes 0101 overlay block is 128 bytes 0110 overlay block is 256 bytes 0111 overlay block is 512 bytes 1xxx reserved motorola chapter 21. calram operation 21-21 register definitions 21.4.3 calram overlay configuration register (cramovlcr) 21.4.4 calram ownership trace register (cramotr) this register is provided to support a separate module called readi. refer to chapter 23, ?readi module.? the reads from this register will return 0?s. msb 0 1 23456789101112131415 ovl derr clps reserved hard reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 reserved hard reset: 0 0 00000000000000 figure 21-11. cramovlcr ? calram overlay configuration register 0x38 0028 0x38 0068 table 21-7. cramovlcr bit descriptions bit(s) name description 0 ovl overlay enable ? when set, the calram overlay mode operation is enabled. in this mode calram allows eight programmable sections (four to 512 bytes) of the on-chip u-bus flash memory module to be overlaid by sections of the calram. 0 calram module overlay is disabled 1 calram module overlay is enabled 1 derr data error 0 calram module will not generate machine check exception due to normal l-bus array access to the enabled portion overlay region even if overlay is enabled 1 calram module will generate machine check exception due to normal l-bus array access to the enabled portion of overlay region even if overlay is enabled 2 clps collapse the total overlay region from 4 kbytes to 32 bytes; that is, the size is forced to be four bytes for each for the eight regions regardless of the values programmed in cram_rbax[0:3]; these bits are also referred to as rgn_size[0:3]. 0 overlay region of four kbytes; region size as specified by cram_rbax[0:3]. 1 overlay region of 32 bytes; each region size is four bytes long regardless of the values in cram_rbax[0:3]. 3:31 ? reserved 21-22 mpc565/mpc566 reference manual motorola register definitions note cramotr_a is also defined as readi_otr. see section 23.2.1.1, ?user mapped register.? cramotr_b is not used on the mpc565/mpc566. msb 0 123456789101112131415 ownership trace register hard reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 ownership trace register hard reset: 0000000000000000 figure 21-12. cramotr ? calram ownership trace register readi_otr 0x38 002c cramotr_b 0x38 006c motorola chapter 22. development support 22-1 chapter 22 development support the visibility and controllability requirements of emulators and bus analyzers are in opposition to the trend of modern microcomputers and microprocessors where many bus cycles are directed to internal resources and are not visible externally. in order to enhance the development tool visibility and controllability, some of the development support functions are implemented in silicon. these functions include program flow tracking, internal watchpoint, breakpoint generation, and emulation while in debug mode. this section covers program flow tracking support, breakpoint/watchpoint support, development system interface support (debug mode) and software monitor debugger support. these features allow efficiency in debugging systems based on the mpc565/mpc566. 22.1 program flow tracking the mechanism described below allows tracking of program instruction flow with almost no performance degradation. the information provided may be compressed and captured externally and then parsed by a post-processing program using the microarchitecture defined below. the program instructions flow is visible on the external bus when the mpc565/mpc566 is programmed to operate in serial mode and show all fetch cycles on the external bus. this mode is selected by programming the isct_ser (instruction fetch show cycle control) field in the i-bus support control register (ictrl), as shown in table 22-21. in this mode, the processor is fetch serialized, and all internal fetch cycles appear on the external bus. processor performance is, therefore, much lower than when working in regular mode. these features, together with the fact that most fetch cycles are performed internally (e.g., from the i-cache), increase performance but make it very difficult to provide the real program trace. in order to reconstruct a program trace, the program code and the following additional information from the mcu are needed: 22-2 mpc565/mpc566 reference manual motorola program flow tracking a description of the last fetched instruction (stall, sequential, branch not taken, branch direct taken, branch indirect taken, exception taken) the addresses of the targets of all indirect flow change. indirect flow changes include all branches using the link and count registers as the target address, all exceptions, and rfi, mtmsr and mtspr (to some registers) because they may cause a context switch. the number of instructions canceled each clock instructions are fetched sequentially until branches (direct or indirect) or exceptions appear in the program flow or some stall in execution causes the machine not to fetch the next address. instructions may be architecturally executed, or they may be canceled in some stage of the machine pipeline. the following sections define how this information is generated and how it should be used to reconstruct the program trace. the issue of data compression that could reduce the amount of memory needed by the debug system is also mentioned. 22.1.1 program trace cycle to allow visibility of the events happening in the machine a few dedicated pins are used and a special bus cycle attribute, program trace cycle, is defined. the program trace cycle attribute is attached to all fetch cycles resulting from indirect flow changes. when program trace recording is needed, make sure these cycles are visible on the external bus. the vsync indication, when asserted, forces all fetch cycles marked with the program trace cycle attribute to be visible on the external bus even if their data is found in one of the internal devices. to enable the external hardware to properly synchronize with the internal activity of the cpu, the assertion and negation of vsync forces the machine to synchronize. the first fetch after this synchronization is marked as a program trace cycle and is visible on the external bus. for more information on the activity of the external hardware during program trace refer to section 22.1.4, ?the external hardware.? in order to keep the pin count of the chip as low as possible, vsync is not implemented as one of the chip?s external pins. it is asserted and negated using the serial interface implemented in the development port. for more information on this interface refer to section 22.4, ?development port.? forcing the cpu to show all fetch cycles marked with the program trace cycle attribute can be done either by asserting the vsync pin (as mentioned above) or by programming the fetch show cycle bits in the instruction support control register, ictrl. for more information refer to section 22.1.5, ?instruction fetch show cycle control.? when the vsync indication is asserted, all fetch cycles marked with the program trace cycle attribute are made visible on the external bus. these cycles can generate regular bus motorola chapter 22. development support 22-3 program flow tracking cycles (address phase and data phase) when the instructions reside only in one of the external devices. or, they can generate address-only cycles when the instructions reside in one of the internal devices (internal memory, etc.). when vsync is asserted, some performance degradation is expected due to the additional external bus cycles. however, since this performance degradation is expected to be very small, it is possible to program the machine to show all indirect flow changes. in this way, the machine will always perform the additional external bus cycles and maintain exactly the same behavior both when vsync is asserted and when it is negated. for more information refer to section 22.6.6, ?i-bus support control register.? the status pins are divided into two groups and one special case listed below: 22.1.1.1 instruction queue status pins ? vf [0:2] instruction queue status pins denote the type of the last fetched instruction or how many instructions were flushed from the instruction queue. these status pins are used for both functions because queue flushes only happen in clocks that there is no fetch type information to be reported. possible instruction types are defined in table 22-1. table 22-2 shows vf[0:2] encodings for instruction queue flush information. table 22-1. vf pins instruction encodings vf[0:2] instruction type vf next clock will hold 000 none more instruction type information 001 sequential more instruction type information 010 branch (direct or indirect) not taken more instruction type information 011 vsync was asserted/negated and therefore the next instruction will be marked with the indirect change-of-flow attribute more instruction type information 100 exception taken ? the target will be marked with the indirect change-of-flow attribute queue flush information 1 1 unless next clock vf=111. see below. 101 branch indirect taken, rfi, mtmsr, isync and in some cases mtspr to cmpa-f, ictrl, ecr, or der ? the target will be marked with the indirect change-of-flow attribute 2 2 the sequential instructions listed here affect the machine in a manner similar to indirect branch instructions. refer to section 22.1.3, ?sequential instructions marked as indirect branch.? queue flush information 1 110 branch direct taken queue flush information 1 111 branch (direct or indirect) not taken queue flush information 1 22-4 mpc565/mpc566 reference manual motorola program flow tracking 22.1.1.2 history buffer flushes status pins? vfls [0:1] the history buffer flushes status pins denote how many instructions are flushed from the history buffer this clock due to an exception.table 22-3 shows vfls encodings. 22.1.1.3 queue flush information special case there is one special case when although queue flush information is expected on the vf pins, (according to the last value on the vf pins), regular instruction type information is reported. the only instruction type information that can appear in this case is vf = 111, branch (direct or indirect) not taken. since the maximum queue flushes possible is five, it is easy to identify this special case. 22.1.2 program trace when in debug mode when entering debug mode an interrupt/exception taken is reported on the vf pins, (vf = 100) and a cycle marked with the program trace cycle is made visible externally. when the cpu is in debug mode, the vf pins equal ?000? and the vfls pins equal ?11?. for more information on debug mode refer to section 22.3, ?development system interface.? table 22-2. vf pins queue flush encodings vf[0:2] queue flush information 000 0 instructions flushed from instruction queue 001 1 instruction flushed from instruction queue 010 2 instructions flushed from instruction queue 011 3 instructions flushed from instruction queue 100 4 instructions flushed from instruction queue 101 5 instructions flushed from instruction queue 110 reserved 111 instruction type information 1 1 refer to table 22-1. table 22-3. vfls pin encodings vfls[0:1] history buffer flush information 00 0 instructions flushed from history queue 01 1 instruction flushed from history queue 10 2 instructions flushed from history queue 11 used for debug mode indication (freeze). program trace external hardware should ignore this setting. motorola chapter 22. development support 22-5 program flow tracking if vsync is asserted/negated while the cpu is in debug mode, this information is reported as the first vf pins report when the cpu returns to regular mode. if vsync was not changed while in debug mode. the first vf pins report will be of an indirect branch taken (vf = 101), suitable for the rfi instruction that is being issued. in both cases the first instruction fetch after debug mode is marked with the program trace cycle attribute and therefore is visible externally. 22.1.3 sequential instructions marked as indirect branch there are cases when non-branch (sequential) instructions may effect the machine in a manner similar to indirect branch instructions. these instructions include rfi, mtmsr, isync and mtspr to cmpa-f, ictrl, ecr and der. these instructions are marked by the cpu as indirect branch instructions (vf = 101) and the following instruction address is marked with the same program trace cycle attribute as if it were an indirect branch target. therefore, when one of these special instructions is detected in the cpu, the address of the following instruction is visible externally. in this way the reconstructing software is able to evaluate correctly the effect of these instructions. 22.1.4 the external hardware when program trace is needed, the external hardware needs to sample the status pins (vf and vfls) each clock cycle and the address of all cycles marked with the program trace cycle attribute. program trace can be used in various ways. below are two examples of how program trace can be used: back trace ? back trace is useful when a record of the program trace before some event occurred is needed. an example of such an event is some system failure. in case back trace is needed the external hardware should start sampling the status pins (vf and vfls) and the address of all cycles marked with the program trace cycle attribute immediately when reset is negated. if show cycles is programmed out of reset to show all, all cycles marked with program trace cycle attribute are visible on the external bus. vsync should be asserted sometime after reset and negated when the programmed event occurs. if no show is programmed for show cycles, make sure vsync is asserted before the instruction show cycles programming is changed from show all. note that in case the timing of the programmed event is unknown it is possible to use cyclic buffers. after vsync is negated the trace buffer will contain the program flow trace of the program executed before the programmed event occurred. window trace ? window trace is useful when a record of the program trace between two events is needed. in case window trace is needed the vsync pin 22-6 mpc565/mpc566 reference manual motorola program flow tracking should be asserted between these two events. after the vsync pin is negated the trace buffer will contain information describing the program trace of the program executed between the two events. 22.1.4.1 synchronizing the trace window to the cpu internal events the assertion/negation of vsync is done using the serial interface implemented in the development port. in order to synchronize the assertion/negation of vsync to an internal event of the cpu, it is possible to use the internal breakpoints together with debug mode. this method is available only when debug mode is enabled. for more information on debug mode refer to section 22.3, ?development system interface.? the following is an example of steps that enable synchronization of the trace window to the cpu internal events: 1. enter debug mode, either immediately out of reset or using the debug mode request 2. program the hardware to break on the event that marks the start of the trace window using the control registers defined in section 22.2, ?watchpoints and breakpoints support? 3. enable debug mode entry for the programmed breakpoint in the debug enable register (der). see section 22.6.12, ?debug enable register (der)?) 4. return to the regular code run (see section 22.3.1.6, ?exiting debug mode?) 5. the hardware generates a breakpoint when the programmed event is detected and the machine enters debug mode (see section 22.3.1.2, ?entering debug mode?) 6. program the hardware to break on the event that marks the end of the trace window 7. assert vsync 8. return to the regular code run. the first report on the vf pins is a vsync (vf = 011). 9. the external hardware starts sampling the program trace information upon the report on the vf pins of vsync 10. the hardware generates a breakpoint when the programmed event is detected and the machine enters debug mode 11. negate vsync 12. return to the regular code run (issue an rfi). the first report on the vf pins is a vsync (vf = 011) 13. the external hardware stops sampling the program trace information upon the report on the vf pins of vsync motorola chapter 22. development support 22-7 program flow tracking 22.1.4.2 detecting the trace window start address when using back trace, latching the value of the status pins (vf and vfls), and the address of the cycles marked as program trace cycle, should start immediately after the negation of reset. the start address is the first address in the program trace cycle buffer. when using window trace, latching the value of the status pins (vf and vfls), and the address of the cycles marked as program trace cycle, should start immediately after the first vsync is reported on the vf pins. the start address of the trace window should be calculated according to first two vf pins reports. assuming that vf1 and vf2 are the two first vf pins reports and t1 and t2 are the two addresses of the first two cycles marked with the program trace cycle attribute that were latched in the trace buffer, use the following table to calculate the trace window start address. 22.1.4.3 detecting the assertion/negation of vsync since the vf pins are used for reporting both instruction type information and queue flush information, the external hardware must take special care when trying to detect the assertion/negation of vsync. when vf = 011 it is a vsync assertion/negation report only if the previous vf pins value was one of the following values: 000, 001, or 010. 22.1.4.4 detecting the trace window end address the information on the status pins that describes the last fetched instruction and the last queue/history buffer flushes, changes every clock. cycles marked as program trace cycle are generated on the external bus only when possible (when the siu wins the arbitration over the external bus). therefore, there is some delay between the information reported on the status pins that a cycle marked as program trace cycle will be performed on the external bus and the actual time that this cycle can be detected on the external bus. when vsync is negated (through the serial interface of the development port), the cpu delays the report of the of the assertion/negation of vsync on the vf pins (vf = 011) until all addresses marked with the program trace cycle attribute were visible externally. therefore, the external hardware should stop sampling the value of the status pins (vf and table 22-4. detecting the trace buffer start point vf1 vf2 starting point description 011 vsync 001 sequential t1 vsync asserted followed by a sequential instruction. the start address is t1 011 vsync 110 branch direct taken t1 - 4 + offset (t1 - 4) vsync asserted followed by a taken direct branch. the start address is the target of the direct branch 011 vsync 101 branch indirect taken t2 vsync asserted followed by a taken indirect branch. the start address is the target of the indirect branch 22-8 mpc565/mpc566 reference manual motorola watchpoints and breakpoints support vfls), and the address of the cycles marked as program trace cycle immediately after the vsync report on the vf pins. the last two instructions reported on the vf pins are not always valid. therefore at the last stage of the reconstruction software, the last two instructions should be ignored. 22.1.4.5 compress in order to store all the information generated on the pins during program trace (five bits per clock + 30 bits per show cycle) a large memory buffer may be needed. however, since this information includes events that were canceled, compression can be very effective. external hardware can be added to eliminate all canceled instructions and report only on branches (taken and not taken), indirect flow change, and the number of sequential instructions after the last flow change. 22.1.5 instruction fetch show cycle control instruction fetch show cycles are controlled by the bits in the ictrl and the state of vsync. the following table defines the level of fetch show cycles generated by the cpu. for information on the fetch show cycles control bits refer to table 22-5. note a cycle marked with the program trace cycle attribute is generated for any change in the vsync state (assertion or negation). 22.2 watchpoints and breakpoints support watchpoints, when detected, are reported to the external world on dedicated pins but do not change the timing and the flow of the machine. breakpoints, when detected, force the machine to branch to the appropriate exception handler. the cpu supports internal watchpoints, internal breakpoints, and external breakpoints. table 22-5. fetch show cycles control vsync isctl instruction fetch show cycle control bits show cycles generated x00allfetchcycles x 01 all change of flow (direct & indirect) x 10 all indirect change of flow 0 11 no show cycles are performed 1 11 all indirect change of flow motorola chapter 22. development support 22-9 watchpoints and breakpoints support internal watchpoints are generated when a user programmable set of conditions are met. internal breakpoints can be programmed to be generated either as an immediate result of the assertion of one of the internal watchpoints, or after an internal watchpoint is asserted for a user programmable times. programming a certain internal watchpoint to generate an internal breakpoint can be done either in software, by setting the corresponding software trap enable bit, or on the fly using the serial interface implemented in the development port to set the corresponding development port trap enable bit. external breakpoints can be generated by any of the peripherals of the system, including those found on the mpc565/mpc566 or externally, and also by an external development system. peripherals found on the external bus use the serial interface of the development port to assert the external breakpoint. in the cpu, as in other risc processors, saving/restoring machine state on the stack during exception handling, is done mostly in software. when the software is in the middle of saving/restoring machine state, the msrri bit is cleared. exceptions that occur and that are handled by the cpu when the msrri bit is clear result in a non-restartable machine state. for more information refer to section 3.15.4, ?exceptions.? in general, breakpoints are recognized in the cpu is only when the msrri bit is set, which guarantees machine restartability after a breakpoint. in this working mode breakpoints are said to be masked. there are cases when it is desired to enable breakpoints even when the msrri bit is clear, with the possible risk of causing a non-restartable machine state. therefore internal breakpoints have also a programmable non-masked mode, and an external development system can also choose to assert a non-maskable external breakpoint. watchpoints are not masked and therefore always reported on the external pins, regardless of the value of the msrri bit. the counters, although counting watchpoints, are part of the internal breakpoints logic and therefore are not decremented when the cpu is operating in the masked mode and the msrri bit is clear. the following figure illustrates the watchpoints and breakpoints support of the cpu. 22-10 mpc565/mpc566 reference manual motorola watchpoints and breakpoints support figure 22-1. watchpoints and breakpoint support in the cpu 22.2.1 internal watchpoints and breakpoints this section describes the internal breakpoints and watchpoints support of the cpu. for information on external breakpoints support refer to section 22.3, ?development system interface.? internal breakpoint and watchpoint support is based on eight comparators comparing information on instruction and load/store cycles, two counters, and two and-or logic structures. the comparators perform compare on the instruction address (i-address), on the load/store address (l-address) and on the load/store data (l-data). the comparators are able to detect the following conditions: equal, not equal, greater than, less than (greater than or equal and less than or equal are easily obtained from these four conditions; for more information refer to section 22.2.1.6, ?generating six compare types?). using the and-or logic structures ?in range? and ?out of range? detections (on x breakpoint non-maskable breakpoint msrri watchpoints to watchpoints pins maskable breakpoint development port trap enable bits counters (non-masked control bit) internal watchpoints logic development port lctrl2 msr software trap enable bits to cpu development system or external peripherals internal peripherals x x x bit wise and bit wise or x motorola chapter 22. development support 22-11 watchpoints and breakpoints support address and on data) are supported. using the counters, it is possible to program a breakpoint to be recognized after an event was detected a predefined number of times. the l-data comparators can operate on fix point data of load or store. when operating on fix point data the l-data comparators are able to perform compare on bytes, half-words and words and can treat numbers either as signed or as unsigned values. the comparators generate match events. the match events enter the instruction and-or logic where the instruction watchpoints and breakpoint are generated. the instruction watchpoints, when asserted, may generate the instruction breakpoint. two of them may decrement one of the counters. if one of the instruction watchpoints expires in a counter that is counting, the instruction breakpoint is asserted. the instruction watchpoints and the load/store match events (address and data) enter the load/store and-or logic where the load/store watchpoints and breakpoint are generated. the load/store watchpoints, when asserted, may generate the load/store breakpoint or they may decrement one of the counters. when a counter that is counting one of the load/store watchpoints expires, the load/store breakpoint is asserted. the readi module provides watchpoint messaging using gepdis standard (version 1.0) defined public messages. the watchpoint status signals from the rcpu are snooped, and when watchpoints occur, a message is sent to the pin output formatter to be messaged out (the general message queue is bypassed to prevent watchpoint messages from being cancelled in the event of a queue overflow). the watchpoint message has the second highest priority. refer to section 23.3.2.1, ?message priority,? for further details on message priorities. the watchpoint message contains the watchpoint code which indicates all the unique watchpoints have occurred since the last watchpoint message. if duplicate watchpoints occur before the watchpoint message is sent out, a watchpoint overrun message is generated. the watchpoint source field will indicate which watchpoints occurred. watchpoints progress in the machine and are reported on retirement. internal breakpoints progress in the machine until they reach the top of the history buffer when the machine branches to the breakpoint exception routine. in order to enable the use of the breakpoint features without adding restrictions on the software, the address of the load/store cycle that generated the load/store breakpoint is not stored in the dar (data address register), like other load/store type exceptions. in case of a load/store breakpoint, the address of the load/store cycle that generated the breakpoint is stored in an implementation-dependent register called the bar (breakpoint address register). key features of internal watchpoint and breakpoint support are: four i-address comparators (each supports equal, not equal, greater than, less than) two l-address comparators (each supports equal, not equal, greater than, less than) including least significant bits masking according to the size of the bus cycle for the 22-12 mpc565/mpc566 reference manual motorola watchpoints and breakpoints support byte and half-word working modes. refer to section 22.2.1.2, ?byte and half-word working modes.? two l-data comparators (each supports equal, not equal, greater than, less than) including byte, half-word and word operating modes and four byte mask bits for each comparator. can be used for fix point data. match is detected only on the valid part of the data bus (according to the cycle?s size and the two address least significant bits). no internal breakpoint/watchpoint matching support for unaligned words and half-words the l-data comparators can be programmed to treat fix point numbers as signed values or as unsigned values combine comparator pairs to detect in and out of range conditions (including either signed or unsigned values on the l-data) a programmable and-or logic structure between the four instruction comparators results with five outputs, four instruction watchpoints and one instruction breakpoint a programmable and-or logic structure between the four instruction watchpoints and the four load/store comparators results with three outputs, two load/store watchpoints and one load/store breakpoint five watchpoint pins, three for the instruction and two for the load/store two dedicated 16-bit down counters. each can be programmed to count either an instruction watchpoint or an load/store watchpoint. only architecturally executed events are counted, (count up is performed in case of recovery). on the fly trap enable programming of the different internal breakpoints using the serial interface of the development port (refer to section 22.4, ?development port?). software control is also available. watchpoints do not change the timing of the machine internal breakpoints and watchpoints are detected on the instruction during instruction fetch internal breakpoints and watchpoints are detected on the load/store during load/store bus cycles both instruction and load/store breakpoints and watchpoints are handled and reported on retirement. breakpoints and watchpoints on recovered instructions (as a result of exceptions, interrupts or miss prediction) are not reported and do not change the timing of the machine. instructions with instruction breakpoints are not executed. the machine branches to the breakpoint exception routine before it executes the instruction. instructions with load/store breakpoints are executed. the machine branches to the breakpoint exception routine after it executes the instruction. the address of the access is placed in the bar (breakpoint address register). motorola chapter 22. development support 22-13 watchpoints and breakpoints support load/store multiple and string instructions with load/store breakpoints first finish execution (all of it) and then the machine branches to the breakpoint exception routine. load/store data compare is done on the load/store, after swap in store accesses and before swap in load accesses (as the data appears on the bus). internal breakpoints may operate either in masked mode or in non-masked mode. both ?go to x? and ?continue? working modes are supported for the instruction breakpoints. 22.2.1.1 restrictions there are cases when the same watchpoint can be detected more than once during the execution of a single instruction, e.g. a load/store watchpoint is detected on more than one transfer when executing a load/store multiple/string or a load/store watchpoint is detected on more than one byte when working in byte mode. in all these cases only one watchpoint of the same type is reported for a single instruction. similarly, only one watchpoint of the same type can be counted in the counters for a single instruction. since watchpoint events are reported upon the retirement of the instruction that caused the event, and more than one instruction can retire from the machine in one clock, consequent events may be reported in the same clock. moreover the same event, if detected on more than one instruction (e.g., tight loops, range detection), in some cases will be reported only once. note that the internal counters count correctly in these cases. do not put a breakpoint on an mtspr ictrl instruction. when a breakpoint is set on an mtspr ictrl rx instruction and the value of bit 28 (ifm) is one, the result will be unpredictable. a breakpoint can be taken or not on the instruction and the value of the ifm bit can be either zero or one. also, do not put a breakpoint on an mtspr ictrl rx instruction when rx contains one in bit 28. 22.2.1.2 byte and half-word working modes the cpu watchpoints and breakpoints support enables detection of matches on bytes and half-words even when accessed using a load/store instruction of larger data widths, for example when loading a table of bytes using a series of load word instructions. in order to use this feature, program the byte mask for each of the l-data comparators and to write the needed match value to the correct half-word of the data comparator when working in half-word mode and to the correct bytes of the data comparator when working in byte mode. since bytes and half-words can be accessed using a larger data width instruction, it is impossible to predict the exact value of the l-address lines when the requested byte/half-word is accessed, (e.g., if the matched byte is byte two of the word and it is accessed using a load word instruction), the l-address value will be of the word (byte zero). 22-14 mpc565/mpc566 reference manual motorola watchpoints and breakpoints support therefore, the cpu masks the two least-significant bits of the l-address comparators whenever a word access is performed and the least-significant bit whenever a half-word access is performed. address range is supported only when aligned according to the access size. (see examples) 22.2.1.3 examples a fully supported scenario: ? looking for : data size: byte address: 0x00000003 data value: greater than 0x07 and less than 0x0c ? programming options : one l-address comparator = 0x00000003 and program for equal one l-data comparator = 0x00000007 and program for greater than one l-data comparator = 0x0000000c and program for less than both byte masks = 0xe both l-data comparators program to byte mode result : the event will be correctly detected regardless of the load/store instruction the compiler chooses for this access a fully supported scenario: ? looking for : data size: half-word address: greater than 0x00000000 and less than 0x0000000c data value: greater than 0x4e204e20 and less than 0x9c409c40 programming option : one l-address comparator = 0x00000000 and program for greater than one l-address comparator = 0x0000000c and program for less than one l-data comparator = 0x4e204e20 and program for greater than one l-data comparator = 0x9c409c40 and program for less than both byte masks = 0x0 both l-data comparators program to half-word mode result : the event will be correctly detected as long as the compiler does not use a load/store instruction with data size of byte. a partially supported scenario: ? looking for : data size: half-word address: greater than or equal 0x00000002 and less than 0x0000000e data value: greater than 0x4e204e20 and less than 0x9c409c40 programming option : one l-address comparator = 0x00000001 and program for greater than motorola chapter 22. development support 22-15 watchpoints and breakpoints support one l-address comparator = 0x0000000e and program for less than one l-data comparator = 0x4e204e20 and program for greater than one l-data comparator = 0x9c409c40 and program for less than both byte masks = 0x0 both l-data comparators program to half-word mode or to word mode result : the event will be correctly detected if the compiler chooses a load/store instruction with data size of half-word. if the compiler chooses load/store instructions with data size greater than half-word (word, multiple), there might be some false detections. these can be ignored only by the software that handles the breakpoints. the following figure illustrates this partially supported scenario. figure 22-2. partially supported watchpoint/breakpoint example 22.2.1.4 context dependent filter the cpu can be programmed to either recognize internal breakpoints only when the recoverable interrupt bit in the msr is set (masked mode) or it can be programmed to always recognize internal breakpoints (non-masked mode). when the cpu is programmed to recognize internal breakpoints only when msrri = 1, it is possible to debug all parts of the code except when the machine status save/restore registers (srr0 and srr1), dar (data address register) and dsisr (data storage interrupt status register) are busy and, therefore, msrri = 0, (in the prologues and epilogues of interrupt/exception handlers). when the cpu is programmed always to recognize internal breakpoints, it is possible to debug all parts of the code. however, if an internal breakpoint is recognized when msrri = 0 (srr0 and srr1 are busy), the machine enters into a non-restartable state. for more information refer to section 3.15.4, ?exceptions.? possible false detect on these half-words when using word/multiple 0x00000000 0x00000004 0x00000008 0x0000000c 0x00000010 22-16 mpc565/mpc566 reference manual motorola watchpoints and breakpoints support when working in the masked mode, all internal breakpoints detected when msrri = 0 are lost. watchpoints detected in this case are not counted by the debug counters. watchpoints detected are always reported on the external pins, regardless of the value of the msrri bit. out of reset, the cpu is in masked mode. programming the cpu to be in non-masked mode is done by setting the brknomsk bit in the lctrl2 register. refer to section 22.6.8, ?l-bus support control register 2.? the brknomsk bit controls all internal breakpoints (i-breakpoints and l-breakpoints). 22.2.1.5 ignore first match in order to facilitate the debugger utilities ?continue? and ?go from x?, the ignore first match option is supported for instruction breakpoints. when an instruction breakpoint is first enabled (as a result of the first write to the instruction support control register or as a result of the assertion of the msrri bit when operating in the masked mode), the first instruction will not cause an instruction breakpoint if the ignore first match (ifm) bit in the instruction support control register (ictrl) is set (used for ?continue?). when the ifm bit is clear, every matched instruction can cause an instruction breakpoint (used for ?go from x?). this bit is set by the software and cleared by the hardware after the first instruction breakpoint match is ignored. load/store breakpoints and all counter generated breakpoints (instruction and load/store) are not affected by this mode. 22.2.1.6 generating six compare types using the four compare types mentioned above (equal, not equal, greater than, less than) it is possible to generate also two more compare types: greater than or equal and less than or equal. generating the greater than or equal compare type can be done by using the greater than compare type and programming the comparator to the needed value minus 1. generating the less than or equal compare type can be done by using the less than compare type and programming the comparator to the needed value plus 1. this method does not work for the following boundary cases: less than or equal of the largest unsigned number (1111...1) greater than or equal of the smallest unsigned number (0000...0) less than or equal of the maximum positive number when in signed mode (0111...1) greater than or equal of the maximum negative number when in signed mode (1000...) these boundary cases need no special support because they all mean ?always true? and can be programmed using the ignore option of the load/store watchpoint programming (refer to section 22.2, ?watchpoints and breakpoints support?). motorola chapter 22. development support 22-17 watchpoints and breakpoints support 22.2.2 instruction support there are four instruction address comparators a,b,c, and d. each is 30 bits long, generating two output signals: equal and less than. these signals are used to generate one of the following four events: equal, not equal, greater than, less than. the instruction watchpoints and breakpoint are generated using these events and according to user programming. note that using the or option enables ?out of range? detect. table 22-6. instruction watchpoints programming options name description programming options iwp0 first instruction watchpoint comparator a comparators (a&b) iwp1 second instruction watchpoint comparator b comparator (a | b) iwp2 third instruction watchpoint comparator c comparators (c&d) iwp3 fourth instruction watchpoint comparator d comparator (c | d) 22-18 mpc565/mpc566 reference manual motorola watchpoints and breakpoints support figure 22-3. instruction support general structure 22.2.2.1 load/store support there are two load/store address comparators e, and f. each compares the 32 address bits and the cycle?s attributes (read/write). the two least-significant bits are masked (ignored) whenever a word is accessed and the least-significant bit is masked whenever a half-word is accessed. (for more information refer to section 22.2.1.2, ?byte and half-word working modes?). each comparator generates two output signals: equal and less than. these signals are used to generate one of the following four events (one from each comparator): equal, not equal, greater than, less than. there are two load/store data comparators (comparators g,h) each is 32 bits wide and can be programmed to treat numbers either as signed values or as unsigned values. each data comparator operates as four independent byte comparators. each byte comparator has a mask bit and generates two output signals: equal and less than, if the mask bit is not set. therefore, each 32 bit comparator has eight output signals. comparator a eq lt compare type comparator b eq lt comparator c eq lt comparator d eq lt events generator and-or logic control bits a b (a&b) (a | b) c d (c&d) (c | d) i-watchpoint 0 i-watchpoint 1 i-breakpoint i-watchpoint 2 i-watchpoint 3 compare type logic compare type logic compare type logic compare type logic motorola chapter 22. development support 22-19 watchpoints and breakpoints support these signals are used to generate the ?equal and less than? signals according to the compare size programmed (byte, half-word, word). when operating in byte mode all signals are significant, when operating in half-word mode only four signals from each 32 bit comparator are significant. when operating in word mode only two signals from each 32 bit comparator are significant. from the new ?equal and less than? signals and according to the compare type programmed one of the following four match events are generated: equal, not equal, greater than, less than. therefore, from the two 32-bit comparators eight match indications are generated: gmatch[0:3], hmatch[0:3]. according to the lower bits of the address and the size of the cycle, only match indications that were detected on bytes that have valid information are validated, the rest are negated. note that if the cycle executed has a smaller size than the compare size (e.g., a byte access when the compare size is word or half-word) no match indication will be asserted. using the match indication signals four load/store data events are generated in the following way. the four load/store data events together with the match events of the load/store address comparators and the instruction watchpoints are used to generate the load/store watchpoints and breakpoint according to the programming. table 22-7. load/store data events event name event function 1 1 ?&? denotes a logical and, ?|? denotes a logical or g (gmatch0 | gmatch1 | gmatch2 | gmatch3) h (hmatch0 | hmatch1 | hmatch2 | hmatch3) (g&h) ((gmatch0 & hmatch0) | (gmatch1 & hmatch1) | (gmatch2 & hmatch2) | (gmatch3 & hmatch3)) (g | h) ((gmatch0 | hmatch0) | (gmatch1 | hmatch1) | (gmatch2 | hmatch2) | (gmatch3 | hmatch3)) table 22-8. load/store watchpoints programming options name description instruction events programming options l-address events programming options l-data events programming options lwp0 first load/store watchpoint iwp0, iwp1, iwp2, iwp3, ignore instruction events comparator e comparator f comparators (e&f) comparators (e | f) ignore l-addr events comparator g comparator h comparators (g&h) comparators (g | h) ignore l-data events lwp1 second load/store watchpoint iwp0, iwp1, iwp2, iwp3, ignore instruction events comparator e comparator f comparators (e&f) comparators (e | f) ignore i-addr events comparator g comparator h comparators (g&h) comparators (g | h) ignore l-data events 22-20 mpc565/mpc566 reference manual motorola watchpoints and breakpoints support note that when programming the load/store watchpoints to ignore l-addr events and l-data events, it does not reduce the load/store watchpoints detection logic to be instruction watchpoint detection logic since the instruction must be a load/store instruction for the load/store watchpoint event to trigger. motorola chapter 22. development support 22-21 watchpoints and breakpoints support figure 22-4. load/store support general structure comparator g byte 0 eq lt compare size compare type byte 1 eq lt byte 2 eq lt byte 3 eq lt eq lt eq lt eq lt eq lt comparator h byte 0 eq lt byte 1 eq lt byte 2 eq lt byte 3 eq lt eq lt eq lt eq lt eq lt add(30:31) data cycle size compare size valid 0 valid 1 valid 2 valid 3 g h (g&h) (g | h) instruction watchpoints l-watchpoint 0 l-watchpoint 1 l-breakpoint size logic compare byte qualifier logic events generator and-or logic size logic byte qualifier logic control bits e f (e&f) (e | f) comparator e type logic events generator lt eq comparator f type logic lt eq compare type type logic compare type logic byte mask byte mask 22-22 mpc565/mpc566 reference manual motorola watchpoints and breakpoints support 22.2.3 watchpoint counters there are two 16-bit watchpoint counters. each counter is able to count one of the instruction watchpoints or one of the load/store watchpoints. both generate the corresponding breakpoint when they reach zero. when working in the masked mode, the counters do not count watchpoints detected when msrri = 0. see section 22.2.1.4, ?context dependent filter.? the counters value when counting watchpoints programmed on the actual instructions that alter the counters, are not predictable. reading values from the counters when they are active, must be synchronized by inserting a sync instruction before the actual read is performed. note when programmed to count instruction watchpoints, the last instruction which decrements the counter to zero is treated like any other instruction breakpoint in the sense that it is not executed and the machine branches to the breakpoint exception routine before it executes this instruction. as a side effect of this behavior, the value of the counter inside the breakpoint exception routine equals one and not zero as might be expected. when programmed to count load/store watchpoints, the last instruction which decrements the counter to zero is treated like any other load/store breakpoint in the sense that it is executed and the machine branches to the breakpoint exception routine after it executes this instruction. therefore, the value of the counter inside the breakpoint exception routine equals zero. 22.2.3.1 trap enable programming the trap enable bits can be programmed by regular software (only if msrpr = 0) using the mtspr instruction or ?on the fly? using the special development port interface. for more information refer to section section 22.4.6.5, ?development port serial communications ? trap enable mode.? the value used by the breakpoints generation logic is the bit wise or of the software trap enable bits, (the bits written using the mtspr) and the development port trap enable bits (the bits serially shifted using the development port). all bits, the software trap enable bits and the development port trap enable bits, can be read from ictrl and the lctrl2 using mfspr. for the exact bits placement refer to section 22.6.6, ?i-bus support control register? and to section 22.6.8, ?l-bus support control register 2.? motorola chapter 22. development support 22-23 development system interface 22.3 development system interface when debugging an existing system, it is sometimes desirable to be able to do so without the need to insert any changes in the existing system. in some cases it is not desired, or even impossible, to add load to the lines connected to the existing system. the development system interface of the cpu supports such a configuration. the development system interface of the cpu uses a dedicated serial port (the development port) and, therefore, does not need any of the regular system interfaces. controlling the activity of the system from the development port is done when the cpu is in the debug mode. the development port is a relatively economical interface (three pins) that allows the development system to operate in a lower frequency than the frequency of the cpu. note that it is also possible to debug the cpu using monitor debugger software, for more information refer to section 22.5, ?software monitor debugger support.? debug mode is a state where the cpu fetches all instructions from the development port. in addition, when in debug mode, data can be read from the development port and written to the development port. this allows memory and registers to be read and modified by a development tool (emulator) connected to the development port. for protection purposes, two possible working modes are defined: debug mode enable and debug mode disable. these working modes are selected only during reset. for more information refer to section 22.3.1.1, ?debug mode enable vs. debug mode disable.? the user can work in debug mode starting from reset or the cpu can be programmed to enter debug mode as a result of a predefined list of events. these events include all possible interrupts and exceptions in the cpu system, including the internal breakpoints, together with two levels of development port requests (masked and non-masked) and one peripheral breakpoint request that can be generated by any one of the peripherals of the system (including internal and external modules). each event can be programmed either to be treated as a regular interrupt that causes the machine to branch to its interrupt vector, or to be treated as a special interrupt that causes debug mode entry. when in debug mode an rfi instruction will return the machine to its regular work mode. the relationship between the debug mode logic to the rest of the cpu chip is shown in the following figure. 22-24 mpc565/mpc566 reference manual motorola development system interface figure 22-5. functional diagram of mpc565/mpc566 debug mode support the development port provides a full duplex serial interface for communications between the internal development support logic of the cpu and an external development tool. the development port can operate in two working modes: the trap enable mode and the debug mode. the trap enable mode is used in order to shift into the cpu internal development support logic the following control signals: 1. instruction trap enable bits, used for on the fly programming of the instruction breakpoint 2. load/store trap enable bits, used for on the fly programming of the load/store breakpoint 3. non-maskable breakpoint, used to assert the non-maskable external breakpoint 4. maskable breakpoint, used to assert the maskable external breakpoint 5. vsync, used to assert and negate vsync 32 development port development port 32 35 ecr der cpu core dpir dpdr 9 tecr control logic shift register dsdo vfls, frz ext bus siu/ ebi bkpt, te, vsync dsdi dsck development support logic port internal bus motorola chapter 22. development support 22-25 development system interface in debug mode the development port controls also the debug mode features of the cpu. for more information section 22.4, ?development port.? 22.3.1 debug mode support the debug mode of the cpu provides the development system with the following basic functions: gives an ability to control the execution of the processor and maintain control on it under all circumstances. the development port is able to force the cpu to enter to the debug mode even when external interrupts are disabled. it is possible to enter debug mode immediately out of reset thus allowing debugging of a rom-less system. it is possible to selectively define, using an enable register, the events that will cause the machine to enter into the debug mode. when in debug mode detect the reason upon which the machine entered debug mode by reading a cause register. entering into the debug mode in all regular cases is restartable in the sense that it is possible to continue to run the regular program from the location where it entered the debug mode. when in debug mode all instructions are fetched from the development port but load/store accesses are performed on the real system memory. data register of the development port is accessed using mtspr and mfspr instructions via special load/store cycles. (this feature together with the last one enables easy memory dump & load). upon entering debug mode, the processor gets into the privileged state (msrpr = 0). this allows execution of any instruction, and access to any storage location. an or signal of all exception cause register (ecr) bits (ecr_or) enables the development port to detect pending events while already in debug mode. an example is the ability of the development port to detect a debug mode access to a non existing memory space. the following figure illustrates the debug mode logic implemented in the cpu. 22-26 mpc565/mpc566 reference manual motorola development system interface figure 22-6. debug mode logic 5 event valid event set reset ecr_or freeze rfi decoder exception cause register debug enable register q (ecr) (der) debug mode enable internal debug mode signal motorola chapter 22. development support 22-27 development system interface 22.3.1.1 debug mode enable vs. debug mode disable for protection purposes two possible working modes are defined: debug mode enable and debug mode disable. these working modes are selected only during reset. debug mode is enabled by asserting the dsck pin during reset. the state of this pin is sampled three clocks before the negation of sreset . note since sreset negation is done by an external pull up resistor any reference here to sreset negation time refers to the time the mpc565/mpc566 releases sreset . if the actual negation is slow due to large resistor, set up time for the debug port signals should be set accordingly. if the dsck pin is sampled negated, debug mode is disabled until a subsequent reset when the dsck pin is sampled in the asserted state. when debug mode is disabled the internal watchpoint/breakpoint hardware will still be operational and may be used by a software monitor program for debugging purposes. when working in debug mode disable, all development support registers (see list in table 22-14) are accessible to the supervisor code (msrpr = 0) and can be used by a monitor debugger software. however, the processor never enters debug mode and, therefore, the exception cause register (ecr) and the debug enable register (der) are used only for asserting and negating the freeze signal. for more information on the software monitor debugger support refer to section 22.5, ?software monitor debugger support.? when working in debug mode enable, all development support registers are accessible only when the cpu is in debug mode. therefore, even supervisor code that may be still under debug cannot prevent the cpu from entering debug mode. the development system has full control of all development support features of the cpu through the development port. refer to table 22-16 22.3.1.2 entering debug mode entering debug mode can be a result of a number of events. all events have a programmable enable bit to selectively decide which events result in debug mode entry and which in regular interrupt handling. entering debug mode is also possible immediately out of reset, thus allowing the debugging of even a rom-less system. using this feature is possible by special programming of the development port during reset. if the dsck pin continues to be asserted following sreset negation (after enabling debug mode) the processor will take a breakpoint exception and go directly to debug mode instead of fetching the reset vector. to avoid entering debug mode following reset, the dsck pin must be negated no later than seven clock cycles after sreset negates. in this case, the processor will jump to the reset vector 22-28 mpc565/mpc566 reference manual motorola development system interface and begin normal execution. when entering debug mode immediately after reset, bit 31 (development port interrupt) of the exception cause register (ecr) is set. figure 22-7. debug mode reset configuration when debug mode is disabled all events result in regular interrupt handling. the internal freeze signal is asserted whenever an enabled event occurs, regardless if debug mode is enabled or disabled. the internal freeze signal is connected to all relevant internal modules. these modules can be programmed to stop all operations in response to the assertion of the freeze signal. refer to section 22.5.1, ?freeze indication.? the freeze indication is negated when exiting debug mode. refer to section 22.3.1.6, ?exiting debug mode.? the following list contains the events that can cause the cpu to enter debug mode. each event results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. the reset values of the enable bits allow, in most cases, the use of the debug mode features without the need to program the debug enable register (der). for more information refer to section 22.6.12, ?debug enable register (der).? nmi exception as a result of the assertion of the irq0_b pin. for more information refer to section 3.15.4.1, ?system reset exception and nmi (0x0100)? check stop. refer to section 22.3.1.3, ?the check stop state and debug mode? machine check exception implementation specific instruction protection error implementation specific data protection error external interrupt, recognized when msree = 1 alignment interrupt dsck out clk sreset dsck asserts high while sreset is asserted to enable debug mode operation. 012345891011121314151617 dsck asserts high following sreset negation to enable debug mode immediately. motorola chapter 22. development support 22-29 development system interface program interrupt floating point unavailable exception floating point assist exception decrementer exception, recognized when msree = 1 system call exception trace, asserted when in single trace mode or when in branch trace mode (refer to section 3.15.4.11, ?trace exception (0x0d00)) implementation dependent software emulation exception instruction breakpoint, when breakpoints are masked (brknomsk bit in the lctrl2 is clear) recognized only when msrri = 1, when breakpoints are not masked (brknomsk bit in the lctrl2 is set) always recognized load/store breakpoint, when breakpoints are masked (brknomsk bit in the lctrl2 is cleared) recognized only when msrri = 1, when breakpoints are not masked (brknomsk bit in the lctrl2 is set) always recognized peripherals breakpoint, from the development port, internal and external modules. are recognized only when msrri = 1. development port non-maskable interrupt, as a result of a debug station request. useful in some catastrophic events like an endless loop when msrri = 0. as a result of this event the machine may enter a non-restartable state, for more information refer to section 3.15.4, ?exceptions.? the processor enters into the debug mode state when at least one of the bits in the exception cause register (ecr) is set, the corresponding bit in the debug enable register (der) is enabled and debug mode is enabled. when debug mode is enabled and an enabled event occurs, the processor waits until its pipeline is empty and then starts fetching the next instructions from the development port. for information on the exact value of machine status save/restore registers (srr0 and srr1) refer to section 3.15.4, ?exceptions.? when the processor is in debug mode the freeze indication is asserted thus allowing any peripheral that is programmed to do so to stop. the fact that the cpu is in debug mode is also broadcast to the external world using the value b11 on the vfls pins. note the freeze signal can be asserted by software when debug mode is disabled. the development port should read the value of the exception cause register (ecr) in order to get the cause of the debug mode entry. reading the exception cause register (ecr) clears all its bits. 22-30 mpc565/mpc566 reference manual motorola development system interface 22.3.1.3 the check stop state and debug mode the cpu enters the check stop state if the machine check interrupt is disabled (msrme = 0) and a machine check interrupt is detected. however, if a machine check interrupt is detected when msrme = 0, debug mode is enabled and the check stop enable bit in the debug enable register (der) is set, the cpu enters debug mode rather then the check stop state. the different actions taken by the cpu when a machine check interrupt is detected are shown in the following table. 22.3.1.4 saving machine state upon entering debug mode if entering debug mode was as a result of any load/store type exception, and therefore the dar (data address register) and dsisr (data storage interrupt status register) have some significant value, these two registers must be saved before any other operation is performed. failing to save these registers may result in loss of their value in case of another load/store type exception inside the development software. since exceptions are treated differently when in debug mode (refer to section 22.3.1.5, ?running in debug mode?), there is no need to save machine status save/restore zero register (srr0) and machine status save/restore one register (srr1). 22.3.1.5 running in debug mode when running in debug mode all fetch cycles access the development port regardless of the actual address of the cycle. all load/store cycles access the real memory system according to the cycle?s address. the data register of the development port is mapped as a special control register therefore it is accessed using mtspr and mfspr instructions via special load/store cycles (refer to section 22.6.13, ?development port data register (dpdr)?). table 22-9. the check stop state and debug mode msr me debug mode enable chstpe 1 1 check stop enable bit in the debug enable register (der) mcie 2 2 machine check interrupt enable bit in the debug enable register (der) action performed by the cpu when detecting a machine check interrupt exception cause register (ecr) value 0 0 x x enter the check stop state 0x20000000 1 0 x x branch to the machine check interrupt 0x10000000 0 1 0 x enter the check stop state 0x20000000 0 1 1 x enter debug mode 0x20000000 1 1 x 0 branch to the machine check interrupt 0x10000000 1 1 x 1 enter debug mode 0x10000000 motorola chapter 22. development support 22-31 development port exceptions are treated differently when running in debug mode. when already in debug mode, upon recognition of an exception, the exception cause register (ecr) is updated according to the event that caused the exception, a special error indication (ecr_or) is asserted for one clock cycle to report to the development port that an exception occurred and execution continues in debug mode without any change in srr0 and srr1. ecr_or is asserted before the next fetch occurs to allow the development system to detect the excepting instruction. not all exceptions are recognized when in debug mode. breakpoints and watchpoints are not generated by the hardware when in debug mode (regardless of the value of msrri). upon entering debug mode msree is cleared by the hardware thus forcing the hardware to ignore external and decrementer interrupts. warning setting the msree bit while in debug mode, (by the debug software), is strictly forbidden. the reason for this restriction is that the external interrupt event is a level signal, and since the cpu only reports exceptions while in debug mode but do not treat them, the cpu does not clear the msree bit and, therefore, this event, if enabled, is recognized again every clock cycle. when the ecr_or signal is asserted the development station should investigate the exception cause register (ecr) in order to find out the event that caused the exception. since the values in srr0 and srr1 do not change if an exception is recognized while already in debug mode, they only change once when entering debug mode, saving them when entering debug mode is not necessary. 22.3.1.6 exiting debug mode the rfi instruction is used to exit from debug mode in order to return to the normal processor operation and to negate the freeze indication. the development system may monitor the freeze status to make sure the mpc565/mpc566 is out of debug mode. it is the responsibility of the software to read the exception cause register (ecr) before performing the rfi. failing to do so will force the cpu to immediately re-enter to debug mode and to re-assert the freeze indication in case an asserted bit in the interrupt cause register (ecr) has a corresponding enable bit set in the debug enable register (der). 22.4 development port the development port provides a full duplex serial interface for communications between the internal development support logic including debug mode and an external development tool. 22-32 mpc565/mpc566 reference manual motorola development port the relationship of the development support logic to the rest of the cpu chip is shown in figure 22-5. the development port support logic is shown as a separate block for clarity. it is implemented as part of the siu module. 22.4.1 development port pins the following development port pin functions are provided: 1. development serial clock (dsck) 2. development serial data in (dsdi) 3. development serial data out (dsdo) 22.4.2 development serial clock the development serial clock (dsck) is used to shift data into and out of the development port shift register. at the same time, the new most significant bit of the shift register is presented at the dsdo pin. in all further discussions references to the dsck signal imply the internal synchronized value of the clock. the dsck input must be driven either high or low at all times and not allowed to float. a typical target environment would pull this input low with a resistor. the clock may be implemented as a free running clock or as gated clock. as discussed in section section 22.4.6.5, ?development port serial communications ? trap enable mode? and section section 22.4.6.8, ?development port serial communications ? debug mode,? the shifting of data is controlled by ready and start signals so the clock does not need to be gated with the serial transmissions. the dsck pin is also used at reset to enable debug mode and immediately following reset to optionally cause immediate entry into debug mode following reset. 22.4.3 development serial data in data to be transferred into the development port shift register is presented at the development serial data in (dsdi) pin by external logic. to be sure that the correct value is used internally. when driven asynchronous (synchronous) with the system clock, the data presented to dsdi must be stable a setup time before the rising edge of dsck (clkout) and a hold time after the rising edge of dsck (clkout). the dsdi pin is also used at reset to control the overall chip configuration mode and to determine the development port clock mode. see section section 22.4.6.4, ?development port serial communications ? clock mode selection? for more information. motorola chapter 22. development support 22-33 development port 22.4.4 development serial data out the debug mode logic shifts data out of the development port shift register using the development serial data out (dsdo) pin. all transitions on dsdo are synchronous with dsck or clkout depending on the clock mode. data will be valid a setup time before the rising edge of the clock and will remain valid a hold time after the rising edge of the clock. refer to table 22-12 for dsdo data meaning. 22.4.5 freeze signal the freeze indication means that the processor is in debug mode (i.e., normal processor execution of user code is frozen). on the mpc565/mpc566, the freeze state can be indicated by three different pins. the frz signal is generated synchronously with the system clock. this indication may be used to halt any off-chip device while in debug mode as well as a handshake means between the debug tool and the debug port. the internal freeze status can also be monitored through status in the data shifted out of the debug port. 22.4.5.1 sgpio6/frz/ptr pin the sgpio6/frz/ptr pin powers up as the ptr function and its function is controlled by the gpc bits in the siumcr. 22.4.5.2 iwp[0:1]/vfls[0:1] pins the iwp[0:1]/vfls[0:1] pins power up as the vfls[0:1] function and their function can be changed via the dbgc bits in the siumcr. they can also be set via the reset configuration word (see section 7.5.2, ?hard reset configuration word?). the frz state is indicated by the value b11 on the vfls[0:1] pins. 22.4.5.3 vfls[0:1]_mpio32b[3:4] pins the vfls[0:1]_mpio32b[3:4] pins power up as the mpio32b[3:4] function and their function can be changed via the vfls bit in the mios1tpcr register. the frz state is indicated by the value b11 on the vfls[0:1] pins. 22.4.6 development port registers the development port consists logically of the three registers: development port instruction register (dpir), development port data register (dpdr), and trap enable control register (tecr). these registers are physically implemented as two registers, development port shift register and trap enable control register. the development port shift register acts as both the dpir and dpdr depending on the operation being performed. it is also used as a 22-34 mpc565/mpc566 reference manual motorola development port temporary holding register for data to be stored into the tecr. these registers are discussed below in more detail. 22.4.6.1 development port shift register the development port shift register is a 35-bit shift register. instructions and data are shifted into it serially from dsdi using dsck (or clkout depending on the debug port clock mode, refer to section 22.4.6.4, ?development port serial communications ? clock mode selection? ) as the shift clock. these instructions or data are then transferred in parallel to the cpu, the trap enable control register (tecr). when the processor enters debug mode it fetches instructions from the dpir which causes an access to the development port shift register. these instructions are serially loaded into the shift register from dsdi using dsck (or clkout) as the shift clock. in a similar way, data is transferred to the cpu by moving it into the shift register which the processor reads as the result of executing a ?move from special purpose register dpdr? instruction. data is also parallel-loaded into the development port shift register from the cpu by executing a ?move to special purpose register dpdr? instruction. it is then shifted out serially to dsdo using dsck (or clkout) as the shift clock. 22.4.6.2 trap enable control register the trap enable control register is a 9-bit register that is loaded from the development port shift register. the contents of the control register are used to drive the six trap enable signals, the two breakpoint signals, and the vsync signal to the cpu. the ?transfer data to trap enable control register? commands will cause the appropriate bits to be transferred to the control register. the trap enable control register is not accessed by the cpu, but instead supplies signals to the cpu. the trap enable bits, vsync bit, and the breakpoint bits of this register are loaded from the development port shift register as the result of trap enable mode transmissions. the trap enable bits are reflected in ictrl and lctrl2 special registers. see section 22.6.6, ?i-bus support control register? and section 22.6.8, ?l-bus support control register 2.' 22.4.6.3 development port registers decode the development port shift register is selected when the cpu accesses dpir or dpdr. accesses to these two special purpose registers occur in debug mode and appear on the internal bus as an address and the assertion of an address attribute signal indicating that a special purpose register is being accessed. the dpir register is read by the cpu to fetch all instructions when in debug mode and the dpdr register is read and written to transfer data between the cpu and external development tools. the dpir and dpdr are pseudo registers. decoding either of these registers will cause the development port shift register to be accessed. the debug mode logic knows whether the cpu is fetching instructions or motorola chapter 22. development support 22-35 development port reading or writing data. if what the cpu is expecting and what the register receives from the serial port do not match (instruction instead of data) the mismatch is used to signal a sequence error to the external development tool. 22.4.6.4 development port serial communications ? clock mode selection all of the serial transmissions are clock transmissions and are therefore synchronous communications. however, the transmission clock may be either synchronous or asynchronous with the system clock (clkout). the development port allows the selection of two methods for clocking the serial transmissions. the first method allows the transmission to occur without being externally synchronized with clkout, in this mode a serial clock dsck must be supplied to the mpc565/mpc566. the other communication method requires a data to be externally synchronized with clkout. the first clock mode is called ?asynchronous clock? since the input clock (dsck) is asynchronous with clkout. to be sure that data on dsdi is sampled correctly, transitions on dsdi must occur a setup time ahead and a hold time after the rising edge of dsck. this clock mode allows communications with the port from a development tool which does not have access to the clkout signal or where the clkout signal has been delayed or skewed. refer to the timing diagram in figure 22-8 the second clock mode is called ?synchronous self clock?. it does not require an input clock. instead the port is timed by the system clock. the dsdi input is required to meet setup and hold time requirements with respect to clkout rising edge. the data rate for this mode is always the same as the system clock. refer to the timing diagram in figure 22-9. the selection of clock or self clock mode is made at reset. the state of the dsdi input is latched eight clocks after sreset negates. if it is latched low, asynchronous clock mode is enabled. if it is latched high then synchronous self clock mode is enabled. since dsdi is used to select the development port clocking scheme, it is necessary to prevent any transitions on dsdi during this time from being recognized as the start of a serial transmission. the port will not begin scanning for the start bit of a serial transmission until 16 clocks after the negation of sreset .ifdsdiisasserted16clocksaftersreset negation, the port will wait until dsdi is negated to begin scanning for the start bit. 22-36 mpc565/mpc566 reference manual motorola development port note: dsck and dsdi transitions are not required to be synchronous with clkout. figure 22-8. asynchronous clock serial communications figure 22-9. synchronous self clock serial communication dsck dsdi mode cntrl di<0> s<0> s<1> do<0> start ready dsdo debug port drives ?ready? bit onto dsdo when ready for a new transmission. debug port detects the ?start? bit on dsdi and follows the ?ready? bit with two status bits and 7 or 32 output data bits. development tool drives the ?start? bit on dsdi (after detecting ?ready? bit on dsdo when in debug mode). the ?start? bit is immediately followed by a mode bit and a control bit and then 7 or 32 input data bits. di di di motorola chapter 22. development support 22-37 development port figure 22-10. enabling clock mode following reset 22.4.6.5 development port serial communications ? trap enable mode when in not in debug mode the development port starts communications by setting dsdo (the msb of the 35-bit development port shift register) low to indicate that all activity related to the previous transmission are complete and that a new transmission may begin. the start of a serial transmission from an external development tool to the development port is signaled by a start bit. a mode bit in the transmission defines the transmission as either a trap enable mode transmission or a debug mode transmission. if the mode bit is set the transmission will only be 10 bits long and only seven data bits will be shifted into the shift register. these seven bits will be latched into the tecr. a control bit determines whether the data is latched into the trap enable and vsync bits of the tecr or into the breakpoints bits of the tecr. 22.4.6.6 serial data into development port ? trap enable mode the development port shift register is 35 bits wide but trap enable mode transmissions only use the start/ready bit, a mode/status bit, a control/status bit, and the seven least significant data bits. the encoding of data shifted into the development port shift register (through the dsdi pin) is shown in table 22-10 and table 22-11 below: dsdi out clk sreset dsdi negates following sreset negation to enable clocked mode. clken internal clock enable signal asserts 8 clocks after sreset negation if dsdi is negated. this enables clocked mode. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 first start bit detected after dsdi negation (self clocked mode) 22-38 mpc565/mpc566 reference manual motorola development port the watchpoint trap enables and vsync functions are described in section section 22.2, ?watchpoints and breakpoints support? and section section 22.1, ?program flow tracking.? the debug port command function allows the development tool to either assert or negate breakpoint requests, reset the processor, activate or deactivate the fast down-load procedure. 22.4.6.7 serial data out of development port ? trap enable mode in trap enable mode the only response out of the development port is ?sequencing error.? data that can come out of the development port is shown in table 22-12. ?valid data from cpu? and ?cpu interrupt? status cannot occur in trap enable mode. table 22-10. trap enable data shifted into development port shift register start mode control 1st 2nd 3rd 4th 1st 2nd vsync function ------instruction------ --data-- watchpoint trap enables 1 1 0 0 = disabled; 1 = enabled transfer data to trap enable control register table 22-11. debug port command shifted into development port shift register start mode control extended opcode major opcode function 1 1 1 x x 00000 nop 00001 hard reset request 00010 soft reset request 0 x 00011 reserved 1 0 00011 end download procedure 1 1 00011 start download procedure x x 00100... 11110 reserved x 0 11111 negate maskable breakpoint. x 1 11111 assert maskable breakpoint. 0 x 11111 negate non maskable breakpoint. 1 x 11111 assert non maskable breakpoint. motorola chapter 22. development support 22-39 development port when not in debug mode the sequencing error encoding indicates that the transmission from the external development tool was a debug mode transmission. when a sequencing error occurs the development port will ignore the data shifted in while the sequencing error was shifting out. it will be treated as a nop function. finally, the null output encoding is used to indicate that the previous transmission did not have any associated errors. when not in debug mode, ready will be asserted at the end of each transmission. if debug mode is not enabled and transmission errors can be guaranteed not to occur, the status output is not needed. 22.4.6.8 development port serial communications ? debug mode when in debug mode the development port starts communications by setting dsdo low to indicate that the cpu is trying to read an instruction from dpir or data from dpdr. when the cpu writes data to the port to be shifted out the ready bit is not set. the port waits for the cpu to read the next instruction before asserting ready. this allows duplex operation of the serial port while allowing the port to control all transmissions from the external development tool. after detecting this ready status the external development tool begins the transmission to the development port with a start bit (logic high) on the dsdi pin. 22.4.6.9 serial data into development port in debug mode the 35 bits of the development port shift register are interpreted as a start/ready bit, a mode/status bit, a control/status bit, and 32 bits of data. all instructions and data for the cpu are transmitted with the mode bit cleared indicating a 32-bit data field. the encoding of data shifted into the development port shift register (through the dsdi pin) is shown below in table 22-13. table 22-12. status / data shifted out of development port shift register ready status [0:1] data function bit 0 bit 1 bits 2:31 or 2:6 ? (depending on input mode) (0) 0 0 data valid data from cpu (0) 0 1 freeze status 1 1 the ?freeze? status is set to (1) when the cpu is in debug mode and to (0) otherwise. download procedure in progress 2 2 the ?download procedure in progress? status is asserted (0) when debug port in the download procedure and is negated (1) otherwise. 1?s sequencing error (0) 1 0 1?s cpu interrupt (0) 1 1 1?s null 22-40 mpc565/mpc566 reference manual motorola development port . data values in the last two functions other than those specified are reserved. all transmissions from the debug port on dsdo begin with a ?0? or ?ready? bit. this indicates that the cpu is trying to read an instruction or data from the port. the external development tool must wait until it sees dsdo go low to begin sending the next transmission. the control bit differentiates between instructions and data and allows the development port to detect that an instruction was entered when the cpu was expecting data and vice versa. if this occurs a sequence error indication is shifted out in the next serial transmission. the trap enable function allows the development tool to transfer data to the trap enable control register. the debug port command function allows the development tool to either negate breakpoint requests, reset the processor, activate or deactivate the fast down load procedure. the nop function provides a null operation for use when there is data or a response to be shifted out of the data register and the appropriate next instruction or command will be determined by the value of the response or data shifted out. 22.4.6.10 serial data out of development port the encoding of data shifted out of the development port shift register in debug mode (through the dsdo pin) is the same as for trap enable mode and is shown in table 22-12. valid data encoding is used when data has been transferred from the cpu to the development port shift register. this is the result of an instruction to move the contents of a general purpose register to the debug port data register (dpdr). the valid data encoding table 22-13. debug instructions / data shifted into development port shift register start mode control instruction / data (32 bits) function bits 0:6 bits 7:31 1 0 0 cpu instruction transfer instruction to cpu 1 0 1 cpu data transfer data to cpu 1 1 0 trap enable 1 1 refer to table 22-10 does not exist transfer data to trap enable control register 1 1 1 0011111 does not exist negate breakpoint requests to the cpu. 1 1 1 0 does not exist nop motorola chapter 22. development support 22-41 development port has the highest priority of all status outputs and will be reported even if an interrupt occurs at the same time. since it is not possible for a sequencing error to occur and also have valid data there is no priority conflict with the sequencing error status. also, any interrupt that is recognized at the same time that there is valid data is not related to the execution of an instruction. therefore, a valid data status will be output and the interrupt status will be saved for the next transmission. the sequencing error encoding indicates that the inputs from the external development tool are not what the development port and/or the cpu was expecting. two cases could cause this error: 1. the processor was trying to read instructions and there was data shifted into the development port, or 2. the processor was trying to read data and there was instruction shifted into the development port. the port will terminate the read cycle with a bus error. this bus error will cause the cpu to signal that an interrupt (exception) occurred. since a status of sequencing error has a higher priority than exception, the port will report the sequencing error first, and the cpu interrupt on the next transmission. the development port will ignore the command, instruction, or data shifted in while the sequencing error or cpu interrupt is shifted out. the next transmission after all error status is reported to the port should be a new instruction, trap enable or command (possibly the one that was in progress when the sequencing error occurred). the interrupt-occurred encoding is used to indicate that the cpu encountered an interrupt during the execution of the previous instruction in debug mode. interrupts may occur as the result of instruction execution (such as unimplemented opcode or arithmetic error), because of a memory access fault, or from an unmasked external interrupt. when an interrupt occurs the development port will ignore the command, instruction, or data shifted in while the interrupt encoding was shifting out. the next transmission to the port should be a new instruction, trap enable or debug port command. finally, the null encoding is used to indicate that no data has been transferred from the cpu to the development port shift register. 22.4.6.11 fast download procedure the download procedure is used to download a block of data from the debug tool into system memory. this procedure can be accomplished by repeating the following sequence of transactions from the development tool to the debug port for the number of data words to be down loaded: 22-42 mpc565/mpc566 reference manual motorola development port figure 22-11. download procedure code example for large blocks of data this sequence may take significant time to complete. the ?fast download procedure? of the debug port may be used to reduce this time. this time reduction is achieved by eliminating the need to transfer the instructions in the loop to the debug port. the only transactions needed are those required to transfer the data to be placed in system memory. figure 22-12 and figure 22-13 illustrate the time benefit of the ?fast download procedure?. figure 22-12. slow download procedure loop figure 22-13. fast download procedure loop the sequence of the instructions used in the ?fast download procedure? is the one illustrated in figure 22-11 with rx = r31 and ry = r30. this sequence is repeated infinitely until the ?end download procedure? command is issued to the debug port. init: save rx, ry ry <- memory block address- 4 ? repeat: mfspr rx, dpdr data word to be moved to memory stwu rx, 0x4(ry) until here restore rx,ry external mfspr data stwu transaction internal activity external data transaction internal activity motorola chapter 22. development support 22-43 software monitor debugger support note that, the internal general purpose register 31 is used for temporary storage data value. before beginning the ?fast download procedure? by the ?start download procedure command?, the value of the first memory block address, ? 4, must be written to the general purpose register 30. to end a download procedure, an ?end download procedure? command should be issued to the debug port, and then, additional data transaction should be sent by the development tool. this data word will not be placed into the system memory, but it is needed to stop the procedure gracefully. 22.5 software monitor debugger support when in debug mode disable, a software monitor debugger can make use of all of the development support features defined in the cpu. when debug mode is disabled all events result in regular interrupt handling, i.e. the processor resumes execution in the corresponding interrupt handler. the exception cause register (ecr) and the debug enable register (der) only influence the assertion and negation of the freeze signal. 22.5.1 freeze indication the internal freeze signal is connected to all relevant internal modules. these modules can be programmed to stop all operations in response to the assertion of the freeze signal. in order to enable a software monitor debugger to broadcast the fact that the debug software is now executed, it is possible to assert and negate the internal freeze signal also when debug mode is disabled. the assertion and negation of the freeze signal when in debug mode disable is controlled by the exception cause register (ecr) and the debug enable register (der) as described in figure 22-6. in order to assert the freeze signal the software needs to program the relevant bits in the debug enable register (der). in order to negate the freeze line the software needs to read the exception cause register (ecr) in order to clear it and perform an rfi instruction. if the exception cause register (ecr) is not cleared before the rfi is performed the freeze signal is not negated. therefore it is possible to nest inside a software monitor debugger without affecting the value of the freeze line although rfi may be performed a few times. only before the last rfi the software needs to clear the exception cause register (ecr). the above mechanism enables the software to accurately control the assertion and the negation of the freeze signal. 22.6 development support registers table 22-14 lists the registers used for development support. the registers are accessed with the mtspr and mfspr instructions. 22-44 mpc565/mpc566 reference manual motorola development support registers 22.6.1 register protection table 22-15 and table 22-16 summarize protection features of development support registers during read and write accesses, respectively. table 22-14. development support programming model spr number (decimal) name 144 comparator a value register (cmpa) see table 22-17 for bit descriptions. 145 comparator b value register (cmpb) see table 22-17 for bit descriptions. 146 comparator c value register (cmpc) see table 22-17 for bit descriptions. 147 comparator d value register (cmpd) see table 22-17 for bit descriptions. 148 exception cause register (ecr) see table 22-27 for bit descriptions. 149 debug enable register (der) see table 22-28 for bit descriptions. 150 breakpoint counter a value and control register (counta) see table 22-25 for bit descriptions. 151 breakpoint counter b value and control register (countb) see table 22-26 for bit descriptions. 152 comparator e value register (cmpe) see table 22-18 for bit descriptions. 153 comparator f value register (cmpf) see table 22-18 for bit descriptions. 154 comparator g value register (cmpg) see table 22-20 for bit descriptions. 155 comparator h value register (cmph) see table 22-20 for bit descriptions. 156 l-bus support control register 1 (lctrl1) see table 22-23 for bit descriptions. 157 l-bus support control register 2 (lctrl2) see table 22-24 for bit descriptions. 158 i-bus support control register (ictrl) see table 22-21 for bit descriptions. 159 breakpoint address register (bar) see table 22-19 for bit descriptions. 630 development port data register (dpdr) see section 22.6.13, ?development port data register (dpdr)? for bit descriptions. motorola chapter 22. development support 22-45 development support registers 22.6.2 comparator a?d value registers (cmpa?cmpd) table 22-15. development support registers read access protection msr[pr] debug mode enable in debug mode result 0 0 x read is performed. ecr is cleared when read. reading dpdr yields indeterminate data. 0 1 0 read is performed. ecr is not cleared when read. reading dpdr yields indeterminate data. 0 1 1 read is performed. ecr is cleared when read. 1 x x program exception is generated. read is not performed. ecr is not cleared when read. table 22-16. development support registers write access protection msr[pr] debug mode enable in debug mode result 0 0 x write is performed. write to ecr is ignored. writing to dpdr is ignored. 0 1 0 write is not performed. writing to dpdr is ignored. 011writeisperformed. write to ecr is ignored. 1 x x write is not performed. program exception is generated. 0123456789101112131415 cmpad reset: unaffected 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 cmpad reset: unaffected figure 22-14. cmpa?cmpd ? comparator a?d value register spr 144 ? spr 147 22-46 mpc565/mpc566 reference manual motorola development support registers these registers are unaffected by reset. 22.6.3 comparator e?f value registers these registers are unaffected by reset. 22.6.4 breakpoint address register (bar) table 22-17. cmpa-cmpd bit descriptions bits mnemonic description 0:31 cmpad address bits to be compared 012345678910111213141516171819202122232425262728293031 cmpef reset: unaffected figure 22-15. cmpe?cmpf ? comparator e?f value registers spr 152, 153 table 22-18. cmpe-cmpf bit descriptions bits mnemonic description 0:31 cmpv address bits to be compared 012345678910111213141516171819202122232425262728293031 cmpef reset: unaffected figure 22-16. bar ? breakpoint address register spr 159 table 22-19. bar bit descriptions bits mnemonic description 0:31 barv[0:31] the address of the load/store cycle that generated the breakpoint motorola chapter 22. development support 22-47 development support registers 22.6.5 comparator g?h value registers (cmpg?cmph) these registers are unaffected by reset. 22.6.6 i-bus support control register note: changing the instruction show cycle programming starts to take effect only from the second instruction after the actual mtspr to ictrl. if the processor aborts a fetch of the target of a direct branch (due to an exception), the target is not always visible on the external pins. program trace is not affected by this phenomenon. 0 31 cmpgh reset: unaffected figure 22-17. cmpg?cmph ? comparator g?h value registers spr 154, 155 table 22-20. cmpg-cmph bit descriptions bits mnemonic description 0:31 cmpgh data bits to be compared 0123 4 5 6 7 8 9 10 1112131415 cta ctb ctc ctd iwp0 iwp1 reset: 0000 0 0 0 0 0 0 0 0 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 iwp2 iwp3 siwp0 en siwp1 en siwp2 en siwp3 en diwp0 en diwp1 en diwp2 en diwp3 en iifm isct_ser* reset: 0000 0 0 0 0 0 0 0 0 0000 figure 22-18. ictrl ? i-bus support control registerspr 158 table 22-21. ictrl bit descriptions bits mnemonic description function 0:2 cta compare type of comparator a 0xx not active (reset value) 100 equal 101 less than 110 greater than 111 not equal 3:5 ctb compare type of comparator b 6:8 ctc compare type of comparator c 9:11 ctd compare type of comparator d 22-48 mpc565/mpc566 reference manual motorola development support registers 12:13 iwp0 i-bus 1st watchpoint programming 0x not active (reset value) 10 match from comparator a 11 match from comparators (a&b) 14:15 w1 i-bus 2nd watchpoint programming 0x not active (reset value) 10 match from comparator b 11 match from comparators (a | b) 16:17 iwp2 i-bus 3rd watchpoint programming 0x not active (reset value) 10 match from comparator c 11 match from comparators (c&d) 18:19 iwp3 i-bus 4th watchpoint programming 0x not active (reset value) 10 match from comparator d 11 match from comparators (c | d) 20 siwp0en software trap enable selection of the 1st i-bus watchpoint 0 trap disabled (reset value) 1 trap enabled 21 siwp1en software trap enable selection of the 2nd i-bus watchpoint 22 siwp2en software trap enable selection of the 3rd i-bus watchpoint 23 siwp3en software trap enable selection of the 4th i-bus watchpoint 24 diwp0en development port trap enable selection of the 1st i-bus watchpoint (read only bit) 0 trap disabled (reset value) 1 trap enabled 25 diwp1en development port trap enable selection of the 2nd i-bus watchpoint (read only bit) 26 diwp2en development port trap enable selection of the 3rd i-bus watchpoint (read only bit) 27 diwp3en development port trap enable selection of the 4th i-bus watchpoint (read only bit) 28 iifm ignore first match, only for i-bus breakpoints 0 do not ignore first match, used for ?go to x? (reset value) 1 ignore first match (used for ?continue?) 29:31 isct_ser instruction fetch show cycle and rcpu serialize control these bits control serialization and instruction fetch show cycles. see table 22-22 for the bit definitions. note: changing the instruction show cycle programming starts to take effect only from the second instruction after the actual mtspr to ictrl. table 22-21. ictrl bit descriptions (continued) bits mnemonic description function motorola chapter 22. development support 22-49 development support registers 22.6.7 l-bus support control register 1 table 22-22. isct_ser bit descriptions serialize (ser) isctl functions selected 0 00 rcpu is fully serialized and show cycles will be performed for all fetched instructions (reset value) 1 1 in compression mode, the mpc566 can not perform a show cycles of all instructions. only changes of flow or all indirect changes of flow are supported. if the isct_ser bits are set to 0b000, the rcpu will show changes of flow only (i.e., treatitasifisct_serweresetto0b001). 0 01 rcpu is fully serialized and show cycles will be performed for all changes in the program flow 0 10 rcpu is fully serialized and show cycles will be performed for all indirect changes in the program flow 0 11 rcpu is fully serialized and no show cycles will be performed for fetched instructions 1 00 illegal. this mode should not be selected. 1 01 rcpu is not serialized (normal mode) and show cycles will be performed for all changes in the program flow 1 10 rcpu is not serialized (normal mode) and show cycles will be performed for all indirect changes in the program flow 1 11 rcpu is not serialized (normal mode) and no show cycles will be performed for fetched instructions 0123456789101112131415 cte ctf ctg cth crwe crwf reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 csg csh sus g sush cgbmsk chbmsk unused reset: 0000000000000000 figure 22-19. lctrl1 ? l-bus support control register 1 spr 156 table 22-23. lctrl1 bit descriptions bits mnemonic description function 0:2 cte compare type, comparator e 0xx not active (reset value) 100 equal 101 less than 110 greater than 111 not equal 3:5 ctf compare type, comparator f 6:8 ctg compare type, comparator g 9:11 cth compare type, comparator h 22-50 mpc565/mpc566 reference manual motorola development support registers note: lctrl1 is cleared following reset. 22.6.8 l-bus support control register 2 12:13 crwe select match on read/write of comparator e 0x don?t care (reset value) 10 matchonread 11 matchonwrite 14:15 crwf select match on read/write of comparator f 16:17 csg compare size, comparator g 00 reserved 01 word 10 half word 11 byte (must be programmed to word for floating point compares) 18:19 csh compare size, comparator h 20 susg signed/unsigned operating mode for comparator g 0unsigned 1 signed (must be programmed to signed for floating point compares) 21 sush signed/unsigned operating mode for comparator h 22:25 cgbmsk byte mask for 1st l-data comparator 0000 all bytes are not masked 0001 the last byte of the word is masked . . . 1111 all bytes are masked 26:29 chbmsk byte mask for 2nd l-data comparator 30:31 ? reserved ? 0 123 4 56789 101112131415 lw0en lw0ia lw0 iadc lw0la lw0 ladc lw0ld lw0 lddc lw1en lw1ia lw1 iadc lw1la reset: 0 000 0 00000 0 00000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lw1 ladc lw1ld lw1 lddc brk nomsk reserved dlw0 en dlw1 en slw0 en slw1 en reset: 0 000 0 00000 0 00000 figure 22-20. lctrl2 ? l-bus support control register 2spr 157 table 22-23. lctrl1 bit descriptions (continued) bits mnemonic description function motorola chapter 22. development support 22-51 development support registers table 22-24. lctrl2 bit descriptions bits mnemonic description function 0 lw0en 1st l-bus watchpoint enable bit 0 watchpoint not enabled (reset value) 1 watchpoint enabled 1:2 lw0ia 1st l-bus watchpoint i-addr watchpoint selection 00 first i-bus watchpoint 01 second i-bus watchpoint 10 third i-bus watchpoint 11 fourth i-bus watchpoint 3 lw0iadc 1st l-bus watchpoint care/don?t care i-addr events 0 don?t care 1care 4:5 lw0la 1st l-bus watchpoint l-addr events selection 00 match from comparator e 01 match from comparator f 10 match from comparators (e&f) 11 match from comparators (e | f) 6 lw0ladc 1st l-bus watchpoint care/don?t care l-addr events 0 don?t care 1care 7:8 lw0ld 1st l-bus watchpoint l-data events selection 00 match from comparator g 01 match from comparator h 10 match from comparators (g&h) 11 match from comparators (g | h) 9 lw0lddc 1st l-bus watchpoint care/don?t care l-data events 0 don?t care 1care 10 lw1en 2nd l-bus watchpoint enable bit 0 watchpoint not enabled (reset value) 1 watchpoint enabled 11:12 lw1ia 2nd l-bus watchpoint i-addr watchpoint selection 00 first i-bus watchpoint 01 second i-bus watchpoint 10 third i-bus watchpoint 11 fourth i-bus watchpoint 13 lw1iadc 2nd l-bus watchpoint care/don?t care i-addr events 0 don?t care 1care 14:15 lw1la 2nd l-bus watchpoint l-addr events selection 00 match from comparator e 01 match from comparator f 10 match from comparators (e&f) 11 match from comparators (e | f) 16 lw1ladc 2nd l-bus watchpoint care/don?t care l-addr events 0 don?t care 1care 17:18 lw1ld 2nd l-bus watchpoint l-data events selection 00 match from comparator g 01 match from comparator h 10 match from comparators (g&h) 11 match from comparator (g | h) 19 lw1lddc 2nd l-bus watchpoint care/don?t care l-data events 0 don?t care 1care 20 brknomsk internal breakpoints non-mask bit 0 masked mode; breakpoints are recognized only when msr[ri]=1 (reset value) 1 non-masked mode; breakpoints are always recognized 22-52 mpc565/mpc566 reference manual motorola development support registers note: lctrl2 is cleared following reset. for each watchpoint, three control register fields (lwxia, lwxla, lwxld) must be programmed. for a watchpoint to be asserted, all three conditions must be detected. 22.6.9 breakpoint counter a value and control register 21:27 ? reserved ? 28 dlw0en development port trap enable selection of the 1st l-bus watchpoint (read only bit) 0 trap disabled (reset value) 1 trap enabled 29 dlw1en development port trap enable selection of the 2nd l-bus watchpoint (read only bit) 30 slw0en software trap enable selection of the 1st l-bus watchpoint 31 slw1en software trap enable selection of the 2nd l-bus watchpoint 0123456789101112131415 cntv reset: unaffected 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved cntc reset: 0000000000000000 figure 22-21. counta ? breakpoint counter a value and control register spr 150 table 22-24. lctrl2 bit descriptions (continued) bits mnemonic description function motorola chapter 22. development support 22-53 development support registers note: counta[16:31] are cleared following reset; counta[0:15] are unaffected by reset. 22.6.10breakpoint counter b value and control register note: countb[16:31] are cleared following reset; countb[0:15] are unaffected by reset. 22.6.11exception cause register (ecr) the ecr indicates the cause of entry into debug mode. all bits are set by the hardware and cleared when the register is read when debug mode is disabled, or if the processor is in debug mode. attempts to write to this register are ignored. when the hardware sets a bit in table 22-25. breakpoint counter a value and control register (counta) bit(s) name description 0:15 cntv counter preset value 16:29 ? reserved 30:31 cntc counter source select 00 not active (reset value) 01 i-bus first watchpoint 10 l-bus first watchpoint 11 reserved 0123456789101112131415 cntv reset: unaffected 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved cntc reset: 0000000000000000 figure 22-22. countb ? breakpoint counter b value and control register spr 151 table 22-26. breakpoint counter b value and control register (countb) bit(s) name description 0:15 cntv counter preset value 16:29 ? reserved 30:31 cntc counter source select 00 not active (reset value) 01 i-bus second watchpoint 10 l-bus second watchpoint 11 reserved 22-54 mpc565/mpc566 reference manual motorola development support registers this register, debug mode is entered only if debug mode is enabled and the corresponding mask bit in the der is set. all bits are cleared to zero following reset. 01 2 3 4 5 678 9 1011121314 15 0 rst chstp mce reserved exti ale pre fpuve dece reserved syse tr fpase reset: 00 0 0 0 0 000 0 0000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 see reser ved itlber rese rved dtlb er reserved lbrk ibrk ebrkd dpi reset: 00 0 0 0 0 000 0 0000 0 0 figure 22-23. ecr ? exception cause register spr 148 table 22-27. ecr bit descriptions bit(s) name description 0?reserved 1 rst reset interrupt bit. this bit is set when the system reset pin is asserted. 2 chstp checkstop bit. set when the processor enters checkstop state. 3 mce machine check interrupt bit. set when a machine check exception (other than one caused by a data storage or instruction storage error) is asserted. 4:5 ? reserved 6 exti external interrupt bit. set when the external interrupt is asserted. 7 ale alignment exception bit. set when the alignment exception is asserted. 8 pre program exception bit. set when the program exception is asserted. 9 fpuve floating point unavailable exception bit. set when the program exception is asserted. 10 dece decrementer exception bit. set when the decrementer exception is asserted. 11:12 ? reserved 13 syse system call exception bit. set when the system call exception is asserted. 14 tr trace exception bit. set when in single-step mode or when in branch trace mode. 15 fpase floating point assist exception bit. set when the floating point assist exception occurs. 16 ? reserved 17 see software emulation exception. set when the software emulation exception is asserted. 18 ? reserved 19 itlber implementation specific instruction protection error this bit is set as a result of an instruction protection error. results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. motorola chapter 22. development support 22-55 development support registers 22.6.12debug enable register (der) this register enables selectively masking the events that may cause the processor to enter into debug mode. 20 ? reserved 21 dtlber implementation specific data protection error this bit is set as a result of an data protection error. results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. 22:27 ? reserved 28 lbrk l-bus breakpoint exception bit. this bit is set as a result of the assertion of a load/store breakpoint. results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. 29 ibrk i-bus breakpoint exception bit. this bit is set as a result of the assertion of an instruction breakpoint. results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. 30 ebrk external breakpoint exception bit. set when an external breakpoint is asserted (by an on-chip imb or l-bus module, or by an external device or development system through the development port). this bit is set as a result of the assertion of an external breakpoint. results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. 31 dpi development port interrupt bit. set by the development port as a result of a debug station non-maskable request or when debug mode is entered immediately out of reset. 012 3 456789 101112131415 0 rste chst pe mcee reserved ext ie alee pr ee fpuv ee decee reserved sys ee tre fpa se reset: 001 0000000 0 00010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rese rved seee rese rved itlbe re rese rved dtlb ere reserved lbr ke ibr ke ebrk e dpie reset: 000 0000000 0 01111 figure 22-24. der ? debug enable register spr 149 table 22-27. ecr bit descriptions (continued) bit(s) name description 22-56 mpc565/mpc566 reference manual motorola development support registers table 22-28. der bit descriptions bit(s) name description 0:1 ? reserved 1 rste reset enable 0 debug entry is disabled (reset value) 1 debug entry is enabled 2 chstpe checkstop enable bit 0 debug mode entry disabled 1 debug mode entry enabled (reset value) 3 mcee machine check exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 4:5 ? reserved 6 extie external interrupt enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 7 alee alignment exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 8 pree program exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 9 fpuvee floating point unavailable exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 10 decee decrementer exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 11:12 ? reserved 13 sysee system call exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 14 tre trace exception enable bit 0 debug mode entry disabled 1 debug mode entry enabled (reset value) 15 fpasee floating point assist exception enable bit. 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 16 ? reserved 17 seee software emulation exception enable bit 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 18 ? reserved motorola chapter 22. development support 22-57 development support registers 22.6.13development port data register (dpdr) this 32-bit special purpose register physically resides in the development port logic. it is used for data interchange between the core and the development system. an access to this register is initiated using mtspr and mfspr (spr 630) and implemented using a special bus cycle on the internal bus. 19 itlbere implementation specific instruction protection error enable bit. 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 20 ? reserved 21 dtlbere implementation specific data protection error enable bit. 0 debug mode entry disabled (reset value) 1 debug mode entry enabled 22:27 ? reserved 28 lbrke load/store breakpoint enable bit. 0 debug mode entry disabled 1 debug mode entry enabled (reset value) 29 ibrke instruction breakpoint interrupt enable bit. 0 debug mode entry disabled 1 debug mode entry enabled (reset value) 30 ebrke external breakpoint interrupt enable bit (development port, internal or external modules). 0 debug mode entry disabled 1 debug mode entry enabled (reset value) 31 dpie development port interrupt enable bit 0 debug mode entry disabled 1 debug mode entry enabled (reset value) table 22-28. der bit descriptions (continued) bit(s) name description 22-58 mpc565/mpc566 reference manual motorola development support registers motorola chapter 23. readi module 23-1 chapter 23 readi module 23.1 overview the readi module provides real-time development capabilities for rcpu-based mcus in compliance with the ieee-isto 5001-1999. this module provides development support capabilities for mcus in single chip mode, without requiring address and data pins for internal visibility. the auxiliary port, along with rcpu development features (such as background debug mode and watchpoints) supports all software and hardware development in single chip mode. the auxiliary port, along with (on-chip) calibration ram, allows calibration variable acquisition and calibration constant tuning in single chip mode, for automotive powertrain development systems. note in this section the bit numbering in the register definitions of tool mapped registers follows the nexus ieee-isto 5001 - 1999 bit numbering convention of msb = bit 31 and lsb = bit 0, unlike the mpc500 standard msb = bit 0 and lsb = bit 31. the bit description tables list the bit numbering and nexus bit numbering. 23.1.1 general description the readi module interfaces to the rcpu processor and internal buses to provide development support as per the ieee-isto 5001-1999. the development features supported are program trace, data trace, watchpoint trace, ownership trace, run-time access to the mcu?s internal memory map, and access to rcpu internal registers during halt, via the auxiliary port. 23-2 mpc565/mpc566 reference manual motorola overview 23.1.2 feature summary list the readi module is compliant with class 3 of the ieee-isto 5001-1999. the following features are implemented: program trace via branch trace messaging (btm). branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions etc.), allowing the development tool to interpolate what transpires between the discontinuities. thus static code may be traced. data trace via data write messaging (dwm) and data read messaging (drm). this provides the capability for the development tool to trace reads and/or writes to (selected) internal memory resources. data trace also allows for calibration variable acquisition in automotive powertrain development systems. ? two data trace windows with programmable address range and access attributes. data trace windowing reduces the requirements on the auxiliary port bandwidth by constraining the number of trace locations. ownership trace via ownership trace messaging (otm). otm facilitates ownership trace by providing visibility of which process id or operating system task is activated. an ownership trace message is transmitted to indicate when a new process/task is activated, allowing development tools to trace process/task flow. run-time access to on-chip memory map and mpc500 special purpose registers (sprs) via the readi read/write access protocol. this feature supports accesses for runtime internal visibility, calibration constant acquisition and tuning, and external rapid prototyping for powertrain automotive development systems. watchpoint messaging via the auxiliary port nine or 16 full-duplex auxiliary pin interface for medium and high visibility throughput ? one of two modes selected during reset: full port mode (fpm) and reduced port mode (rpm). ? fpm comprises 16 pins and rpm comprises nine pins ? auxiliary output port ? one mcko (message clock out) pin ? two or eight mdo (message data out) pins ?onemseo (message start/end out) pin ? auxiliary input port ?onemcki (message clock in) pin ? one or two mdi (message data in) pins ?onemsei (message start/end in) pin ?oneevti (event in) pin ?onersti (reset in) pin motorola chapter 23. readi module 23-3 overview all features configurable and controllable via the auxiliary port security features for production environment support of existing rcpu development access protocol via the auxiliary port readi module can be reset independent of system reset parametrics: ? two bits are downloaded per clock in full port mode. for example, with input clock running at 28 mhz, this translates to a download rate of 56 mbits/s. ? one bit is downloaded per clock in reduced port mode. for example, with input clock running at 28 mhz, this translates to a download rate of 28 mbits/s. ? eight bits are uploaded per clock in full port mode. for example, with system clock running at 56 mhz, this translates to a upload rate of 448 mbits/s. ? two bits are uploaded per clock in reduced port mode. for example, with system clock running at 56 mhz, this translates to a upload rate of 112 mbits/s. 23.1.3 functional block diagram the functional block diagram of the readi module is shown in figure 23-1. 23-4 mpc565/mpc566 reference manual motorola overview figure 23-1. readi functional block diagram 23.1.4 modes of operation the various operating modes of the readi module are: 1. reset 2. secure 3. normal 4. disabled u-bus snoop l-bus snoop l-bus master data trace encoding program encoding trace r/w access control registers message queues mdo[0:1] brkpt_out l-bus mcko watchpoint capture security pin interface message out formatter message in formatter mdi[0] or mcki rcpu evti rsti ownership rcpu development access usiu l-bus snoop l-bus l-bus trace encoding pin interface u-bus usiu mseo msei or mdo[0:7] mdo[0:1] motorola chapter 23. readi module 23-5 overview 23.1.4.1 readi reset configuration the readi reset configuration information is received via evti and mdi[0] to enable or disable the readi module, and select the port size. evti and mdi[0] are sampled synchronously at the negation of rsti . reset configuration information must be valid on evti and mdi[0] at least four clocks prior to the negation of rsti . the following table describes the readi reset configuration options. if evti is asserted at negation of rsti , the readi module will be enabled. the readi module will three-state the auxiliary output port when rsti is asserted. 23.1.4.2 security security is provided via the uc3f censorship mechanism. if a uc3f array is in censored mode, reads or writes to the uc3f will not be allowed (rcpu will not be able to fetch instructions from the uc3f) once any of the following cases are detected: program trace and/or data trace are enabled read/write access is attempted (can be to any address location) rcpu development access is enabled. 23.1.4.3 disabled if evti is negated at negation of rsti , the readi module will be disabled. no trace output will be provided, and output auxiliary port will be three-stated. any message sent by the tool is ignored. 23.1.5 parametrics with 16 message queues, throughput numbers were calculated for the following benchmark codes [assuming full port mode]: for an example benchmark which had 10.9% direct branches, 2.5% indirect branches, 10.4% data writes, and 19.3% data reads, approximately 20% of total data trace accesses will be traced. table 23-1. readi reset configuration options evti mdi [0] configuration 1 x module disabled. all outputs three-stated. 0 1 module enabled, full port configuration 2 mdi, 8 mdo 0 0 module enabled, reduced port configuration 1 mdi, 2 mdo 23-6 mpc565/mpc566 reference manual motorola overview for another example benchmark which had 9.8% direct branches, 2.8% indirect branches, 6.6% data writes, and 18.3% data reads, approximately 27% of total data trace accesses will be traced. for reduced port mode, the data trace feature should not be used, or used sparingly, so as not to cause queue overruns. 23.1.6 programmer?s model the readi registers do not follow the recommendations of the ieee-isto 5001 - 1999, but are loosely based on the 0.9 release of the standard. see http://www.nexus5001.org/. readi registers are classified into two categories: user mapped register and tool mapped registers. user mapped register (memory mapped register): ownership trace register tool mapped registers (registers which can be accessed only through the development tool and are not memory mapped): device id register development control register user base address register read/write access register upload/download information register data trace attributes register 1 data trace attributes register 2 23.1.7 messages the readi module implements messaging via the auxiliary port according to the ieee-isto 5001 - 1999. messaging will be implemented via transfer codes (tcodes) on the auxiliary port. the tcode number for the message identifies the transfer format (the number and/or size of packets to be transferred) and the purpose of each packet. public messages outlined in table 23-2 are supported by readi. . table 23-2. public messages tcode number message name 1 device id. refer to section 23.2.1.3, ?device id (did) register.? 2 ownership trace message. refer to section 23.9.1, ?ownership trace messaging.? motorola chapter 23. readi module 23-7 overview vendor-defined messages outlined in table 23-3 are also supported by readi. 3 program trace ? direct branch message. refer to section 23.4.3.1, ?direct branch messages.? 4 program trace ? indirect branch message. refer to section 23.4.3.2, ?indirect branch messages.? 5 data trace ? data write message. refer to section 23.5.2.1, ?data write message.? 6 data trace ? data read message. refer to section 23.5.2.2, ?data read message.? 8 error message. refer to table 23-20. 10 (0x0a) program trace correction. refer to section 23.4.3.3, ?program trace correction message.? 11 (0x0b program trace ? direct branch synchronization message. refer to section 23.4.3.6, ?direct branch synchronization message.? 12 (0x0c) program trace ? indirect branch synchronization message. refer to section 23.4.3.7, ?indirect branch synchronization message.? 13 (0x0d) data trace ? data write synchronization message. refer to section 23.5.2.4, ?data write synchronization message.? 14 (0x0e) data trace ? data read synchronization message. refer to section 23.5.2.5, ?data read synchronization messaging.? 15 (0x0f) watchpoint message. refer to section 23.8.1, ?watchpoint messaging.? 16 (0x10) auxiliary access ? device ready for upload/download message. refer to section 23.2.2, ?accessing memory mapped locations via the auxiliary port.? 17 (0x11) auxiliary access ? upload request (tool requests information) message. refer to section 23.2.3, ?accessing readi tool mapped registers via the auxiliary port.? 18 (0x12) auxiliary access ? download request (tool provides information) message. refer to section 23.2.2, ?accessing memory mapped locations via the auxiliary port.? 19 (0x13) auxiliary access ? upload/download information (device/tool provides information) message. refer to section 23.2.3, ?accessing readi tool mapped registers via the auxiliary port.? table 23-3. vendor-defined messages tcode number message name 56 (0x38) rcpu development access ? dsdi data (tool provides information) message 57 (0x39) rcpu development access ? dsdo data (device provides information) message 58 (0x3a) rcpu development access ? bdm status (device provides information) message 59 (0x3b) program trace ? indirect branch message with compressed code 60 (0x3c) program trace ? direct branch synchronization message with compressed code 61 (0x3d) program trace ? indirect branch synchronization message with compressed code table 23-2. public messages (continued) tcode number message name 23-8 mpc565/mpc566 reference manual motorola overview 23.1.8 terms and definitions table 23-4. terms and definitions term description auxiliary port refers to ieee-isto 5001 auxiliary port. branch trace messaging (btm) external visibility of addresses for taken branches and exceptions, and the number of sequential instructions executed between each taken branch. bdm background debug mode. compressed code mode current instruction stream is fetching compressed code. calibration constants performance related constants which must be tuned for automotive powertrain and disk drive applications. calibration variables intermediate calculations which must be visible during the calibration or tuning process to enable accurate tuning of calibration constants. data read message (drm) external visibility of data reads to internal memory-mapped resources. data write message (dwm) external visibility of data writes to internal memory-mapped resources. data trace messaging (dtm) external visibility of how data flows through the embedded system. may include drm and/or dwm. download tool sends information to the device field number of bits representing single piece of information fpm full port mode. this is the default port mode for readi. ieee-isto 5001 ieee-isto 5001, formerly known as global embedded processor debug interface standard. worldwide web documentation at http://www.nexus5001.org/. halt rcpu is in freeze state (typically in debug mode) instruction fetch the process of reading the instruction data received from the instruction memory. instruction issue the process of driving valid instruction bits inside the processor. the instruction is decoded by each execution unit, and the appropriate execution unit prepares to execute the instruction during the next clock cycle. instruction taken an instruction is taken after it has been issued and recognized by the appropriate execution unit. all resources to perform the instruction are ready, and the processor begins to execute it. instruction retire completion of the instruction issue, execution and writeback stages. an instruction is ready to be retired if it completes without generating an exception and all instructions ahead of it in history buffer have completed without generating an exception. ictrl instruction bus support control register. ownership trace message (otm) visibility of process/function that is currently executing. public messages messages on the auxiliary pins for accomplishing common visibility and controllability requirements e.g. drm and dwm. rcpu processor that implements the powerpc-based architecture used in the motorola mpc500 family of microcontrollers. readi real time embedded applications development interface. motorola chapter 23. readi module 23-9 programming model 23.2 programming model this section describes the readi programmer?s model. readi resources can only be configured and accessed via the auxiliary port. the readi registers do not follow the recommendations of the ieee-isto 5001-1999, but are loosely based on the 0.9 release of the standard. 23.2.1 register map readi registers are accessible via the auxiliary port. they can be classified into two categories: user mapped registers and tool mapped registers. 23.2.1.1 user mapped register the operating system writes the id for the current task/process in the otr register. table 23-5 shows the location of the register bits. their functions are explained below. readi pins refers to ieee-isto 5001 auxiliary port. rpm reduced port mode. this is the alternate port mode for readi. run-time rcpu is executing program code in normal mode sequential instruction any instruction other than a flow-control instruction or isync. snooping monitoring addresses driven by a bus master to detect the need for coherency actions. standard the phrase ?according to the standard? implies according the ieee-isto 5001 - 1999. superfield one or more message ?fields? delimited by mseo /msei assertion/negation. the information transmitted between ?start-message? and ?end-packet? states. show cycle an internal access (e.g., to an internal memory) reflected on the external bus using a special cycle (marked with a dedicated transfer code). for an internal memory ?hit,? an address-only bus cycle is generated; for an internal memory ?miss,? a complete bus cycle is generated. transfer code (tcode) message header that identifies the number and/or size of packets to be transferred, and how to interpret each of the packets. tck_dsck multiplexed pin: jtag clock or development port clock. tdi_dsdi multiplexed pin: jtag data in or development port serial data in. tdo_dsdo multiplexed pin: jtag data out or development port serial data out. upload device sends information to the tool. vsync internal rcpu signal vf internal rcpu signal which indicates instruction queue status. vfls internal rcpu signal which indicates history buffer flush status. table 23-4. terms and definitions (continued) term description 23-10 mpc565/mpc566 reference manual motorola programming model the current task/process (ctp) field is updated by the operating system software to provide task/process id information. the ot register can only be accessed by supervisor data attributes. only cpu writes to this register will be transmitted out. this register is not accessible via the auxiliary port download request message. 23.2.1.2 tool mapped registers table 23-6 defines readi registers which are not memory mapped and can only be accessed through the development tool. their corresponding access opcodes are also defined. . msb 0 123456789101112131415 current task process (ctp) hard reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 lsb 31 current task process (ctp) hard reset: 0000000000000000 figure 23-2. readi_otr ? readi ownership trace register0x38 002c table 23-5. readi_otr bit descriptions bit(s) name description 0:31 ctp readi ownership trace register, write only. table 23-6. tool mapped register space access opcode register access type 8 (0x08) device id register (did) read only 10 (0x0a) development control register (dc) read/write 13 (0x0d) user base address register (uba) read only 15 (0x0f) read/write access register (rwa) read/write 16 (0x10) upload/download information register (udi) read/write 20 (0x14) data trace attributes register 1 (dta1) read/write 21 (0x15) data trace attributes register 2 (dta2) read/write motorola chapter 23. readi module 23-11 programming model 23.2.1.3 device id (did) register accessing the did register provides key attributes to the development tool concerning the mcu. this information is also transmitted via the auxiliary output port upon exit of readi reset (rsti ), if evti is asserted at rsti negation. table 23-7 gives the bit descriptions. 23.2.1.4 development control (dc) register the dc register is used for basic development control of the readi module. table 23-8 shows the location of register bits. msb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rev mdc pn hreset: ???? 0 0 0 010000011 151413121110987654321lsb 0 pn mid rese rved hreset: 0011000000111001 figure 23-3. readi_did ? readi device id register0x08 table 23-7. readi_did bit descriptions rcpu bit(s) nexus bit(s) name description 0:3 31:28 rev readi version number. this field contains the revision level of the device. 4:9 27:22 mdc 1 1 the ieee-isto 5001-1999 defines these two fields as a single combined field. readi manufacturer design center. this field identifies the manufacturer?s design center. the mpc565 has a value of 0x02. 10:19 21:12 pn 1 readi part number. this part number identification field. the mpc565 is 0x033. 20:30 11:1 mid readi manufacturer id. this field identifies the manufacturer of the device, motorola?s id is 0x1c. 31 0 ? reserved msb 7 654321lsb 0 dor dme dpa tm ec hard reset: 00000000 figure 23-4. readi_dc ? readi development control (dc) register0x0a 23-12 mpc565/mpc566 reference manual motorola programming model 23.2.1.5 rcpu development access modes table 23-9 describes the allowed modes for rcpu development access. table 23-8. readi_dc bit descriptions rcpu bit(s) nexus bit(s) name description 07dor 1 1 the dor, dme, and dpa fields in the dc register can only be modified when system reset is asserted, or reset (to default state) when the readi module is reset by the assertion of rsti . readi debug mode entry out-of-reset field can be configured to enable or disable debug mode entry out of reset. 0 debug mode not entered out-of-reset 1 debug mode entered out-of-reset 16dme 1 readi debug mode enable field can be configured to enable or disable debug mode. 0 debug mode disabled 1 debug mode enabled 25dpa 1 readi rcpu development access field can be configured to access the rcpu developmentfeaturesviathereadimoduleorviathedebugpins(tck_dsck, tdi_dsdi and tdo_dsdo). the default dpa setting configures the rcpu development features to be accessed via debug pins. 0 rcpu development access disabled through readi, bdm pins enabled 1 rcpu development access enabled through readi 3:5 4:2 tm readi trace mode field can be configured to enable btm, dtm and otm. any or all types of trace may be enabled. 000 no trace 1xx btm branch trace messaging enabled x1x dtm data trace messaging enabled xx1 otm ownership trace messaging enabled 6:7 1:0 ec readi evti control field can be configured for synchronization and breakpoint generation. if the ec is equal to 0b00, asserting evti will cause the next program and data trace message to be a synchronization message (providing program and data trace are enabled). if the ec field is equal to 0b01, a breakpoint will be generated. if the field is configured to one of the reserved states, its action reverts to that of the default state. note: the evti pin is level sensitive when ec is configured for breakpoint generation. this implies that as long as evti assertion is continued (with ec set to 0b01), the readi module will continue requesting a breakpoint. the user must detect breakpoint generation and negate the evti pin appropriately. 00 evti for program and data trace synchronization 01 evti for breakpoint generation 1x no action table 23-9. rcpu development access modes dor dme dpa rcpu development access through readi x x 0 no rcpu development access via readi. rcpu access is done through bdm pins. x 0 1 non-debug mode access of rcpu development through readi. motorola chapter 23. readi module 23-13 programming model 23.2.1.6 user base address (uba) register the uba register defines the memory map address for the ot register. table 23-10 gives a description of the register bits. 23.2.1.7 read/write access (rwa) register the rwa register provides dma-like access to memory mapped locations, mpc500 special purpose registers, and readi tool mapped registers. table 23-11 shows the location of register bits. 0 1 1 debug mode is enabled through readi (rcpu is still in normal mode, out of reset) 1 1 1 debug mode is enabled through readi and entered out-of-reset. debug mode entry causes rcpu to halt. msb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 uba hard reset: 0000000000111000 151413121110987654321lsb 0 uba hard reset: 0000000000101100 figure 23-5. readi_uba ? readi user base address register 0x0d table 23-10. readi_uba bit descriptions rcpu bit(s) nexus bit(s) name description 0:31 31:0 uba the user base address (uba) field defines the memory map address for the ot register. the mpc565 user base address is 0x38002c. the uba register is read-only by the development tool. table 23-9. rcpu development access modes (continued) dor dme dpa rcpu development access through readi 23-14 mpc565/mpc566 reference manual motorola programming model msb 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 sc rwad hard reset: 0000000000000000 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 rwad rw sz wd hard reset: 0000000000000000 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 wd hard reset: 0000000000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wd prv map hard reset: 0000000000000000 151413121110987654321lsb 0 cnt hard reset: 0000000000000000 figure 23-6. readi_rwa ? readi read/write access register0x0f table 23-11. readi_rwa read/write access bit descriptions rcpu bit(s) nexus bit(s) name description 0 79 sc the start complete (sc) field is set when a read or write access is initiated. the device will clear the sc bit once the read or write access completes. during a block access, if the sc bit is reset, the access will terminate. 0 access complete 1 start access 1:25 78:54 rwad read/write address (rwad) bits are used to identify the address of internal memory-mapped resources to be accessed, or the lowest address (i.e., lowest unsigned value) for a block move (cnt > 0). the address range for a block move is from rwad to rwad + cnt. note: the rwd field of the udi register is shared with the wd field of the rwa register. motorola chapter 23. readi module 23-15 programming model 23.2.1.8 upload/download information (udi) register the udi register is used to store the data to be written for block write access, and the data read for read (single and block) accesses. table 23-12 gives a description of the register bits. 26 53 rw the read/write (rw) field can be configured to allow selection of a read or a write access. 0readaccess 1 write access 27:28 52:51 sz the word size (sz) field can be configured to allow 32-bit, 16-bit, or 8-bit read/write accesses. if the field is configured to one of the reserved states, its action reverts to that of the default state. 00 32-bit 01 16-bit 10 8-bit 11 reserved 29:60 50:19 wd write data (wd) bits contain the data to be written. for a read access, the data stored is a don?t care. 61:62 18:17 prv the privilege attribute field can be configured to select different read/write access attributes. 00 user data 01 user instruction 10 supervisor data 11 supervisor instruction 63 16 map the map select field can be configured to allow access to multiple memory maps. the primary processor memory map (map equal to 0b0) is designated as the default. the secondary memory map (map equal to 0b1) can be set to select the mpc500 special purpose registers. 0 primary memory map 1 secondary memory map (ppc special purpose registers) 64:79 15:0 cnt the access count field can be configured to indicate the number of accesses of word size (defined in sz field). the cnt value is used to increment the specified address in the rwad field for block read/write accesses. for a single read/write access, the cnt value should equal to 0x0000. a 64-kbyte block read/write access can be performed by configuring the cnt bits as 0xffff. if a user wants to terminate a block read or write access which has not completed, the cnt bits should be reset. table 23-11. readi_rwa read/write access bit descriptions (continued) rcpu bit(s) nexus bit(s) name description 23-16 mpc565/mpc566 reference manual motorola programming model msb 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 rwd hard reset: 0000000000000000 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lsb 0 rwd err dv hard reset: 0000000000000000 figure 23-7. readi_udi ? readi upload/download information register0x10 table 23-12. readi_udi bit descriptions rcpu bit(s) nexus bit(s) name description 0:31 33:2 rwd the read/write data field is used to store data for read accesses and block write accesses. it can contain three sizes of data. refer to table 23-13, table 23-14 and table 23-8 for details. 32 1 err the error field is used to determine the status of the read or write access. refer to table 23-13 and table 23-14 for details. 0 read or write access has not been completed. 1 read or write access has completed. note: the err field is read-only. 33 0 dv the data valid field is used to determine the status of the read or write access. refer to table 23-13 and table 23-14 for details. 0 no error has occurred. 1 access error occurred. note: the dv field is read-only. table 23-13. read access status err dv status 0 0 read access has not yet completed 0 1 read access has completed and no access error occurred 1 0 access error occurred 1 1 not allowed table 23-14. write access status err dv status 0 0 write access has completed and no access error occurred 1 0 write access error occurred (error message sent out) 0 1 write access has not yet completed 1 1 not allowed motorola chapter 23. readi module 23-17 programming model . note the rwd field of the udi register is shared with the wd field of the rwa register. 23.2.1.9 data trace attributes 1 and 2 (dta1 and dta2) registers the dta1 and dta2 registers allow data trace messaging (dtm) to be restricted to reads, writes or both for a user programmable address range. two dta registers allow two address ranges to be selected for dtm. refer to table 23-15 for register bit descriptions. lsb 8 bit reserved ? read as zeros ls byte err dv 16 bit reserved ? read as zeros ms byte ls byte err dv 32 bit ms byte ls byte err dv figure 23-8. rwd field configuration msb 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dtea hard reset: 0000000000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dtea dtsa hard reset: 0000000000000000 151413121110987654321lsb 0 dtsa ta hard reset: 0000000000000000 figure 23-9. readi_dta 1 ? readi data trace attributes 1 register 0x14 readi_dta 2 ? readi data trace attributes 2 register 0x15 23-18 mpc565/mpc566 reference manual motorola programming model note there is no way to distinguish between off-core mpc500 special purpose register (spr) map and normal memory map accesses via the defined address range control. if data trace ranges are set up such that the off-core mpc500 spr map falls within active ranges, then accesses to these off-core mpc500 sprs will be traced, and the messages will not be distinguishable from accesses to normal memory map space. off-core mpc500 sprs typically exist in the 8- to 16-kbyte lowest memory block (0x2000 ? 0x3ff0). if data or peripherals are mapped to this space, load/stores to mpc500 sprs will be indistinguishable from data or peripheral accesses. 23.2.2 accessing memory mapped locations via the auxiliary port the control and status information is accessed via the four auxiliary access public messages: device ready for upload/download, upload request (tool requests information), download request (tool provides information), and upload/download information (device/tool provides information). table 23-15. readi_dta 1 and 2 bit descriptions rcpu bit(s) nexus bit(s) name description 0:22 47:25 dtea 1 1 data trace range start and end addresses must be word-aligned. the read/write end field defines the end address for the address range. refer to table 23-16. 23:45 24:2 dtsa 1 the read/write start field defines the starting address for the address range. refer to table 23-16. 46:47 1:0 ta the read/write trace field can be configured to allow enabling or disabling data read and/or data write traces. 00 disable data read and data write trace x1 enable data read trace 1x enable data write trace table 23-16. data trace values programmed values range motorola chapter 23. readi module 23-19 programming model to write control or status to memory mapped locations the following sequence would be required. 1. the tool confirms that the device is ready (so as to not cancel an ongoing read write access). the tool transmits the download request public message (tcode 18) which contains write attributes, write data, and target address. 2. the tool waits for device ready for upload/download (tcode 16) message before initiating next access. to read control or status from memory mapped locations the following sequence would be required. 1. the tool confirms that the device is ready. the tool transmits the download request public message (tcode 18) which contains read attributes and target address. 2. when device reads data it transmits upload/download information message (tcode 19) containing read data. device is now ready for next access. for a block write to memory mapped locations the following sequence would be required. 1. the tool confirms that the device is ready. the tool transmits the download request public message (tcode 18) which contains block write attributes, first write data, and target address. 2. the tool waits for device ready for upload/download message (tcode 16). when it is transmitted by device, tool transmits upload/download information message (tcode 19) containing next write data. this step is repeated until all data is written for a block read from memory mapped locations the following sequence would be required. 1. the tool confirms that the device is ready. the tool transmits the download request public message (tcode 18) which contains block read attributes and target address. 2. the tool waits for upload/download information message (tcode 19) from device, which contains read data. this step is repeated until all data is read. refer to section 23.6, ?read/write access,? for more details on read/write access protocol. 23.2.3 accessing readi tool mapped registers via the auxiliary port to write control or status data to readi tool mapped registers the following sequence would be required. 1. the tool confirms that the device is ready. the tool transmits the download request message (tcode 18) which contains write data, and register opcode. 23-20 mpc565/mpc566 reference manual motorola programming model 2. the tool waits for device ready for upload/download message (tcode 16) before initiating next access. to read control or status from readi tool mapped registers the following sequence would be required 1. the tool confirms that the device is ready. the tool transmits the upload request message (tcode 17) which contains the target opcode. 2. when device reads data it transmits upload/download information message (tcode 19) containing read data. device is now ready for next access. refer to section 23.6, ?read/write access,? for more details on read/write access protocol. 23.2.4 partial register updates registers may be updated via the auxiliary port using the download request message with the message containing only n (where n is less than register width) most-significant bits of the register. in such cases the bits not transmitted will be reset to 0b0. the bits transmitted will be aligned such that the last bit transmitted will be the most significant bit of the register. therefore a message size that is divisible by the input port size should be transmitted. 23.2.5 programming considerations the following programing guidelines are recommended for users of the readi features. 23.2.5.1 program trace guidelines program trace via btm is not supported during bdm. for program trace synchronization to work, the ictrl (refer to table 23-20) register must be programmed such that show cycle will be performed for all changes in the program flow (isctl field = 0b01). note the user must program the ictrl for change of flow show cycles early in the reset vector, before any branches, otherwise trace is not guaranteed. if bdm is enabled, the ictrl register cannot be modified through the program and can only be modified through rcpu development access. it is also recommended that the usiu be programmed to ignore instruction show cycles (so as to not impact u-bus performance). see section 6.14.1.1, ?siu module configuration register (siumcr).? motorola chapter 23. readi module 23-21 programming model to correctly trace program execution using btm, the readi module must be enabled prior to release of system reset. if the readi module is enabled (evti asserted, rsti negated) after the rcpu has started execution of the program, the trace cannot be guaranteed. refer to figure 23-10 for further details. 23.2.5.2 compressed code mode guidelines the ictrl register must be programmed such that a show cycle will be performed for all changes in the program flow (isctl field = 0b01). (see table 22-21.) the bbc must be enabled to display data on instruction show cycles. bbcmcr[decomp_sc_en] (refer to section 4.7.2.1, ?bbc module configuration register bbcmcr?) must be set when decompression is enabled. this will allow readi to track the compressed code. bbcmcr[decomp_sc_en] should not be set if there is no intention to use compressed code, as it will degrade u-bus performance. 23-22 mpc565/mpc566 reference manual motorola programming model figure 23-10. enabling program trace out of system reset 23.2.5.3 reset sequence guidelines refer to section 23.3.3, ?readi reset configuration,? for further details. hreset rsti msei mdi mseo mdo (tool drives) (tool drives) evti (tool drives) 1 evti must be asserted 4 system clocks prior to the readi module. did message dc message 2 device sends out did message after 3 tool sends in dc message with desired program trace mode enabled. (bdmcanalsobeenabledthrough. after receiving device ready message. the device will start executing the reset instruction sequence user program. in this user program, if background debug mode (bdm) is enabled, the ictrl register cannot be modified through user program. this register can only be accessed through the development port. 4 dc register configuration. see the note below) note: settheisctlfield=0b01inthe ictrl register. also the usiu should be programmed to ignore instruction showcycles to avoid impacting u-bus performance. negation of rsti to enable after the hreset negation, tool negates hreset 16 clocks negation of rsti device ready tcode=1 tcode=16 tcode=18 motorola chapter 23. readi module 23-23 pin interface 23.2.5.4 bdm guidelines refer to section 23.3.3.1, ?reset configuration for debug mode,? for further details. 23.3 pin interface this section details information regarding the readi pins and pin protocol. 23.3.1 functional description the readi pin interface provides the function of transmitting messages from the message queues to the external tools. the pin interface also provides the control for timing and logic for formatting the messages. 23.3.1.1 pins implemented the readi module implements one mcko, mcki, evti ,rsti ,mseo and msei pin. it also implements 1 or 2 mdi and 2 or 8 mdo pins. the input pins are synchronized to mcki input clock and the output pins are synchronized to free running mcko output clock.the readi pin definition is outlined in table 23-17. note mcki clock frequency has to be less than or equal to one half of mcko clock frequency. table 23-17. description of readi pins ieee-isto 5001 pin name input/ output description of pin mcko output message clock-out (mcko) is a free-running output clock to development tools for timing of mdo and mseo pin functions. mcko is the same as the mcu system clock. mdo[7:0] or mdo[1:0] output message data out (mdo[7:0] or mdo[1:0]) are output pins used for uploading otm, btm, dtm, and read/write accesses. external latching of mdo will occur on rising edge of mcko. eight pins are implemented. mdo[7:0] are used in full port mode, mdo[1:0] are used in reduced port mode. mseo output message start/end out (mseo ) is an output pin which indicates when a message on the mdo pins has started, when a variable length packet has ended, and when the message has ended. 1 mseo pin is implemented. external latching of mseo will occur on rising edge of mcko. mcki input message clock-in (mcki) is a input clock from development tools for timing of mdi and msei pin functions. mcki frequency has to be less than or equal to one half of mcko frequency. 23-24 mpc565/mpc566 reference manual motorola pin interface 23.3.2 functional block diagram figure 23-11 depicts the functional block diagram of the pin interface. . figure 23-11. functional diagram of pin interface mdi[1:0] or mdi[0] input message data in (mdi[1:0] or mdi[0]) are input pins used for downloading configuration information, writes to user resources, etc. internal latching of mdi will occur on rising edge of mcki. 2 pins are implemented on the mpc565. mdi[1:0] are used in full port mode, mdi[0] only is used in reduced port mode. mse i input message start/end in (msei ) is an input pin which indicates when a message on the mdi pins has started, when a variable length packet has ended, and when the message has ended. 1 msei pin is implemented. internal latching of msei will occur on rising edge of mcki. evti input event in (evti ) ? the evti pin is level sensitive when configured for breakpoint generation, otherwise it is edge sensitive. rsti input reset in (rsti ). table 23-17. description of readi pins (continued) ieee-isto 5001 pin name input/ output description of pin control unit pin interface trace messages from queue data to readi registers output formatter input formatter mdo[7:0] mdi[1:0] mcko mseo msei mcki rsti evti mux buf buf auxiliary messages watchpoint message rcpu dev. port message data control invalid message r/w access message motorola chapter 23. readi module 23-25 pin interface the pin interface is responsible for handshaking with the message queue and registers. it is also responsible for requesting new messages from the message queue. a message is always requested from the message queue if the message queue is not empty, the message buffer is available and a higher priority message is not requesting to be transmitted. the rate at which data is removed from the queue depends on the average message length, the number of mdo pins, and the mcko clocking rate. 23.3.2.1 message priority message formatting is performed in the pin interface block. the following priority scheme is implemented for messages sent to the pin output formatter block, with 1 being the highest priority and 5 being the lowest priority: 1. invalid message 2. readi register access handshakes (device ready/download information) 3. watchpoint messages 4. read/write access message 5. rcpu development access message 6. queued messages (program trace, data trace, and ownership trace) 23.3.2.2 pin protocol the protocol for the mcu receiving and transmitting messages via the auxiliary pins will be accomplished with the msei and mseo pin functions respectively. the msei pin will provide the protocol for the mcu receiving messages, and the mseo pin will provide the protocol for the mcu transmitting messages. the msei /mseo protocol is illustrated in table 23-18. msei /mseo are used to signal the end of variable-length packets and messages. they are not required to indicate end of fixed length packets. msei /mseo are sampled on the rising edge of mcki and mcko respectively. table 23-18. msei /mseo protocol operation mseo /msei state idle ?1?s at all clocks start two ?1?s followed by one ?0? active ?0?s at all clocks during transmission of a message end of variable length packet ?0? followed by ?1? end of packet and message ?0? followed by two or more ?1?s 23-26 mpc565/mpc566 reference manual motorola pin interface fixed width fields can be concatenated before variable length fields without regard to the individual fields starting or ending at message n bit boundaries. variable width fields must end at message n bit boundaries (where n is mdi/mdo pins). figure 23-12 shows the basic relation between the mdo and mseo pins, and packet structure. mdo and mseo are sampled on the rising edge of mcko. figure 23-12. auxiliary pin packet structure for program trace indirect branch message figure 23-13 illustrates the state diagram for msei /mseo transfers. tcode = 4 number of sequential instructions since last taken branch = 4 relative address = 0x534 don?t care data (idle clock) mcko mseo mdo[7:0] 00000100 00000001 00110100 00000101 00000000 motorola chapter 23. readi module 23-27 pin interface figure 23-13. msei /mseo transfers note in the ?end message? state, data on the mdi/mdo pins is ignored. 23.3.2.3 messages public messages outlined in table 23-2 are supported by readi. table 23-19. public messages supported message name minimum packet size (bits) maximum packet size (bits) packet type packet description direction device id 6 6 fixed tcode number = 1 from device 32 32 fixed device id information ownership trace message 6 6 fixed tcode number = 2 from device 32 32 fixed task/process id tag idle start message normal transfer end message mse =1 mse =1 mse =0 mse =0 mse =1 mse =1 mse =0 mse =0 mse =0 mse =1 mdi/o: ignored mdi/o: ignored end packet mse represents msei /mseo mdi/o represents mdo/mdi mdi/o: valid mdi/o: valid mdi/o: valid readi reset 23-28 mpc565/mpc566 reference manual motorola pin interface program trace ? direct branch message 6 6 fixed tcode number = 3 from device 1 8 variable number of sequential instructions executed since last taken branch program trace ? indirect branch message 6 6 fixed tcode number = 4 from device 1 8 variable number of sequential instructions executed since last taken branch 1 23 variable unique portion of the target address for taken branches and exceptions data trace ? data write message 6 6 fixed tcode number = 5 from device 1 25 variable unique portion of the data write address 8 32 variable data write value (8, 16, 32 bits) data trace ? data read message 6 6 fixed tcode number = 6 from device 1 25 variable unique portion of the data read address 8 32 variable data read value (8, 16, 32 bits) error message 1 6 6 fixed tcode number = 8 from device 5 5 fixed error code program trace correction message 6 6 fixed tcode number = 10 (0xa) from device 1 8 variable correcting the number of instructions in the trace program trace ? direct branch synchronization message 6 6 fixed tcode number = 11 (0xb) from device 1 1 variable number of program trace messages cancelled 1 23 variable full target address program trace ? indirect branch synchronization message 6 6 fixed tcode number = 12 (0xc) from device 1 1 variable number of program trace messages cancelled 1 23 variable full target address data trace ? data write synchronization message 6 6 fixed tcode number = 13 (0xd) from device 1 1 variable number of messages canceled 1 25 variable full target address 8 32 variable data write value (8, 16, 32 bits) table 23-19. public messages supported (continued) message name minimum packet size (bits) maximum packet size (bits) packet type packet description direction motorola chapter 23. readi module 23-29 pin interface data trace ? data read synchronization message 6 6 fixed tcode number = 14 (0xe) from device 1 1 variable number of messages canceled 1 25 variable full target address 8 32 variable data read value (8, 16, 32 bits) watchpoint message 6 6 fixed tcode number = 15 (0xf) from device 6 6 fixed number indicating watchpoint source auxiliary access ? device ready for upload/download message 6 6 fixed tcode number = 16 (0x10) from device auxiliary access ? upload request message 6 6 fixed tcode number = 17 (0x11) from tool 8 8 fixed opcode to enable selected configuration, status or data upload from mcu auxiliary access ? download request message 6 6 fixed tcode number = 18 (0x12) from tool 8 8 fixed opcode to enable selected configuration or data download to mcu 8 80 variable depending upon opcode selected for download, information to be downloaded to device will vary. auxiliary access ? upload/download information message 6 6 fixed tcode number = 19 (0x13) from device / tool 8 80 variable 1). for an access, depending on word size selected (sz field in rwa register), variable-length packets of information (10, 18, or 34 bits) will be uploaded/downloaded from/to device. 2). depending upon opcode selected for upload from internal readi registers, information to be uploaded to the device will vary. 1 refer to table 23-20 for the error code encoding for error messages. table 23-20. error codes error code description 00000 ownership trace overrun (not used) 00001 program trace overrun (not used) table 23-19. public messages supported (continued) message name minimum packet size (bits) maximum packet size (bits) packet type packet description direction 23-30 mpc565/mpc566 reference manual motorola pin interface vendor-defined messages outlined in table 23-21 are also supported by readi. 00010 data trace overrun (not used) 00011 read/write access error 00100 invalid message 00101 invalid access opcode 00110 watchpoint overrun 00111 program/data/ownership trace overrun 01000-10111 reserved 11000-11111 vendor defined table 23-21. vendor-defined messages supported tcode name minimum packet size (bits) maximum packet size (bits) packet type packet description direction dev port access ? dsdi data message 6 6 fixed tcode number = 56 (0x38) from tool 10 35 variable bdm development serial data in (dsdi) dev port access ?dsdo data message 6 6 fixed tcode number = 57 (0x39) from device 10 35 variable bdm development serial data out (dsdo) dev port access ? bdm status message 6 6 fixed tcode number = 58 (0x3a) from device 11fixedbdmstatus program trace ? indirect branch message with compressed code 6 6 fixed tcode number = 59 (0x3b) from device 1 8 variable number of sequential instructions executed since last taken branch 6 6 fixed bit address 1 23 variable unique portion of the target address for taken branches and exceptions (compressed code) program trace ? direct branch synchronization message with compressed code 6 6 fixed tcode number = 60 (0x3c) from device 6 6 fixed bit address 1 23 variable current instruction address program trace ? indirect branch synchronization message with compressed code 6 6 fixed tcode number = 61 (0x3d) from device 6 6 fixed bit address 1 23 variable current instruction address table 23-20. error codes (continued) error code description motorola chapter 23. readi module 23-31 pin interface 23.3.2.4 message formats message formatting is performed in the pin interface block. raw messages read from the message queue are independent of the number of mdo pins implemented. table 23-22 shows the various message formats that the pin interface formatter has to encounter. note for variable length fields, the transmitted size of the field is determined as the bits from the least significant bit to the most significant non-zero valued bit, (i.e., most significant 0 value bits are not transmitted). table 23-22. message field sizes message tcode field # 1 field # 2 field # 3 max size 1 min. size 2 device id 1 fixed = 32 na na 38 bits 38 bits ownership trace message 2fixed=32 na na 38 bits 38 bits program trace ? direct branch message 3 variable max = 8 min = 1 na na 14 bits 7 bits program trace ? indirect branch message 4 variable max = 8 min = 1 variable max = 23 min = 1 na 37 bits 8 bits data trace ? data write message 5 variable max = 25 min = 1 variable max = 32 min = 8 na 63 bits 15 bits data trace ? data read message 6 variable max = 25 min = 1 variable max = 32 min = 8 na 63 bits 15 bits error message 3 8fixed=5 na na 11 bits 11 bits program trace correction message 10 (0xa) variable max = 8 min = 1 na na 14 bits 7 bits program trace ? direct branch synchronization message 11 (0xb) variable max = 1 min = 1 variable max = 23 min = 1 na 30 bits 8 bits program trace ? indirect branch synchronization message 12 (0xc) variable max = 1 min = 1 variable max = 23 min = 1 na 30 bits 8 bits 23-32 mpc565/mpc566 reference manual motorola pin interface data trace ? data write synchronization message 13 (0xd) variable max = 1 min = 1 variable max = 25 min = 1 variable max = 32 min = 8 64 bits 16 bits data trace ? data read synchronization message 14 (0xe) variable max = 1 min = 1 variable max = 25 min = 1 variable max = 32 min = 8 64 bits 16 bits watchpoint message 15 (0xf) fixed = 6 na na 12 bits 12 bits auxiliary access ? device ready for upload/download message 16 (0x10) na na na 6 bits 6 bits auxiliary access ? upload request (tool requests information) message 17 (0x11) fixed = 8 na na 14 bits 14 bits auxiliary access ?download request (tool provides information) message 18 (0x12) fixed = 8 variable max = 80 min = 8 na 94 bits 22 bits auxiliary access ? upload/download information (device/tool provides information) message 19 (0x13) variable max = 80 min = 8 na na 86 bits 14 bits dev port access ? dsdi data (tool provides information) message 56 (0x38) variable max = 35 min = 10 na na 41 bits 16 bits dev port access ? dsdo data (device provides information) message 57 (0x39) variable max = 35 min = 10 na na 41 bits 16 bits dev port access ?bdm status (device provides information) message 58 (0x3a) fixed = 1 na na 7 bits 7 bits program trace ? indirect branch message with compressed code 59 (0x3b) variable max = 8 min = 1 fixed = 6 variable min = 1 max = 23 43 bits 14 bits table 23-22. message field sizes (continued) message tcode field # 1 field # 2 field # 3 max size 1 min. size 2 motorola chapter 23. readi module 23-33 pin interface the maximum message length is 94 bits. the maximum number of fields is 3, excluding the tcode itself. the double edges in table 23-22 indicate the required mseo /msei assertion or negation indicating the start of message or end of message respectively. the shaded edges in table 23-22 indicate how information can be packed into super-fields delimited via mseo /msei assertion followed by mseo /msei negation. 23.3.2.5 rules of messages a variable sized field within a message must end on a port boundary. a variable sized field may start within a port boundary only when following a fixed length packet. super-fields must end on a port boundary (2-, 4-, or 8-bit boundaries depending on whether the device receives or sends messages, and the port size configured). when a variable length field is sized such that it does not end on a port boundary, it is necessary to extend and zero fill the remaining bits after the highest-order bit so that it can end on a port boundary. a data field within a data trace message must be eight, 16, or 32 bits in length. the field containing the tcode number is always transferred out first, followed by subsequent fields of information. within a field, the lowest significant bits are shifted out first. figure 23-14 shows the transmission sequence of a message which is made up of a tcode, a variable length field, and finally a super-field consisting of a fixed length and a variable length field. the only exception to this rule is the dev program trace ? direct branch synchronization message with compressed code 60 (0x3c) fixed = 6 variable max = 23 min = 1 na 35 bits 13 bits program trace? indirect branch synchronization message with compressed code 61 (0x3d) fixed = 6 variable max = 23 min = 1 na 35 bits 13 bits 1 maximum information size. the actual number of bits transmitted is dependant on the number of mdo pins. 2 minimum information size. the actual number of bits transmitted is dependent on the number of mdo pins. 3 refer to table 23-20. table 23-22. message field sizes (continued) message tcode field # 1 field # 2 field # 3 max size 1 min. size 2 23-34 mpc565/mpc566 reference manual motorola pin interface port access messages. see section 23.10.1, ?rcpu development access messaging,? for further details. figure 23-14. transmission sequence of messages 23.3.2.6 examples the following are examples of branch trace messages. table 23-23 illustrates an example of how the indirect branch public message is transmitted. note the example uses a four-bit output port. note also that t0, i0, and a0 are the least significant bits where: tx = tcode number (fixed) ix = number of sequential instructions (variable) ax = unique portion of the address (variable) note during clock 7, the tool should ignore data on mdo pins. tcode(6bits) field#1(var) field#2 123 msb lsb msb lsb msb lsb field #3 lsb msb 4 msex motorola chapter 23. readi module 23-35 pin interface table 23-23 is an example of the minimum transmission of any message containing a variable length field (three clocks). note the example uses a 4-bit output port. note also that t0, and i0 are the least significant bits where: tx = tcode number (fixed) ix = number of sequential instructions (variable) note during clock 3, the tool should ignore data on mdo pins. 23.3.2.7 non-temporal ordering of transmitted messages trace messages sent out may not be in the sequence they actually occurred. the traces are monitored on the internal buses and these traces are captured as they occur and are sent out in the order they were captured and processed. btms are in sequence and dtms are in sequence, however, temporal order of dtms interleaved with btms may not be accurate with regard to logical flow of code. table 23-23. indirect branch message clock mdo[3:0] mseo 3210 1 idle 0 xxxx 1 idle (or end of last message) 1 t3t2t1t0 0 start message 2i1i0t5t4 0 normal transfer 3 i5i4i3i2 0 normal transfer 400i7i6 1 end packet 5 a3a2a1a0 0 normal transfer 6 a7a6a5a4 1 end packet 7 0000 1 end message 8 t3t2t1t0 0 start message table 23-24. direct branch message clock mdo[3:0] mseo 3210 1 idle 1 t3t2t1t0 0 start message 2i1i0t5t4 1 end packet 3 0000 1 end message 23-36 mpc565/mpc566 reference manual motorola pin interface 23.3.3 readi reset configuration the readi reset configuration information is received via evti and mdi[0] to enable or disable the readi module and select the port size. evti and mdi[0] are sampled synchronously at the negation of rsti. reset configuration information must be valid on evti and mdi[0] at least four clocks prior to the negation of rsti . if evti is sampled asserted at negation of rsti , the readi module will be enabled. this is illustrated in figure 23-15. readi control and status information will be reset and the auxiliary output port will be three-stated, when rsti is asserted. system reset will not reset the readi control and status information and not three-state the auxiliary output port. port size configuration is selected via the value of mdi[0] at the negation of rsti . table 23-25 describes the readi reset configuration options. rsti has a pull-down resistor in the pads. if the auxiliary port is not connected to a tool, readi module will be in reset state and not drive the auxiliary output port. figure 23-15. readi module enabled table 23-25. readi reset configuration options evti mdi [0] configuration 1 x module disabled. all outputs three-stated. 0 1 module enabled, default port configuration 2mdi,8mdo 0 0 module enabled, alternate port configuration 1mdi,2mdo rsti evti evti is sampled at the negation of rsti . since evti is asserted, the readi module is enabled. reset configuration information must be valid on evti at least 4 system clocks prior to rsti negation. system clock motorola chapter 23. readi module 23-37 pin interface 23.3.3.1 reset configuration for debug mode to enable rcpu development access via the readi pins, the reset sequence outlined below should be used: assert readi reset (rsti ), event-in (evti ) and system reset (hreset ) negate rsti upon negation of rsti , tool should configure the dor, dme, and dpa fields in the dc register to desired setting. tool negates hreset at least 16 system clocks after receiving the device ready message refer to figure 23-81 for further details. 23.3.3.2 reset configuration for non-debug mode refer to section 23.3.3.1, ?reset configuration for debug mode,? for details on reset configuration for non-debug mode. the only difference between non-debug mode reset configuration and debug mode reset configuration is the values of the dor, dme, and dpa fields in the dc register. 23.3.3.3 secure mode refer to section 23.1.4.2, ?security,? for further details. 23.3.3.4 disabled mode if evti is negated at negation of rsti , the readi module will be disabled. no trace output will be provided, and output auxiliary pins will be three-stated. this is illustrated in figure 23-16. 23-38 mpc565/mpc566 reference manual motorola program trace figure 23-16. readi module disabled 23.3.3.5 guidelines for transmitting input messages an error message is sent out when an invalid tcode is detected by the pin input formatter. refer to section 23.6.8.2, ?invalid message,? for further details. an error message is sent out when an invalid access opcode is detected in auxiliary input messages by the pin input formatter. refer to section 23.6.8.3, ?invalid access opcode,? for further details. if the tcode is valid, then readi will expect that the correct number of packets have been received and no further checking will be performed. if the number of packets received by readi is not correct, readi response is not defined, unless the message is a download request message (refer to section 23.2.4, ?partial register updates,? for further details). 23.4 program trace this section details the program trace mechanism supported by readi for the rcpu. program trace is implemented via branch trace messaging (btm) as per the ieee-isto 5001-1999 definition. system rsti evti reset configuration information must be valid on evti at least 4 clocks prior to rsti negation. evti is sampled at the negation of rsti . since evti is negated, the readi module is disabled. clock motorola chapter 23. readi module 23-39 program trace 23.4.1 branch trace messaging branch trace messaging facilitates program trace by providing the following types of information: messaging for taken direct branches includes how many sequential instructions were executed since the last taken branch or exception. direct (or indirect) branches not taken are counted as sequential instructions. messaging for taken indirect branches and exceptions includes how many sequential instructions were executed since the last taken branch or exception and the unique portion of the branch target address or exception vector address. for some mispredicted branches and exception occurrences, program trace correction messages correct the number of instructions since last taken branch as transmitted in prior btm message. 23.4.1.1 rcpu instructions that cause btm messages the following rcpu instructions, when executed, cause indirect branch messages to be encoded: 1. taken branch relative to link or counter registers 2. context switching sequential instructions 3. exception taken (error/interrupts) the following rcpu instruction, when executed, causes direct branch messages to be encoded: 1. taken direct branch instructions 23.4.2 review of rcpu instruction execution branch trace messaging for the rcpu is accomplished by snooping the u-bus address, data and program trace signals, and rcpu vf and vfls signals, and performing algorithms necessary to generate the trace messages. 23.4.2.1 rcpu pipeline and execution model the rcpu instruction sequencer provides the central control for data flow between execution units and data files. it also implements the instruction pipeline to fetches and issues instructions to the execution units, and to control the pipeline. figure 23-17 depicts the rcpu instruction flow. 23-40 mpc565/mpc566 reference manual motorola program trace figure 23-17. rcpu instruction flow a generalized execution flow for the sequencer is as follows. for more details refer to the rcpu reference manual (rcpurm/ad). 1. fetch instructions into the prefetch queue [4+1 instructions deep]. 2. decode instructions fetched into the prefetch queue. signal instruction type based on the decode through the vf signals. ? if the decoded branch instruction is unconditional, instructions subsequent to the branch instruction in the prefetch queue are flushed. fetching of instructions is started from the new target address. ? if the decoded branch instruction is conditional and predicted not taken, the branch instruction is treated as a sequential instruction. instructions are not flushed from the prefetch queue. ? if the decoded branch instruction is conditional and predicted taken, instructions subsequent to the branch instruction in the prefetch queue are flushed. fetching of instructions is started from the new target address. 3. issue decoded instructions at the top of the prefetch queue to the execution units, and load processor status into history buffer [six instructions deep]. branch unit instruction fetch decode buffer pre-fetch queue issue history buffer retire write back execution units vf[0:2] vfls[0:1] motorola chapter 23. readi module 23-41 program trace 4. if the conditional branch instruction which was predicted taken, is subsequently discovered to be mispredicted (condition not met), fetched instructions (from the new target address specified by the branch instruction) are flushed. the cancelled branch and the number of flushed instructions are signalled through the vf signals. now fetching of instructions is started from the old address (before the branch was predicted as taken). 5. an instruction is ?retired? when the execution unit completes execution (without an exception) of the issued instruction (write-back completed) and the instruction is at the top of the history buffer queue; (i.e., all previously issued instructions completed without exception). ? issued instructions may complete execution out of order, but are always retired from the history buffer in order. 6. when an instruction-caused exception is recognized, instructions that appear earlier in the instruction stream are required to complete before the exception is taken. an instruction is said to have ?completed? when the results of that instruction?s execution has been committed to the appropriate registers (i.e., following the writeback stage). ? exception conditions may be recognized out of order, but they are handled strictly in order. 7. instructions that appear after the exception-causing instruction which have not been executed are flushed from the prefetch queue. the number of instructions flushed is signalled via the vf signals. instructions that appear after the exception-causing instruction which have been executed are flushed from the history buffer. the number of instructions flushed from the history buffer are signaled via the vfls signals. 8. when exceptions occur, information about the state of the processor is saved to certain registers, and the processor begins execution at an address predetermined for each exception. as can be seen from the above flow, the following issues arise, when tracking the execution of the rcpu: 1. not all fetched (decoded) instructions are executed. 2. not all executed (issued and completed) instructions are retired. 3. taken branches may be cancelled due to misprediction or exceptions. 4. executed instructions (sequential or branches) which are subsequent to the exception-causing instruction will be flushed from the history buffer due to exception. the trace information that is generated by rcpu is ideally suited for off-line software oriented processing, where there is the ability to trace back and recover from flushed queues. 23-42 mpc565/mpc566 reference manual motorola program trace 23.4.2.2 rcpu branch trace indicators the rcpu supports program trace by providing information on the status of the instruction decode, instruction queue flush and history buffer flush. for more information, consult the section on development support in the rcpu reference manual . the branch trace indicators from the rcpu are the vf and the vfls signals. the vf signals indicate the type for the current instruction decoded and the outcomes of change-of-flow instructions. they also indicate the number of instructions flushed from the instruction prefetch queue on change of flow. this indication is in the clock following the indication of change of flow. for details on vf instruction type encoding and vf queue flush information refer to table 23-26 and table 23-27 respectively. the rcpu vf signals indicate (instruction pre-fetch) queue flush information in the clock following a taken change-of-flow indication. this encoding is as follows. table 23-26. vf instruction type encoding vf instruction type next vf encoding 000 none instruction type 001 sequential 010 branch (direct or indirect) not taken 011 vsync was asserted/negated and therefore the next instruction will be marked with program trace cycle attribute 100 interrupt/exception taken ? the target instruction fetch will be marked with program trace cycle attribute. queue flush information 101 branch indirect taken, rfi, mtmsr, isync and in some cases mtspr ? the target instruction fetch will be marked with program trace cycle attribute. 110 branch direct taken 111 branch (direct or indirect) not taken (misprediction) table 23-27. vf queue flush information vf instruction type next vf encoding 000 0 instructions flushed from instruction queue instruction type 001 1 instructions flushed from instruction queue 010 2 instructions flushed from instruction queue 011 3 instructions flushed from instruction queue 100 4 instructions flushed from instruction queue 101 5 instructions flushed from instruction queue 110 reserved 111 branch (direct or indirect) not taken (misprediction) queue flush information motorola chapter 23. readi module 23-43 program trace note encoding vf equal to 0b111 for the queue flush information indicates that the predicted branch (indicated in the previous clock by appropriate vf encoding) is cancelled, and that further flush information follows in the next clock. the vfls signals track the history buffer flushes. this aids the readi module to determine how many instructions actually executed and retired. refer to table 23-28 for details on vfls encoding. note the history buffer has a queue depth of six instructions, but can flush (restore processor state) up to two instructions at a time. using the rcpu program trace information available via the vf and the vfls signals, and snooping the u-bus for instruction fetches, the readi module generates program trace messages to track the change of flow for the rcpu. 23.4.3 btm message formats btm messages are of five types ? direct, indirect, correction, error, and synchronization. 23.4.3.1 direct branch messages direct branches (conditional or unconditional) are all taken branches whose destination is fixed in the instruction opcode. the program trace direct branch message has the following format: figure 23-18. direct branch message format table 23-28. vfls history buffer flush encoding vfls history buffer flush information 00 0 instructions flushed from history buffer 01 1 instructions flushed from history buffer 10 2 instructions flushed from history buffer 11 ignored for program trace tcode (3) sequence count [1 - 8 bits] max length = 14 bits [6 bits] min length = 7 bits 23-44 mpc565/mpc566 reference manual motorola program trace 23.4.3.2 indirect branch messages indirect branches include interrupts, exceptions, and all taken branches whose destination is determined at run time. for the rcpu, certain sequential instructions are tagged with the indirect change-of-flow attribute because these instruction affect the machine in a similar manner to true indirect change-of-flow instructions. these instructions are the rfi, isync, mtmsr and certain mtspr (to cmpa ? cmpf, ictrl, ecr and der) the program trace indirect branch message has the following format: figure 23-19. indirect branch message format for compressed code support, six additional bits indicate the starting bit address within the word of the compressed instruction. the program trace indirect branch with compressed code message has the format shown in figure 23-20. the format of the bit address field is shown in figure 23-21. the bit definitions are shown in table 23-29. note on the mpc566, the bit pointer should be multiplied by 2 (shift left on bit) for the actual starting bit position. figure 23-20. indirect branch message format with compressed code figure 23-21. bit pointer format with compressed code tcode (4) sequence count relative address [1 - 8 bits] [1 - 23 bits] max length = 37 bits [6 bits] min length = 8 bits tcode (59) sequence count bit address relative address [6 bits] [1-8 bits] [6 bits] [1-23 bits] max length = 40 bits min length = 14 bits 543210 reserved bit pointer msb lsb motorola chapter 23. readi module 23-45 program trace 23.4.3.3 program trace correction message in case of a mispredicted branch or an exception, a program trace correction message may also be sent indicating a number which corrects the number of instructions (not messages) in the trace. in the case of a synchronizing branch trace message getting corrected due to an exception or misprediction, the next branch trace message will be a synchronizing message. table 23-30 illustrates an example of a program trace correction message in case of a mispredicted branch. table 23-31 illustrates an example of a program trace correction message in case of an exception. note in case of an exception, the sequential instruction count is reset to 0, after the program trace correction message is sent. note in case of an mispredicted branch, the correction count is always 1 and the sequential instruction count is reset to 1 (to denote the not-taken branch as a sequential instruction), after the program trace correction message is sent. this is because a mispredicted branch is considered to be a sequential instruction. table 23-29. bit address format rcpu bits nexus bits name description 4:5 0:1 ? reserved (unused) 0:3 2:5 bp bit pointer. this value is 1/2 the actual bit start. table 23-30. program trace correction due to a mispredicted branch time processor state message sent 1 sequential instruction 2 sequential instruction 3 sequential instruction 4 sequential instruction 5 sequential instruction 6 direct branch instruction direct branch message tcode = 3 number of sequential instructions executed since last taken branch = 5 7 sequential instruction 23-46 mpc565/mpc566 reference manual motorola program trace 8 sequential instruction 9 sequential instruction 10 sequential instruction 11 indirect branch instruction (mispredicted taken) indirect branch message tcode = 4 number of sequential instructions executed since last taken branch = 4 unique portion of the target address 12 sequential instruction 13 sequential instruction 14 sequential instruction 15 branch correction program trace correction message tcode = 10 number of instructions to rewind from trace = 1 16 sequential instruction 17 sequential instruction 18 indirect branch instruction (predicted taken) indirect branch message tcode = 4 number of sequential instructions executed since last valid taken branch = 3 unique portion of the target address at time 11, the indirect branch is mispredicted taken. at time 15, branch correction occurs due to the mispredicted branch which was taken at time 11. a program trace correction message is sent out correcting the number of instructions in the trace (1). sequential instruction which occurred at time 12, 13, and 14 respectively are not included in the correction count because the tool is not aware that they occurred (they were not transmitted out). at time 18, the indirect branch message indicates that 3 sequential instructions were executed since trace correction (this includes the mispredicted branch instruction which is considered to be a sequential instruction). table 23-31. program trace correction due to an exception time processor state message sent 1 sequential instruction 2 sequential instruction 3 sequential instruction 4 direct branch instruction direct branch message tcode = 3 number of sequential instructions executed since last taken branch = 3 5 sequential instruction 6 sequential instruction table 23-30. program trace correction due to a mispredicted branch (continued) time processor state message sent motorola chapter 23. readi module 23-47 program trace the program trace correction message has the following format: figure 23-22. program trace correction message format 23.4.3.4 error message (queue overflow) a program/data/ownership trace overrun error occurs when a trace message cannot be queued due to the queue being full, provided program trace is enabled. 7 sequential instruction 8 sequential instruction 9 indirect branch instruction indirect branch message tcode = 4 number of sequential instructions executed since last taken branch = 4 unique portion of the target address 10 sequential instruction 11 sequential instruction 12 indirect branch instruction indirect branch message tcode = 4 number of sequential instructions executed since last taken branch = 2 unique portion of the target address 13 sequential instruction 14 exception due to instruction at time 8 program trace correction message tcode = 10 number of instructions to rewind from trace = 5 16 indirect branch instruction indirect branch message tcode = 4 number of sequential instructions executed since last taken branch = 0 unique portion of the target address at time 8, the sequential instruction that causes an exception is issued. at time 14, the instruction issued at time 8 causes an exception. a program trace correction message is sent out correcting the number of instructions in the trace (5). the sequential instruction that occurred at time 13 is not included in the correction count because the tool is not aware that it occurred (it was not transmitted out). note: the sequential instruction at time 8 did not retire and is included in the correction number. table 23-31. program trace correction due to an exception (continued) time processor state message sent tcode (10) [6 bits] number of instructions to rewind from trace [1 - 8 bits] max length = 14 bits minlength=7bits 23-48 mpc565/mpc566 reference manual motorola program trace the overrun error causes the message queue to be flushed, and an error message to be queued. the error code within the error message indicates that a program/data/ownership trace overrun error has occurred. the next btm will be a synchronization message. refer to table 23-20. the error message has the following format: figure 23-23. error message (queue overflow) format 23.4.3.5 program trace synchronization messages a program trace synchronization message is transmitted via the auxiliary port (provided program trace is enabled) for the following conditions: initial program trace message upon exit of any system reset will be a synchronization message. upon exit of sleep, deep-sleep and low power down mode, the first btm will be a synchronization message. initial program trace message upon exit of background debug mode. upon exiting bdm, the next btm will be a synchronization message. when btm is enabled, the first btm will be a synchronization message. after 255 program trace messages have been queued without synchronization, the next btm will be a synchronization message. upon assertion of an event in (evti ) pin. if the readi module is not disabled, an evti assertion will cause the next btm to be a synchronization message (provided the ec field is 0b00 in the dc register). upon occurrence of a watchpoint, the next btm will be a synchronization message (provided program trace is enabled). occurrence of queue overrun. a program trace overrun error occurs when a trace message cannot be queued due to the queue being full. this causes the message queue to be flushed, and an error message is placed as the first message in the queue. the error code within the error message will indicate that program/data/ownership trace overrun has occurred. the next btm will be a synchronization message. sequential instruction count overflow. when the sequential instruction counter reaches its maximum count (up to 256 sequential instructions may be executed), the next btm will be a program trace synchronization message.the sequential instruction counter is reset. tcode (8) error code (0b00111) length = 11 bits [5 bits] [6 bits] motorola chapter 23. readi module 23-49 program trace upon entering or exiting code compression mode, the next btm will be a synchronization message. the next change-of-flow instruction fetch following vsync will be a synchronization message. program trace synchronization messages provide the full address (without leading zeros) and ensure that development tools fully synchronize with program trace regularly. synchronization messages provide a reference address for subsequent btms, in which only the unique portion of the program trace address is transmitted. note for program trace synchronization to work, the ictrl register must be programmed such that show cycle will be performed for all changes in the program flow (isctl field = 01). it is also recommended that the usiu be programmed to ignore instruction show cycles (so as to not impact u-bus performance). synchronization will only occur at changes in program flow boundaries, and cannot be forced by the readi module. synchronizations on errors, overflows, as well as periodic synchronizations will not be deterministic to the nearest instruction, but to the next taken change in program flow. the start of program trace (enabled via any means) will be also deferred to the next change in program flow. program trace synchronization messages are of the following types: direct branch with compressed code indirect branch with compressed code direct branch indirect branch 23.4.3.6 direct branch synchronization message the program trace direct branch synchronization message has the following format: figure 23-24. direct branch synchronization message format tcode (11) messages cancelled full target address [1 bit] [1?23bits] min length = 8 bits [6 bits] max length = 30 bits 23-50 mpc565/mpc566 reference manual motorola program trace 23.4.3.7 indirect branch synchronization message the program trace indirect branch synchronization message has the following format: figure 23-25. indirect branch synchronization message format 23.4.3.8 direct branch synchronization message with compressed code for compressed code support, six additional bits indicate the starting bit address within the word of the compressed instruction. the program trace direct branch synchronization with compressed code message has the following format: figure 23-26. direct branch synchronization message format with compressed code 23.4.3.9 indirect branch synchronization message with compressed code for compressed code support, six additional bits indicate the starting bit address within the word of the compressed instruction. the program trace indirect branch synchronization with compressed code message has the following format: figure 23-27. indirect branch synchronization message format with compressed code tcode (12) full target address [1?23bits] [6 bits] [1 bit] messages cancelled minlength=8bits max length = 30 bits tcode (60) full target address [1?23bits] [6 bits] [6 bits] bit address min length = 8 bits max length = 30 bits tcode (61) full target address [1?23bits] [6 bits] [6 bits] bit address min length = 13bits max length = 35 bits motorola chapter 23. readi module 23-51 program trace 23.4.3.10 relative addressing the relative address feature is compliant with the ieee-isto 5001 - 1999 recommendations, and is designed to reduce the number of bits transmitted for addresses of indirect branch messages. the address transmitted is relative to the address of the previous branch trace message. it is generated by xoring the new address with the previous address, and then using only the results up to the most significant ?1? in the result. to recreate this address, an xor of the (most-significant 0-padded) message address with the previously decoded address gives the current address. figure 23-28 shows how a relative address is generated and how it can be used to recreate the original address. figure 23-28. relative address generation and re-creation 23.4.4 btm operation 23.4.4.1 btm capture and encoding algorithm btm is accomplished by capturing instruction fetch information from the u-bus and instruction execution information from the rcpu (vf and vfls signals), and combining them to generate program trace messages. previous address (a1) = 0x0003 fc01, new address (a2) = 0x0003 f365 a1 = 0000 0000 0000 0011 1111 1100 0000 0001 a2 = 0000 0000 0000 0011 1111 0011 0110 0101 address message (m1) = 1111 0110 0100 a1 y a2 = 0000 0000 0000 0000 0000 111 0110 0100 a1 y m1 = a2 a1 = 0000 0000 0000 0011 1111 1100 0000 0001 m1 = 0000 0000 0000 0000 0000 1111 0110 0100 a2 = 0000 0000 0000 0011 1111 0011 0110 0101 y address recreation: message generation: 23-52 mpc565/mpc566 reference manual motorola program trace 23.4.4.2 instruction fetch snooping instruction fetches are snooped on the u-bus. there is a one-to-one correspondence between instruction fetches marked with the u-bus program trace attribute and the indication of rcpu vf signal (only 3, 4, 5, and 6) between two synchronization events. since u-bus program trace attribute occurs after the indication of vf, it is latched and paired with the nearest (previous) unpaired vf (3, 4, 5, and 6) indication to determine the instruction address. for all other vf indications, except 3, 4, 5, and 6, it is not possible to determine the instruction address. 23.4.4.3 instruction execution tracking instruction execution tracking is performed by capturing the rcpu vf and vfls signals, and decoding them to infer the state of the processor. the rcpu vf signals indicate two classifications of information: the current instruction type which is being loaded into the rcpu instruction queue. for further details refer to the rcpu reference manual . the number of instructions which are currently being flushed from the rcpu instruction queue. for further details refer to the rcpu reference manual . the algorithm to detect the information that is being indicated on the vf signals is depicted in figure 23-29. motorola chapter 23. readi module 23-53 program trace figure 23-29. vf state decoding based on the determination of the vf state decoding, figure 23-30 depicts the sequence for generating and queueing program trace messages. a vfinfo = none nextvf = inst type nextvf == flush? vfinfo = none | seq | sync nextvf = inst type fc = 0 vfinfo = excp | dir | indir | cancel nextvf = flush vf < 6 fc = vf vfinfo = cancel nextvf = flush vf < 4 vf == 7 reset a a a yes no no no yes no yes vfinfo is the type of information the rcpu vf signals indicate during this cycle nextvf is the type of information the rcpu vf signals will indicate in the next cycle fc is the number of instructions flushed from the prefetch queue flush = 0 fc = 0 fc = 0 vfinfo = flush nextvf = inst type a flow for vf queue flush info flow for vf inst. type encoding yes 23-54 mpc565/mpc566 reference manual motorola program trace figure 23-30. btm encoding flow a a a c c a b c sequence_count ++ vfinfo == cancel vfinfo == flush yes yes no no yes no fc >= sequence_count correction messages sequence _count =-fc no no no no no yes yes yes yes a a b c c yes yes yes reset u-bus access with program trace trace_address = ub_addr[7:29] vfinfo == sequential no no vfinfo == sync vfinfo == indirect vfinfo == direct queue message sequence_count = 0 sequence_count ++ address = trace_address *an indirect branch message is generated when vsync occurs address = trace_address vfinfo == exception vfinfo correction vfinfo == flush fc = + vflc fc =1 correction message sequence_count = - fc vfinfo is the type of information the rcpu vf signals indicate during this cycle nextvf is the type of information the rcpu vf signals will indicate during the next cycle flush is a state of rcpu vf signals vfls indicates history buffer flush fc indicates the number of instructions to be flushed motorola chapter 23. readi module 23-55 program trace note in figure 23-30 some operations require multiple cycles. the rcpu vfls signals may take up to three clocks to indicate the full status of the history buffer flush (two instructions are flushed per clock). for compressed code support, refer to figure 23-31 for further details. figure 23-31. btm encoding flow ? compressed code support 23.4.4.4 instruction flush cases the various conditions under which the rcpu may signal instruction flushes of the rcpu prefetch queue or rcpu history buffer are: 1. a taken branch (direct, indirect, interrupt or exception) will cause the instruction prefetch queue (which contains instructions from the now old stream) to be flushed, and fetching will start from the branch target stream. the sequential instruction count will be updated to reflect this 2. a mispredicted branch will cause instructions fetched from the new stream to be flushed, and fetching will resume from the old stream. it will also require a program trace message to be cancelled and the trace to be corrected. 3. an exception can cause cancellation of multiple taken branches which may require cancelling multiple program trace messages. 23.4.5 btm queueing readi implements a queue 16 message deep for program trace, data trace, and ownership trace messages. messages that enter the queue are transmitted via the output auxiliary port in the order in which they are queued. u-bus access with program trace trace_address = ub_addr[7:29] c_trace_address = ub_data[1:6] c_trace_address = additional information for compressed code. 23-56 mpc565/mpc566 reference manual motorola program trace note if multiple trace messages need to be queued at the same time, program trace messages will have the highest priority unless the data trace buffers are full, in which case the data trace messages are given temporary higher priority than the program trace messages. 23.4.6 timing diagram figure 23-32. direct branch message figure 23-33. indirect branch message mcko mseo mdo[7:0 ] 00000011 0010 00000000 tcode = 3 number of sequential instructions since last taken branch = 72 don?t care data (idle clock) 0001 don?t care data (idle clock) tcode = 4 number of sequential instructions since last taken branch = 4 relative address = 0x534 mcko mseo mdo[7:0] 00000100 00000001 00110100 00000101 00000000 motorola chapter 23. readi module 23-57 program trace figure 23-34. indirect branch message with compressed code figure 23-35. program trace correction message figure 23-36. error message (program/data/ownership trace overrun) tcode = 59 (0x3b) bit address = 3 relative address = 0x432 don?t care data (idle clock) number of sequential instructions since last taken branch = 4 mcko mseo mdo[7:0] 00111011 00000001 10000011 00001100 00000001 00000000 tcode = 10 (0xa) number of instructions corrected in trace= 65 don?t care data (idle clock) mcko mseo mdo[7:0] 01001010 00010000 00000000 tcode = 8 error code = 0b00111 (program/data/ownership trace overrun) don?t care data (idle clock) mcko mseo mdo[7:0] 11001000 00000001 00000000 23-58 mpc565/mpc566 reference manual motorola program trace figure 23-37. direct branch synchronization message figure 23-38. indirect branch synchronization message figure 23-39. direct branch synchronization message with compressed code tcode = 11 (0xb) number of messages cancelled = 0 full target address = 0x654320 don?t care data (idle clock) mcko mseo mdo[7:0] 00001011 00000000 00100000 01000011 01100101 00000000 tcode = 12 (0xc) number messages cancelled = 0 full target address = 0x654320 don?t care data (idle clock) mcko mseo mdo[7:0] 00001100 00000000 00100000 01000011 01100101 00000000 tcode = 60 (0x5c) bit address = 9 full target address = 0xca864 don?t care data (idle clock) mcko mseo mdo[7:0] 01111100 01000010 10000110 11001010 00000000 motorola chapter 23. readi module 23-59 data trace figure 23-40. indirect branch synchronization message with compressed code 23.4.7 program trace guidelines refer to section 23.2.5.1, ?program trace guidelines,? for further details. 23.5 data trace this section details the data trace mechanism supported by readi. data trace is implemented via data write messaging (dwm) and data read messaging (drm), as per the ieee-isto 5001 - 1999. 23.5.1 data trace for the load/store bus (l-bus) the l-bus allows the rcpu to perform loads and stores, and the l2u to read and write the l-bus resources. snooping for data trace on the l-bus requires the readi module to handle the full range of l-bus cycles. this includes various cases of pipelining and aborted cycles. data trace requires snooping the l-bus cycles, and storing the information for qualifying accesses (based on enabled features and matching target addresses). the readi module traces all data accesses that meet the selected range and attributes. this includes all rcpu initiated accesses and all l-bus accesses. l-bus data cycles can have data sizes of 8, 16 or 32 bits.the readi module supports all three data sizes. 23.5.2 data trace message formats data trace messages are of five types: data write data read tcode = 61 (0x5d) bit address = 9 full target address = 0xca864 don?t care data (idle clock) mcko mseo mdo[7:0] 01111101 01000010 10000110 11001010 00000000 23-60 mpc565/mpc566 reference manual motorola data trace data write synchronization data read synchronization error message 23.5.2.1 data write message the data write message contains the data write value and the address of the target location, relative to the previous data trace message. the data write message has the following format: figure 23-41. data write message format 23.5.2.2 data read message the data read message contains the data read value and the address of the target location, relative to the previous data trace message. the data read message has the following format: figure 23-42. data read message format 23.5.2.3 data trace synchronization messages a data trace synchronization message shall be transmitted via the auxiliary port (provided data trace is enabled) for the following conditions: initial data trace message upon exit of any system reset will be a synchronization message. upon exit of sleep, deep-sleep and low power down mode, the first data trace message will be a synchronization message. initial data trace message upon exit of background debug mode. upon exiting bdm, the next data trace message will be a synchronization message. when data trace is enabled, the first data trace message will be a synchronization message. tcode (5) relative address [1 to 25 bits] max length = 63 bits [8, 16, or 32 bits] data value [6 bits] min length = 15 bits tcode (6) relative address [1 to 25 bits] max length = 63 bits [8, 16, or 32 bits] data value [6 bits] min length = 15 bits motorola chapter 23. readi module 23-61 data trace after 255 data trace messages have been queued without synchronization, the next data trace message will be a synchronization message. upon assertion of an event in (evti ) pin. if the readi module is not disabled at reset, when evti asserts, if the ec field is 0b00 in the dc register, the next data trace message will be a synchronization message. upon occurrence of a watchpoint, the next data trace message will be a synchronization message. occurrence of queue overrun. a data trace overrun error occurs when a trace message cannot be queued due to the queue being full (provided data trace is enabled). this causes the message queue to be flushed, and an error message is placed as the first message in the queue. the error code within the error message indicates that program/data/ownership trace overrun has occurred. the next data trace message will be a synchronization message. data trace synchronization messages provide the full address (without leading zeros) and ensure that development tools fully synchronize with data trace regularly. synchronization messages provide a reference address for subsequent dtms, in which only the unique portion of the data trace address is transmitted. data trace synchronization messages are of two types: data write data read 23.5.2.4 data write synchronization message the data write synchronization message has the following format: figure 23-43. data write synchronization message format 23.5.2.5 data read synchronization messaging the data read synchronization message has the following format: figure 23-44. data read synchronization message format tcode (13) data value [1 to 25 bits] max length = 64 bits [8, 16, or 32 bits] messages cancelled [1 bit] [6 bits] min length = 16 bits full target address tcode (14) data value [1 to 25 bits] max length = 64 bits [8, 16, or 32 bits] messages cancelled [1 bit] [6 bits] min length = 16 bits full target address 23-62 mpc565/mpc566 reference manual motorola data trace 23.5.2.6 relative addressing refer to section 23.5.2.6, ?relative addressing,? for further details. 23.5.3 error message (queue overflow) a program/data/ownership trace overrun error occurs when a trace message cannot be queued due to the queue being full, provided data trace is enabled. the overrun error causes the message queue to be flushed, and a error message to be queued. the error code within the error message indicates that a program/data/ownership trace overrun error has occurred. the next dtm will be a synchronization message. refer to table 23-20. the error message has the following format: figure 23-45. error message (queue overflow) format 23.5.4 data trace operation data trace is performed by snooping the l-bus for read or write cycles. data trace functions are enabled by setting the appropriate fields in the dc register and the dta registers. for details on field configuration, refer to section 23.2.1.4, ?development control (dc) register,? and section 23.2.1.9, ?data trace attributes 1 and 2 (dta1 and dta2) registers,? respectively. data trace flow is depicted in figure 23-46. tcode (8) error code (0b00111) length = 11 bits [5 bits] [6 bits] motorola chapter 23. readi module 23-63 data trace figure 23-46. data trace flow diagram for non-pipelined access 23.5.5 data trace windowing data trace windowing is achieved via the address range within the dtea and the dtsa fields of the dta registers. all l-bus accesses which fall within these two address ranges, provided the address ranges are enabled in either dta register, are candidates to be idle data read/write detected store address cancelled queue message cycle no yes address in either wait for data phase store data no ? range data error ? yes reset 23-64 mpc565/mpc566 reference manual motorola data trace transmitted. data read and/or data write trace may be enabled via the ta field of the data trace attributes registers (dta). note data trace ranges are word aligned. therefore, the address range fields (dtea and dtsa) of the dta registers are only 23 bits wide and, as such, should be assigned by the tool with the 23 most significant bits of the intended 25-bit range address. note the off-core mpc500 special purpose register (spr) map cannot be distinguished from the normal memory map accesses via the defined address range control. if data trace ranges are set up such that the off-core mpc500 spr map falls within active ranges, then accesses to these off-core mpc500 sprs will be traced, and the messages will not be distinguishable from accesses to normal memory map space. off-core mpc500 sprs typically exist in the 8-kbyte ? 16-kbyte lowest memory block (0x2000 - 0x3ff0). if data or peripherals are mapped to this space, load/stores to mpc500 sprs will be indistinguishable from data or peripheral accesses. 23.5.6 special l-bus cases special l-bus cases are handled as described in table 23-32. table 23-32. special l-bus case handling special case action l-bus cycle aborted cycle ignored l-bus cycle with data error message discarded l-bus cycle terminated due to address error cycle ignored l-bus cycle completed without error cycle captured and transmitted l-bus cycle initiated by readi (read/write access) cycle ignored l-bus cycle is an instruction fetch cycle ignored data storage interrupt cycle ignored system rese cycle ignored motorola chapter 23. readi module 23-65 data trace 23.5.7 data trace queuing readi implements a queue 16 messages deep for queuing program trace, data trace, and ownership trace messages. messages that enter the queue are transmitted via the output auxiliary port in the order in which they are queued. note if multiple trace messages need to be queued at the same time, program trace messages have a higher priority for queue entry than data trace messages, unless the data trace buffers are full, in which case the data trace messages are given temporary higher priority than the program trace messages. 23.5.8 throughput and latency 23.5.8.1 assumptions for throughput analysis all accesses are data trace only 56-mhz operation output pins are always free (not in middle of transmission) when requested relative address field for data trace messages is 20 bits data field for data trace messages is 32 bits one idle clock between data trace messages 23.5.8.2 throughput calculations the data (read or write) trace message is 58 bits (6 [tcode] + 20 [relative address] + 32 [data]). data trace messages are transmitted out via the mdo pins. hence it will take eight clocks (58 bits/8 mdo pins) to send a message. there will be one idle clock before the next data trace message can be sent. at 56 mhz, it will take 161ns ((8+1) x 17.8) to transmit the message. therefore, the average number of data trace messages that can be transmitted out is 6.2 million (1/161ns) per second, or 24.8 million bytes of read/write data per second. 23-66 mpc565/mpc566 reference manual motorola data trace 23.5.9 timing diagrams figure 23-47. date write message figure 23-48. data read message figure 23-49. data write synchronization message tcode = 5 relative address = 0x318 data = 0x4a don?t care data (idle clock) mcko mseo mdo[7:0] 00000101 11000110 01001010 00000000 00000000 relative address = 0x1d0a9 don?t care data (idle clock) mcko mseo mdo[7:0] tcode = 6 data = 0x1234 01000110 00101010 01110100 00110100 00010010 00000000 don?t care data (idle clock) tcode = 13 (0xd) number of messages cancelled = 0 full target address = 0x1468ace data = 0xbe mcko mseo mdo[7:0] 00001101 00000000 11001110 10001010 01000110 00000001 10111110 00000000 00000000 motorola chapter 23. readi module 23-67 read/write access figure 23-50. data read synchronization message figure 23-51. error message (program/data/ownership trace overrun) 23.6 read/write access the read/write access feature allows access to internal memory mapped space via the auxiliary port. read/write mechanism supports single and block, reads and writes. 23.6.1 functional description the readi module is capable of bus mastership on the l-bus and for setting up and reading data and status. all accesses are setup and initiated to the read/write access register (rwa) and upload/download information register (udi) via the four auxiliary access public messages: device ready for upload/download, upload request (tool requests information), download request (tool provides information), upload/download information (device/tool provides information). don?t care data (idle clock) tcode = 14 (0xe) number of messages cancelled = 0 full target address = 0x1468ace data = 0x5c mcko mseo mdo[7:0] 00001110 00000000 11001110 10001010 01000110 00000001 01011100 00000000 00000000 tcode = 8 error code = 0b00111 (program/data/ownership trace overrun) don?t care data (idle clock) mcko mseo mdo[7:0] 11001000 00000001 00000000 23-68 mpc565/mpc566 reference manual motorola read/write access read/write access features are enabled by setting the appropriate fields in the rwa register. for details on field configuration, refer to section 23.2.1.7, ?read/write access (rwa) register.? the functional flow for read/write access to memory mapped locations and mpc500 registers is depicted in figure 23-56. figure 23-52. target ready message figure 23-53. read register message figure 23-54. write register message figure 23-55. read/write response message tcode (16) max length = 6 bits [6 bits] min length = 6 bits tcode (17) opcode [8 bits] max length = 14 bits [6 bits] min length = 14 bits tcode (18) opcode [8 bits] max length = 94 bits [8-80 bits] register value [6 bits] min length = 22 bits tcode (19) return value [8-80 bits] max length = 86 bits [6 bits] min length = 14 bits motorola chapter 23. readi module 23-69 read/write access figure 23-56. read/write access flow diagram download request public cnt= 0 decrement cnt no read/write ? message (tcode 18) tool sends to device idle module read/write device ready for upload/ (tcode 16) latch data download public message device sends to tool upload/download (tcode 19) information public message tool sends to device write read ? read/write ? upload/download (tcode 19) information public message device sends to tool write read sc = 0 yes reset increment address 23-70 mpc565/mpc566 reference manual motorola read/write access 23.6.2 write operation to memory mapped locations and mpc500 registers 23.6.2.1 single write operation for a single write access to memory mapped locations and mpc500 registers, the following sequence of operations need to be performed via the auxiliary port: 1. the tool confirms that the device is ready before transmitting download request public message (tcode=18). 2. the download request public message contains: a) tcode(18) b) access opcode 0xf which signals that subsequent data needs to be stored in the rwa register. c) configure the rwa register fields as follows: ? start/complete (1 to indicate start access) -> sc ? read/write address (write address) -> rwad ? read/write (1 to indicate a write access) -> rw ? word size (32 bits, 16 bits, 8 bits) -> sz ? write data (write data) -> wd ? privilege (user data/instruction, supervisor data/instruction) -> prv ? map select (select memory map, 00 or 01) -> map ? access count (0 to indicate single access) -> cnt 3. after completion of the write operation, the device ready for upload/download public message (tcode=16) is transmitted to the tool indicating that the device is ready for next access. 4. the sc bit is cleared to indicate that the write access is complete. 23.6.2.2 block write operation for a block write access to memory mapped locations and mpc500 registers, the following sequence of operations need to be performed via the auxiliary port: 1. the tool confirms that the device is ready before transmitting download request public message (tcode = 18). 2. the download request public message contains: a) tcode(18) b) access opcode 0xf which signals that subsequent data needs to be stored in the rwa register. c) configure the rwa register fields as follows motorola chapter 23. readi module 23-71 read/write access ? start/complete (1 to indicate start access) -> sc ? read/write address (starting write address of block) -> rwad ? read/write (1 to indicate a write access) -> rw ? word size (32 bits, 16 bits, 8 bits) -> sz ? write data (write data) -> wd ? privilege (user data/instruction, supervisor data/instruction) -> prv ? map select (select memory map, 00 or 01) -> map ? access count (non zero number to indicate size of block access) -> cnt 3. after completion of this write operation, the device ready for upload/download public message (tcode = 16) is transmitted to the tool indicating that the device is ready for next access. 4. the specified address (stored in rwad field) is incremented to the next word size and the number in the cnt field is decremented. the sc field is not cleared. 5. the tool transmits the next upload/download information public message (tcode = 19). 6. the upload/download information public message contains: a) tcode(19) b) write data (write data -> udi) 7. after the completion of this write operation, the device ready for upload/download public message (tcode = 16) is transmitted to the tool indicating that the device is ready for next access. 8. the specified address (in rwad field) is incremented to the next word size and the number in the cnt field is decremented. the sc field is not cleared. 9. steps 5 through 8 are repeated until the count value in the cnt field of rwa register equals zero. the sc bit is cleared to indicate end of the block write access. note for downloading write data to the device for block write operation, the download request public message (tcode = 18) should not be used to write subsequent data to the udi register. data written to the udi register (via download request message, tcode 18) is not used by the device for any read/write operation. 23-72 mpc565/mpc566 reference manual motorola read/write access 23.6.3 read operation to memory mapped locations and mpc500 registers 23.6.3.1 single read operation for a single read access to memory mapped locations and mpc500 registers, the following sequence of operations need to be performed via the auxiliary port: 1. the tool confirms that the device is ready before transmitting download request public message (tcode = 18). 2. the download request public message contains: a) tcode(18) b) access opcode 0xf which signals that subsequent data needs to be stored in the rwa register. c) configure the rwa fields as follows: ? start/complete (1 to indicate start access) -> sc ? read/write address (read address) -> rwad ? read/write (0 to indicate a read access) -> rw ? word size (32 bits, 16 bits, 8 bits) -> sz ? write data (0xxxxxxxxx-> wd [don?t care]) ? privilege (user data/instruction, supervisor data/instruction) > prv ? map select (select memory map, 00 or 01) -> map ? access count (0 to indicate single access) -> cnt 3. data read from the specified address is stored in the udi register. 4. once the read access is completed, the upload/download information public message (tcode = 19) is transmitted to the tool along with the data read from the udi register. this message also indicates that the device is ready for next access. 5. the sc field in the rwa register is cleared. 23.6.3.2 block read operation for a block read access to memory mapped locations and mpc500 registers, the following sequence of operations need to be performed via the auxiliary port: 1. the tool confirms that the device is ready before transmitting download request public message (tcode = 18). 2. the download request public message contains: a) tcode(18) b) access opcode 0xf which signals that subsequent data needs to be stored in the rwa register. motorola chapter 23. readi module 23-73 read/write access c) configure the rwa fields as follows: ? start/complete (1 to indicate start access) -> sc ? read/write address (starting read address of block) -> rwad ? read/write (0 to indicate a read access) -> rw ? word size (32 bits, 16 bits, 8 bits) -> sz ? write data (0xxxxxxxxx-> wd [don?t care]) ? privilege (user data/instruction, supervisor data/instruction) > prv ? map select (select memory map, 00 or 01) -> map ? access count (non-zero number to indicate block access) -> cnt 3. data read from the specified address is stored in the udi register. 4. after the completion of this read operation, the upload/download information public message (tcode=19) is transmitted to the tool along with the data read from the udi register. this message also indicates that the device is ready to perform the next read operation. 5. the specified address (in rwad field) is incremented to the next word size and the number in the cnt field is decremented. the sc field is not cleared. 6. the data read from the new address is stored in the udi register. 7. steps 4 through 7 are repeated until the count value in the cnt field of rwa register equals zero. the sc bit is cleared to indicate end of the block read access. 23.6.4 read/write access to internal readi registers 23.6.4.1 write operation for a write access to internal readi registers, the following sequence of operations need to be performed via the auxiliary port: 1. the tool confirms that the device is ready before transmitting download request public message (tcode = 18). 2. the download request public message contains: a) tcode(18) b) access opcode, which specifies the register where data needs to be written, (e.g., access opcode 0x14 indicates that dta1 register is the target register). c) data to be written to the register. 3. after the data has been written to the targeted register, the device ready for upload/download public message (tcode = 16) is transmitted to the tool indicating that the device is ready for next access. 23-74 mpc565/mpc566 reference manual motorola read/write access 23.6.4.2 read operation for a read access to internal readi registers, the following sequence of operations need to be performed via the auxiliary port: 4. the tool confirms that the device is ready before transmitting upload request public message (tcode = 17). 5. the upload request public message contains: a) tcode(17) b) access opcode, which specifies the register where data needs to be read from, (for example, access opcode 0x14 indicates that dta1 register is the target register). 6. the upload/download information public message (tcode=19) is transmitted to the tool along with the data read from the targeted register indicating that the device is ready for next access. 23.6.5 error handling the readi module handles the various error conditions in the manner shown in the following sections. 23.6.5.1 access alignment the readi module will force address alignment based on the word size field (sz) value. if the sz field indicates word (32-bit) access, the least significant two bits of the read/write address field (rwad) are ignored. if the sz field indicates half-word (16-bit) access, the least significant bit of the read/write address field (rwad) is ignored. 23.6.5.2 l-bus address error an address error occurs on the l-bus when the address phase of a cycle is not completed normally. this could occur because of address not being valid or the address map not being valid. in such cases: 1. the access is terminated without retrying. 2. the sc bit of the rwa is reset. block accesses do not continue. 3. the error message (tcode = 8) is transmitted (error code 0b00011). refer to table 23-20. 23.6.5.3 l-bus data error l-bus data error is signalled due to: l-bus data phase error. motorola chapter 23. readi module 23-75 read/write access u-bus address phase error (for a l-bus to u-bus cycle). u-bus data phase error (for a l-bus to u-bus cycle). l-bus data error conditions are signalled along with the transfer acknowledge for the access. l-bus data error conditions may occur because of privilege violations, access to protected memory, etc. in such cases, for a read access, the err bit of the udi is set, and the dv bit in the udi is reset at the termination of the access. for a write access, an error public message (tcode = 8) is transmitted (error code 0b00011). 23.6.6 exception sequences the following cases are defined for sequences of the read/write protocol that differ from those described in the above sections: 1. if the sc bit is set to start readi read/write accesses, without valid values in the rwad, then an l-bus address error may occur, which is handled as described above. 2. if a block access is in progress with all the cycles not yet completed, and the rwa is written to again, (with or without modifications), then the block access is terminated at the boundary of the nearest completed access. the resulting data is discarded and not written to the udi. if a new access has been programmed in the rwa register, then that access will start once the controller has recovered. 3. when a block access is in progress with all the cycles not yet completed, writing the sc bit to 0 in rwa register will terminate the block access and device will send out device ready for upload/download message. 4. if a any type (single/block) of access is in progress with the cycles not yet completed, and system reset occurs, the device will send out an error message. the access will be terminated and the sc bit will be reset. refer to table 23-20. 5. if any type of (single/block) of access is requested while system is in reset, the device will send out an error message. the access will not be started and the sc bit will be reset. 23.6.7 secure mode for details refer to section 23.1.4.2, ?security.? 23.6.8 error messages 23.6.8.1 read/write access error an error message is sent out when an l-bus access error or data error on a write access occurs. the error code within the error message indicates that an l-bus address or l-bus data error occurred. for other error handling, see section 23.6.5, ?error handling.? for a list of error codes, refer to table 23-20. 23-76 mpc565/mpc566 reference manual motorola read/write access the error message has the following format: figure 23-57. error message (read/write access error) format 23.6.8.2 invalid message an error message is sent out when an invalid message is received by readi. the error code within the error message indicates that an invalid tcode was detected in the auxiliary input messages by the pin input formatter. refer to table 23-20. the error message has the following format: figure 23-58. error message (invalid message) format note if the tcode is valid, then readi will expect that the correct number of packets have been received and no further checking will be performed. if the number of packets received by readi is not correct, readi response is not deterministic. 23.6.8.3 invalid access opcode an error message is sent out when an invalid access opcode is received by readi. the error code within the error message indicates that an invalid access opcode was detected in the auxiliary input messages by the pin input formatter. refer to table 23-20. the error message has the following format: figure 23-59. error message (invalid access opcode) format tcode (8) error code (0b00011) length = 11 bits [5 bits] [6 bits] tcode (8) error code (0b00100) length = 11 bits [5 bits] [6 bits] tcode (8) error code (0b00101) length = 11 bits [5 bits] [6 bits] motorola chapter 23. readi module 23-77 read/write access 23.6.9 faster read/write accesses with default attributes read/write access throughput may be increased by taking advantage of the default settings of the rwa register, and truncating the least significant zero bits of the download request message. for example, to read a word from the default memory map, with default attributes, a download request message that selects the rwa register, and transmits the sc, rwad, rw fields only is sufficient. this message will contain 41 bits instead of the 94 bits for writing the full contents of the rwa register. see table 23-11 and section 23.2.4, ?partial register updates,? for rwar and partial register update details respectively. note the last data bit transmitted in the download request message (tcode 18) will always be the msb of the register referenced by the opcode (sc field in the case of the rwa register). 23.6.10throughput and latency throughput analysis has been performed for various read/write access cases such as single write, block write, single byte read, single word read, block byte read, block word read accesses to memory mapped locations. data is presented for the two cases when the rwa register is written partially and completely. 23.6.10.1 assumptions for throughput analysis all accesses are single read accesses only. mcki running at 28 mhz. mcko running at 56 mhz. 56-mhz internal operation. five clock internal l-bus access (read) output pins always free (not in middle of transmission) when requested. four idle clocks between read messages. no delay from tool in responding ? tool keeps up with readi port. 23-78 mpc565/mpc566 reference manual motorola read/write access table 23-33. throughput comparison for fpm and rpm mdo/mdi configurations access type reduced port mode 2mdo/1mdipins full port mode 8mdo/2mdipins full rwar update partial rwar update full rwar update partial rwar update single write access to memory mapped location ? word and byte access (in million messages per second) 0.28 0.35 0.53 0.65 single read access to memory mapped location ?wordaccess (in million messages per second) 0.25 0.51 0.52 1.05 single read access to memory mapped location ?byteaccess (in million messages per second) 0.27 0.56 0.53 1.05 block write access to memory mapped locations ? 64-kbyte block (word and byte) write access (in 64-kbyte block writes per second) 9 9 17 17 block read access to memory mapped locations ? 64-kbyte block (word) read access (in 64-kbyte block writes per second) 32 32 77 77 block read access to memory mapped locations ? 64-kbyte block (byte) read access (in 64-kbyte block writes per second) 61 61 95 95 motorola chapter 23. readi module 23-79 timing diagrams 23.7 timing diagrams figure 23-60. block write access figure 23-61. block read access msei mseo mdi mdo download request message upload/download information message device ready for upload/ download device ready for upload/ download tcode 18 tcode 19 tcode 16 tcode 16 msei mseo mdi mdo download request message tcode 18 upload/download information message tcode 19 upload/download information message tcode 19 23-80 mpc565/mpc566 reference manual motorola timing diagrams figure 23-62. device ready for upload/download request message figure 23-63. upload request message mcko mseo mdo[7:0] 00010000 00000000 00000000 tcode = 16 (0x10) don?t care data (idle clock) mcki msei mdi[1:0] 01 00 01 11 11 00 00 00 tcode = 17 (0x11) access opcode = 15 (rwa register) (0xe) don?t care data (idle clock) motorola chapter 23. readi module 23-81 timing diagrams figure 23-64. download request message figure 23-65. upload/download information message don?t care data (idle clock) tcode = 18 (0x12) access opcode = 10 (dc register) (0xa) ec = 0b00 tm = 0b100 dpa = 0b0 dme = 0b0 dor = 0b0 data written to dc register: mcki msei mdi[1:0] 10 00 01 10 10 00 00 00 00 01 00 00 tcode = 19 (0x13) dv =1 err = 0 data read = 0x3c16 (16 bit read access) don?t care data (idle clock) mcko mseo mdo[7:0] 01010011 00010110 00111100 00000000 23-82 mpc565/mpc566 reference manual motorola watchpoint support figure 23-66. error message (invalid access opcode) 23.8 watchpoint support this section details the watchpoint support features of the readi module. the readi module provides watchpoint messaging via the auxiliary port, as defined by the ieee-isto 5001-1999. readi is not compliant with all the breakpoint/watchpoint requirements defined in the ieee-isto 5001 standard. watchpoint trigger and breakpoint/watchpoint control registers are not implemented. watchpoint setting via readi can only be done using the bdm protocol. 23.8.1 watchpoint messaging the readi module provides watchpoint messaging using ieee-isto 5001-1999 defined public messages. the watchpoint status signals from the rcpu are snooped, and when watchpoints occur, a message is sent to the pin output formatter to be messaged out (the general message queue is bypassed to prevent watchpoint messages from being cancelled in the event of a queue overflow). the watchpoint message has the second highest priority. refer to section 23.3.2.1, ?message priority,? for further details on message priorities. the watchpoint message contains the watchpoint code which indicates all the unique watchpoints have occurred since the last watchpoint message. if duplicate watchpoints occur before the watchpoint message is sent out, a watchpoint overrun message is generated. the watchpoint source field will indicate which watchpoints occurred. the watchpoint message has the following format: tcode = 8 error code = 0b00101 (invalid access opcode) don?t care data (idle clock) mcko mseo mdo[7:0] 01001000 00000001 00000000 motorola chapter 23. readi module 23-83 watchpoint support figure 23-67. watchpoint message format 23.8.1.1 watchpoint source field the watchpoint source field is outlined in table 23-34. 23.8.2 error message (watchpoint overrun) a watchpoint overrun error occurs when the same watchpoint occurs multiple times before the first occurrence of that watchpoint has been messaged out. the watchpoint message (which has information of all the watchpoints that occurred prior to the detection of the same watchpoint occurring multiple times) will be sent before the error message can be sent. the overrun error causes further watchpoint occurrences to be ignored, until the error message has been sent. the error code within the error message indicates that a watchpoint overrun error has occurred. refer to table 23-20. the error message has the following format: figure 23-68. error message (watchpoint overrun) format 23.8.3 synchronization upon occurrence of a watchpoint, the next program and data trace message will be a synchronization message (provided program and data trace are enabled). table 23-34. watchpoint source watchpoint source description 0bxxxxx1 first l-bus watchpoint (lw0) 0bxxxx1x second l-bus watchpoint (lw1) 0bxxx1xx first i-bus watchpoint (iw0) 0bxx1xxx second i-bus watchpoint (iw1) 0bx1xxxx third i-bus watchpoint (iw2) 0b1xxxxx fourth i-bus watchpoint (iw3) length = 12 bits tcode (15) watchpoint source [6 bits] [6 bits] tcode (8) error code (0b00110) length = 11 bits [5 bits] [6 bits] 23-84 mpc565/mpc566 reference manual motorola ownership trace 23.8.4 timing diagrams figure 23-69. watchpoint message figure 23-70. error message (watchpoint overrun) 23.9 ownership trace this section details the ownership trace support features of the readi module. ownership trace provides a macroscopic view, such as task flow reconstruction, when debugging software written in a high level (or object-oriented) language. it offers the highest level of abstraction for tracking operating system software execution. this is especially useful when the developer is not interested in debugging at lower levels. 23.9.1 ownership trace messaging ownership trace information is messaged via the auxiliary port using an ownership trace message (otm). the ownership trace register (ot), which can be accessed via auxiliary port, is updated by the operating system software to provide task/process id information. don?t care data (idle clock) tcode = 15 (0xe) watchpoint source = 0b110001 this indicates that first l-bus watchpoint (lwo), third i-bus watchpoint (iw2), and fourth i-bus watchpoint (iw3) have occurred. mcko mseo mdo[7:0] 01001111 00001100 00000000 tcode = 8 error code = 0b00110 (watchpoint overrun) don?t care data (idle clock) mcko mseo mdo[7:0] 10001000 00000001 00000000 motorola chapter 23. readi module 23-85 ownership trace when new information is updated in the register by the embedded processor, it is messaged out via the auxiliary port, allowing development tools to trace ownership flow. ownership trace information is messaged out in the following format: figure 23-71. ownership trace message format 23.9.2 error message (queue overflow) a program/data/ownership trace overrun error occurs when a trace message cannot be queued due to the queue being full, provided ownership trace is enabled. the overrun error causes the message queue to be flushed, and a error message to be queued. the error code within the error message indicates that a program/data/ownership trace overrun error has occurred. refer to table 23-20. the error message has the following format: figure 23-72. error message format 23.9.2.1 otm flow ownership trace messages are generated when the operating system (privileged supervisor task) writes to the memory mapped ownership trace register. the following flow describes the otm process. 1. the ot register is a memory mapped register, whose address is located in the uba. the ot register address can be read from the uba register by the ieee-isto 5001 tool. 2. only privileged writes (byte/half word or word) initiated by the rcpu to the ot register that terminate normally are valid. the data value (word) written into the register is formed into the ownership trace message that is queued to be transmitted. 3. ot register reads and non-privileged ot register writes, or writes initiated by any source other than the rcpu, do not cause ownership trace messages to be transmitted by the readi module. length = 38 bits tcode (2) task/process id tag [32 bits] [6 bits] tcode (8) error code (0b00111) length = 11 bits [5 bits] [6 bits] 23-86 mpc565/mpc566 reference manual motorola ownership trace 23.9.2.2 otm queueing readi implements a 16-message-deep queue for program trace, data trace, and ownership trace messages. messages that enter the queue are transmitted via the output auxiliary port in the order in which they are queued. note if multiple trace messages need to be queued at the same time, ownership trace messages will have the lowest priority. 23.9.3 timing diagram figure 23-73. ownership trace message figure 23-74. error message (program/data/ownership trace overrun) don?t care data (idle clock) tcode = 2 task/process id tag = 0x87654321 mcko mseo mdo[7:0] 01000010 11001000 01010000 11011001 00100001 00000000 tcode = 8 error code = 0b00111 (program/data/ownership trace overrun) don?t care data (idle clock) mcko mseo mdo[7:0] 11001000 00000001 00000000 motorola chapter 23. readi module 23-87 rcpu development access 23.10 rcpu development access this section details rcpu development access support features of the readi module. the readi development port provides a full duplex serial interface for accessing existing rcpu user register and development features including bdm (background debug mode). for further details on rcpu development function and usage, consult chapter 22, ?development support,? or the development port chapter of the rcpu reference manual . rcpu development access can be achieved either via the readi pins or the bdm pins on the mcu. the access method is determined during readi module configuration. figure 23-75 shows how readi and bdm pins are multiplexed for rcpu development access. when the readi module is configured for rcpu development access, ieee-isto 5001 compliant vendor-defined messages are used for transmission of data in and out of the mcu. figure 23-75. rcpu development access multiplexing between readi and bdm pins readi usiu jtag rcpu tck_dsck tdo_dsdo tdi_dsdi readi pins multiplexer dsck dsdi dsdo rcpu development mux control debug development access bdm pins 23-88 mpc565/mpc566 reference manual motorola rcpu development access 23.10.1rcpu development access messaging the following rcpu development access messages are used for handshaking between the device and the tool ? dsdi data message, dsdo data message and bdm status message. 23.10.1.1 dsdi message the dsdi message is used by the tool to download information to the rcpu. the dsdi data field has a 3-bit status header followed by 7 or 32 bits of data/instruction, depending on the rcpu development port mode. the dsdi message has the following format: figure 23-76. dsdi message format note when sending in a dsdi data message, the dsdi data should contain the control and status bits (start, mode, control), followed by the 7 or 32-bit cpu instruction/data or trap enable, msbit first. see figure 23-82 for dsdi data message transmission sequence. 23.10.1.2 dsdo message the dsdo message is used by the device to upload information from the rcpu. the dsdo data field has a 3-bit status header followed by 7 or 32 bits of data/instruction, depending on the rcpu development port mode. the three status bits in the dsdo data indicates if the device is ready to receive the next message from the tool. the dsdo message has the following format: figure 23-77. dsdo message format max length = 41 bits tcode (56) dsdi data [10 or 35 bits] [6 bits] min length = 16 bits tcode (57) dsdo data [10 or 35 bits] [6 bits] max length = 41 bits min length = 16 bits motorola chapter 23. readi module 23-89 rcpu development access note the dsdo data received will contain the control and status bits and data from the cpu, msbit first. see figure 23-82 for dsdo data message transmission sequence. 23.10.1.3 bdm status message bdm status message is generated by the device to let the tool know about the status of debug mode. bdm status message (with bdm status field equal to 0b1) is sent when the rcpu is in debug mode and the device is ready to receive debug mode messages. bdm status message (with bdm status field equal to 0b0) is sent out when the device exits bdm mode and rcpu is in normal operating mode. the bdm status message has the following format: figure 23-78. bdm status message format 23.10.1.4 error message (invalid message) an error message is sent out when an invalid message is received by readi. the error code within the error message indicates that an invalid tcode was detected in the auxiliary input messages by the pin input formatter. refer to table 23-20. the error message has the following format: figure 23-79. error message (invalid message) format 23.10.2rcpu development access operation the rcpu development access can be achieved either via the readi pins or the bdm pins. the default access is via the bdm pins. to enable rcpu development access via the readi pins, the tool has to configure the dc register during the readi reset (rsti ). once the readi module takes the control of length = 7 bits tcode (58) bdm status [1 bit] [6 bits] tcode (8) error code (0b00100) length = 11 bits [5 bits] [6 bits] 23-90 mpc565/mpc566 reference manual motorola rcpu development access rcpu development access, the protocol for transmission of development serial data in (dsdi) and out (dsdo) is performed through the ieee-isto 5001-1999 compliant vendor-defined messages. after enabling rcpu development access via the readi pins, the readi module can enable debug mode and enter debug mode. when debug mode is enabled and entered, readi sends a bdm status message (bdm status field equal to 0b1) to the development tool indicating that the rcpu has entered debug mode and is now expecting instructions from the readi pins. the development tool then uses the dsdi data message to send in the serial transmission data to readi. data is transmitted to the tool using the dsdo data message. this process continues until the rcpu exits debug mode and readi sends the bdm status message (bdm status field equal to 0b0) indicating debug mode exit. note only after the dsdo data message is sent out should another dsdi data message be sent in. synchronous self-clocked mode is selected by readi for rcpu development access. in this mode, the internal transmission between readi and the usiu is performed at system frequency. when the rcpu is in debug mode, program trace is not allowed. if program trace is enabled, a program trace synchronization message is generated when debug mode exits. whenthercpuisindebugmode,datatraceandr/w access are allowed. the flow chart in figure 23-80 shows rcpu development access configuration via readi. the modes of rcpu development access via readi are described below. allowed modes are also summarized in table 23-9 of section 23.2.1.5, ?rcpu development access modes.? 23.10.2.1 enabling rcpu development access via readi pins reset sequencing is done by the tool to initialize the readi pins and registers by asserting rsti (the device sends out the device id message after the rsti negation). system reset is held by the tool until the readi module is reset and initialized with desired rcpu development access setting. for rcpu development access to be enabled via the readi pins, the tool has to configure the dc register (dpa field equal to 0b1) after the negation of rsti , but before the negation of system reset. system reset should only be negated at least 16 system clocks after the dc register has been configured. if the dc register is not configured such that readi module has control of the rcpu development access signals before the negation of the system reset, then rcpu motorola chapter 23. readi module 23-91 rcpu development access development access is via debug mode pins. this is the default setting (dpa=0b0, dme=0bx, dor=0bx in dc register). note the readi module will ignore any incoming dsdi data messages when the module is not configured for rcpu development access. 23.10.2.2 enabling background debug mode (bdm) via readi pins after rcpu development access has been enabled via the readi pins, debug mode is enabled by setting bits in the dc register (dpa=0b1, dme=0b1, dor=0b0). 23.10.2.3 entering background debug mode (bdm) via readi pins there are three ways to enter debug mode (provided debug mode has been enabled): 1. enter debug mode (halted state) out-of-system reset through readi module configuration. this is displayed in figure 23-81. 2. enter debug mode by downloading breakpoint instructions through rcpu development access when in non-debug (running) mode. 3. enter debug mode if an exception or interrupt occurs. when entering debug mode following an exception/breakpoint, the rcpu signals vfls[0:1] are equal to 0b11. this causes readi to send a bdm status message to the tool indicating that the rcpu has entered debug mode and is now expecting instructions from the readi pins. debug mode enabling through readi and entering debug mode out of system reset is done by setting the following bits in the dc register (dpa=0b1, dme=0b1, dor=0b1) during system reset. debug mode entry causes rcpu to halt. 23.10.2.4 non-debug mode access of rcpu development access the rcpu development access can be also be used while the rcpu is not halted (in debug mode). this feature is used to send in breakpoints or synchronization events to the rcpu. please refer to the rcpu reference manual for further details. non-debug mode access of rcpu development can be achieved by configuring the readi module to take control of rcpu development access during module configuration of the dc register (dpa=0b1, dme=0b0, dor=0bx). 23.10.2.5 rcpu development access flow diagram figure 23-80 has flow diagram describing how the rcpu development access can be achieved via readi pins. 23-92 mpc565/mpc566 reference manual motorola rcpu development access figure 23-80. rcpu development access flow diagram tool sends download request message and configures readi module (assign dpa, dme & dor, etc.) dpa=1 ? dsdi=1 (sync. self-clk mode) tool sends dsdi message device sends dsdo message no no yes yes (debug out-of-reset) (no debug out-of-reset) no device sends debug mode status ?bdm entry? (status bit = 1) bdm configuration out-of-reset generic rcpu development protocol tool asserts hreset tools negates hreset 16 clocks after receiving device ready negation to enter debug mode negation to not enter debug mode dor=1 ? yes yes (debug mode enabled) (debug mode not enabled) no dme=1 ? no (dev. (dev. port access via readi module)yes (dpa,dme,dor,etc.bitslocked) bdm entry? tool sends dsdi message device sends dsdo message bdm exit? debug mode not enalbed debug mode enabled (dme=0) (dme=1) tool asserts and negates rsti device sends did message (@ subsequent readi reset) (@ subsequent rcpu reset) *a* *b* *(exit loop via readi reset (*a*) or system reset (*b*)) device sends debug mode ?bdm exit? (status bit = 0) *(exit loop via readi reset (*a*)orvia system reset (*b*)) *(exit loop via readi system reset (*b*)) reset (*a*) or via dsdi=1 port access via bdm pins) (synch.self-clk mode) dsdi=1 (sync. self-clk mode) dsck=1 until 16 clocks after sreset dsck=0 within 8 clocks of sreset message status message motorola chapter 23. readi module 23-93 rcpu development access 23.10.3throughput the tool can send a dsdi data message into device upon the receipt of a dsdo data message as soon as the tool decodes the first two status bits of the dsdo data message just received and confirms valid data from the rcpu. an example throughput analysis is performed with the following assumptions: readi configuration of rcpu development access and debug mode is already entered through readi the module is configured for reduced port mode mcki running at 28 mhz mcko running at 56 mhz 56-mhz internal operation readi auxiliary input and output pins are free (not in middle of transmission) no delay from tool in responding ? tool keeps up with readi port tool reads the complete dsdo data message before shifting in dsdi data message 10 clocks estimated to format and encode/decode dsdi data and dsdo data messages within readi the dsdi data message is 41 bits (six bits of tcode and 35 bits of dsdi data.). it takes 41 clocks (41 bits / 1 mdi pins) to shift in the dsdi data message. it is estimated that readi will take approximately 10 clocks to decode the dsdi data message. after the message has been decoded, readi will take 35 clocks to serially shift in the 35 bits of dsdi data to the rcpu development port. hence, it takes a total of 86 clocks (41 + 10 + 35) to decode and shift in dsdi data from the tool to the rcpu development port. at 28 mhz, it translates to 3079 ns (35.8 x 81) to decode and shift in dsdi data to rcpu development port as dsdi bits are shifted into the rcpu development register, dsdo bits are shifted out from the same rcpu development register (dpdr) and these are captured by readi. it is estimated that readi will take approximately 10 clocks to encode the dsdo data. the dsdo message is 41 bits (6 bits of tcode and 35 bits of dsdo data). it will take 21 clocks (41 bits / 2 mdo pins) for readi to transmit this message. hence, it will take a total of 31 clocks (10 + 21) to encode the dsdo data message and shift out the dsdo data message to the tool. at 56 mhz, it will take 552 ns (17.8 x 31) to encode and shift out dsdo data to the tool. thus, it will take 3631 ns (3079 + 552) for one complete dsdi data and dsdo data messaging cycle. 23-94 mpc565/mpc566 reference manual motorola rcpu development access 23.10.4timing diagrams figure 23-81 shows the timing diagram of rcpu development access and entering debug mode out-of-system reset through readi. figure 23-81. rcpu development access timing diagram ? debug mode entry out-of-reset figure 23-82 shows the transmission sequence of dsdi/dsdo data messages. hreset sreset rsti msei mdi mseo mdo dc reg (bdm) config msg dsdi message bdm message entry dsdo message dsdo message dsdi message can be sent to device dsdo message indicates it is ready. is sent out. after tcode and 2 status bits in the tool negates system clocks after receiving device ready message sreset is negated by the mcu hreset at least 16 dev id message dc register config message (bdm) is sent in after dev id message is received by 1 2 3 4 6 5 dsdi message sent in after bdm message 7 (usiu drives) (tool drives) after some internal system clocks delay. (tool drives) tool. bdm is set based on readi module configuration and bdm entry message is sent out when vfls[0:1]=11. device sends out dev id message after negation of rsti device ready message tc = 18 tc = 56 dsdi message tc = 56 tc = 1 tc = 16 tc = 58 tc = 57 dsdo message tc = 57 bdm message exit tc = 58 motorola chapter 23. readi module 23-95 rcpu development access figure 23-82. transmission sequence of dsdx data messages figure 23-83. error message (invalid message) figure 23-84. dsdi data message (assert non-maskable breakpoint) tcode(6bits) header(3bits) data(7or32bits) 12 3 msb lsb msb lsb msb lsb tcode = 8 error code = 0b00100 (invalid message) don?t care data (idle clock) mcko mseo mdo[7:0] 00001000 00000001 00000000 mcki msei mdi[1:0] 00 10 11 11 11 10 11 11 00 don?t care data (idle clock) tcode = 56 (0x3b) header = (start=1, mode=1, control=1) data = 0b1011111 (assert non maskable breakpoint) 23-96 mpc565/mpc566 reference manual motorola power management figure 23-85. dsdi data message (cpu instruction ? rfi) figure 23-86. dsdo data message (cpu data out) 23.11 power management this section details the power management features of the readi module. the readi module is a development interface, and is not expected to function under normal (non-development) conditions. therefore power management is required to reduce and minimize power consumption during normal operation of the part. 23.11.1functional description the following are the candidates for power management: mcki msei mdi[1:0] 00 10 11 01 00 01 10 01 00 00 00 00 00 00 00 00 00 11 00 01 00 00 tcode = 56 (0x3b) header = (start=1, mode=0, control=0) data = 0x4c000064 (rfi instruction) don?t care data (idle clock) mcko mseo mdo[7:0] 11111110 00000001 10101010 01011110 00000001 00000000 tcode = 57 (0x3c) header = (start=0, mode=0, control=0) data = ff00aaf5 (cpu data out) don?t care data (idle clock) 00111001 motorola chapter 23. readi module 23-97 application notes 23.11.2low power modes when the mcu is in sleep, deep-sleep or low power-down mode, all internal clocks on the mcu are shut down, including the mcko. the mseo pin will be held negated. low power mode entry for the mcu will be held off until the readi module has transmitted all existing messages (in the queues and transmit buffers). during this time, input messages from the development tool are ignored. upon restoration of clocks in normal mode, program and data traces will be synchronized, if enabled. 23.12 application notes this section describes application notes for readi. 23.12.1automotive calibration readi has features that can be used for calibration tasks during automotive system development. the basic needs for automotive development tools are 1. to acquire, while running an engine or vehicle, crank shaft synchronous data relating to calibration factors as they are being used or modified during high speed transient events, with acceptable impact to the system under development. 2. to acquire, while running an engine or vehicle, time synchronous data relating to calibration factors as they are being used or modified during high speed transient events, with acceptable impact to the system under development. 3. to coherently modify table(s) of calibration constant with the engine control unit is running an engine or vehicle. 23.12.1.1 calibration variable acquisition calibration variable acquisition refers to the first two points listed in the basic needs for automotive development tools. readi supports calibration variable acquisition via data trace (read and write) messaging and read/write access. table 23-35. power management mechanism overview feature power saving mechanism disabled mode if evti is negated at negation of rsti , the readi module will be disabled. no trace output will be provided, and output auxiliary port will be three-stated. sleep, deep-sleep and low power-down mode all outputs will be held static. readi reset (rsti ) output auxiliary pins will be three-stated. 23-98 mpc565/mpc566 reference manual motorola application notes requirements for measurement: time synchronous as well as engine synchronous selection of values must be flexible data to be measured (minimum) ? 29 values engine speed synchronous ? 45 values 10 ms synchronous ? 45 values 100 ms synchronous minimal interrupt load minimal impact to system 23.12.2calibration variables located in contiguous memory locations 23.12.2.1 data read messaging calibration variables located in two contiguous memory (ram) locations can be acquired using data read messaging. the software routines must read these variables for them to be traced and messaged via the readi port. readi queue sizes and readi port throughput will require few clocks between the individual ?reads? of the variables, otherwise information will be lost. drm is accomplished by snooping the l-bus hence there is no impact to the rcpu performance. 23.12.2.2 read/write access in case the throughput requirements for data traces are not acceptable, block read/write access should be used to load the variables from the calibration memory. this method may be more preferable because it is more likely to be synchronized and coherent data for multiple task scenarios. the disadvantage of using read/write access is the impact it has on rcpu performance. block word read accesses can be done on the l-bus every 13 clocks. if the block word read accesses happen to be overlapped with a block access via the rcpu, the maximum intrusion will be 7.7%. motorola chapter 23. readi module 23-99 application notes 23.12.3calibration variables not located in contiguous memory locations 23.12.3.1 data write messaging option a: if calibration variables are not located in contiguous memory locations, then a contiguous section of the ram can be reserved for variable acquisition tracing. at engine/time synchronous points, the software can write these contiguous locations with the values of the variables. this activity will be traced and messaged out data write messaging. this method requires a ?shadow? location for each word being monitored. a load and a store will be required for each variable to update the shadow locations, which are traced. readi queue sizes and ieee-isto 5001 port throughput will require few clocks between the individual ?writes? of the variables. this could be achieved by adding a few ?nop? instructions. option b: another possibility is to allocate a (single/few) word(s) in the ram that are configured to be traced by the readi module. then at engine/time synchronous points, the software will write the values of a series of variables to a corresponding location. this activity will be traced and messaged out data write messaging. this method requires a ?shadow? location, for each series (of related) variables or channels, in the ram. a load and a store will be required for each variable to update the shadow locations, which are traced. the 1st write to the location could be a byte which indicates the channel number. the calibration tool then will not be required to know the address translation for channel information. the advantage of using this option is that fewer locations need to be reserved in memory for measurement and the data trace messages are smaller, since a whole table (45 values) may be written to the same location. the disadvantage of using this option is that the calibration tool needs to be aware of which series a particular location represents, and the order in which the values are written. readi queue sizes and readi port throughput will require few clocks between the individual ?writes? of the variables. this could be achieved by adding a few ?nop? instructions. 23-100 mpc565/mpc566 reference manual motorola application notes 23.12.3.2 read/write access in case the throughput requirements for block data traces are not acceptable, read/write access should be used to load the variables from the calibration memory. option a: block read access this method calls for setting aside some memory (~ 1-kbyte ram locations) for calibration variable measurement. when the software tasks that modify the variables are completed, they will copy the variables into contiguous locations in this reserved space. then the tasks will indicate to the external tool that the variables are valid by any of various means (write keyword to special address, watchpoint etc.). the calibration tool will then proceed to read the variables corresponding to the channel completed using the block read access feature. this method may be more preferable because it is more likely to be synchronized and coherent data for multiple task scenarios. the disadvantage of using block read access is the impact it has on rcpu performance. block word read accesses can be done on the l-bus every 13 clocks. if the block word read accesses happen to be overlapped with a block access via the rcpu, the maximum intrusion will be 7.7%. option b: single read access single read accesses can also be used to acquire calibration variables which are not located in contiguous memory locations. single read accesses also have an the impact on rcpu performance. single word read accesses can be done on the l-bus every 74 clocks. if single word read accesses happen to be overlapped with a block access via the rcpu, the maximum intrusion will be 1.3%. this is significantly better when compared to block read accesses (7.7%). the disadvantage of using single read access the data trace throughput. for single read accesses, 0.41 million words can be messaged out via the readi port, whereas for block read accesses, approximately 4 million words can be messaged out via the readi port. 23.12.3.3 calibration constant tuning calibration constant tuning refers to the third basic requirement for automotive development tools. readi supports calibration constant tuning via the read/write access feature. the read/write access protocol provides run-time access to mcu registers and memory map. readi implements the run-time read/write access feature via two mdi pins and eight mdo pins or one mdi pin and two mdo pins. motorola chapter 23. readi module 23-101 application notes read/write accesses can be either single or block write accesses. if the calibration constants that need to be modified are located in contiguous memory locations, the block write access feature should be used. the disadvantage of using read/write access is the impact it has on rcpu performance. block write accesses can be done on the l-bus every 26 clocks. if the block write happens to be overlapped with a block access via the rcpu, the maximum intrusion will be 3.9%. 23.12.4uc3f programming guideline flowchart via readi read/write access the user can use readi features such as read/write access or rcpu development access to program the uc3f. for details on how the uc3f can be programmed via readi read/write access, refer to figure 23-87 and figure 23-88. 23-102 mpc565/mpc566 reference manual motorola application notes figure 23-87. programming uc3f flash via readi r/w access (sheet 1 of 2) tool asserts evti ,rsti and hreset tool asserts evti 4 clocks prior to the negation of rsti to enable readi module tool negates rsti epee pin = 1 (for program/erase mode) device sends out did message r/w access to c3fmcr register to clear protect field array block to be programmed, ses=1 and pe=0. tool negates hreset r/w access to c3fctl register to write block field to select the r/w access to send address and data to be programmed r/w access to c3fctl register to write ehv=1 to enable high voltage r/w access to read c3fctl register hvs = 0 ? yes no - check hvs=0 - confirm pegood=1 r/w access to c3fctl register to write ehv=0 program ? r/w access to c3fctl register to write ses=0 start end/epee pin = 0/reset yes no program/erase ? program erase b a c3f programming flow readi dc register configuration to enter bdm (bdm entry will halt cpu) device sends out bdm entry message motorola chapter 23. readi module 23-103 application notes figure 23-88. programming uc3f flash via readi r/w access (sheet 2 of 2) block to be erased, ses=1 and pe=1. r/w access to c3fctl register to write block field to select the r/w access to c3fctl register to write ehv=1 to enable high voltage r/w access to read c3fctl register hvs = 0 ? yes no - check hvs=0 - confirm pegood=1 r/w access to c3fctl register to write ehv=0 r/w access to c3fctl register to write ses=0 b a c3f erase flow r/w access to send address and data write to any location. this is an erase interlock write to any c3f array location to perform the erase operation. 23-104 mpc565/mpc566 reference manual motorola application notes motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-1 chapter 24 ieee 1149.1-compliant interface (jtag) 24.1 ieee 1149.1 test access port (tap) and joint test action group (jtag) the chip design includes user-accessible test logic that is compatible with the ieee 1149.1-1994 standard test access port and boundary scan architecture.the implementation supports circuit-board test strategies based on this standard. an overview of the pins requirement on jtag is shown: figure 24-1. pin requirement on jtag 24.2 ieee 1149.1 test access port the mpc565/mpc566 provides a dedicated user-accessible test access port (tap) that is compatible with the ieee 1149.1 standard test access port and boundary scan architecture in all but 2 areas listed below. problems associated with testing high density circuit boards have led to development of this proposed standard under the sponsorship of the test technology committee of ieee and the joint test action group (jtag). the mpc565/mpc566 implementation supports circuit-board test strategies based on this standard. tap bsc bsc bsc bsc bsc bsc bsc bsc bsc bsc bsc tdi tck tmb trst tdo mpc565/mpc566 24-2 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port ieee1149.1 compatibility exceptions the mpc565 enters jtag mode by going through a standard device reset sequence with a specific configuration word applied to the databus. once jtag has been entered, the mpc565 remains in jtag mode until another reset sequence is applied to exit jtag mode, or the device is powered down. the jtag output port, ?tdo_dsdo? is configured with a weak pull-up when its output drivers are disabled, rather than being tri-stated. the tap consists of five dedicated signal pins, a 16-state tap controller, and two test data registers. a boundary scan register links all device signal pins into a single shift register. the test logic implemented utilizes static logic design. the mpc565/mpc566 implementation provides the capability to: 1. perform boundary scan operations to test circuit-board electrical continuity. 2. bypass the mpc565/mpc566 for a given circuit-board test by effectively reducing the boundary scan register to a single cell. 3. sample the mpc565/mpc566 system pins during operation and transparently shift out the result in the boundary scan register. 4. disable the output drive to pins during circuit-board testing. note certain precautions must be observed to ensure that the ieee 1149.-like test logic does not interfere with nontest operation. see section 24.3.1, ?non-scan chain operation? for details. 24.2.1 overview an overview of the mpc565/mpc566 scan chain implementation is shown in figure 24-2. the mpc565/mpc566 implementation includes a tap controller, a 4-bit instruction register, and two test registers (a one-bit bypass register and a 520-bit boundary scan register). this implementation includes a dedicated tap consisting of the following signals: tck ? a test clock input to synchronize the test logic. (with an internal pull-down resistor) tms ? a test mode select input (with an internal pullup resistor) that is sampled on the rising edge of tck to sequence the tap controller?s state machine. tdi ? a test data input (with an internal pullup resistor) that is sampled on the rising edge of tck. tdo ? a three-state test data output that is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. (this pin also has a weak pull-up that is active when output drivers are disabled, except during a hi-z instruction). motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-3 ieee 1149.1 test access port trst ? an asynchronous reset with an internal pull-up resistor that provides initialization of the tap controller and other logic required by the standard. jcomp ? this signal enables the ieee1149.1 jtag circuitry in the mpc565/mpc566. this pin was trst on the k85h mask set of the mpc566. note jtag mode does not provide access to the internal mpc565/mpc566 circuitry. it allows access only to the input or output pad (periphery) circuitry figure 24-2. test logic block diagram 24.2.1.1 tap controller the tap controller is responsible for interpreting the sequence of logical values on the tms signal. it is a synchronous state machine that controls the operation of the jtag logic. boundary scan register bypass m u x instruction apply & decode register 4-bit instruction register m u x tdo tdi tms tck trst 0 1 2 tap controller 3 poreset 24-4 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port the state machine is shown in figure 24-3. the value shown adjacent to each arc represents the value of the tms signal sampled on the rising edge of the tck signal. figure 24-3. tap controller state machine 24.2.1.2 boundary scan register the mpc565/mpc566 scan chain implementation has a 520-bit boundary scan register. this register contains bits for most device signals, clock pins and associated control signals. the xtal, extal and xfc pins are associated with analog signals and are not included in the boundary scan register. the poreset ,hreset , and sreset pins are also excluded from the boundary scan register. test logic reset run-test/idle select-dr_scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir_scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 00 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-5 ieee 1149.1 test access port the 520-bit boundary scan register can be connected between tdi and tdo by selecting the extest or sample/preload instructions. this register is used to capturing signal pin data on the input pins, forcing fixed values on the output signal pins, and selecting the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state signal pins. the key to using the boundary scan register is knowing the boundary scan bit order and the pins that are associated with them. table 24-1 shows the bit order starting from the tdo output and going to the tdi input. table 24-1. boundary scan bit definition bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type 0 bc_2 * internal 1 1 bc_2 mdo_2 output2 1 o 26v 2 bc_2 * internal 1 3 bc_2 mdo_3 output2 1 o 26v 4 bc_2 * internal 1 5 bc_2 mseo_b output2 1 o 26v 6 bc_2 * internal 1 7 bc_2 iwp0_vfls0 output2 1 o 26v 8 bc_2 * internal 1 9 bc_2 iwp1_vfls1 output2 1 o 26v 10 bc_2 * controlr 0 11 bc_7 addr_sgpioa(16) bidir 0 10 0 z i/o 26v5vs 12 bc_2 * controlr 0 13 bc_7 addr_sgpioa(17) bidir 0 12 0 z i/o 26v5vs 14 bc_2 * controlr 0 15 bc_7 sgpioc6_frz_ptr_b bidir 0 14 0 z i/o 26v5vs 16 bc_2 * controlr 0 17 bc_7 addr_sgpioa(8) bidir 0 16 0 z i/o 26v5vs 18 bc_2 * controlr 0 19 bc_7 addr_sgpioa(18) bidir 0 18 0 z i/o 26v5vs 20 bc_2 * controlr 0 21 bc_7 addr_sgpioa(19) bidir 0 20 0 z i/o 26v5vs 22 bc_2 * controlr 0 23 bc_7 addr_sgpioa(9) bidir 0 22 0 z i/o 26v5vs 24 bc_2 * controlr 0 24-6 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port 25 bc_7 addr_sgpioa(10) bidir 0 24 0 z i/o 26v5vs 26 bc_2 * controlr 0 27 bc_7 addr_sgpioa(20) bidir 0 26 0 z i/o 26v6vs 28 bc_2 * controlr 0 29 bc_7 addr_sgpioa(21) bidir 0 28 0 z i/o 26v5vs 30 bc_2 * controlr 0 31 bc_7 addr_sgpioa(11) bidir 0 30 0 z i/o 26v5vs 32 bc_2 * controlr 0 33 bc_7 addr_sgpioa(12) bidir 0 32 0 z i/o 26v5vs 34 bc_2 * controlr 0 35 bc_7 addr_sgpioa(22) bidir 0 34 0 z i/o 26v5vs 36 bc_2 * controlr 0 37 bc_7 addr_sgpioa(23) bidir 0 36 0 z i/o 26v5vs 38 bc_2 * controlr 0 39 bc_7 addr_sgpioa(13) bidir 0 38 0 z i/o 26v5vs 40 bc_2 * controlr 0 41 bc_7 addr_sgpioa(24) bidir 0 40 0 z i/o 26v5vs 42 bc_2 * controlr 0 43 bc_7 addr_sgpioa(25) bidir 0 42 0 z i/o 26v5vs 44 bc_2 * controlr 0 45 bc_7 addr_sgpioa(14) bidir 0 44 0 z i/o 26v5vs 46 bc_2 * controlr 0 47 bc_7 addr_sgpioa(15) bidir 0 46 0 z i/o 26v5vs 48 bc_2 * controlr 0 49 bc_7 addr_sgpioa(30) bidir 0 48 0 z i/o 26v5vs 50 bc_2 * controlr 0 51 bc_7 addr_sgpioa(26) bidir 0 50 0 z i/o 26v5vs 52 bc_2 * controlr 0 53 bc_7 addr_sgpioa(27) bidir 0 52 0 z i/o 26v5vs 54 bc_2 * controlr 0 55 bc_7 addr_sgpioa(31) bidir 0 54 0 z i/o 26v5vs 56 bc_2 * controlr 0 57 bc_7 addr_sgpioa(28) bidir 0 56 0 z i/o 26v5vs table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-7 ieee 1149.1 test access port 58 bc_2 * controlr 0 59 bc_7 addr_sgpioa(29) bidir 0 58 0 z i/o 26v5vs 60 bc_2 * controlr 0 61 bc_7 data_sgpiod(0) bidir 0 60 0 z i/o 26v5vs 62 bc_2 * controlr 0 63 bc_7 data_sgpiod(29) bidir 0 62 0 z i/o 26v5vs 64 bc_2 * controlr 0 65 bc_7 data_sgpiod(1) bidir 0 64 0 z i/o 26v5vs 66 bc_2 * controlr 0 67 bc_7 data_sgpiod(2) bidir 0 66 0 z i/o 26v5vs 68 bc_2 * controlr 0 69 bc_7 data_sgpiod(3) bidir 0 68 0 z i/o 26v5vs 70 bc_2 * controlr 0 71 bc_7 data_sgpiod(27) bidir 0 70 0 z i/o 26v5vs 72 bc_2 * controlr 0 73 bc_7 data_sgpiod(4) bidir 0 72 0 z i/o 26v5vs 74 bc_2 * controlr 0 75 bc_7 data_sgpiod(28) bidir 0 74 0 z i/o 26v5vs 76 bc_2 * controlr 0 77 bc_7 data_sgpiod(31) bidir 0 76 0 z i/o 26v5vs 78 bc_2 * controlr 0 79 bc_7 data_sgpiod(5) bidir 0 78 0 z i/o 26v5vs 80 bc_2 * controlr 0 81 bc_7 data_sgpiod(6) bidir 0 80 0 z i/o 26v5vs 82 bc_2 * controlr 0 83 bc_7 data_sgpiod(30) bidir 0 82 0 z i/o 26v5vs 84 bc_2 * controlr 0 85 bc_7 data_sgpiod(7) bidir 0 84 0 z i/o 26v5vs 86 bc_2 * controlr 0 87 bc_7 data_sgpiod(25) bidir 0 86 0 z i/o 26v5vs 88 bc_2 * controlr 0 89 bc_7 data_sgpiod(8) bidir 0 88 0 z i/o 26v5vs 90 bc_2 * controlr 0 table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type 24-8 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port 91 bc_7 data_sgpiod(24) bidir 0 90 0 z i/o 26v5vs 92 bc_2 * controlr 0 93 bc_7 data_sgpiod(9) bidir 0 92 0 z i/o 26v5vs 94 bc_2 * controlr 0 95 bc_7 data_sgpiod(10) bidir 0 94 0 z i/o 26v5vs 96 bc_2 * controlr 0 97 bc_7 data_sgpiod(26) bidir 0 96 0 z i/o 26v5vs 98 bc_2 * controlr 0 99 bc_7 data_sgpiod(22) bidir 0 98 0 z i/o 26v5vs 100 bc_2 * controlr 0 101 bc_7 data_sgpiod(11) bidir 0 100 0 z i/o 26v5vs 102 bc_2 * controlr 0 103 bc_7 data_sgpiod(12) bidir 0 102 0 z i/o 26v5vs 104 bc_2 * controlr 0 105 bc_7 data_sgpiod(13) bidir 0 104 0 z i/o 26v5vs 106 bc_2 * controlr 0 107 bc_7 data_sgpiod(20) bidir 0 106 0 z i/o 26v5vs 108 bc_2 * controlr 0 109 bc_7 data_sgpiod(14) bidir 0 108 0 z i/o 26v5vs 110 bc_2 * controlr 0 111 bc_7 data_sgpiod(23) bidir 0 110 0 z i/o 26v5vs 112 bc_2 * controlr 0 113 bc_7 data_sgpiod(15) bidir 0 112 0 z i/o 26v5vs 114 bc_2 * controlr 0 115 bc_7 data_sgpiod(16) bidir 0 114 0 z i/o 26v5vs 116 bc_2 * controlr 0 117 bc_7 data_sgpiod(21) bidir 0 116 0 z i/o 26v5vs 118 bc_2 * controlr 0 119 bc_7 data_sgpiod(17) bidir 0 118 0 z i/o 26v5vs 120 bc_2 * controlr 0 121 bc_7 data_sgpiod(18) bidir 0 120 0 z i/o 26v5vs 122 bc_2 * controlr 0 123 bc_7 data_sgpiod(19) bidir 0 122 0 z i/o 26v5vs table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-9 ieee 1149.1 test access port 124 bc_2 * controlr 0 125 bc_7 irq3_b_kr_b_retry_b_ sgpioc3 bidir 0 124 0 z i/o 26v5vs 126 bc_2 * controlr 0 127 bc_7 irq4_b_at2_sgpioc4 bidir 0 126 0 z i/o 26v5vs 128 bc_2 * controlr 0 129 bc_7 irq1_b_rsv_b_sgpioc 1 bidir 0 128 0 z i/o 26v5vs 130 bc_2 * controlr 0 131 bc_7 sgpioc7_irqout_b_lw p0 bidir 0 130 0 z i/o 26v5vs 132 bc_2 * controlr 0 133 bc_7 bb_b_vf2_iwp3 bidir 0 132 0 z i/o 26v 134 bc_2 * controlr 0 135 bc_7 bg_b_vf0_lwp1 bidir 0 134 0 z i/o 26v 136 bc_2 * controlr 0 137 bc_7 br_b_vf1_iwp2 bidir 0 136 0 z i/o 26v 138 bc_2 * controlr 0 139 bc_7 rd_wr_b bidir 0 138 0 z i/o 26v 140 bc_2 * internal 1 141 bc_2 oe_b output2 1 o 26v 142 bc_2 * controlr 0 143 bc_7 tea_b bidir 0 142 0 z o 26v 144 bc_2 * controlr 0 145 bc_7 irq2_b_cr_b_sgpioc2 bidir 0 144 0 z i/o 26v5vs 146 bc_2 * controlr 0 147 bc_7 irq0_b_sgpioc0 bidir 0 146 0 z i/o 26v5vs 148 bc_2 * internal 1 149 bc_2 we_b_at(0) output2 1 o 26v 150 bc_2 * internal 1 151 bc_2 we_b_at(1) output2 1 o 26v 152 bc_2 * internal 1 153 bc_2 we_b_at(2) output2 1 o 26v 154 bc_2 * internal 1 table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type 24-10 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port 155 bc_2 we_b_at(3) output2 1 o 26v 156 bc_2 * internal 1 157 bc_2 cs0_b output2 1 o 26v 158 bc_2 * internal 1 159 bc_2 cs1_b output2 1 o 26v 160 bc_2 * internal 1 161 bc_2 cs2_b output2 1 o 26v 162 bc_2 * internal 1 163 bc_2 cs3_b output2 1 o 26v 164 bc_2 * controlr 0 165 bc_7 burst_b bidir 0 164 0 z i/o 26v 166 bc_2 * controlr 0 167 bc_7 bi_b_sts_b bidir 0 166 0 z i/o 26v 168 bc_2 * controlr 0 169 bc_7 tsiz0 bidir 0 168 0 z i/o 26v 170 bc_2 * controlr 0 171 bc_7 tsiz1 bidir 0 170 0 z i/o 26v 172 bc_2 * controlr 0 173 bc_7 ts_b bidir 0 172 0 z i/o 26v 174 bc_2 * controlr 0 175 bc_7 ta_b bidir 0 174 0 z i/o 26v 176 bc_2 * controlr 0 177 bc_7 bdip_b bidir 0 176 0 z i/o 26v 178 bc_2 * internal 0 179 bc_4 b0epee input x i 26v 180 bc_2 * internal 0 181 bc_4 epee input x i 26v 182 bc_2 * internal 1 183 bc_2 clkout output2 1 i/o 26vf 184 bc_2 * internal 1 185 bc_2 engclk_buclk output2 1 o 26vs5vr 186 bc_2 * controlr 0 table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-11 ieee 1149.1 test access port 187 bc_7 irq5_b_sgpioc5_mod ck1 bidir 0 186 0 z i/o 26v 188 bc_2 * controlr 0 189 bc_7 irq6_b_modck2 bidir 0 188 0 z i 26v 190 bc_2 * controlr 0 191 bc_7 irq7_b_modck3 bidir 0 190 0 z i 26v 192 bc_2 * controlr 0 193 bc_7 rstconf_b_texp bidir 0 192 0 z i/o 26v 194 bc_4 extclk input x i extclk 195 bc_2 * controlr 0 196 bc_7 a_cnrx0 bidir 0 195 0 z i 5vsa 197 bc_2 * internal 1 198 bc_2 a_cntx0 output2 1 o 5vfa 199 bc_2 * controlr 0 200 bc_7 a_pcs0_ss_b_qgpio0 bidir 0 199 0 z i/o 5vfa 201 bc_2 * internal 0 202 bc_4 a_eck input x i 5vfa 203 bc_2 * controlr 0 204 bc_7 a_pcs1_qgpio1 bidir 0 203 0 z i/o 5vfa 205 bc_2 * internal 1 206 bc_2 a_txd2_qgpo2 output2 1 o 5vfa 207 bc_2 * controlr 0 208 bc_7 a_pcs2_qgpio2 bidir 0 207 0 z i/o 5vfa 209 bc_4 a_rxd2_qgpi2 input x i 5vido 210 bc_4 b_rxd1_qgpi1 input x i 5vido 211 bc_4 a_rxd1_qgpi1 input x i 5vido 212 bc_2 * controlr 0 213 bc_7 a_mosi_qgpio5 bidir 0 212 0 z i/o 5vh 214 bc_2 * controlr 0 215 bc_7 a_pcs3_qgpio3 bidir 0 214 0 z i/o 5vfa 216 bc_2 * controlr 0 217 bc_7 a_miso_qgpio4 bidir 0 216 0 z i/o 5vh 218 bc_2 * controlr 0 table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type 24-12 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port 219 bc_7 a_sck_qgpio6 bidir 0 218 0 z i/o 5vh 220 bc_2 * controlr 0 221 bc_7 b_pcs2_qgpio2 bidir 0 220 0 z i/o 5vfa 222 bc_2 * internal 0 223 bc_4 b_rxd2_j1850_rx input x i 5vsa 224 bc_2 * internal 1 225 bc_2 a_txd1_qgpo1 output2 1 o 5vsa 226 bc_2 * internal 1 227 bc_2 b_txd2_qgpo2 output2 1 o 5vsa 228 bc_2 * internal 1 229 bc_2 b_txd1_qgpo1 output2 1 o 5vsa 230 bc_2 * internal 0 231 bc_4 b_eck input x i 5vsa 232 bc_2 * controlr 0 233 bc_7 b_sck_qgpio6 bidir 0 232 0 z i/o 5vh 234 bc_2 * controlr 0 235 bc_7 b_mosi_qgpio5 bidir 0 234 0 z i/o 5vh 236 bc_2 * controlr 0 237 bc_7 b_miso_qgpio4 bidir 0 236 0 z i/o 5vh 238 bc_2 * controlr 0 239 bc_7 b_pcs3_j1850_tx bidir 0 238 0 z o 5vfa 240 bc_2 * controlr 0 241 bc_7 b_pcs1_qgpio1 bidir 0 240 0 z i/o 5vfa 242 bc_2 * controlr 0 243 bc_7 b_pcs0_ss_b_qgpio0 bidir 0 242 0 z i/o 5vfa 244 bc_2 * controlr 0 245 bc_7 vfls1_mpio32b4 bidir 0 244 0 z i/o 26v5vs 246 bc_2 * controlr 0 247 bc_7 vfls0_mpio32b3 bidir 0 246 0 z i/o 26v5vs 248 bc_2 * controlr 0 249 bc_7 vf2_mpio32b2 bidir 0 248 0 z i/o 26v5vs 250 bc_2 * controlr 0 251 bc_7 vf1_mpio32b1 bidir 0 250 0 z i/o 26v5vs table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-13 ieee 1149.1 test access port 252 bc_2 * controlr 0 253 bc_7 vf0_mpio32b0 bidir 0 252 0 z i/o 26v5vs 254 bc_2 * controlr 0 255 bc_7 mpwm4_mpio32b5 bidir 0 254 0 z i/o 5vsa 256 bc_2 * controlr 0 257 bc_7 mpwm19 bidir 0 256 0 z i/o 5vsa 258 bc_2 * controlr 0 259 bc_7 mpio32b15 bidir 0 258 0 z i/o 5vsa 260 bc_2 * controlr 0 261 bc_7 c_cnrx0_mpio32b14 bidir 0 260 0 z i/o 5vsa 262 bc_2 * controlr 0 263 bc_7 c_cntx0_mpio32b13 bidir 0 262 0 z i/o 5vfa 264 bc_2 * controlr 0 265 bc_7 mpwm21_mpio32b12 bidir 0 264 0 z i/o 5vsa 266 bc_2 * controlr 0 267 bc_7 mpwm20_mpio32b11 bidir 0 266 0 z i/o 5vsa 268 bc_2 * controlr 0 269 bc_7 mda15 bidir 0 268 0 z i/o 5vsa 270 bc_2 * controlr 0 271 bc_7 mda14 bidir 0 270 0 z i/o 5vsa 272 bc_2 * controlr 0 273 bc_7 mpwm16 bidir 0 272 0 z i/o 5vsa 274 bc_2 * controlr 0 275 bc_7 mpwm3 bidir 0 274 0 z i/o 5vsa 276 bc_2 * controlr 0 277 bc_7 mpwm2 bidir 0 276 0 z i/o 5vsa 278 bc_2 * controlr 0 279 bc_7 mpwm1 bidir 0 278 0 z i/o 5vsa 280 bc_2 * controlr 0 281 bc_7 mpwm0 bidir 0 280 0 z i/o 5vsa 282 bc_2 * controlr 0 283 bc_7 mda31 bidir 0 282 0 z i/o 5vsa 284 bc_2 * controlr 0 table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type 24-14 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port 285 bc_7 mda30 bidir 0 284 0 z i/o 5vsa 286 bc_2 * controlr 0 287 bc_7 mda29 bidir 0 286 0 z i/o 5vsa 288 bc_2 * controlr 0 289 bc_7 mda28 bidir 0 288 0 z i/o 5vsa 290 bc_2 * controlr 0 291 bc_7 mda27 bidir 0 290 0 z i/o 5vsa 292 bc_2 * controlr 0 293 bc_7 mda13 bidir 0 292 0 z i/o 5vsa 294 bc_2 * controlr 0 295 bc_7 mda12 bidir 0 294 0 z i/o 5vsa 296 bc_2 * controlr 0 297 bc_7 mda11 bidir 0 296 0 z i/o 5vsa 298 bc_2 * controlr 0 299 bc_7 mpwm18 bidir 0 298 0 z i/o 5vsa 300 bc_2 * controlr 0 301 bc_7 mpwm17 bidir 0 300 0 z i/o 5vsa 302 bc_2 * controlr 0 303 bc_7 b_t2clk bidir 0 302 0 z i/o 5vsa 304 bc_2 * controlr 0 305 bc_7 b_tpuch1 bidir 0 304 0 z i/o 5vsa 306 bc_2 * controlr 0 307 bc_7 b_tpuch0 bidir 0 306 0 z i/o 5vsa 308 bc_2 * controlr 0 309 bc_7 mpwm5_mpio32b6 bidir 0 308 0 z i/o 5vsa 310 bc_2 * controlr 0 311 bc_7 b_tpuch2 bidir 0 310 0 z i/o 5vsa 312 bc_2 * controlr 0 313 bc_7 b_tpuch15 bidir 0 312 0 z i/o 5vsa 314 bc_2 * controlr 0 315 bc_7 b_tpuch14 bidir 0 314 0 z i/o 5vsa 316 bc_2 * controlr 0 317 bc_7 b_tpuch13 bidir 0 316 0 z i/o 5vsa table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-15 ieee 1149.1 test access port 318 bc_2 * controlr 0 319 bc_7 b_tpuch12 bidir 0 318 0 z i/o 5vsa 320 bc_2 * controlr 0 321 bc_7 b_tpuch11 bidir 0 320 0 z i/o 5vsa 322 bc_2 * controlr 0 323 bc_7 b_tpuch10 bidir 0 322 0 z i/o 5vsa 324 bc_2 * controlr 0 325 bc_7 b_tpuch9 bidir 0 324 0 z i/o 5vsa 326 bc_2 * controlr 0 327 bc_7 b_tpuch8 bidir 0 326 0 z i/o 5vsa 328 bc_2 * controlr 0 329 bc_7 b_tpuch7 bidir 0 328 0 z i/o 5vsa 330 bc_2 * controlr 0 331 bc_7 b_tpuch6 bidir 0 330 0 z i/o 5vsa 332 bc_2 * controlr 0 333 bc_7 b_tpuch5 bidir 0 332 0 z i/o 5vsa 334 bc_2 * controlr 0 335 bc_7 b_tpuch4 bidir 0 334 0 z i/o 5vsa 336 bc_2 * controlr 0 337 bc_7 b_tpuch3 bidir 0 336 0 z i/o 5vsa 338 bc_2 * controlr 0 339 bc_7 a_tpuch1 bidir 0 338 0 z i/o 5vsa 340 bc_2 * controlr 0 341 bc_7 a_tpuch0 bidir 0 340 0 z i/o 5vsa 342 bc_2 * controlr 0 343 bc_7 a_t2clk bidir 0 342 0 z i/o 5vsa 344 bc_2 * controlr 0 345 bc_7 a_tpuch15 bidir 0 344 0 z i/o 5vsa 346 bc_2 * controlr 0 347 bc_7 a_tpuch14 bidir 0 346 0 z i/o 5vsa 348 bc_2 * controlr 0 349 bc_7 a_tpuch13 bidir 0 348 0 z i/o 5vsa 350 bc_2 * controlr 0 table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type 24-16 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port 351 bc_7 a_tpuch12 bidir 0 350 0 z i/o 5vsa 352 bc_2 * controlr 0 353 bc_7 a_tpuch11 bidir 0 352 0 z i/o 5vsa 354 bc_2 * controlr 355 bc_7 a_tpuch10 bidir 0 354 0 z i/o 5vsa 356 bc_2 * controlr 0 357 bc_7 a_tpuch9 bidir 0 356 0 z i/o 5vsa 358 bc_2 * controlr 0 359 bc_7 a_tpuch8 bidir 0 358 0 z i/o 5vsa 360 bc_2 * controlr 0 361 bc_7 a_tpuch7 bidir 0 360 0 z i/o 5vsa 362 bc_2 * controlr 0 363 bc_7 a_tpuch6 bidir 0 362 0 z i/o 5vsa 364 bc_2 * controlr 0 365 bc_7 a_tpuch5 bidir 0 364 0 z i/o 5vsa 366 bc_2 * controlr 0 367 bc_7 a_tpuch4 bidir 0 366 0 z i/o 5vsa 368 bc_2 * controlr 0 369 bc_7 a_tpuch3 bidir 0 368 0 z i/o 5vsa 370 bc_2 * controlr 0 371 bc_7 a_tpuch2 bidir 0 370 0 z i/o 5vsa 372 bc_2 * internal 0 373 bc_4 etrig1 input x i 5vsa 374 bc_2 * internal 0 375 bc_4 etrig2 input x i 5vsa 376 bc_2 * controlr 0 377 bc_7 an64_b_pqb0 bidir 0 376 0 z i/o 5vsa 378 bc_2 * controlr 0 379 bc_7 an65_b_pqb1 bidir 0 378 0 z i/o 5vsa 380 bc_2 * controlr 0 381 bc_7 an66_b_pqb2 bidir 0 380 0 z i/o 5vsa 382 bc_2 * controlr 0 383 bc_7 an67_b_pqb3 bidir 0 382 0 z i/o 5vsa table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-17 ieee 1149.1 test access port 384 bc_2 * controlr 0 385 bc_7 an68_b_pqb4 bidir 0 384 0 z i/o 5vsa 386 bc_2 * controlr 0 387 bc_7 an69_b_pqb5 bidir 0 386 0 z i/o 5vsa 388 bc_2 * controlr 0 389 bc_7 an70_b_pqb6 bidir 0 388 0 z i/o 5vsa 390 bc_2 * controlr 0 391 bc_7 an71_b_pqb7 bidir 0 390 0 z i/o 5vsa 392 bc_2 * controlr 0 393 bc_7 an72_b_ma0_pqa0 bidir 0 392 0 z i/o 5vsa 394 bc_2 * controlr 0 395 bc_7 an73_b_ma1_pqa1 bidir 0 394 0 z i/o 5vsa 396 bc_2 * controlr 0 397 bc_7 an74_b_ma2_pqa2 bidir 0 396 0 z i/o 5vsa 398 bc_2 * controlr 0 399 bc_7 an75_b_pqa3 bidir 0 398 0 z i/o 5vsa 400 bc_2 * controlr 0 401 bc_7 an76_b_pqa4 bidir 0 400 0 z i/o 5vsa 402 bc_2 * controlr 0 403 bc_7 an77_b_pqa5 bidir 0 402 0 z i/o 5vsa 404 bc_2 * controlr 0 405 bc_7 an78_b_pqa6 bidir 0 404 0 z i/o 5vsa 406 bc_2 * controlr 0 407 bc_7 an79_b_pqa7 bidir 0 406 0 z i/o 5vsa 408 bc_2 * controlr 0 409 bc_7 an59_a_pqa7 bidir 0 408 0 z i/o 5vsa 410 bc_2 * controlr 0 411 bc_7 an58_a_pqa6 bidir 0 410 0 z i/o 5vsa 412 bc_2 * controlr 0 413 bc_7 an57_a_pqa5 bidir 0 412 0 z i/o 5vsa 414 bc_2 * controlr 0 415 bc_7 an56_a_pqa4 bidir 0 414 0 z i/o 5vsa 416 bc_2 * controlr 0 table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type 24-18 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port 417 bc_7 an55_a_pqa3 bidir 0 416 0 z i/o 5vsa 418 bc_2 * controlr 0 419 bc_7 an54_a_ma2_pqa2 bidir 0 418 0 z i/o 5vsa 420 bc_2 * controlr 0 421 bc_7 an53_a_ma1_pqa1 bidir 0 420 0 z i/o 5vsa 422 bc_2 * controlr 0 423 bc_7 an52_a_ma0_pqa0 bidir 0 422 0 z i/o 5vsa 424 bc_2 * controlr 0 425 bc_7 an51_a_pqb7 bidir 0 424 0 z i/o 5vsa 426 bc_2 * controlr 0 427 bc_7 an50_a_pqb6 bidir 0 426 0 z i/o 5vsa 428 bc_2 * controlr 0 429 bc_7 an49_a_pqb5 bidir 0 428 0 z i/o 5vsa 430 bc_2 * controlr 0 431 bc_7 an48_a_pqb4 bidir 0 430 0 z i/o 5vsa 432 bc_2 * controlr 0 433 bc_7 an47_anz_a_pqb3 bidir 0 432 0 z i/o 5vsa 434 bc_2 * controlr 0 435 bc_7 an46_any_a_pqb2 bidir 0 434 0 z i/o 5vsa 436 bc_2 * internal 0 437 bc_4 an80 input x i 5vsa 438 bc_2 * internal 0 439 bc_4 an81 input x i 5vsa 440 bc_2 * internal 0 441 bc_4 an82 input x i 5vsa 442 bc_2 * internal 0 443 bc_4 an83 input x i 5vsa 444 bc_2 * internal 0 445 bc_4 an84 input x i 5vsa 446 bc_2 * internal 0 447 bc_4 an85 input x i 5vsa 448 bc_2 * internal 0 449 bc_4 an86 input x i 5vsa table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-19 ieee 1149.1 test access port 450 bc_2 * internal 0 451 bc_4 an87 input x i 5vsa 452 bc_2 * controlr 0 453 bc_7 an45_anx_a_pqb1 bidir 0 452 0 z i/o 5vsa 454 bc_2 * controlr 0 455 bc_7 an44_anw_a_pqb0 bidir 0 454 0 z i/o 5vsa 456 bc_2 * controlr 0 457 bc_7 b_cnrx0 bidir 0 456 0 z i 5vsa 458 bc_2 * internal 1 459 bc_2 b_cntx0 output2 1 o 5vfa 460 bc_2 * controlr 0 461 bc_7 c_t2clk bidir 0 460 0 z i/o 5vsa 462 bc_2 * controlr 0 463 bc_7 c_tpuch15 bidir 0 462 0 z i/o 5vsa 464 bc_2 * controlr 0 465 bc_7 c_tpuch14 bidir 0 464 0 z i/o 5vsa 466 bc_2 * controlr 0 467 bc_7 c_tpuch13 bidir 0 466 0 z i/o 5vsa 468 bc_2 * controlr 0 469 bc_7 c_tpuch12 bidir 0 468 0 z i/o 5vsa 470 bc_2 * controlr 0 471 bc_7 c_tpuch11 bidir 0 470 0 z i/o 5vsa 472 bc_2 * controlr 0 473 bc_7 c_tpuch10 bidir 0 472 0 z i/o 5vsa 474 bc_2 * controlr 0 475 bc_7 c_tpuch9 bidir 0 474 0 z i/o 5vsa 476 bc_2 * controlr 0 477 bc_7 c_tpuch8 bidir 0 476 0 z i/o 5vsa 478 bc_2 * controlr 0 479 bc_7 c_tpuch7 bidir 0 478 0 z i/o 5vsa 480 bc_2 * controlr 0 481 bc_7 c_tpuch6 bidir 0 480 0 z i/o 5vsa 482 bc_2 * controlr 0 table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type 24-20 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port 483 bc_7 c_tpuch5 bidir 0 482 0 z i/o 5vsa 484 bc_2 * controlr 0 485 bc_7 c_tpuch4 bidir 0 484 0 z i/o 5vsa 486 bc_2 * controlr 0 487 bc_7 c_tpuch3 bidir 0 486 0 z i/o 5vsa 488 bc_2 * controlr 0 489 bc_7 c_tpuch2 bidir 0 488 0 z i/o 5vsa 490 bc_2 * controlr 0 491 bc_7 c_tpuch1 bidir 0 490 0 z i/o 5vsa 492 bc_2 * controlr 0 493 bc_7 c_tpuch0 bidir 0 492 0 z i/o 5vsa 494 bc_2 * controlr 495 bc_7 mcki bidir 0 494 0 z i 26v 496 bc_2 * controlr 0 497 bc_7 mdi_0 bidir 0 496 0 z i 26v 498 bc_2 * controlr 0 499 bc_7 mdi_1 bidir 0 498 0 z i 26v 500 bc_2 * controlr 0 501 bc_7 msei_b bidir 0 500 0 z i 26v 502 bc_2 * internal 1 503 bc_2 mdo_1 output2 1 o 26v 504 bc_2 * internal 1 505 bc_2 mdo_0 output2 1 o 26v 506 bc_2 * internal 1 507 bc_2 mcko output2 1 i/o 26v 508 bc_2 * controlr 0 509 bc_7 mdo_7_mpio32b7 bidir 0 508 0 z i/o 26v5vs 510 bc_2 * controlr 0 511 bc_7 mdo_6_mpio32b8 bidir 0 510 0 z i/o 26v5vs 512 bc_2 * controlr 0 513 bc_7 mdo_5_mpio32b9 bidir 0 512 0 z i/o 26v5vs 514 bc_2 * controlr 0 515 bc_7 mdo_4_mpio32b10 bidir 0 514 0 z i/o 26v5vs table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-21 ieee 1149.1 test access port 1.bi-state outputs (pin function = o) such as mdo_2, and mdo_3, are incorporated with general i/o pads hard-wired to keep output enable always on in system mode. the jtag control cell, indicated by the next lower bsdl bit in the chain, is configured as an ?internal? only cell to be held at a ?1? value (always driving out) during jtag testing. 2. some input-only cells made with generic i/o pads are configured with ?internal? control cells to keep them always in input mode, such as epee, b0epee, and input pins that may be attached to analog references. other input-only cells are configured as bidirectional for jtag testing, to give the board-level atpg tools the flexability to use the pad as an input or output, depending on the network of other devices that the pin is connected too. if it is desired to restrict these pins to only act as receivers during jtag mode, then these jtag bsdl entries can be converted as shown in the example below: 3. this description allows atpg tools to use a pin as a driver or receiver: 4. a modification to restrict atpg tools to use a functional input-only pin as an input receiver only: . 5. the poreset , hreset , and sreset pins are not part of the jtag boundary scan chain. these pins are used in the reset configuration to enter jtag. board-level connections to them will not be testable with the extest and clamp instructions. they do respond to the hi-z jtag instruction for parametric testing purposes.6. 6. the xtal, extal, and xfc pins are associated with analog signals and are excluded from the boundary scan chain. 7. the readi module reset pin, rsti_b, (bsdl pin 517) is in the jtag boundary scan chain, but must be kept at a ?0? level during jtag testing, (except for hi-z testing), due to system interactions. it is classified as a ?linkage? pin, and its data and control cells are configured to advise atpg tools to drive a ?0? value in during jtag testing. 8. pad type naming conventions: ?26v?2.6v ?5v?5v ?s?slow ?f?fast ?h?highdrive ? a ? analog input ? i ? input only ? d ? has direct connection to the pad (may be used for module test) ? r ? resized cell instance 9. column descriptions: ? columns 1 through 8 are entries from the boundary-scan description from the bsdl file. the columns and formats for each of these entries are defined in the ieee std. 1149.1b-1994 supplement to the 516 bc_2 * internal 0 517 bc_4 * [rsti_b force to 0] internal 0 i 26v 518 bc_2 * controlr 0 519 bc_7 evti_b bidir 0 518 0 z i 26v 188 bc_2 * controlr 0 189 bc_7 irq6_b_modck2 bidir 0 188 0 z i 26v 188 bc_2 * internal 0 189 bc_4 irq6_b_modck2 input x i 26v table 24-1. boundary scan bit definition (continued) bsdl bit cell type port name bsdl function saf. val. cnt. cell dis. val. rslt pin function pad type 24-22 mpc565/mpc566 reference manual motorola ieee 1149.1 test access port ieee std. 1149.1-1990, ieee standard test access port and boundary-scan architecture document. descriptions of these columns are described below: ? column 1: defines the bit?s ordinal position in the boundary scan register. the shift register cell nearest tdo (i.e., first to be shifted in) is defined as bit 0; the last bit to be shifted in is 519. ? column 2: references one of the three standard jtag cell types (bc_4, bc_2, and bc_7) that are used for this jtag cell in the mpc565/mpc566. see the ieee std. 1149.1-1990, ieee standard test access port and boundary-scan architecture document for further description of these standard cell types. ? column 3: lists the pin name (also called the portid) for all pin-related cells. for jtag control cells or data cells that have been designated as ?internal?, an asterisk, is shown in this column. ? column 4: lists the bsdl pin function. ? column 5: the ?safe bit? column specifies the value that should be loaded into the capture (and update) flip-flop of a given cell when board-level test generation software might otherwise choose a value randomly. ? column 6: the ?control cell? column identifies the cell number of the control cell that is associated with this data cell, and can disable its output. ? column 7: the ?disable value? column gives the value that must be scanned into the control cell identified by the previous ?control cell? (column 6) to disable the port named by the relevant portid. ? column 8: the ?disable result? column identifies a given signal value of the portid if that signal can be disabled. the values shown specifies the condition of the driver of that signal when it is disabled. ? column 9: the ?pin function? column indicates the normal system pin directionality. (? input only pin, o ? output only pin, i/o ? bidirectional i/o pin) ? column 10: the pad type column describes relevant characteristics about each pad type. see the pad type keys in note 5 above. 24.2.2 instruction register the mpc565/mpc566 jtag implementation includes the public instructions (extest, sample/preload, and bypass), and also supports the clamp instruction. one additional public instruction (hi-z) provides the capability for disabling all device output drivers. the mpc565/mpc566 includes a 4-bit instruction register without parity consisting of a shift register with four parallel outputs. data is transferred from the shift register to the parallel outputs during the update-ir controller state. the four bits are used to decode the five unique instructions listed in. note b0 (lsb) is shifted first. the parallel output of the instruction register is reset to all ones in the test-logic-reset controller state. table 24-2. instruction decoding code b3 b2 b1 b0 instruction 0000 extest 0001sample/preload 0 x 1 x bypass 0100 hi-z 0101clampandbypass motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-23 ieee 1149.1 test access port note this preset state is equivalent to the bypass instruction. during the capture-ir controller state, the parallel inputs to the instruction shift register are loaded with the clamp command code. 24.2.2.1 extest the external test (extest) instruction selects the 520-bit boundary scan register. extest also asserts internal reset for the mpc565/mpc566 system logic to force a predictable beginning internal state while performing external boundary scan operations. by using the tap, the register is capable of: a) scanning user-defined values into the output buffers b) capturing values presented to input pins c) controlling the output drive of three-state output or bidirectional pins 24.2.2.2 sample/preload the sample/preload instruction initializes the boundary scan register output cells prior to selection of extest. this initialization ensures that known data will appear on the outputs when entering the extest instruction. the sample/preload instruction also provides a means to obtain a snapshot of system data and control signals. note since there is no internal synchronization between the scan chain clock (tck) and the system clock (clkout), there must be provision of some form of external synchronization to achieve meaningful results. 24.2.2.3 bypass the bypass instruction selects the single-bit bypass register as shown in figure 24-4. this creates a shift register path from tdi to the bypass register and, finally, to tdo, circumventing the 520-bit boundary scan register. this instruction is used to enhance test efficiency when a component other than the mpc565/mpc566 becomes the device under test. 24-24 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions figure 24-4. bypass register when the bypass register is selected by the current instruction, the shift register stage is set to a logic zero on the rising edge of tck in the capture-dr controller state. therefore, the first bit to be shifted out after selecting the bypass register will always be a logic zero. 24.2.2.4 clamp the clamp instruction selects the single-bit bypass register as shown in figure 24-4, and the state of all signals driven from system output pins is completely defined by the data previously shifted into the boundary scan register (for example, using the sample/preload instruction). 24.2.3 hi-z the hi-z instruction is provided as a manufacturer?s optional public instruction to prevent having to backdrive the output pins during circuit-board testing. when hi-z is invoked, all output drivers, including the two-state drivers, are turned off (i.e., high impedance). the instruction selects the bypass register. 24.3 mpc565/mpc566 restrictions the control afforded by the output enable signals using the boundary scan register and the extest instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. the user must avoid situations in which the mpc565/mpc566 output drivers are enabled into actively driven networks. the mpc565/mpc566 features a low-power stop mode. the interaction of the scan chain interface with low-power stop mode is as follows: 1. the tap controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode. leaving the tap controller in the test-logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality. 2. the tck input is not blocked in low-power stop mode. to consume minimal power, the tck input should be externally connected to v dd or ground. 1 1 mux g1 c d to tdo from tdi 0 shift dr clock dr motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-25 mpc565/mpc566 restrictions 3. thetms,tdi,trst pins include on-chip pull-up resistors. in low-power stop mode, these three pins should remain either unconnected or connected to v dd to achieve minimal power consumption. note that for proper reset of the scan chain test logic, the best approach is to pull active trst at power on reset (poreset). 24.3.1 non-scan chain operation in non-scan chain operation, there are two constraints. first, the tck input does not include an internal pull-up resistor and should not be left unconnected to preclude mid-level inputs. the second constraint is to ensure that the scan chain test logic is kept transparent to the system logic by forcing tap into the test-logic-reset controller state, using either of two methods. connecting pin trst to logic 0 (or one of the reset pins), or tms must be sampled as a logic one for five consecutive tck rising edges. if then tms either remains unconnected or is connected to v dd , then the tap controller cannot leave the test-logic-reset state, regardless of the state of tck. 24-26 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions 24.3.2 motorola mpc565/mpc566 bsdl description entity spanishoak is generic(physical_pin_map: string := ?die?); port( a_cnrx0: inout bit; a_cntx0: buffer bit; a_eck: in bit; a_miso_qgpio4: inout bit; a_mosi_qgpio5: inout bit; a_pcs0_ss_b_qgpio0: inout bit; a_pcs1_qgpio1: inout bit; a_pcs2_qgpio2: inout bit; a_pcs3_qgpio3: inout bit; a_rxd1_qgpi1: in bit; a_rxd2_qgpi2: in bit; a_sck_qgpio6: inout bit; a_t2clk: inout bit; a_tpuch0: inout bit; a_tpuch1: inout bit; a_tpuch10: inout bit; a_tpuch11: inout bit; a_tpuch12: inout bit; a_tpuch13: inout bit; a_tpuch14: inout bit; a_tpuch15: inout bit; a_tpuch2: inout bit; a_tpuch3: inout bit; a_tpuch4: inout bit; a_tpuch5: inout bit; motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-27 mpc565/mpc566 restrictions a_tpuch6: inout bit; a_tpuch7: inout bit; a_tpuch8: inout bit; a_tpuch9: inout bit; a_txd1_qgpo1: buffer bit; a_txd2_qgpo2: buffer bit; addr_sgpioa: inout bit_vector(8 to 31); an44_anw_a_pqb0: inout bit; an45_anx_a_pqb1: inout bit; an46_any_a_pqb2: inout bit; an47_anz_a_pqb3: inout bit; an48_a_pqb4: inout bit; an49_a_pqb5: inout bit; an50_a_pqb6: inout bit; an51_a_pqb7: inout bit; an52_a_ma0_pqa0: inout bit; an53_a_ma1_pqa1: inout bit; an54_a_ma2_pqa2: inout bit; an55_a_pqa3: inout bit; an56_a_pqa4: inout bit; an57_a_pqa5: inout bit; an58_a_pqa6: inout bit; an59_a_pqa7: inout bit; an64_b_pqb0: inout bit; an65_b_pqb1: inout bit; an66_b_pqb2: inout bit; an67_b_pqb3: inout bit; an68_b_pqb4: inout bit; an69_b_pqb5: inout bit; an70_b_pqb6: inout bit; 24-28 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions an71_b_pqb7: inout bit; an72_b_ma0_pqa0: inout bit; an73_b_ma1_pqa1: inout bit; an74_b_ma2_pqa2: inout bit; an75_b_pqa3: inout bit; an76_b_pqa4: inout bit; an77_b_pqa5: inout bit; an78_b_pqa6: inout bit; an79_b_pqa7: inout bit; an80: in bit; an81: in bit; an82: in bit; an83: in bit; an84: in bit; an85: in bit; an86: in bit; an87: in bit; b0epee: in bit; b_cnrx0: inout bit; b_cntx0: buffer bit; b_eck: in bit; b_miso_qgpio4: inout bit; b_mosi_qgpio5: inout bit; b_pcs0_ss_b_qgpio0: inout bit; b_pcs1_qgpio1: inout bit; b_pcs2_qgpio2: inout bit; b_pcs3_j1850_tx: inout bit; b_rxd1_qgpi1: in bit; b_rxd2_j1850_rx: in bit; b_sck_qgpio6: inout bit; motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-29 mpc565/mpc566 restrictions b_t2clk: inout bit; b_tpuch0: inout bit; b_tpuch1: inout bit; b_tpuch10: inout bit; b_tpuch11: inout bit; b_tpuch12: inout bit; b_tpuch13: inout bit; b_tpuch14: inout bit; b_tpuch15: inout bit; b_tpuch2: inout bit; b_tpuch3: inout bit; b_tpuch4: inout bit; b_tpuch5: inout bit; b_tpuch6: inout bit; b_tpuch7: inout bit; b_tpuch8: inout bit; b_tpuch9: inout bit; b_txd1_qgpo1: buffer bit; b_txd2_qgpo2: buffer bit; bb_b_vf2_iwp3: inout bit; bdip_b: inout bit; bg_b_vf0_lwp1: inout bit; bi_b_sts_b: inout bit; br_b_vf1_iwp2: inout bit; burst_b: inout bit; c_cnrx0_mpio32b14: inout bit; c_cntx0_mpio32b13: inout bit; c_t2clk: inout bit; c_tpuch0: inout bit; c_tpuch1: inout bit; 24-30 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions c_tpuch10: inout bit; c_tpuch11: inout bit; c_tpuch12: inout bit; c_tpuch13: inout bit; c_tpuch14: inout bit; c_tpuch15: inout bit; c_tpuch2: inout bit; c_tpuch3: inout bit; c_tpuch4: inout bit; c_tpuch5: inout bit; c_tpuch6: inout bit; c_tpuch7: inout bit; c_tpuch8: inout bit; c_tpuch9: inout bit; clkout: buffer bit; clockout1: linkage bit; cs0_b: buffer bit; cs1_b: buffer bit; cs2_b: buffer bit; cs3_b: buffer bit; d_corner: linkage bit; data_sgpiod: inout bit_vector(0 to 31); engclk_buclk: buffer bit; epee: in bit; etrig1: in bit; etrig2: in bit; evti_b: inout bit; extal: linkage bit; extclk: in bit; hreset_b: linkage bit; motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-31 mpc565/mpc566 restrictions irq0_b_sgpioc0: inout bit; irq1_b_rsv_b_sgpioc1: inout bit; irq2_b_cr_b_sgpioc2: inout bit; irq3_b_kr_b_retry_b_sgpioc3: inout bit; irq4_b_at2_sgpioc4: inout bit; irq5_b_sgpioc5_modck1: inout bit; irq6_b_modck2: inout bit; irq7_b_modck3: inout bit; iwp0_vfls0: buffer bit; iwp1_vfls1: buffer bit; kapwr: linkage bit; l_corner: linkage bit; mcki: inout bit; mcko: buffer bit; mda11: inout bit; mda12: inout bit; mda13: inout bit; mda14: inout bit; mda15: inout bit; mda27: inout bit; mda28: inout bit; mda29: inout bit; mda30: inout bit; mda31: inout bit; mdi_0: inout bit; mdi_1: inout bit; mdo_0: buffer bit; mdo_1: buffer bit; mdo_2: buffer bit; mdo_3: buffer bit; 24-32 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions mdo_4_mpio32b10: inout bit; mdo_5_mpio32b9: inout bit; mdo_6_mpio32b8: inout bit; mdo_7_mpio32b7: inout bit; mpio32b15: inout bit; mpwm0: inout bit; mpwm1: inout bit; mpwm16: inout bit; mpwm17: inout bit; mpwm18: inout bit; mpwm19: inout bit; mpwm2: inout bit; mpwm20_mpio32b11: inout bit; mpwm21_mpio32b12: inout bit; mpwm3: inout bit; mpwm4_mpio32b5: inout bit; mpwm5_mpio32b6: inout bit; mrtc_extal32: linkage bit; mrtc_xtal32: linkage bit; msei_b: inout bit; mseo_b: buffer bit; nvddl: linkage bit_vector(1 to 19); oe_b: buffer bit; poreset_b: linkage bit; qvddl: linkage bit_vector(1 to 12); r_corner: linkage bit; rd_wr_b: inout bit; rstconf_b_texp: inout bit; rsti_b: linkage bit; sgpioc6_frz_ptr_b: inout bit; motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-33 mpc565/mpc566 restrictions sgpioc7_irqout_b_lwp0: inout bit; sreset_b: linkage bit; ta_b: inout bit; tck_dsck: in bit; tdi_dsdi: in bit; tdo_dsdo: out bit; tea_b: inout bit; tms: in bit; trst_b: in bit; ts_b: inout bit; tsiz0: inout bit; tsiz1: inout bit; u_corner: linkage bit; vdd: linkage bit_vector(1 to 6); vdda: linkage bit; vddf: linkage bit; vddh: linkage bit_vector(1 to 6); vddsram1: linkage bit; vddsram2: linkage bit; vddsram3: linkage bit; vddsyn: linkage bit; vddsyn32: linkage bit; vf0_mpio32b0: inout bit; vf1_mpio32b1: inout bit; vf2_mpio32b2: inout bit; vflash: linkage bit; vfls0_mpio32b3: inout bit; vfls1_mpio32b4: inout bit; vrh: linkage bit; vrhaltref: linkage bit; 24-34 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions vrl: linkage bit; vss: linkage bit_vector(1 to 28); vssa: linkage bit; vssf: linkage bit; vsssyn: linkage bit; vsssyn32: linkage bit; we_b_at: buffer bit_vector(0 to 3); xfc: linkage bit; xtal: linkage bit); use std_1149_1_1994.all; attribute component_conformance of spanishoak: entity is ?std_1149_1_1993?; -- complies with std. 1149.1a-1993 attribute pin_map of spanishoak: entity is physical_pin_map; constant die: pin_map_string := ?a_cnrx0:1,? & ?a_cntx0:2,? & ?a_eck:3,? & ?a_miso_qgpio4:4,? & ?a_mosi_qgpio5:5,? & ?a_pcs0_ss_b_qgpio0:6,? & ?a_pcs1_qgpio1:7,? & ?a_pcs2_qgpio2:8,? & ?a_pcs3_qgpio3:9,? & ?a_rxd1_qgpi1:10,? & ?a_rxd2_qgpi2:11,? & ?a_sck_qgpio6:12,? & ?a_t2clk:13,? & ?a_tpuch0:14,? & ?a_tpuch1:15,? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-35 mpc565/mpc566 restrictions ?a_tpuch10:16,? & ?a_tpuch11:17,? & ?a_tpuch12:18,? & ?a_tpuch13:19,? & ?a_tpuch14:20,? & ?a_tpuch15:21,? & ?a_tpuch2:22,? & ?a_tpuch3:23,? & ?a_tpuch4:24,? & ?a_tpuch5:25,? & ?a_tpuch6:26,? & ?a_tpuch7:27,? & ?a_tpuch8:28,? & ?a_tpuch9:29,? & ?a_txd1_qgpo1:30,? & ?a_txd2_qgpo2:31,? & ?addr_sgpioa:(32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,5 0,51,52,53,54,55),? & ?an44_anw_a_pqb0:56,? & ?an45_anx_a_pqb1:57,? & ?an46_any_a_pqb2:58,? & ?an47_anz_a_pqb3:59,? & ?an48_a_pqb4:60,? & ?an49_a_pqb5:61,? & ?an50_a_pqb6:62,? & ?an51_a_pqb7:63,? & ?an52_a_ma0_pqa0:64,? & ?an53_a_ma1_pqa1:65,? & ?an54_a_ma2_pqa2:66,? & 24-36 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?an55_a_pqa3:67,? & ?an56_a_pqa4:68,? & ?an57_a_pqa5:69,? & ?an58_a_pqa6:70,? & ?an59_a_pqa7:71,? & ?an64_b_pqb0:72,? & ?an65_b_pqb1:73,? & ?an66_b_pqb2:74,? & ?an67_b_pqb3:75,? & ?an68_b_pqb4:76,? & ?an69_b_pqb5:77,? & ?an70_b_pqb6:78,? & ?an71_b_pqb7:79,? & ?an72_b_ma0_pqa0:80,? & ?an73_b_ma1_pqa1:81,? & ?an74_b_ma2_pqa2:82,? & ?an75_b_pqa3:83,? & ?an76_b_pqa4:84,? & ?an77_b_pqa5:85,? & ?an78_b_pqa6:86,? & ?an79_b_pqa7:87,? & ?an80:88,? & ?an81:89,? & ?an82:90,? & ?an83:91,? & ?an84:92,? & ?an85:93,? & ?an86:94,? & ?an87:95,? & ?b0epee:96,? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-37 mpc565/mpc566 restrictions ?b_cnrx0:97,? & ?b_cntx0:98,? & ?b_eck:99,? & ?b_miso_qgpio4:100,? & ?b_mosi_qgpio5:101,? & ?b_pcs0_ss_b_qgpio0:102,? & ?b_pcs1_qgpio1:103,? & ?b_pcs2_qgpio2:104,? & ?b_pcs3_j1850_tx:105,? & ?b_rxd1_qgpi1:106,? & ?b_rxd2_j1850_rx:107,? & ?b_sck_qgpio6:108,? & ?b_t2clk:109,? & ?b_tpuch0:110,? & ?b_tpuch1:111,? & ?b_tpuch10:112,? & ?b_tpuch11:113,? & ?b_tpuch12:114,? & ?b_tpuch13:115,? & ?b_tpuch14:116,? & ?b_tpuch15:117,? & ?b_tpuch2:118,? & ?b_tpuch3:119,? & ?b_tpuch4:120,? & ?b_tpuch5:121,? & ?b_tpuch6:122,? & ?b_tpuch7:123,? & ?b_tpuch8:124,? & ?b_tpuch9:125,? & ?b_txd1_qgpo1:126,? & 24-38 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?b_txd2_qgpo2:127,? & ?bb_b_vf2_iwp3:128,? & ?bdip_b:129,? & ?bg_b_vf0_lwp1:130,? & ?bi_b_sts_b:131,? & ?br_b_vf1_iwp2:132,? & ?burst_b:133,? & ?c_cnrx0_mpio32b14:134,? & ?c_cntx0_mpio32b13:135,? & ?c_t2clk:136,? & ?c_tpuch0:137,? & ?c_tpuch1:138,? & ?c_tpuch10:139,? & ?c_tpuch11:140,? & ?c_tpuch12:141,? & ?c_tpuch13:142,? & ?c_tpuch14:143,? & ?c_tpuch15:144,? & ?c_tpuch2:145,? & ?c_tpuch3:146,? & ?c_tpuch4:147,? & ?c_tpuch5:148,? & ?c_tpuch6:149,? & ?c_tpuch7:150,? & ?c_tpuch8:151,? & ?c_tpuch9:152,? & ?clkout:153,? & ?clockout1:154,? & ?cs0_b:155,? & ?cs1_b:156,? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-39 mpc565/mpc566 restrictions ?cs2_b:157,? & ?cs3_b:158,? & ?d_corner:159,? & ?data_sgpiod:(160,161,162,163,164,165,166,167,168,169,170,171,17,173, 174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,1 91),? & ?engclk_buclk:192,? & ?epee:193,? & ?etrig1:194,? & ?etrig2:195,? & ?evti_b:196,? & ?extal:197,? & ?extclk:198,? & ?hreset_b:199,? & ?irq0_b_sgpioc0:200,? & ?irq1_b_rsv_b_sgpioc1:201,? & ?irq2_b_cr_b_sgpioc2:202,? & ?irq3_b_kr_b_retry_b_sgpioc3:203,? & ?irq4_b_at2_sgpioc4:204,? & ?irq5_b_sgpioc5_modck1:205,? & ?irq6_b_modck2:206,? & ?irq7_b_modck3:207,? & ?iwp0_vfls0:208,? & ?iwp1_vfls1:209,? & ?kapwr:210,? & ?l_corner:211,? & ?mcki:212,? & ?mcko:213,? & ?mda11:214,? & ?mda12:215,? & 24-40 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?mda13:216,? & ?mda14:217,? & ?mda15:218,? & ?mda27:219,? & ?mda28:220,? & ?mda29:221,? & ?mda30:222,? & ?mda31:223,? & ?mdi_0:224,? & ?mdi_1:225,? & ?mdo_0:226,? & ?mdo_1:227,? & ?mdo_2:228,? & ?mdo_3:229,? & ?mdo_4_mpio32b10:230,? & ?mdo_5_mpio32b9:231,? & ?mdo_6_mpio32b8:232,? & ?mdo_7_mpio32b7:233,? & ?mpio32b15:234,? & ?mpwm0:235,? & ?mpwm1:236,? & ?mpwm16:237,? & ?mpwm17:238,? & ?mpwm18:239,? & ?mpwm19:240,? & ?mpwm2:241,? & ?mpwm20_mpio32b11:242,? & ?mpwm21_mpio32b12:243,? & ?mpwm3:244,? & ?mpwm4_mpio32b5:245,? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-41 mpc565/mpc566 restrictions ?mpwm5_mpio32b6:246,? & ?mrtc_extal32:247,? & ?mrtc_xtal32:248,? & ?msei_b:249,? & ?mseo_b:250,? & ?nvddl:(251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,2 66,267,268,269),? & ?oe_b:270,? & ?poreset_b:271,? & ?qvddl:(272,273,274,275,276,277,278,279,280,281,282,283),? & ?r_corner:284,? & ?rd_wr_b:285,? & ?rstconf_b_texp:286,? & ?rsti_b:287,? & ?sgpioc6_frz_ptr_b:288,? & ?sgpioc7_irqout_b_lwp0:289,? & ?sreset_b:290,? & ?ta_b:291,? & ?tck_dsck:292,? & ?tdi_dsdi:293,? & ?tdo_dsdo:294,? & ?tea_b:295,? & ?tms:296,? & ?trst_b:297,? & ?ts_b:298,? & ?tsiz0:299,? & ?tsiz1:300,? & ?u_corner:301,? & ?vdd:(302,303,304,305,306,307),? & 24-42 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?vdda:308,? & ?vddf:309,? & ?vddh:(310,311,312,313,314,315),? & ?vddsram1:316,? & ?vddsram2:317,? & ?vddsram3:318,? & ?vddsyn:319,? & ?vddsyn32:320,? & ?vf0_mpio32b0:321,? & ?vf1_mpio32b1:322,? & ?vf2_mpio32b2:323,? & ?vflash:324,? & ?vfls0_mpio32b3:325,? & ?vfls1_mpio32b4:326,? & ?vrh:327,? & ?vrhaltref:328,? & ?vrl:329,? & ?vss:(330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345 ,346,347,348,349,350,351,352,353,354,355,356,357),? & ?vssa:358,? & ?vssf:359,? & ?vsssyn:360,? & ?vsssyn32:361,? & ?we_b_at:(362,363,364,365),? & ?xfc:366,? & ?xtal:367?; attribute tap_scan_in of tdi_dsdi: signal is true; attribute tap_scan_mode of tms: signal is true; motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-43 mpc565/mpc566 restrictions attribute tap_scan_out of tdo_dsdo: signal is true; attribute tap_scan_reset of trst_b: signal is true; attribute tap_scan_clock of tck_dsck: signal is (20.0e6, both); attribute instruction_length of spanishoak: entity is 4; attribute instruction_opcode of spanishoak: entity is ?extest (0000),? & ?sample (0001),? & ?clamp (0101),? & ?highz (0100),? & ?bypass (0111, 0010, 0110, 0011)?; attribute instruction_capture of spanishoak: entity is ?0101?; attribute boundary_length of spanishoak: entity is 520; attribute boundary_register of spanishoak: entity is -- numcellport functionsafe[ccell disval rslt] ?0( bc_2,* ,internal, 1), ? & ?1( bc_2,mdo_2,output2 , 1), ? & ?2( bc_2,* ,internal, 1),? & ?3 ( bc_2,mdo_3,output2 , 1),? & ?4 ( bc_2,* ,internal, 1), ? & ?5 ( bc_2,mseo_b,output2 , 1), ? & ?6 ( bc_2,* ,internal, 1),? & ?7 ( bc_2,iwp0_vfls0,output2 , 1),? & 24-44 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?8 ( bc_2,* ,internal, 1),? & ?9( bc_2,iwp1_vfls1,output2 , 1),? & ?10 ( bc_2,*,controlr, 0),? & ?11( bc_7,addr_sgpioa(16),bidir, 0, 10, 0, z),? & ?12 ( bc_2,* ,controlr, 0),? & ?13 ( bc_7, addr_sgpioa(17),bidir, 0, 12, 0, z),? & ?14 ( bc_2,* ,controlr, 0), ? & ?15 ( bc_7,sgpioc6_frz_ptr_b,bidir, 0, 14, 0, z),? & ?16 ( bc_2, * ,controlr, 0), ? & ?17 ( bc_7, addr_sgpioa(8),bidir, 0, 16, 0, z),? & ?18 ( bc_2,* ,controlr, 0),? & ?19 ( bc_7,addr_sgpioa(18),bidir, 0, 18, 0, z),? & ?20 ( bc_2,* ,controlr, 0),? & ?21 ( bc_7,addr_sgpioa(19),bidir, 0, 20, 0, z),? & ?22 ( bc_2,* ,controlr, 0), ? & ?23 ( bc_7,addr_sgpioa(9),bidir, 0, 22, 0, z),? & ?24 ( bc_2,* ,controlr, 0), ? & ?25 ( bc_7,addr_sgpioa(10),bidir, 0, 24, 0, z),? & ?26 ( bc_2,* ,controlr, 0), ? & ?27 ( bc_7,addr_sgpioa(20),bidir, 0, 26, 0, z),? & ?28 ( bc_2,* ,controlr, 0), ? & ?29 ( bc_7,addr_sgpioa(21),bidir, 0, 28, 0, z),? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-45 mpc565/mpc566 restrictions ?30 ( bc_2,* ,controlr, 0), ? & ?31 ( bc_7,addr_sgpioa(11),bidir, 0, 30, 0, z),? & ?32 ( bc_2,* ,controlr, 0), ? & ?33 ( bc_7, addr_sgpioa(12),bidir, 0, 32, 0, z),? & ?34 ( bc_2,* ,controlr, 0), ? & ?35 ( bc_7, addr_sgpioa(22),bidir, 0, 34, 0, z),? & ?36 ( bc_2,* ,controlr, 0), ? & ?37 ( bc_7, addr_sgpioa(23),bidir, 0, 36, 0, z),? & ?38 ( bc_2,* ,controlr, 0), ? & ?39 ( bc_7,addr_sgpioa(13),bidir, 0, 38, 0, z),? & ?40 ( bc_2,* ,controlr, 0), ? & ?41 ( bc_7, addr_sgpioa(24),bidir, 0, 40, 0, z),? & ?42 ( bc_2, * ,controlr, 0), ? & ?43 ( bc_7, addr_sgpioa(25),bidir, 0, 42, 0, z),? & ?44( bc_2, * ,controlr, 0), ? & ?45( bc_7, addr_sgpioa(14),bidir, 0, 44, 0, z),? & ?46 ( bc_2, *,controlr, 0), ? & ?47 ( bc_7, addr_sgpioa(15),bidir, 0, 46, 0, z),? & ?48 ( bc_2, *,controlr,0), ? & ?49 ( bc_7, addr_sgpioa(30),bidir, 0, 48, 0, z),? & 24-46 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?50 ( bc_2, * ,controlr, 0), ? & ?51 ( bc_7, addr_sgpioa(26),bidir, 0, 50, 0, z),? & ?52 ( bc_2, * ,controlr, 0), ? & ?53 ( bc_7, addr_sgpioa(27),bidir, 0, 52, 0, z)? & ?54 ( bc_2, * ,controlr, 0), ? & ?55 ( bc_7, addr_sgpioa(31),bidir, 0, 54, 0, z),? & ?56 ( bc_2, * ,controlr, 0), ? & ?57 ( bc_7, addr_sgpioa(28),bidir, 0, 56, 0, z),? & ?58 ( bc_2, * ,controlr, 0), ? & ?59 ( bc_7, addr_sgpioa(29),bidir, 0 ,58, 0, z),? & ?60 ( bc_2, * ,controlr, 0), ? & ?61 ( bc_7, data_sgpiod(0),bidir, 0, 60, 0, z),? & ?62 ( bc_2, * ,controlr, 0), ? & ?63 ( bc_7, data_sgpiod(29),bidir, 0, 62, 0, z),? & ?64 ( bc_2, * ,controlr, 0), ? & ?65 ( bc_7, data_sgpiod(1),bidir, 0, 64, 0, z),? & ?66 ( bc_2, * ,controlr, 0), ? & ?67 ( bc_7, data_sgpiod(2),bidir, 0, 66, 0, z),? & ?68 ( bc_2, *,controlr, 0), ? & ?69 ( bc_7, data_sgpiod(3),bidir, 0, 68, 0, z),? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-47 mpc565/mpc566 restrictions ?70 ( bc_2, * ,controlr, 0), ? & ?71 ( bc_7, data_sgpiod(27),bidir, 0, 70, 0, z),? & ?72 ( bc_2, * ,controlr, 0), ? & ?73 ( bc_7, data_sgpiod(4),bidir, 0, 72, 0, z),? & ?74 ( bc_2, * ,controlr, 0), ? & ?75 ( bc_7, data_sgpiod(28),bidir, 0, 74, 0, z),? & ?76 ( bc_2, * ,controlr, 0), ? & ?77 ( bc_7, data_sgpiod(31),bidir, 0, 76, 0, z),? & ?78( bc_2,*,controlr, 0), ? & ?79( bc_7, data_sgpiod(5),bidir, 0 78, 0, z),? & ?80 ( bc_2, * ,controlr, 0), ? & ?81 ( bc_7, data_sgpiod(6),bidir, 0, 80, 0, z),? & ?82 ( bc_2, * ,controlr, 0), ? & ?83 ( bc_7, data_sgpiod(30),bidir, 0, 82, 0, z),? & ?84 ( bc_2, * ,controlr, 0), ? & ?85 ( bc_7, data_sgpiod(7),bidir, 0, 84 0 z),? & ?86 ( bc_2, * ,controlr,0), ? & ?87 ( bc_7, data_sgpiod(25),bidir, 0, 86, 0, z),? & ?88 ( bc_2, * ,controlr, 0), ? & ?89 ( bc_7, data_sgpiod(8),bidir, 0, 88, 0, z),? & 24-48 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?90 ( bc_2, * ,controlr, 0), ? & ?91 ( bc_7, data_sgpiod(24),bidir, 0, 90, 0, z),? & ?92 ( bc_2, * ,controlr, 0), ? & ?93 ( bc_7, data_sgpiod(9),bidir, 0, 92, 0, z) ? & ?94 ( bc_2, * ,controlr, 0), ? & ?95 ( bc_7, data_sgpiod(10),bidir, 0, 94, 0, z),? & ?96 ( bc_2, * ,controlr, 0), ? & ?97 ( bc_7, data_sgpiod(26),bidir, 0, 96, 0, z),? & ?98 ( bc_2, * ,controlr, 0), ? & ?99 ( bc_7, data_sgpiod(22),bidir, 0, 98, 0, z),? & ?100 ( bc_2, * ,controlr, 0), ? & ?101 ( bc_7, data_sgpiod(11),bidir, 0, 100, 0, z),? & ?102 ( bc_2, * ,controlr, 0), ? & ?103 ( bc_7, data_sgpiod(12),bidir, 0, 102, 0, z),? & ?104 ( bc_2, * ,controlr, 0), ? & ?105 ( bc_7, data_sgpiod(13),bidir, 0, 104, 0, z),? & ?106 ( bc_2, * ,controlr, 0), ? & ?107 ( bc_7, data_sgpiod(20),bidir, 0, 106, 0, z),? & ?108 ( bc_2, * ,controlr, 0), ? & ?109 ( bc_7, data_sgpiod(14),bidir, 0, 108, 0, z),? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-49 mpc565/mpc566 restrictions ?110 ( bc_2, * ,controlr, 0), ? & ?111 ( bc_7, data_sgpiod(23),bidir, 0, 110, 0, z),? & ?112 ( bc_2, * ,controlr, 0), ? & ?113 ( bc_7, data_sgpiod(15),bidir, 0, 112, 0, z),? & ?114 ( bc_2, * ,controlr, 0), ? & ?115 ( bc_7, data_sgpiod(16),bidir, 0, 114, 0, z),? & ?116 ( bc_2, * ,controlr, 0), ? & ?117 ( bc_7, data_sgpiod(21),bidir, 0, 116, 0, z),? & ?118 ( bc_2, * controlr, 0), ? & ?119 ( bc_7, data_sgpiod(17),bidir, 0, 118, 0, z),? & ?120 ( bc_2, * ,controlr, 0), ? & ?121 ( bc_7, data_sgpiod(18),bidir, 0, 120, 0, z),? & ?122 ( bc_2, * ,controlr, 0), ? & ?123 ( bc_7, data_sgpiod(19),bidir, 0, 122, 0, z),? & ?124 ( bc_2, * ,controlr, 0),? & ?125 (bc_7,irq3_b_kr_b_retry_b_sgpioc3,bidir,0,124,0,z),?& ?126 ( bc_2, * ,controlr, 0),? & ?127 ( bc_7,irq4_b_at2_sgpioc4,bidir, 0, 126, 0, z),? & ?128 ( bc_2, * ,controlr, 0), ? & ?129 ( bc_7,irq1_b_rsv_b_sgpioc1,bidir, 0, 128, 0, z),? & 24-50 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?130 ( bc_2, * ,controlr, 0), ? & ?131 ( bc_7,sgpioc7_irqout_b_lwp0,bidir, 0, 130, 0, z),? & ?132 ( bc_2, * ,controlr, 0), ? & ?133 ( bc_7, bb_b_vf2_iwp3,bidir, 0, 132, 0, z),? & ?134 ( bc_2, * ,controlr, 0), ? & ?135 ( bc_7, bg_b_vf0_lwp,bidir, 0, 134, 0, z),? & ?136 ( bc_2, * ,controlr, 0), ? & ?137 ( bc_7, br_b_vf1_iwp2,bidir, 0, 136, 0, z),? & ?138 ( bc_2, * ,controlr, 0), ? & ?139 ( bc_7, rd_wr_b,bidir, 0, 138, 0, z),? & ?140 ( bc_2, * ,internal, 1),? & ?141 ( bc_2, oe_b,output2, 1),? & ?142 ( bc_2, * ,controlr, 0),? & ?143 ( bc_7, tea_b,bidir, 0, 142, 0, z),? & ?144 ( bc_2, * ,controlr, 0),? & ?145 ( bc_7, irq2_b_cr_b_sgpioc2,bidir, 0, 144, 0, z),? & ?146 ( bc_2, * ,controlr, 0),? & ?147 ( bc_7, irq0_b_sgpioc0,bidir, 0, 146, 0, z),? & ?148 ( bc_2, * ,internal, 1),? & ?149 ( bc_2, we_b_at(0),output2, 1),? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-51 mpc565/mpc566 restrictions ?150 ( bc_2, * ,internal, 1), ? & ?151 ( bc_2, we_b_at(1),output2, 1),? & ?152 ( bc_2, * ,internal, 1), ? & ?153 ( bc_2, we_b_at(2),output2, 1),? & ?154 ( bc_2, * ,internal, 1), ? & ?155 ( bc_2, we_b_at(3),output2, 1),? & ?156 ( bc_2, * ,internal, 1), ? & ?157 ( bc_2, cs0_b,output2, 1),? & ?158 ( bc_2, *,internal, 1),? & ?159 ( bc_2, cs1_b,output2 , 1),? & ?160 ( bc_2, *,internal, 1),? & ?161 ( bc_2, cs2_b,output2 , 1),? & ?162 ( bc_2, *,internal, 1),? & ?163 ( bc_2, cs3_b,output2 , 1),? & ?164 ( bc_2, *,controlr, 0),? & ?165 ( bc_7, burst_b,bidir, 0, 164, 0, z),? & ?166 ( bc_2, *,controlr, 0),? & ?167 ( bc_7, bi_b_sts_b,bidir, 0, 166, 0, z),? & ?168 ( bc_2, *,controlr, 0),? & ?169 ( bc_7, tsiz0,bidir, 0, 168, 0, z),? & 24-52 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?170( bc_2, *,controlr, 0),? & ?171( bc_7, tsiz1,bidir, 0, 170, 0, z),? & ?172 ( bc_2, *,controlr, 0),? & ?173 ( bc_7, ts_b,bidir, 0, 172, 0, z),? & ?174 ( bc_2, *,controlr, 0),? & ?175 ( bc_7, ta_b,bidir, 0, 174, 0, z),? & ?176 ( bc_2, *,controlr, 0),? & ?177 ( bc_7, bdip_b,bidir, 0, 176, 0, z),? & ?178 ( bc_2, *,internal, 0), ? & ?179 ( bc_4, b0epee,input, x), ? & ?180 ( bc_2, *,internal, 0), ? & ?181 ( bc_4, epee,input, x), ? & ?182 ( bc_2, *,internal, 1),? & ?183 ( bc_2, clkout,output2, 1), ? & ?184 ( bc_2, *,internal, 1), ? & ?185 ( bc_2, engclk_buclk,output2 , 1), ? & ?186 ( bc_2, *,controlr, 0), ? & ?187 ( bc_7,irq5_b_sgpioc5_modck1,bidir, 0, 186, 0, z),? & ?188 ( bc_2, *,controlr, 0), ? & ?189 ( bc_7, irq6_b_modck2,bidir, 0, 188, 0, z),? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-53 mpc565/mpc566 restrictions ?190 ( bc_2, *,controlr, 0), ? & ?191 ( bc_7, irq7_b_modck3,bidir, 0, 190, 0, z),? & ?192 ( bc_2, * ,controlr, 0) ? & ?193 ( bc_7, rstconf_b_texp,bidir, 0, 192, 0, z),? & ?194 ( bc_4, extclk,input, x),? & ?195 ( bc_2, *,controlr, 0),? & ?196 ( bc_7, a_cnrx0,bidir, 0, 195, 0, z),? & ?197 ( bc_2, * ,internal, 1),? & ?198 ( bc_2, a_cntx0,output2 , 1),? & ?199 ( bc_2, * ,controlr, 0),? & ?200 ( bc_7, a_pcs0_ss_b_qgpio0,bidir, 0, 199, 0, z),? & ?201 ( bc_2, * ,internal, 0),? & ?202 ( bc_4, a_eck ,input, x), ? & ?203 ( bc_2, * ,controlr, 0),? & ?204 ( bc_7, a_pcs1_qgpio1,bidir, 0, 203, 0, z),? & ?205 ( bc_2, * ,internal, 1),? & ?206 ( bc_2, a_txd2_qgpo2,output2 , 1),? & ?207 ( bc_2, * ,controlr, 0),? & ?208 ( bc_7, a_pcs2_qgpio2,bidir, 0, 207, 0, z),? & ?209 ( bc_4, a_rxd2_qgpi2,input, x),? & 24-54 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?210 ( bc_4, b_rxd1_qgpi1,input, x),? & ?211 ( bc_4, a_rxd1_qgpi1,input, x),? & ?212 ( bc_2, * ,controlr, 0),? ?213 ( bc_7, a_mosi_qgpio5,bidir, 0, 212, 0, z),? & ?214 ( bc_2, * ,controlr, 0),? & ?215 ( bc_7, a_pcs3_qgpio3,bidir, 0, 214, 0, z),? & ?216 ( bc_2, * ,controlr, 0),? & ?217 ( bc_7, a_miso_qgpio4,bidir, 0, 216, 0, z),? & ?218 ( bc_2, * ,controlr, 0),? & ?219 ( bc_7, a_sck_qgpio6,bidir, 0, 218, 0, z),? & ?220 ( bc_2, * ,controlr, 0),? & ?221 ( bc_7, b_pcs2_qgpio2,bidir, 0, 220, 0, z),? & ?222 ( bc_2, * ,internal, 0),? & ?223 ( bc_4, b_rxd2_j1850_rx,input, x),? & ?224 ( bc_2, * ,internal, 1),? & ?225 ( bc_2, a_txd1_qgpo1,output2 , 1),? & ?226 ( bc_2, * ,internal, 1),? & ?227 ( bc_2, b_txd2_qgpo2,output2, 1),? & ?228 ( bc_2, * ,internal, 1),? & ?229 ( bc_2, b_txd1_qgpo1,output2 , 1),? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-55 mpc565/mpc566 restrictions ?230 ( bc_2, * ,internal, 0),? & ?231 ( bc_4, b_eck,input, x), ? & ?232 ( bc_2, * ,controlr, 0),? & ?233 ( bc_7, b_sck_qgpio6,bidir, 0, 232, 0, z),? & ?234 ( bc_2, * ,controlr, 0), ? & ?235 ( bc_7, b_mosi_qgpio5,bidir, 0, 234, 0, z),? & ?236 ( bc_2, * ,controlr, 0), ? & ?237 ( bc_7, b_miso_qgpio4,bidir, 0, 236, 0, z),? & ?238 ( bc_2, * ,controlr, 0), ? & ?239 ( bc_7, b_pcs3_j1850_tx,bidir, 0, 238, 0, z),? & ?240 ( bc_2, * ,controlr, 0), ? & ?241 ( bc_7, b_pcs1_qgpio1,bidir, 0, 240, 0, z),? & ?242 ( bc_2, * ,controlr, 0), ? & ?243 ( bc_7, b_pcs0_ss_b_qgpio0,bidir, 0, 242, 0, z),? & ?244 ( bc_2, * ,controlr, 0), ? & ?245 ( bc_7, vfls1_mpio32b4,bidir, 0, 244, 0, z),? & ?246 ( bc_2, * ,controlr, 0), ? & ?247 ( bc_7, vfls0_mpio32b3,bidir, 0, 246, 0, z),? & ?248 ( bc_2, * ,controlr, 0), ? & ?249 ( bc_7, vf2_mpio32b2,bidir, 0, 248, 0, z),? & 24-56 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?250 ( bc_2, * ,controlr, 0), ? & ?251 ( bc_7, vf1_mpio32b1,bidir, 0, 250, 0, z),? & ?252 ( bc_2, * ,controlr, 0), ? & ?253 ( bc_7, vf0_mpio32b0,bidir, 0, 252, 0, z),? & ?254 ( bc_2, * ,controlr, 0),? & ?255 ( bc_7, mpwm4_mpio32b5,bidir, 0, 254, 0, z),? & ?256 ( bc_2, * ,controlr, 0), ? & ?257 ( bc_7, mpwm19,bidir, 0, 256, 0, z),? & ?258 ( bc_2, * ,controlr, 0),? & ?259 ( bc_7, mpio32b15,bidir, 0, 258, 0, z),? & ?260 ( bc_2, * ,controlr, 0), ? & ?261 ( bc_7, c_cnrx0_mpio32b14,bidir, 0, 260, 0, z),? & ?262 ( bc_2,* ,controlr, 0), ? & ?263 ( bc_7, c_cntx0_mpio32b1,bidir, 0, 262, 0, z),? & ?264 ( bc_2,* ,controlr, 0), ? & ?265 ( bc_7, mpwm21_mpio32b12,bidir, 0, 264, 0, z),? & ?266 ( bc_2, * ,controlr, 0), ? & ?267 ( bc_7, mpwm20_mpio32b11,bidir, 0, 266, 0, z),? & ?268 ( bc_2, * ,controlr, 0), ? & ?269 ( bc_7, mda15 ,bidir, 0, 268, 0, z),? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-57 mpc565/mpc566 restrictions ?270 ( bc_2, * ,controlr, 0), ? & ?271 ( bc_7, mda14,bidir, 0, 270, 0, z),? & ?272 ( bc_2, * ,controlr, 0), ? & ?273 ( bc_7, mpwm16,bidir, 0, 272, 0, z), ? & ?274 ( bc_2, * ,controlr, 0), ? & ?275 ( bc_7, mpwm3,bidir, 0, 274, 0, z),? & ?276 ( bc_2, * ,controlr, 0), ? & ?277 ( bc_7, mpwm2,bidir, 0, 276, 0, z),? & ?278 ( bc_2, * ,controlr, 0), ? & ?279 ( bc_7, mpwm1,bidir, 0, 278, 0, z),? & ?280 ( bc_2, * ,controlr, 0), ? & ?281 ( bc_7, mpwm0,bidir, 0, 280, 0, z),? & ?282 ( bc_2, * ,controlr, 0), ? & ?283 ( bc_7, mda31,bidir, 0, 282, 0, z),? & ?284 ( bc_2, * ,controlr, 0), ? & ?285 ( bc_7, mda30,bidir, 0, 284, 0, z),? & ?286 ( bc_2, * ,controlr, 0), ? & ?287 ( bc_7, mda29,bidir, 0, 286, 0, z),? & ?288 ( bc_2, * ,controlr, 0), ? & ?289 ( bc_7, mda28,bidir, 0, 288, 0, z),? & 24-58 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?290 ( bc_2, * ,controlr, 0), ? & ?291 ( bc_7, mda27,bidir, 0 290, 0, z),? & ?292 ( bc_2, * ,controlr, 0), ? & ?293 ( bc_7, mda13,bidir, 0, 292, 0, z),? & ?294 ( bc_2, * ,controlr, 0), ? & ?295 ( bc_7, mda12,bidir, 0, 294, 0, z),? & ?296 ( bc_2, * ,controlr, 0), ? & ?297 ( bc_7, mda11,bidir, 0, 296, 0, z),? & ?298 ( bc_2, * ,controlr, 0), ? & ?299 ( bc_7, mpwm18,bidir, 0, 298, 0, z),? & ?300 ( bc_2, * ,controlr, 0), ? & ?301 ( bc_7, mpwm17,bidir, 0, 300, 0, z)? & ?302 ( bc_2, * ,controlr, 0), ? & ?303 ( bc_7, b_t2clk,bidir, 0, 302, 0, z),? & ?304 ( bc_2, * ,controlr, 0), ? & ?305 ( bc_7, b_tpuch1 ,bidir, 0, 304, 0, z),? & ?306 ( bc_2, * ,controlr, 0), ? & ?307 ( bc_7, b_tpuch0,bidir, 0, 306, 0, z),? & ?308 ( bc_2, * ,controlr, 0), ? & ?309 ( bc_7, mpwm5_mpio32b6,bidir, 0, 308, 0, z),? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-59 mpc565/mpc566 restrictions ?310 ( bc_2, * ,controlr, 0), ? & ?311 ( bc_7, b_tpuch2,bidir, 0, 310, 0, z),? & ?312 ( bc_2, * ,controlr, 0), ? & ?313 ( bc_7, b_tpuch15,bidir, 0, 312, 0, z),? & ?314 ( bc_2, * ,controlr, 0), ? & ?315 ( bc_7, b_tpuch14,bidir, 0, 314, 0, z),? & ?316 ( bc_2, * ,controlr, 0), ? & ?317 ( bc_7, b_tpuch13,bidir, 0, 316, 0, z),? & ?318 ( bc_2, * ,controlr, 0), ? & ?319 ( bc_7, b_tpuch12,bidir, 0, 318, 0, z),? & ?320 ( bc_2, * ,controlr, 0), ? & ?321 ( bc_7, b_tpuch11,bidir, 0, 320, 0, z),? & ?322 ( bc_2, * ,controlr, 0), ? & ?323 ( bc_7, b_tpuch10,bidir, 0, 322, 0, z),? & ?324 ( bc_2, * ,controlr, 0), ? & ?325 ( bc_7, b_tpuch9,bidir, 0, 324, 0, z),? & ?326 ( bc_2, * ,controlr, 0), ? & ?327 ( bc_7, b_tpuch8,bidir, 0, 326, 0, z),? & ?328 ( bc_2, * ,controlr, 0), ? & ?329 ( bc_7, b_tpuch7,bidir, 0, 328, 0, z),? & 24-60 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?330 ( bc_2, * ,controlr, 0), ? & ?331 ( bc_7, b_tpuch6,bidir, 0, 330, 0, z),? & ?332 ( bc_2, * ,controlr, 0), ? & ?333 ( bc_7, b_tpuch5,bidir, 0, 332, 0, z),? & ?334 ( bc_2, * ,controlr, 0), ? & ?335 ( bc_7, b_tpuch4,bidir, 0, 334, 0, z),? & ?336 ( bc_2, * ,controlr, 0), ? & ?337 ( bc_7, b_tpuch3,bidir, 0, 336, 0, z),? & ?338 ( bc_2, * ,controlr, 0), ? & ?339 ( bc_7, a_tpuch1,bidir, 0, 338, 0, z),? & ?340 ( bc_2, * ,controlr, 0), ? & ?341 ( bc_7, a_tpuch0,bidir, 0, 340, 0, z),? & ?342 ( bc_2, * ,controlr, 0), ? & ?343 ( bc_7, a_t2cl,bidir, 0, 342, 0, z),? & ?344 ( bc_2, * ,controlr, 0), ? & ?345 ( bc_7, a_tpuch15,bidir, 0, 344, 0, z),? & ?346 ( bc_2, * ,controlr, 0), ? & ?347( bc_7, a_tpuch14,bidir, 0, 346, 0, z),? & ?348 ( bc_2, * ,controlr, 0), ? & ?349 ( bc_7, a_tpuch13,bidir, 0, 348, 0, z),? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-61 mpc565/mpc566 restrictions ?351 ( bc_7, a_tpuch12,bidir, 0, 350, 0, z),? & ?352 ( bc_2, * ,controlr, 0), ? & ?353 ( bc_7, a_tpuch11,bidir, 0, 352, 0, z),? & ?354 ( bc_2, * ,controlr, 0), ? & ?355 ( bc_7, a_tpuch10,bidir, 0, 354, 0, z),? & ?356 ( bc_2, * ,controlr, 0), ? & ?357 ( bc_7, a_tpuch9 ,bidir, 0, 356, 0, z),? & ?358 ( bc_2, * ,controlr, 0), ? & ?359 ( bc_7, a_tpuch8,bidir, 0, 358, 0, z),? & ?360 ( bc_2, * ,controlr, 0), ? & ?361 ( bc_7, a_tpuch7,bidir, 0, 360, 0, z),? & ?362 ( bc_2, * ,controlr, 0), ? & ?363 ( bc_7, a_tpuch6,bidir, 0, 362, 0, z),? & ?364 ( bc_2, * ,controlr, 0), ? & ?365 ( bc_7, a_tpuch5,bidir, 0, 364, 0, z),? & ?366 ( bc_2, * ,controlr, 0), ? & ?367 ( bc_7, a_tpuch4,bidir, 0, 366, 0, z),? & ?368 ( bc_2, * ,controlr, 0), ? & ?369 ( bc_7, a_tpuch3,bidir, 0, 368, 0, z),? & 24-62 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?370 ( bc_2, * ,controlr, 0), ? & ?371 ( bc_7, a_tpuch2,bidir, 0, 370, 0, z),? & ?372 ( bc_2, * ,internal, 0), ? & ?373 ( bc_4, etrig1,input, x), ? & ?374 ( bc_2, * ,internal, 0), ? & ?375 ( bc_4, etrig2,input, x), ? & ?376 ( bc_2, * ,controlr, 0), ? & ?377 ( bc_7, an64_b_pqb0,bidir, 0, 376, 0, z),? & ?378 ( bc_2, * ,controlr, 0), ? & ?379 ( bc_7, an65_b_pqb1,bidir, 0, 378, 0, z)? & ?380 ( bc_2, * ,controlr, 0), ? & ?381 ( bc_7, an66_b_pqb2,bidir, 0, 380, 0, z),? & ?382 ( bc_2, * ,controlr, 0), ? & ?383 ( bc_7, an67_b_pqb3,bidir, 0, 382, 0, z),? & ?384 ( bc_2, * ,controlr, 0), ? & ?385 ( bc_7, an68_b_pqb4,bidir, 0, 384, 0, z),? & ?386 ( bc_2, * ,controlr, 0), ? & ?387 ( bc_7, an69_b_pqb5,bidir, 0, 386, 0, z),? & ?388 ( bc_2, * ,controlr, 0), ? & ?389 ( bc_7, an70_b_pqb6,bidir, 0, 388, 0, z),? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-63 mpc565/mpc566 restrictions ?390 ( bc_2, * ,controlr, 0), ? & ?391 ( bc_7, an71_b_pqb7,bidir, 0, 390, 0, z),? & ?392 ( bc_2, * ,controlr, 0), ? & ?393 ( bc_7, an72_b_ma0_pqa0,bidir, 0, 392, 0, z),? & ?394 ( bc_2, * ,controlr, 0), ? & ?395 ( bc_7, an73_b_ma1_pqa1,bidir, 0, 394, 0, z),? & ?396 ( bc_2, * ,controlr, 0),? & ?397 ( bc_7, an74_b_ma2_pqa2,bidir, 0, 396, 0, z),? & ?398 ( bc_2, * ,controlr, 0), ? & ?399 ( bc_7, an75_b_pqa3,bidir, 0, 398, 0, z),? & ?400 ( bc_2, * ,controlr, 0), ? & ?401 ( bc_7, an76_b_pqa4,bidir, 0, 400, 0, z),? & ?402 ( bc_2, * ,controlr, 0), ? & ?403 ( bc_7, an77_b_pqa5,bidir, 0, 402, 0, z),? & ?404 ( bc_2, * ,controlr, 0), ? & ?405 ( bc_7, an78_b_pqa6,bidir, 0, 404, 0, z),? & ?406 ( bc_2, * ,controlr, 0), ? & ?407 ( bc_7, an79_b_pqa7,bidir, 0, 406, 0, z),? & ?408 ( bc_2, * ,controlr, 0), ? & ?409 ( bc_7, an59_a_pqa7,bidir, 0, 408, 0, z),? & 24-64 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?410 ( bc_2, * ,controlr, 0), ? & ?411 ( bc_7, an58_a_pqa6,bidir, 0, 410, 0, z),? & ?412 ( bc_2, * ,controlr, 0), ? & ?413 ( bc_7, an57_a_pqa5,bidir, 0, 412, 0, z),? & ?414 ( bc_2, * ,controlr, 0), ? & ?415 ( bc_7, an56_a_pqa4,bidir, 0, 414, 0, z),? & ?416 ( bc_2, * ,controlr, 0),? & ?417 ( bc_7, an55_a_pqa3,bidir, 0, 416, 0, z),? & ?418 ( bc_2, * ,controlr, 0), ? & ?419 ( bc_7, an54_a_ma2_pqa2,bidir, 0, 418, 0, z),? & ?420 ( bc_2, * ,controlr, 0), ? & ?421 ( bc_7, an53_a_ma1_pqa1,bidir, 0, 420, 0, z),? & ?422 ( bc_2, * ,controlr, 0), ? & ?423 ( bc_7, an52_a_ma0_pqa0,bidir, 0, 422, 0, z),? & ?424 ( bc_2, * ,controlr, 0), ? & ?425 ( bc_7, an51_a_pqb7,bidir, 0, 424, 0, z),? & ?426 ( bc_2, * ,controlr, 0), ? & ?427 ( bc_7, an50_a_pqb6,bidir, 0, 426, 0, z),? & ?428 ( bc_2, * ,controlr, 0), ? & ?429 ( bc_7, an49_a_pqb5,bidir, 0, 428, 0, z),? & ?430 ( bc_2, * ,controlr, 0), ? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-65 mpc565/mpc566 restrictions ?431 ( bc_7, an48_a_pqb4,bidir, 0, 430, 0, z),? & ?432 ( bc_2, * ,controlr, 0), ? & ?433 ( bc_7, an47_anz_a_pqb3,bidir, 0, 432, 0, z),? & ?434 ( bc_2, * ,controlr, 0), ? & ?435 ( bc_7, an46_any_a_pqb2,bidir, 0, 434, 0, z),? & ?436 ( bc_2, * ,internal, 0), ? & ?437 ( bc_4, an80,input, x), ? & ?438 ( bc_2, * ,internal, 0), ? & ?439 ( bc_4, an81,input, x), ? & ?440 ( bc_2, * ,internal, 0), ? & ?441 ( bc_4, an82,input, x), ? & ?442 ( bc_2, * ,internal, 0), ? & ?443 ( bc_4, an83,input, x), ? & ?444 ( bc_2, * ,internal, 0), ? & ?445 ( bc_4, an84,input, x), ? & ?446 ( bc_2, * ,internal, 0), ? & ?447 ( bc_4, an85,input, x), ? & ?448 ( bc_2, * ,internal, 0), ? & ?449 ( bc_4, an86,input, x), ? & ?450 ( bc_2, * ,internal, 0), ? & 24-66 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?451 ( bc_4, an87,input, x), ? & ?452 ( bc_2, * ,controlr, 0), ? & ?453 ( bc_7, an45_anx_a_pqb1,bidir, 0, 452, 0, z),? & ?454 ( bc_2, * ,controlr, 0), ? & ?455 ( bc_7, an44_anw_a_pqb0,bidir, 0, 454, 0, z),? & ?456 ( bc_2, * ,controlr, 0), ? & ?457 ( bc_7, b_cnrx0,bidir, 0, 456, 0, z),? & ?458 ( bc_2, * ,internal, 1), ? & ?459 ( bc_2, b_cntx0,output2, 1), ? & ?460 ( bc_2, * ,controlr, 0), ? & ?461 ( bc_7, c_t2clk,bidir, 0, 460, 0, z),? & ?462 ( bc_2, * ,controlr, 0), ? & ?463 ( bc_7, c_tpuch15,bidir, 0, 462, 0, z),? & ?464 ( bc_2, * ,controlr, 0), ? & ?465 ( bc_7, c_tpuch14,bidir, 0, 464, 0, z),? & ?466 ( bc_2, * ,controlr, 0), ? & ?467 ( bc_7, c_tpuch13,bidir, 0, 466, 0, z),? & ?468 ( bc_2, * ,controlr, 0), ? & ?469 ( bc_7, c_tpuch12,bidir, 0, 468, 0, z),? & ?470 ( bc_2, * ,controlr, 0), ? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-67 mpc565/mpc566 restrictions ?471 ( bc_7, c_tpuch11,bidir, 0, 470, 0, z),? & ?472 ( bc_2, * ,controlr, 0), ? & ?473 ( bc_7, c_tpuch10,bidir, 0, 472, 0, z),? & ?474 ( bc_2, * ,controlr, 0), ? & ?475 ( bc_7, c_tpuch9,bidir, 0, 474, 0, z),? & ?476 ( bc_2, * ,controlr, 0), ? & ?477 ( bc_7, c_tpuch8,bidir, 0, 476, 0, z),? & ?478 ( bc_2, * ,controlr, 0), ? & ?479 ( bc_7, c_tpuch7,bidir, 0, 478, 0, z),? & ?480 ( bc_2, * ,controlr, 0), ? & ?481 ( bc_7, c_tpuch6,bidir, 0, 480, 0, z),? & ?482 ( bc_2, * ,controlr, 0), ? & ?483 ( bc_7, c_tpuch5,bidir, 0, 482, 0, z),? & ?484 ( bc_2, * ,controlr, 0), ? & ?485 ( bc_7, c_tpuch4,bidir, 0, 484, 0, z),? ?486 ( bc_2, * , controlr, 0), ? & ?487 ( bc_7, c_tpuch3,bidir, 0, 486, 0, z),? & ?488 ( bc_2, * ,controlr, 0), ? & ?489 ( bc_7, c_tpuch2,bidir, 0, 488, 0, z),? & ?490 ( bc_2, * ,controlr, 0), ? & 24-68 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions ?491 ( bc_7, c_tpuch1,bidir, 0, 490, 0, z),? & ?492 ( bc_2, * ,controlr, 0), ? & ?493 ( bc_7, c_tpuch0,bidir, 0, 492, 0, z),? & ?494 ( bc_2, * ,controlr, 0), ? & ?495 ( bc_7, mcki,bidir, 0, 494, 0, z),? & ?496 ( bc_2, * ,controlr, 0), ? & ?497 ( bc_7, mdi_0,bidir, 0, 496, 0, z),? & ?498 ( bc_2, * ,controlr, 0), ? & ?499 ( bc_7, mdi_1,bidir, 0, 498, 0, z),? & ?500 ( bc_2, * ,controlr, 0), ? & ?501 ( bc_7, msei_b,bidir, 0, 500, 0, z),? & ?502 ( bc_2, * ,internal, 1), ? & ?503 ( bc_2, mdo_1,output2 , 1), ? & ?504 ( bc_2, * ,internal, 1), ? & ?505 ( bc_2, mdo_0,output2 , 1), ? & ?506 ( bc_2, * ,internal, 1), ? & ?507 ( bc_2, mcko,output2 , 1), ? & ?508 ( bc_2, * ,controlr, 0), ? & ?509 ( bc_7, mdo_7_mpio32b7,bidir, 0, 508 0 z),? & ?510 ( bc_2, * ,controlr, 0), ? & motorola chapter 24. ieee 1149.1-compliant interface (jtag) 24-69 mpc565/mpc566 restrictions ?511 ( bc_7, mdo_6_mpio32b8,bidir, 0, 510, 0, z),? & ?512 ( bc_2, * ,controlr, 0), ? & ?513 ( bc_7, mdo_5_mpio32b9,bidir, 0, 512, 0, z),? & ?514 ( bc_2, * ,controlr, 0), ? & ?515 ( bc_7, mdo_4_mpio32b10,bidir, 0, 514, 0, z),? & ?516 ( bc_2,* ,controlr, 0),? & ?517 ( bc_4, * ,internal, 0),? & ?518 ( bc_2, * ,controlr, 0), ? & ?519 ( bc_7, evti_b,bidir, 0, 518, 0, z)?; end spanishoak; 24-70 mpc565/mpc566 reference manual motorola mpc565/mpc566 restrictions motorola appendix a. internal memory map a-1 appendix a internal memory map the tables below use the following notations. in the access column: s = supervisor access only, u = user access, t = test access in the reset column: s = sreset ,h=hreset , m = module reset , por = power-on reset , u = unchanged, x = unknown the codes in the reset column indicate which reset has an effect on register values. a.1 index of memory map tables table a-1. spr (special purpose registers) table a-2. uc3f flash array table a-3. decram sram array table a-4. bbc (burst buffer controller module) table a-5. usiu (unified system interface unit) table a-6. cdr3 flash control registers eeprom (uc3f) table a-7. dptram ab and c control registers table a-8. dlcmd2 (data link controller module) table a-9. dptram memory arrays table a-10. time processor unit 3 a and b (tpu3 a and b) table a-11. qadc64e a and b (queued analog-to-digital converter) table a-12. qsmcm a and b (queued serial multi-channel module) table a-13. time processor unit 3 c (tpu3_c) table a-14. mios14 (modular input/output subsystem) table a-15. toucan a, b and c (can 2.0b controller) a-2 mpc565/mpc566 reference manual motorola index of memory map tables table a-16. uimb (u-bus to imb bus interface) table a-17. calram_a and calram_b control registers table a-18. calram_b and calram_a array table a-1. spr (special purpose registers) address access symbol register size reset cr u cr condition state register see section 3.7.4, ?condition register (cr),? for bit descriptions 32 ? fpscr u fpscr floating-point status and control register see table 3-5 for bit descriptions 32 ? msr u msr machine state register see table 3-12 for bit descriptions 32 ? spr 1 u xer integer exception register see table 3-10 for bit descriptions 32 ? spr 8 u lr link register see section 3.7.6, ?link register (lr),? for bit descriptions 32 ? spr 9 u ctr count register see section 3.7.7, ?count register (ctr),? for bit descriptions 32 ? spr 18 u dsisr dae/source instruction service register see section 3.9.2, ?dae/source instruction service register (dsisr),? for bit descriptions 32 ? spr 19 u dar data address register see section 3.9.3, ?data address register (dar),? for bit descriptions 32 ? spr 22 s dec decrementer register. see section 3.9.5, ?decrementer register (dec),? for more information. 32 por, h spr 26 u srr0 machine status save/restore register 0 see section 3.9.6, ?machine status save/restore register 0 (srr0),? for bit descriptions 32 ? spr 27 u srr1 machine status save/restore register1 see section 3.9.7, ?machine status save/restore register 1 (srr1),? for bit descriptions 32 ? spr 80 u eie external interrupt enable see section 3.9.10.1, ?eie, eid, and nri special-purpose registers,? for bit descriptions. 32 ? spr 81 u eid external interrupt disable see section 3.9.10.1, ?eie, eid, and nri special-purpose registers,? for bit descriptions. 32 ? motorola appendix a. internal memory map a-3 indexofmemorymaptables spr 82 u nri non-recoverable interrupt register see section 3.9.10.1, ?eie, eid, and nri special-purpose registers,? for bit descriptions 32 ? spr 144 ? spr 147 ? cmpa ? cmpd comparator a-d value register. see table 22-17 for bit descriptions. 32 ? spr 148 ? ecr exception cause register. see table 22-27 for bit descriptions. 32 ? spr 149 ? der debug enable register. see table 22-28 for bit descriptions. 32 ? spr 150 ? counta breakpoint counter a value and control register. see table 22-25 for bit descriptions. 32 ? spr 151 ? countb breakpoint counter b value and control register. see table 22-26 for bit descriptions. 32 ? spr 152 ? spr 153 ? cmpe ? cmpf comparator e-f value register. see table 22-18 for bit descriptions. 32 ? spr 154 ? spr 155 ? cmpg ? cmph comparator g-h value register. see table 22-20 for bit descriptions. 32 ? spr 156 ? lctrl1 l-bus support control register 1. see table 22-23 for bit descriptions. 32 ? spr 157 ? lctrl2 l-bus support control register 2. see table 22-24 for bit descriptions. 32 ? spr 158 ? ictrl i-bus support control register. see table 22-21 for bit descriptions. 32 ? spr 159 ? bar breakpoint address register. see table 22-19 for bit descriptions. 32 ? spr 268, 269 u tbl/tbu time base register see table 3-11 and section 6.14.4.2, ?time base sprs,? for bit descriptions 32 por, h spr 272 ? spr 275 u sprg0 ? sprg3 general special-purpose registers 0-3 see table 3-15 for bit descriptions 32 ? spr 284, 285 u tbl/tbu time base (write only) register see table 3-14 and section 6.14.4.2, ?time base sprs? for bit descriptions 32 por, h spr 287 u pvr processor version register see table 3-14 for bit descriptions 32 ? spr 1022 u fpecr floating-point exception cause register see table 3-18 for bit descriptions 32 ? spr 528 s mi_gra mi global region attribute register. see table 4-8 for bit descriptions. 32 ? table a-1. spr (special purpose registers) (continued) address access symbol register size reset a-4 mpc565/mpc566 reference manual motorola index of memory map tables spr 529 s eibadr external interrupt relocation table base address register. see table 4-9 for bit descriptions. 32 ? spr 536 s l2u_gra l2u global region attribute register. see table 11-10 for bit descriptions. 32 ? spr 560 s bbcmcr bbc module configuration register. see table 4-4 for bit descriptions. 32 ? spr 568 s l2u_mcr l2u module configuration register. see table 11-7 for bit descriptions. 32 ? spr 630 s dpdr development port data register see section 22.4.6, ?development port registers? for bit descriptions. 32 ? spr 638 s immr internal memory mapping register. see table 6-12 for bit descriptions. 32 por, h spr 784 ? 787 s mi_rbax mi region x base address register. see table 4-5 for bit descriptions. 32 ? spr 792 ? 795 s l2u_rbax l2u region x base address register. see table 11-8 for bit descriptions. 32 ? spr 816 ? 819 s mi_rax mi region x attribute register. see table 4-6 for bit descriptions. 32 ? spr 824 ? 827 s l2u_rax l2u region x attribute register. see table 11-9 for bit descriptions. 32 ? spr 1022 s fpecr floating-point exception cause register see section 3.9.10.2, ?floating-point exception cause register (fpecr)? for bit descriptions. 32 ? table a-2. uc3f flash array address access symbol register size reset uc3f_a 0x00 0000 ? 0x07 ffff u,s uc3f_a uc3f flash array a. 32 ? uc3f_b 0x08 0000 ? 0x0f ffff u,s uc3f_b uc3f flash array b. 32 ? table a-3. decram sram array address access symbol register size reset 0x2f 8000 ? 0x2f 8fff u,s decram decram sram 32 ? table a-1. spr (special purpose registers) (continued) address access symbol register size reset motorola appendix a. internal memory map a-5 indexofmemorymaptables table a-4. bbc (burst buffer controller module) address access symbol register 1 1 see table 4-10 for bit descriptions. size reset 0x2f a004 u dccr1 decompressor class configuration register 32 h 0x2f a008 u dccr2 decompressor class configuration register 32 h 0x2f a00c u dccr3 decompressor class configuration register ? ? 0x2f a010 u dccr4 decompressor class configuration register 16 s 0x2f a014 u dccr5 decompressor class configuration register 32 s 0x2f a018 u dccr6 decompressor class configuration register 32 s 0x2f a01c u dccr7 decompressor class configuration register 32 h 0x2f a020 u dccr8 decompressor class configuration register 32 h 0x2f a024 u dccr9 decompressor class configuration register 32 h 0x2f a028 u dccr10 decompressor class configuration register 32 h 0x2f a02c u dccr11 decompressor class configuration register 32 h 0x2f a030 u dccr12 decompressor class configuration register 32 h 0x2f a034 u dccr13 decompressor class configuration register 32 h 0x2f a038 u dccr14 decompressor class configuration register 32 h 0x2f a03c u dccr15 decompressor class configuration register 32 h table a-5. usiu (unified system interface unit) address access symbol register size reset 0x2f c000 u 1 siumcr siu module configuration register. see table 6-7 for bit descriptions. 32 h 0x2f c004 u 2 sypcr system protection control register. see table 6-15 for bit descriptions. 32 h 0x2f c008 ? ? reserved ? ? 0x2f c00e u, write only swsr software service register. see ion control register. see table 6-16 for bit descriptions. 16 s 0x2f c010 u sipend interrupt pending register. see section 6.14.2.1, ?siu interrupt pending register? for bit descriptions. 32 s 0x2f c014 u simask interrupt mask register. simask is a 32-bit read/write register. each bit in the register corresponds to an interrupt request bit in the sipend register. 32 s 0x2f c018 u siel interrupt edge level mask. see section 6.14.2.7, ?siu interrupt edge level register (siel)? for bit descriptions. 32 h a-6 mpc565/mpc566 reference manual motorola index of memory map tables 0x2f c01c u, read only sivec interrupt vector. see section 6.14.2.8, ?siu interrupt vector register? for bit descriptions. 32 ? 0x2f c020 u tesr transfer error status register. see table 6-17 for bit descriptions. 32 s 0x2f c024 u sgpiodt1 usiu general-purpose i/o data register 1. see table 6-23 for bit descriptions. 32 h 0x2f c028 u sgpiodt2 usiu general-purpose i/o data register 2. see table 6-24 for bit descriptions. 32 h 0x2f c038 u pdmcr2 pads module configuration register 2. see table 2-4 for bit descriptions. 32 h 0x2f c02c u sgpiocr usiu general-purpose i/o control register. see table 6-25 for bit descriptions. 32 h 0x2f c030 u emcr external master mode control register. see table 6-13 for bit descriptions. 32 h 0x2f c038 u pdmcr2 pads module configuration register 2 see table 2-4 for bit descriptions 32 h 0x2f c03c u pdmcr pads module configuration register. see table 2-3 for bit descriptions. 32 h 0x2f c040 ? 0x2f c044 u sipend2 ? sipend3 interrupt pending registers 2 and 3. see section 6.14.2.1, ?siu interrupt pending register? for bit descriptions. 32 s 0x2f c048 ? 0x2f c04c u simask2 ? simask3 interrupt mask register and interrupt mask registers 2 and 3. see section 6.14.2.9, ?interrupt in-service registers? for bit descriptions. 32 s 0x2f c050 ? 0x2f c054 u sisr2 ? sisr3 sisr2and sisr3 registers. see section 6.14.2.9, ?interrupt in-service registers? for bit descriptions. 32 s 0x2f c0fc ? 0x2f c0ff ??reserved ?? table a-5. usiu (unified system interface unit) (continued) address access symbol register size reset motorola appendix a. internal memory map a-7 indexofmemorymaptables memory controller registers 0x2f c100 u br0 base register 0. see table 10-8 for bit descriptions. 32 h 0x2f c104 u or0 option register 0. see table 10-10 for bit descriptions. 32 h 0x2f c108 u br1 base register 1. see table 10-8 for bit descriptions. 32 h 0x2f c10c u or1 option register 1. see table 10-10 for bit descriptions. 32 h 0x2f c110 u br2 base register 2. see table 10-8 for bit descriptions. 32 h 0x2f c114 u or2 option register 2. see table 10-10 for bit descriptions. 32 h 0x2f c118 u br3 base register 3. see table 10-8 for bit descriptions. 32 h 0x2f c11c u or3 option register 3. see table 10-10 for bit descriptions. 32 h 0x2f c120 ? 0x2f c13c ??reserved ?? 0x2f c140 u dmbr dual-mapping base register. see table 10-11 for bit descriptions. 32 h 0x2f c144 u dmor dual-mapping option register. see table 10-12 for bit descriptions. 32 h 0x2f c148 ? 0x2f c174 ??reserved ?? 0x2f c178 u mstat memory status. see table 10-7 for bit descriptions. 16 h system integration timers 0x2f c200 u 3 tbscr time base status and control. see table 6-18 for bit descriptions. 16 h 0x2f c204 u 3 tbref0 time base reference 0. see section 6.14.4.3, ?time base reference registers? for bit descriptions. 32 u 0x2f c208 u 3 tbref1 time base reference 1. see section 6.14.4.3, ?time base reference registers for bit descriptions. 32 u 0x2f c20c ? 0x2f c21c ??reserved ?? 0x2f c220 u 4 rtcsc real-time clock status and control. see table 6-19 for bit descriptions. 16 h table a-5. usiu (unified system interface unit) (continued) address access symbol register size reset a-8 mpc565/mpc566 reference manual motorola index of memory map tables 0x2f c224 u 4 rtc real-time clock. see section 6.14.4.6, ?real-time clock register (rtc)? for bit descriptions. 32 u 0x2f c228 t 4 rtsec real-time alarm seconds, reserved. 32 ? 0x2f c22c u 4 rtcal real-time alarm. see section 6.14.4.7, ?real-time clock alarm register (rtcal) for bit descriptions. 32 u 0x2f c230 ? 0x2f c23c ??reserved ?? 0x2f c240 u 3 piscr pit status and control. see table 6-20 for bit descriptions. 16 h 0x2f c244 u 3 pitc pit count. see table 6-21 for bit descriptions. 32 (half reserved) u 0x2f c248 u, read only pitr pit register. see table 6-22 for bit descriptions. 32 (half reserved) u 0x2f c24c ? 0x2f c27c ??reserved ?? clocks and reset 0x2f c280 u 2 sccr system clock control register. see table 8-9 for bit descriptions. 32 h 0x2f c284 u 3, 5, 6 plprcr pll low power and reset control register. see table 8-11 for bit descriptions. 32 h 0x2f c288 u 3 rsr reset status register. see table 7-3 for bit descriptions. 16 por 0x2f c28c u colir change of lock interrupt register. see table 8-12 for bit descriptions. 16 u 0x2f c290 u vsrcr vddsram1 control register. see table 8-13 for bit descriptions. 16 u 0x2f c294 ? 0x2f c2fc ??reserved ?? system integration timer keys 0x2f c300 u tbscrk time base status and control key. see table 8-8 for bit descriptions. 32 por 0x2f c304 u tbref0k time base reference 0 key. see table 8-8 for bit descriptions. 32 por 0x2f c308 u tbref1k time base reference 1 key. see table 8-8 for bit descriptions. 32 por 0x2f c30c u tbk time base and decrementer key. see table 8-8 for bit descriptions. 32 por table a-5. usiu (unified system interface unit) (continued) address access symbol register size reset motorola appendix a. internal memory map a-9 indexofmemorymaptables 0x2f c310 ? 0x2f c31c ??reserved ?? 0x2f c320 u rtcsck real-time clock status and control key. see table 8-8 for bit descriptions. 32 por 0x2f c324 u rtck real-time clock key. see table 8-8 for bit descriptions. 32 por 0x2f c328 u rtseck real-time alarm seconds key. see table 8-8 for bit descriptions. 32 por 0x2f c32c u rtcalk real-time alarm key. see table 8-8 for bit descriptions. 32 por 0x2f c330 ? 0x2f c33c ??reserved ?? 0x2f c340 u piscrik pit status and control key. see table 8-8 for bit descriptions. 32 por 0x2f c344 u pitck pit count key. see table 8-8 for bit descriptions. 32 por 0x2f c348 ? 0x2f c37c ??reserved ?? clocks and reset keys 0x2f c380 u sccrk system clock control key. see table 8-8 for bit descriptions. 32 por 0x2f c384 u plprcrk pll low-power and reset control register key. see table 8-8 for bit descriptions. 32 por 0x2f c388 u rsrk reset status register key. see table 8-8 for bit descriptions. 32 por 0x2f c38c ? 0x2f c3fc ??reserved ?? 1 entire register is locked if bit 15 (dlk) is set. 2 write once after power on reset (por). 3 must use the key register to unlock if it has been locked by a key register, see section 8.8.3.2, ?keep-alive power registers lock mechanism.? 4 locked after power on reset (por). a write of 0x55ccaa33 must performed to the key register to unlock. see section 8.8.3.2, ?keep-alive power registers lock mechanism.? 5 can have bits 0:11 (mf bits) write-protected by setting bit 4 (mfpdl) in the sccr register to 1. bit 21 (csrc) and bits 22:23 (lpm) can be locked by setting bit 5 (lpml) of the sccr register to 1. 6 bit 24 (csr) is write-once after soft reset. table a-5. usiu (unified system interface unit) (continued) address access symbol register size reset a-10 mpc565/mpc566 reference manual motorola index of memory map tables table a-6. cdr3 flash control registers eeprom (uc3f) address access symbol register size reset c3f_a 0x2f c800 u, s c3fmcr_a c3f eeprom configuration register. see table 20-3 for bit descriptions. 32 por, h 0x2f c804 u, s c3fmcre_a c3f eeprom extended configuration register. see table 20-4 for bit descriptions. 32 por, h 0x2f c808 u, s c3fctl_a c3f eeprom high voltage control register. see table 20-5 for bit descriptions. 32 por, h c3f_b 0x2f c840 u, s c3fmcr_b c3f eeprom configuration register 32 por, h 0x2f c844 u, s c3fmcre_b c3f eeprom extended configuration register 32 por, h 0x2f c848 u, s c3fctl_b c3f eeprom high voltage control register 32 por, h table a-7. dptram ab and c control registers address access symbol register size reset dptram_ab control 0x30 0000 u, s 1 1 access to the dptram_ab array through the imb3 bus is disabled once bit 5 (emu) of either tpumcr_a or tpumcr_b is set. dptmcr_ab dptram module configuration register. see table 19-2 for bit descriptions. 16 s 0x30 0002 s dpttcr_ab test configuration register. 16 s 0x30 0004 s rambar_ab ram array base address register. see table 19-3 for bit descriptions. 16 s 0x30 0006 s misrh_ab multiple input signature register high. 16 s 0x30 0008 s misrl_ab multiple input signature register low. 16 s 0x30 000a s miscnt_ab misc counter register. 16 s dptram_c control 0x30 0040 u, s 2 2 access to the dptram_c array through the imb3 bus is disabled once bit 5 (emu) of tpumcr_c is set. dptmcr_c dptram module configuration register. see table 19-2 for bit descriptions. 16 s 0x30 0042 s dpttcr_c test configuration register. 16 s 0x30 0044 s rambar_c ram array base address register. see table 19-3 for bit descriptions. 16 s 0x30 0046 s misrh_c multiple input signature register high. 16 s 0x30 0048 s misrl_c multiple input signature register low. 16 s 0x30 004a s miscnt_c misc counter register. 16 s motorola appendix a. internal memory map a-11 indexofmemorymaptables table a-8. dlcmd2 (data link controller module) address access symbol register size reset 0x30 0080 s mcr module configuration register. see table 15-7 for bit descriptions. 16 s, m 0x30 0084 s ipr interrupt pending register. see table 15-9 for bit descriptions. 16 s, m 0x30 0086 ? 0x30 0087 s ilr ? ivr interrupt level register and interrupt vector register. see table 15-10 and table 15-12 for bit descriptions. 16 s, m 0x30 0088 s/u sctl symbol timing control and pre-scaler register. see table 15-13 for bit descriptions. 16 s, m 0x30 008a s/u sdata symbol timing control and pre-scaler register. see table 15-15 for bit descriptions. 16 s, m 0x30 008c ? 0x30 008d s/u cmd ? tdata command register and transmit data register. see table 15-17 and table 15-22 for bit descriptions. 16 s, m 0x30 008e ? 0x30 008f s/u stat ? rdata status register and receive data register. see table 15-23 and table 15-29 for bit descriptions. 16 s, m table a-9. dptram memory arrays dptram_c memory array 0x30 1000 ? 0x30 1fff u, s 1 1 access to the dptram_c array through the imb3 bus is disabled once bit 5 (emu) of tpumcr_c is set. dpram_c dptram memory array 16 ? dptram_ab memory array 0x30 2000 ? 0x30 37ff u, s 2 2 access to the dptram_ab array through the imb3 bus is disabled once bit 5 (emu) of either tpumcr_a or tpumcr_b is set. dptram_ab dptram memory array 16 ? table a-10. time processor unit 3 a and b (tpu3 a and b) address access symbol register size reset tpu_a (note: bit descriptions apply to tpu_b and tpu_c as well) 0x30 4000 s 1 tpumcr_a tpu3_a module configuration register. see table 18-7 for bit descriptions. 16 only s, m 0x30 4002 t tcr_a tpu3_a test configuration register. 16 s, m 0x30 4004 s dscr_a tpu3_a development support control register. see table 18-8 for bit descriptions. 16 2 s, m a-12 mpc565/mpc566 reference manual motorola index of memory map tables 0x30 4006 s dssr_a tpu3_a development support status register. see table 18-9 for bit descriptions. 16 2 s, m 0x30 4008 s ticr_a tpu3_a interrupt configuration register. see table 18-10 for bit descriptions. 16 2 s, m 0x30 400a s cier_a tpu3_a channel interrupt enable register. see table 18-11 for bit descriptions. 16 2 s, m 0x30 400c s cfsr0_a tpu3_a channel function selection register 0. see table 18-12 for bit descriptions. 16 2 s, m 0x30 400e s cfsr1_a tpu3_a channel function selection register 1. see table 18-12 for bit descriptions. 16 2 s, m 0x30 4010 s cfsr2_a tpu3_a channel function selection register 2. see table 18-12 for bit descriptions. 16 2 s, m 0x30 4012 s cfsr3_a tpu_a channel function selection register 3. see table 18-12 for bit descriptions. 16 2 s, m 0x30 4014 s/u 3 hsqr0_a tpu_a host sequence register 0. see table 18-13 for bit descriptions. 16 2 s, m 0x30 4016 s/u 3 hsqr1_a tpu_a host sequence register 1. see table 18-13 for bit descriptions. 16 2 s, m 0x30 4018 s/u3 hsrr0_a tpu_a host service request register 0. see table 18-14 for bit descriptions. 16 2 s, m 0x30 401a s/u3 hsrr1_a tpu_a host service request register 1. see table 18-14 for bit descriptions. 16 2 s, m 0x30 401c s cpr0_a tpu_a channel priority register 0. see table 18-15 for bit descriptions. 16 2 s, m 0x30 401e s cpr1_a tpu_a channel priority register 1. see table 18-15 for bit descriptions. 16 2 s, m 0x30 4020 s cisr_a tpu_a channel interrupt status register. see table 18-17 for bit descriptions. 16 s, m 0x30 4022 t lr_a tpu_a link register 4 16 2 s, m 0x30 4024 t sglr_a tpu_a service grant latch register 4 16 2 s, m 0x30 4026 t dcnr_a tpu_a decoded channel number register 4 16 2 s, m 0x30 4028 s 5 tpumcr2_a tpu_a module configuration register 2. see table 18-18 for bit descriptions. 16 2 s, m 0x30 402a s tpumcr3_a tpu_a module configuration register 3. see table 18-21 for bit descriptions. 16 2 s, m 0x30 402c t isdr_a tpu_a internal scan data register 16, 32 2 ? 0x30 402e t iscr_a tpu_a internal scan control register 16, 32 2 ? 0x30 4100 ? 0x30 410f s/u 3 ? tpu_a channel 0 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? table a-10. time processor unit 3 a and b (tpu3 a and b) (continued) address access symbol register size reset motorola appendix a. internal memory map a-13 indexofmemorymaptables 0x30 4110 ? 0x30 411f s/u 3 ? tpu_a channel 1 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 4120 ? 0x30 412f s/u 3 ? tpu_a channel 2 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 4130 ? 0x30 413f s/u 3 ? tpu_a channel 3 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 4140 ? 0x30 414f s/u 3 ? tpu_a channel 4 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 4150 ? 0x30 415f s/u 3 ? tpu_a channel 5 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 4160 ? 0x30 416f s/u 3 ? tpu_a channel 6 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 4170 ? 0x30 417f s/u 3 ? tpu_a channel 7 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 4180 ? 0x30 418f s/u 3 ? tpu_a channel 8 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 4190 ? 0x30 419f s/u 3 ? tpu_a channel 9 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 41a0 ? 0x30 41af s/u 3 ? tpu_a channel 10 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 41b0 ? 0x30 41bf s/u 3 ? tpu_a channel 11 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 41c0 ? 0x30 41cf s/u 3 ? tpu_a channel 11 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 41d0 ? 0x30 41df s/u 3 ? tpu_a channel 11 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 41e0 ? 0x30 41ef s/u 3 ? tpu_a channel 14 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? 0x30 41f0 ? 0x30 41ff s/u 3 ? tpu_a channel 15 parameter registers. see section 18.4.18, ?tpu3 parameter ram for more information. 16, 32 2 ? table a-10. time processor unit 3 a and b (tpu3 a and b) (continued) address access symbol register size reset a-14 mpc565/mpc566 reference manual motorola index of memory map tables tpu_b 0x30 4400 1 s 1 tpumcr_b tpu3_b module configuration register 16 only s, m 0x30 4402 t tcr_b tpu3_b test configuration register 16 s, m 0x30 4404 s dscr_b tpu3_b development support control register 16 2 s, m 0x30 4406 s dssr_b tpu3_b development support status register 16 2 s, m 0x30 4408 s ticr_b tpu3_b interrupt configuration register 16 2 s, m 0x30 440a s cier_b tpu3_b channel interrupt enable register 16 2 s, m 0x30 440c s cfsr0_b tpu3_b channel function selection register 0 16 2 s, m 0x30 440e s cfsr1_b tpu3_b channel function selection register 1 16 2 s, m 0x30 4410 s cfsr2_b tpu3_b channel function selection register 2 16 2 s, m 0x30 4412 s cfsr3_b tpu_b channel function selection register 3 16 2 s, m 0x30 4414 s/u 3 hsqr0_b tpu_b host sequence register 0 16 2 s, m 0x30 4416 s/u 3 hsqr1_b tpu_b host sequence register 1 16 2 s, m 0x30 4418 s/u 3 hsrr0_b tpu_b host service request register 0 16 2 s, m 0x30 441a s/u 3 hsrr1_b tpu_b host service request register 1 16 2 s, m 0x30 441c s cpr0_b tpu_b channel priority register 0 16 2 s, m 0x30 441e s cpr1_b tpu_b channel priority register 1 16 2 s, m 0x30 4420 s cisr_b tpu_b channel interrupt status register 16 s, m 0x30 4422 t lr_b tpu_b link register 16 2 s, m 0x30 4424 t sglr_b tpu_b service grant latch register 16 2 s, m 0x30 4426 t dcnr_b tpu_b decoded channel number register 16 2 s, m 0x30 4428 s 4 tpumcr2_b tpu_b module configuration register 2 16 2 s, m 0x30 442a s tpumcr3_b tpu_b module configuration register 3 16, 32 2 s, m 0x30 442c t isdr_b tpu_b internal scan data register 16, 32 2 ? 0x30 442e t iscr_b tpu_b internal scan control register 16, 32 2 ? 0x30 4500 ? 0x30 450f s/u 3 ? tpu_b channel 0 parameter registers 16, 32 2 ? 0x30 4510 ? 0x30 451f s/u 3 ? tpu_b channel 1 parameter registers 16, 32 2 ? 0x30 4520 ? 0x30 452f s/u 3 ? tpu_b channel 2 parameter registers 16, 32 2 ? 0x30 4530 ? 0x30 453f s/u 3 ? tpu_b channel 3 parameter registers 16, 32 2 ? 0x30 4540 ? 0x30 454f s/u 3 ? tpu_b channel 4 parameter registers 16, 32 2 ? table a-10. time processor unit 3 a and b (tpu3 a and b) (continued) address access symbol register size reset motorola appendix a. internal memory map a-15 indexofmemorymaptables 0x30 4550 ? 0x30 455f s/u 3 ? tpu_b channel 5 parameter registers 16, 32 2 ? 0x30 4560 ? 0x30 456f s/u 3 ? tpu_b channel 6 parameter registers 16, 32 2 ? 0x30 4570 ? 0x30 457f s/u 3 ? tpu_b channel 7 parameter registers 16, 32 2 ? 0x30 4580 ? 0x30 458f s/u 3 ? tpu_b channel 8 parameter registers 16, 32 2 ? 0x30 4590 ? 0x30 459f s/u 3 ? tpu_b channel 9 parameter registers 16, 32 2 ? 0x30 45a0 ? 0x30 45af s/u 3 ? tpu_b channel 10 parameter registers 16, 32 2 ? 0x30 45b0 ? 0x30 45bf s/u 3 ? tpu_b channel 11 parameter registers 16, 32 2 ? 0x30 45c0 ? 0x30 45cf s/u 3 ? tpu_b channel 11 parameter registers 16, 32 2 ? 0x30 45d0 ? 0x30 45df s/u 3 ? tpu_b channel 11 parameter registers 16, 32 2 ? 0x30 45e0 ? 0x30 45ef s/u 3 ? tpu_b channel 14 parameter registers 16, 32 2 ? 0x30 45f0 ? 0x30 45ff s/u 3 ? tpu_b channel 15 parameter registers 16 2 ? 1 bit 10 (tpu3) and bit 11 (t2csl) are write-once. bits 1:2 (tcr1p) and bits 3:4 (tcr2p) are write-once if pwod is not set in the tpumcr3 register. this register cannot be accessed with a 32-bit read. it can only be accessed with an 8- or 16-bit read. 2 some tpu registers can only be read or written with 16- or 32-bit accesses. 8-bit accesses are not allowed. 3 s/u = supervisor accessible only if supv = 1 or unrestricted if supv = 0. unrestricted registers allow both user and supervisor access. the supv bit is in the tpumcr register. 4 tpu code development (debug) register 5 bits 9:10 (etbank), 14 (t2cf), and 15 (dtpu) are write-once. table a-11. qadc64e a and b (queued analog-to-digital converter) address access symbol register size reset qadc_a (note: bit descriptions apply to qadc_b as well) 0x30 4800 s qadc64mcr_a qadc64 module configuration register. see table 13-5 for bit descriptions. 16 s 0x30 4802 s qadc64tst qadc64 test register. 16 s 0x30 4804 s qadc64int_a interrupt register. see section 13.2.2, ?qadc64e interrupt register,? for bit descriptions. 16 s table a-10. time processor unit 3 a and b (tpu3 a and b) (continued) address access symbol register size reset a-16 mpc565/mpc566 reference manual motorola index of memory map tables 0x30 4806 s/u portqa_a/ portqb_a port a and port b data. see table 13-20 for bit descriptions. 16 u 0x30 4808 s/u ddrqa_a/ ddrqb_a port a data and port b direction register. see table 13-20 for bit descriptions. 16 s 0x30 480a s/u qacr0_a qadc64 control register 0. see table 13-8 for bit descriptions. 16 s 0x30 480c s/u 1 qacr1_a qadc64 control register 1. see table 13-8 for bit descriptions. 16 s 0x30 480e s/u 1 qacr2_a qadc64 control register 2. see table 13-12 for bit descriptions. 16 s 0x30 4810 s/u qasr0_a qadc64 status register 0. see table 13-8 for bit descriptions. 16 s 0x30 4812 s/u qasr1_a qadc64 status register 1. see table 13-15 for bit descriptions. 16 s 0x30 4814 ? 0x30 49fe ??reserved ?? 0x30 4a00 ? 0x30 4a7e s/u ccw_a conversion command word table. see table 13-17 for bit descriptions. 16 u 0x30 4a80 ? 0x30 4afe s/u rjurr_a result word table right-justified, unsigned result register. see section 13.2.10, ?result word table,? for bit descriptions. 16 x 0x30 4b00 ? 0x30 4b7e s/u ljsrr_a result word table left-justified, signed result register. see section 13.2.10, ?result word table,? for bit descriptions. 16 x 0x30 4b80 ? 0x30 4bfe s/u ljurr_a result word table left-justified, unsigned result register. see section 13.2.10, ?result word table,? for bit descriptions. 16 x qadc_b 0x30 4c00 s qadc64mcr_b qadc64 module configuration register 16 s 0x30 4c02 t qadc64test_b qadc64 test register 16 ? 0x30 4c04 s qadc64int_b interrupt register 16 s 0x30 4c06 s/u portqa_b/por tqb_b port a and port b data 16 u 0x30 4c08 s/u ddrqa_b/ ddrqb_b port a data and port b direction register 16 s 0x30 4c0a s/u qacr0_b qadc64 control register 0 16 s 0x30 4c0c s/u 1 qacr1_b qadc64 control register 1 16 s 0x30 4c0e s/u 1 qacr2_b qadc64 control register 2 16 s table a-11. qadc64e a and b (queued analog-to-digital converter) (continued) address access symbol register size reset motorola appendix a. internal memory map a-17 indexofmemorymaptables 0x30 4c10 s/u qasr0_b qadc64 status register 0 16 s 0x30 4c12 s/u qasr1_b qadc64 status register 1 16 s 0x30 4c14 ? 0x30 4dfe ??reserved ?? 0x30 4e00 ? 0x30 4e7e s/u ccw_b conversion command word table 16 u 0x30 4e80 ? 0x30 4efe s/u rjurr_b result word table. right-justified, unsigned result register. 16 x 0x30 4f00 ? 0x30 4f7e s/u ljsrr_b result word table. left-justified, signed result register. 16 x 0x30 4f80 ? 0x30 4ffe s/u ljurr_b result word table. left-justified, unsigned result register. 16 x 1 bit 3 (ssex) is readable in test mode only. table a-12. qsmcm a and b (queued serial multi-channel module) address access symbol register size reset qsmcm_a (note: bit descriptions apply to qsmcm_b as well) 0x30 5000 s qsmcmmcr_a qsmcm module configuration register. see table 14-7 for bit descriptions. 16 s 0x30 5002 t qtest_a qsmcm test register 16 s 0x30 5004 s qdsci_il_a dual sci interrupt level. see table 14-8 for bit descriptions. 16 s 0x30 5006 s qspi_il_a queued spi interrupt level. see table 14-9 for bit descriptions. 16 s 0x30 500a s/u scc1r1_a sci1control register 1. see table 14-28 for bit descriptions. 16 s 0x30 500c s/u sc1sr_a sci1 status register. see table 14-29 for bit descriptions. 16 s 0x30 500e s/u sc1dr_a sci1 data register. see table 14-30 for bit descriptions. 16 s 0x30 5010 ? 0x30 5012 ??reserved ?? 0x30 5014 s/u portqs_a qsmcm port qs data register. see section 14.6.1, ?port qs data register (portqs),? for bit descriptions. 16 s 0x30 5016 s/u pqspar/ ddrqst_a qsmcm port qs pin assignment register/ qsmcm port qs data direction register. see table 14-14 for bit descriptions. 16 s table a-11. qadc64e a and b (queued analog-to-digital converter) (continued) address access symbol register size reset a-18 mpc565/mpc566 reference manual motorola index of memory map tables 0x30 5018 s/u spcr0_a qspi control register 0. see table 14-17 for bit descriptions. 16 s 0x30 501a s/u spcr1_a qspi control register 1. see table 14-17 for bit descriptions. 16 s 0x30 501c s/u spcr2_a qspi control register 2. see table 14-20 for bit descriptions. 16 s 0x30 501e s/u spcr3_a qspi control register 3. see table 14-21 for bit descriptions. 8s 0x30 501f s/u spsr_a qspi status register 3. see table 14-22 for bit descriptions. 8s 0x30 5020 s/u scc2r0_a sci2 control register 0. see table 14-27 for bit descriptions. 16 s 0x30 5022 s/u scc2r1_a sci2 control register 1. see table 14-28 for bit descriptions. 16 s 0x30 5024 s/u sc2sr_a sci2 status register. see table 14-29 for bit descriptions. 16 s 0x30 5026 s/u sc2dr_a sci2 data register. see table 14-30 for bit descriptions. 16 s 0x30 5028 s/u 1 qsci1cr_a qsci1 control register. see table 14-35 for bit descriptions. 16 s 0x30 502a s/u 2 qsci1sr_a qsci1 status register. see table 14-36 for bit descriptions. 16 s 0x30 502c ? 0x30 504a s/u sctq_a transmit queue locations 16 s 0x30 504c ? 0x30 506a s/u scrq_a receive queue locations 16 s 0x30 506c ? 0x30 513f ??reserved ?? 0x30 5140 ? 0x30 517f s/u recram_a receive data ram 16 s 0x30 5180 ? 0x30 51bf s/u tran.ram_a transmit data ram 16 s 0x30 51c0 ? 0x30 51df s/u comd.ram_a command ram 16 s qsmcm_b 0x30 5400 s qsmcmmcr_b qsmcm module configuration register. see table 14-7 for bit descriptions. 16 s 0x30 5402 t qtest_b qsmcm test register 16 s 0x30 5404 s qdsci_il_b dual sci interrupt level. see table 14-8 for bit descriptions. 16 s table a-12. qsmcm a and b (queued serial multi-channel module) (continued) address access symbol register size reset motorola appendix a. internal memory map a-19 indexofmemorymaptables 0x30 5406 s qspi_il_b queued spi interrupt level. see table 14-9 for bit descriptions. 16 s 0x30 540a s/u scc1r1_b sci1control register 1. see table 14-28 for bit descriptions. 16 s 0x30 540c s/u sc1sr_b sci1 status register. see table 14-29 for bit descriptions. 16 s 0x30 540e s/u sc1dr_b sci1 data register. see table 14-30 for bit descriptions. 16 s 0x30 5410 ? 0x30 5412 ??reserved ?? 0x30 5414 s/u portqs_b qsmcm port qs data register. see section 14.6.1, ?port qs data register (portqs),? for bit descriptions. 16 s 0x30 5416 s/u pqspar/ ddrqst_b qsmcm port qs pin assignment register/ qsmcm port qs data direction register. see table 14-14 for bit descriptions. 16 s 0x30 5418 s/u spcr0_b qspi control register 0. see table 14-17 for bit descriptions. 16 s 0x30 541a s/u spcr1_b qspi control register 1. see table 14-19 for bit descriptions. 16 s 0x30 541c s/u spcr2_b qspi control register 2. see table 14-20 for bit descriptions. 16 s 0x30 541e s/u spcr3_b qspi control register 3. see table 14-21 for bit descriptions. 8s 0x30 541f s/u spsr_b qspi status register 3. see table 14-22 for bit descriptions. 8s 0x30 5420 s/u scc2r0_b sci2 control register 0 16 s 0x30 5422 s/u scc2r1_b sci2 control register 1 16 s 0x30 5424 s/u sc2sr_b sci2 status register 16 s 0x30 5426 s/u sc2dr_b sci2 data register 16 s 0x30 5428 s/u 3 qsci1cr_b qsci1 control register. see table 14-35 for bit descriptions. 16 s 0x30 542a s/u 4 qsci1sr_b qsci1 status register. see table 14-36 for bit descriptions. 16 s 0x30 542c ? 0x30 544a s/u sctq_b transmit queue locations 16 s 0x30 544c ? 0x30 546a s/u scrq_b receive queue locations 16 s 0x30 546c ? 0x30 553f ??reserved ?? table a-12. qsmcm a and b (queued serial multi-channel module) (continued) address access symbol register size reset a-20 mpc565/mpc566 reference manual motorola index of memory map tables 0x30 5540 ? 0x30 557f s/u recram_b receive data ram 16 s 0x30 5580 ? 0x30 55bf s/u tran.ram_b transmit data ram 16 s 0x30 55c0 ? 0x30 55df s/u comd.ram_b command ram 16 s 1 bits 0?3 writeable only in test mode, otherwise read only. 2 bits 3?11 writeable only in test mode, otherwise read only. 3 bits 0?3 writeable only in test mode, otherwise read only. 4 bits 3?11 writeable only in test mode, otherwise read only. table a-13. time processor unit 3 c (tpu3_c) (see table a-10 for bit descriptions) address access symbol register size reset tpu_c 0x30 5c00 1 s 1 tpumcr_c tpu3_c module configuration register 16 only s, m 0x30 5c02 t tcr_c tpu3_c test configuration register 16 s, m 0x30 5c04 s dscr_c tpu3_c development support control register 16 2 s, m 0x30 5c06 s dssr_c tpu3_c development support status register 16 2 s, m 0x30 5c08 s ticr_c tpu3_c interrupt configuration register 16 2 s, m 0x30 5c0a s cier_c tpu3_c channel interrupt enable register 16 2 s, m 0x30 5c0c s cfsr0_c tpu3_c channel function selection register 0 16 2 s, m 0x30 5c0e s cfsr1_c tpu3_c channel function selection register 1 16 2 s, m 0x30 5c10 s cfsr2_c tpu3_c channel function selection register 2 16 2 s, m 0x30 5c12 s cfsr3_c tpu_c channel function selection register 3 16 2 s, m 0x30 5c14 s/u 3 hsqr0_c tpu_c host sequence register 0 16 2 s, m 0x30 5c16 s/u 3 hsqr1_c tpu_c host sequence register 1 16 2 s, m 0x30 5c18 s/u 3 hsrr0_c tpu_c host service request register 0 16 2 s, m 0x30 5c1a s/u 3 hsrr1_c tpu_c host service request register 1 16 2 s, m 0x30 5cc s cpr0_c tpu_c channel priority register 0 16 2 s, m 0x30 5c1e s cpr1_c tpu_c channel priority register 1 16 2 s, m 0x30 5c20 s cisr_c tpu_c channel interrupt status register 16 s, m table a-12. qsmcm a and b (queued serial multi-channel module) (continued) address access symbol register size reset motorola appendix a. internal memory map a-21 indexofmemorymaptables 0x30 5c22 t lr_c tpu_c link register 16 2 s, m 0x30 5c24 t sglr_c tpu_c service grant latch register 16 2 s, m 0x30 5c26 t dcnr_c tpu_c decoded channel number register 16 2 s, m 0x30 5c28 s 4 tpumcr2_c tpu_c module configuration register 2 16 2 s, m 0x30 5c2a s tpumcr3_c tpu_c module configuration register 3 16, 32 2 s, m 0x30 5c2c t isdr_c tpu_c internal scan data register 16, 32 2 0x30 5c2e t iscr_c tpu_c internal scan control register 16, 32 2 0x30 5d00 ? 0x30 5d0e s/u 3 ? tpu_c channel 0 parameter registers 16, 32 2 0x30 5d10 ? 0x30 5d1e s/u 3 ? tpu_c channel 1 parameter registers 16, 32 2 0x30 5d20 ? 0x30 5d2e s/u 3 ? tpu_c channel 2 parameter registers 16, 32 2 0x30 5d30 ? 0x30 5d3e s/u 3 ? tpu_c channel 3 parameter registers 16, 32 2 0x30 5d40 ? 0x30 5d4e s/u 3 ? tpu_c channel 4 parameter registers 16, 32 2 0x30 5d50 ? 0x30 5d5e s/u 3 ? tpu_c channel 5 parameter registers 16, 32 2 0x30 5d60 ? 0x30 5c6e s/u 3 ? tpu_c channel 6 parameter registers 16, 32 2 0x30 5d70 ? 0x30 5c7e s/u 3 ? tpu_c channel 7 parameter registers 16, 32 2 0x30 5d80 ? 0x30 5d8e s/u 3 ? tpu_c channel 8 parameter registers 16, 32 2 0x30 5d90 ? 0x30 5d9e s/u 3 ? tpu_c channel 9 parameter registers 16, 32 2 0x30 5da0 ? 0x30 5dae s/u 3 ? tpu_c channel 10 parameter registers 16, 32 2 0x30 5db0 ? 0x30 5dbf s/u 3 ? tpu_c channel 11 parameter registers 16, 32 2 0x30 5dc0 ? 0x30 5dcf s/u 3 ? tpu_c channel 11 parameter registers 16, 32 2 0x30 5dd0 ? 0x30 5ddf s/u 3 ? tpu_c channel 11 parameter registers 16, 32 2 0x30 5de0 ? 0x30 5def s/u 3 ? tpu_c channel 14 parameter registers 16, 32 2 0x30 5df0 ? 0x30 5dff s/u 3 ? tpu_c channel 15 parameter registers 16 2 table a-13. time processor unit 3 c (tpu3_c) (continued) (see table a-10 for bit descriptions) (continued) address access symbol register size reset a-22 mpc565/mpc566 reference manual motorola index of memory map tables 1 bit 10 (tpu3) and bit 11 (t2csl) are write-once. bits 1:2 (tcr1p) and bits 3:4 (tcr2p) are write-once if pwod is not set in the tpumcr3 register. this register cannot be accessed with a 32-bit read. it can only be accessed with an 8- or 16-bit read. 2 some tpu registers can only be read or written with 16- or 32-bit accesses. 8-bit accesses are not allowed. 3 s/u = supervisor accessible only if supv = 1 or unrestricted if supv = 0. unrestricted registers allow both user and supervisor access. the supv bit is in the tpumcr register. table a-14. mios14 (modular input/output subsystem) address access symbol register size reset mpwmsm0 (mios pulse width modulation submodule 0) 0x30 6000 s/u mpwmperr mpwmsm0 period register. see table 17-28 for bit descriptions. 16 s 1 0x30 6002 s/u mpwmpulr mpwmsm0 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 6004 s/u mpwmcntr mpwmsm0 counter register. see table 17-30 for bit descriptions. 16 s 0x30 6006 s/u mpwmscr mpwmsm0 status/control register. see table 17-31 for bit descriptions. 16 s mpwmsm1 (mios pulse width modulation submodule 1) 0x30 6008 s/u mpwmperr mpwmsm1 period register. see table 17-28 for bit descriptions. 16 s 0x30 600a s/u mpwmpulr mpwmsm1 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 600c s/u mpwmcntr mpwmsm1 counter register. see table 17-30 for bit descriptions. 16 s 0x30 600e s/u mpwmscr mpwmsm1 status/control register. see table 17-31 for bit descriptions. 16 s mpwmsm2 (mios pulse width modulation submodule 2) 0x30 6010 s/u mpwmperr mpwmsm2 period register. see table 17-28 for bit descriptions. 16 s 0x30 6012 s/u mpwmpulr mpwmsm2 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 6014 s/u mpwmcntr mpwmsm2 counter register. see table 17-30 for bit descriptions. 16 s 0x30 6016 s/u mpwmscr mpwmsm2 status/control register. see table 17-31 for bit descriptions. 16 s mpwmsm3 (mios pulse width modulation submodule 3) 0x30 6018 s/u mpwmperr mpwmsm3 period register. see table 17-28 for bit descriptions. 16 s 0x30 601a s/u mpwmpulr mpwmsm3 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 601c s/u mpwmcntr mpwmsm3 counter register. see table 17-30 for bit descriptions. 16 s motorola appendix a. internal memory map a-23 indexofmemorymaptables 0x30 601e s/u mpwmscr mpwmsm3 status/control register. see table 17-31 for bit descriptions. 16 s mpwmsm4 (mios pulse width modulation submodule 4) 0x30 6020 s/u mpwmperr mpwmsm4 period register. see table 17-28 for bit descriptions. 16 s 0x30 6022 s/u mpwmpulr mpwmsm4 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 6024 s/u mpwmcntr mpwmsm4 counter register. see table 17-30 for bit descriptions. 16 s 0x30 6026 s/u mpwmscr mpwmsm4 status/control register. see table 17-31 for bit descriptions. 16 s mpwmsm5 (mios pulse width modulation submodule 5) 0x30 6028 s/u mpwmperr mpwmsm5 period register. see table 17-28 for bit descriptions. 16 s 0x30 602a s/u mpwmpulr mpwmsm5 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 602c s/u mpwmcntr mpwmsm5 counter register. see table 17-30 for bit descriptions. 16 s 0x30 602e s/u mpwmscr mpwmsm5 status/control register. see table 17-31 for bit descriptions. 16 s mmcsm6 (mios modulus counter submodule 6) 0x30 6030 s/u mmcsmcnt mmcsm6 up-counter register. see table 17-12 for bit descriptions. 16 x 0x30 6032 s/u mmcsmml mmcsm6 modulus latch register. see table 17-13 for bit descriptions. 16 s 0x30 6034 s/u mmcsmscrd mmcsm6 status/control register. see table 17-14 for bit descriptions. 16 s 0x30 6036 s/u mmcsmscr mmcsm6 status/control register. see table 17-14 for bit descriptions. 16 s table a-14. mios14 (modular input/output subsystem) (continued) address access symbol register size reset a-24 mpc565/mpc566 reference manual motorola index of memory map tables mmcsm7 (mios modulus counter submodule 7) 0x30 6038 s/u mmcsmcnt mmcsm7 up-counter register. see table 17-12 for bit descriptions. 16 x 0x30 603a s/u mmcsmml mmcsm7 modulus latch register. see table 17-13 for bit descriptions. 16 s 0x30 603e s/u mmcsmscr mmcsm7 status/control register. see table 17-14 for bit descriptions. 16 s mmcsm8 (mios modulus counter submodule 8) 0x30 6040 s/u mmcsmcnt mmcsm8 up-counter register. see table 17-12 for bit descriptions. 16 x 0x30 6042 s/u mmcsmml mmcsm8 modulus latch register. see table 17-13 for bit descriptions. 16 s 0x30 6046 s/u mmcsmscr mmcsm8 status/control register. see table 17-14 for bit descriptions. 16 s mrtcsm (mios real-time clock submodule) 0x30 6050 s/u mrtcsmfrch mrtcsm 32-bit counter high buffer register. see table 17-46 for bit descriptions. 16 u 0x30 6052 s/u mrtcsmfrcl mrtcsm 32-bit counter low buffer register. see table 17-47 for bit descriptions. 16 u 0x30 6054 s/u mrtcpr mrtcsm prescaler counter buffer register. see table 17-48 for bit descriptions. 16 u 0x30 6056 s/u mrtcsm mrtcsm status/control register. see table 17-49 for bit descriptions. 16 s mdasm11 (mios double action submodule 11) 0x30 6058 s/u mdasmar mdasm11 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 605a s/u mdasmbr mdasm11 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 605a s/u mdasmscr mdasm11 status/control register. see table 17-23 for bit descriptions. 16 s mdasm12 (mios double action submodule 12) 0x30 6060 s/u mdasmar mdasm12 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 6062 s/u mdasmbr mdasm12 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 6064 s/u mdasmscrd mdasm12 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 6066 s/u mdasmscr mdasm status/control register. see table 17-23 for bit descriptions. 16 s table a-14. mios14 (modular input/output subsystem) (continued) address access symbol register size reset motorola appendix a. internal memory map a-25 indexofmemorymaptables mdasm13 (mios double action submodule 13) 0x30 6068 s/u mdasmar mdasm13 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 606a s/u mdasmbr mdasm13 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 606e s/u mdasmscr mdasm13 status/control register. see table 17-23 for bit descriptions. 16 s mdasm14 (mios double action submodule 14) 0x30 6070 s/u mdasmar mdasm14 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 6072 s/u mdasmbr mdasm14 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 6076 s/u mdasmscr mdasm14 status/control register. see table 17-23 for bit descriptions. 16 s mdasm (mios double action submodule 15) 0x30 6078 s/u mdasmar mdasm15 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 607a s/u mdasmbr mdasm15 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 607e s/u mdasmscr mdasm15 status/control register. see table 17-23 for bit descriptions. 16 s mpwmsm16 (mios pulse width modulation submodule 16) 0x30 6080 s/u mpwmperr mpwmsm16 period register. see table 17-28 for bit descriptions. 16 s 0x30 6082 s/u mpwmpulr mpwmsm16 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 6084 s/u mpwmcntr mpwmsm16 counter register. see table 17-30 for bit descriptions. 16 s 0x30 6086 s/u mpwmscr mpwmsm16 status/control register. see table 17-31 for bit descriptions. 16 s mpwmsm17 (mios pulse width modulation submodule 17) 0x30 6088 s/u mpwmperr mpwmsm17 period register. see table 17-28 for bit descriptions. 16 s 0x30 608a s/u mpwmpulr mpwmsm17 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 608c s/u mpwmcntr mpwmsm17 counter register. see table 17-30 for bit descriptions. 16 s 0x30 608e s/u mpwmscr mpwmsm17 status/control register. see table 17-31 for bit descriptions. 16 s table a-14. mios14 (modular input/output subsystem) (continued) address access symbol register size reset a-26 mpc565/mpc566 reference manual motorola index of memory map tables mpwmsm18 (mios pulse width modulation submodule 18) 0x30 6090 s/u mpwmperr mpwmsm18 period register. see table 17-28 for bit descriptions. 16 s 0x30 6092 s/u mpwmpulr mpwmsm18 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 6094 s/u mpwmcntr mpwmsm18 counter register. see table 17-30 for bit descriptions. 16 s 0x30 6096 s/u mpwmscr mpwmsm18 status/control register. see table 17-31 for bit descriptions. 16 s mpwmsm19 (mios pulse width modulation submodule 19) 0x30 6098 s/u mpwmperr mpwmsm19 period register. see table 17-28 for bit descriptions. 16 s 0x30 609a s/u mpwmpulr mpwmsm19 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 609c s/u mpwmcntr mpwmsm19 counter register. see table 17-30 for bit descriptions. 16 s 0x30 609e s/u mpwmscr mpwmsm19 status/control register. see table 17-31 for bit descriptions. 16 s mpwmsm20 (mios pulse width modulation submodule 20) 0x30 60a0 s/u mpwmperr mpwmsm20 period register. see table 17-28 for bit descriptions. 16 s 0x30 60a2 s/u mpwmpulr mpwmsm20 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 60a4 s/u mpwmcntr mpwmsm20 counter register. see table 17-30 for bit descriptions. 16 s 0x30 60a6 s/u mpwmscr mpwmsm20 status/control register. see table 17-31 for bit descriptions. 16 s mpwmsm21 (mios pulse width modulation submodule 21) 0x30 60a8 s/u mpwmperr mpwmsm21 period register. see table 17-28 for bit descriptions. 16 s 0x30 60aa s/u mpwmpulr mpwmsm21 pulse width register. see table 17-29 for bit descriptions. 16 s 0x30 60ac s/u mpwmcntr mpwmsm21 counter register. see table 17-30 for bit descriptions. 16 s 0x30 60ae s/u mpwmscr mpwmsm21 status/control register. see table 17-31 for bit descriptions. 16 s table a-14. mios14 (modular input/output subsystem) (continued) address access symbol register size reset motorola appendix a. internal memory map a-27 indexofmemorymaptables mmcsm22 (mios modulus counter submodule 22) 0x30 60b0 s/u mmcsmcnt mmcsm22 up-counter register. see table 17-12 for bit descriptions. 16 x 0x30 60b2 s/u mmcsmml mmcsm22 modulus latch register. see table 17-13 for bit descriptions. 16 s 0x30 60b6 s/u mmcsmscr mmcsm22 status/control register. see table 17-14 for bit descriptions. 16 s mmcsm23 (mios modulus counter submodule 23) 0x30 60b8 s/u mmcsmcnt mmcsm23 up-counter register. see table 17-12 for bit descriptions. 16 x 0x30 60ba s/u mmcsmml mmcsm23 modulus latch register. see table 17-13 for bit descriptions. 16 s 0x30 60be s/u mmcsmscr mmcsm23 status/control register. see table 17-14 for bit descriptions. 16 s mmcsm24 (mios modulus counter submodule 24) 0x30 60c0 s/u mmcsmcnt mmcsm24 up-counter register. see table 17-12 for bit descriptions. 16 x 0x30 60c2 s/u mmcsmml mmcsm24 modulus latch register. see table 17-13 for bit descriptions. 16 s 0x30 60c6 s/u mmcsmscr mmcsm24 status/control register. see table 17-14 for bit descriptions. 16 s mdasm27 (mios double action submodule 27) 0x30 60d8 s/u mdasmar mdasm27 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 60da s/u mdasmbr mdasm27 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 60de s/u mdasmscr mdasm27 status/control register. see table 17-23 for bit descriptions. 16 s mdasm28 (mios double action submodule 28) 0x30 60e0 s/u mdasmar mdasm28 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 60e2 s/u mdasmbr mdasm28 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 60e6 s/u mdasmscr mdasm28 status/control register. see table 17-23 for bit descriptions. 16 s table a-14. mios14 (modular input/output subsystem) (continued) address access symbol register size reset a-28 mpc565/mpc566 reference manual motorola index of memory map tables mdasm29 (mios double action submodule 29) 0x30 60e8 s/u mdasmar mdasm29 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 60ea s/u mdasmbr mdasm29 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 60ee s/u mdasmscr mdasm29 status/control register. see table 17-23 for bit descriptions. 16 s mdasm30 (mios double action submodule 30) 0x30 60f0 s/u mdasmar mdasm30 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 6f2 s/u mdasmbr mdasm30 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 60f6 s/u mdasmscr mdasm30 status/control register. see table 17-23 for bit descriptions. 16 s mdasm31 (mios double action submodule 31) 0x30 60f8 s/u mdasmar mdasm31 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 60fa s/u mdasmbr mdasm31 dataa register. see table 17-21 for bit descriptions. 16 s 0x30 60fe s/u mdasmscr mdasm31 status/control register. see table 17-23 for bit descriptions. 16 s mpiosm (mios 16-bit parallel port i/o submodule) 0x30 6100 s/u mpiosmdr mpiosm data register. see table 17-35 for bit descriptions. 16 s 0x30 6102 s/u mpiosmddr mpiosm data direction register. see table 17-36 for bit descriptions. 16 s mbism (mios bus interface submodule) 0x30 6800 s/u mios14tpcr mios14 test and pin control register. see table 17-4 for bit descriptions. 16 x 0x30 6802 s/u mios14vect mios14 vector register. see table 17-2 for bit descriptions. 16 x 0x30 6804 s/u mios14vnr mios14 vector register. see section 17.6.1.3, ?mios14 module and version number register for bit descriptions. 16 s 0x30 6806 s/u mios14mcr mios14 module configuration register. see table 17-7 for bit descriptions. 16 x mcpsm (mios status/control submodule) 0x30 6816 s/u mcpsmscr mcpsm status/control register. see table 17-9 for bit descriptions. 16 x table a-14. mios14 (modular input/output subsystem) (continued) address access symbol register size reset motorola appendix a. internal memory map a-29 indexofmemorymaptables miirsm0 (mios interrupt status submodule) 0x30 6c00 s/u mios14sr0 mios14 interrupt status register. see table 17-37 for bit descriptions. 16 x 0x30 6c04 s/u mios14er0 mios14 interrupt enable register. see table 17-38 for bit descriptions. 16 x 0x30 6c06 s/u mios14rpr0 mios14 request pending register. see table 17-39 for bit descriptions. 16 s mirsm1 (mios interrupt request submodule) 0x30 6c40 s/u mios14sr1 mios14 interrupt status register. see table 17-40 for bit descriptions. 16 x 0x30 6c44 s/u mioser1 mios14 interrupt enable register. see table 17-41 for bit descriptions. 16 x 0x30 6c46 s/u mios14rpr1 mios14 request pending register. see table 17-42 for bit descriptions. 16 x mbism0 (mios interrupt request submodule 0) 0x30 6c30 s/u mios14lvl0 mios14 interrupt level 0 register. see table 17-44 for bit descriptions. 16 s 0x30 6c70 s/u mios14lvl1 mios14 interrupt level 1 register. see table 17-45 for bit descriptions. 16 x 1 only bits wen, test, stb, and wip affected by reset. table a-15. toucan a, b and c (can 2.0b controller) address access symbol register size reset to u c a n _ a (note: bit descriptions apply to toucan_b and toucan_c as well) 0x30 7080 s canmcr_a toucan_a module configuration register. see table 16-11 for bit descriptions. 16 s 0x30 7082 t cantcr_a toucan_a test register 16 s 0x30 7084 s canicr_a toucan_a interrupt configuration register. see table 16-12 for bit descriptions. 16 s 0x30 7086 s/u canctrl0_a/ canctrl1_a toucan_a control register 0/ toucan_a control register 1. see table 16-13 and table 16-16 for bit descriptions. 16 s 0x30 7088 s/u presdiv_a/ ctrl2_a toucan_a control and prescaler divider register/toucan_a control register 2. see table 16-17 and table 16-18 for bit descriptions. 16 s 0x30 708a s/u timer_a toucan_a free-running timer register. see table 16-19 for bit descriptions. 16 s table a-14. mios14 (modular input/output subsystem) (continued) address access symbol register size reset a-30 mpc565/mpc566 reference manual motorola index of memory map tables 0x30 708c ? 0x30 708e ??reserved ?? 0x30 7090 s/u rxgmskhi_a toucan_a receive global mask high. see table 16-20 for bit descriptions. 32 s 0x30 7092 s/u rxgmsklo_a toucan_a receive global mask low. see table 16-20 for bit descriptions. 32 s 0x30 7094 s/u rx14mskhi_a toucan_a receive buffer 14 mask high. see section 16.7.10, ?receive buffer 14 mask registers,? for bit descriptions. 32 s 0x30 7096 s/u rx14msklo_a toucan_a receive buffer 14 mask low. see section 16.7.10, ?receive buffer 14 mask registers,? for bit descriptions. 32 s 0x30 7098 s/u rx15mskhi_a toucan_a receive buffer 15 mask high. see section 16.7.11, ?receive buffer 15 mask registers,? for bit descriptions. 32 s 0x30 709a s/u rx15msklo_a toucan_a receive buffer 15 mask low. see section 16.7.11, ?receive buffer 15 mask registers,? for bit descriptions. 32 s 0x30 709c ? 0x30 709e ??reserved ?? 0x30 70a0 s/u estat_a toucan_a error and status register. see table 16-21 for bit descriptions. 16 s 0x30 70a2 s/u imask_a toucan_a interrupt masks. see table 16-24 for bit descriptions. 16 s 0x30 70a4 s/u iflag_a toucan_a interrupt flags. see table 16-25 for bit descriptions. 16 s 0x30 70a6 s/u rxectr_a/ txectr_a toucan_a receive error counter/ toucan_a transmit error counter. see table 16-26 for bit descriptions. 16 s 0x30 7100 ? 0x30 710f s/u mbuff0_a 1 toucan_a message buffer 0 2 ?u 0x30 7110 ? 0x30 711f s/u mbuff1_a 1 toucan_a message buffer 1 2 ?u 0x30 7120 ? 0x30 712f s/u mbuff2_a 1 toucan_a message buffer 2 2 ?u 0x30 7130 ? 0x30 713f s/u mbuff3_a 1 toucan_a message buffer 3 2 ?u 0x30 7140 ? 0x30 714f s/u mbuff4_a 1 toucan_a message buffer 4 2 ?u 0x30 7150 ? 0x30 715f s/u mbuff5_a 1 toucan_a message buffer 5 2 ?u 0x30 7160 ? 0x30 716f s/u mbuff6_a 1 toucan_a message buffer 6 2 ?u table a-15. toucan a, b and c (can 2.0b controller) (continued) address access symbol register size reset motorola appendix a. internal memory map a-31 indexofmemorymaptables 0x307170 ? 0x30717f s/u mbuff7_a 1 toucan_a message buffer 7 2 ?u 0x30 7180 ? 0x30 718f s/u mbuff8_a 1 toucan_a message buffer 8 2 ?u 0x30 7190 ? 0x30 719f s/u mbuff9_a 1 toucan_a message buffer 9 2 ?u 0x30 71a0 ? 0x30 71af s/u mbuff10_a 1 toucan_a message buffer 10 2 ?u 0x30 71b0 ? 0x30 71bf s/u mbuff11_a 1 toucan_a message buffer 11 2 ?u 0x30 71c0 ? 0x30 71cf s/u mbuff12_a 1 toucan_a message buffer 12 2 ?u 0x30 71d0 ? 0x30 71df s/u mbuff13_a 1 toucan_a message buffer 13 2 ?u 0x30 71e0 ? 0x30 71ef s/u mbuff14_a 1 toucan_a message buffer 14 2 ?u 0x30 71f0 ? 0x30 71ff s/u mbuff15_a 1 toucan_a message buffer 15 2 ?u to u c a n _ b 0x30 7480 s canmcr_b toucan_b module configuration register 16 s 0x30 7482 t cantcr_b toucan_b test register 16 s 0x30 7484 s canicr_b toucan_b interrupt configuration register 16 s 0x30 7486 s/u canctrl0_b/ canctrl1_b toucan_b control register 0/ toucan_b control register 1 16 s 0x30 7488 s/u presdiv_b/ ctrl2_b toucan_b control and prescaler divider register/toucan_b control register 2 16 s 0x30 748a s/u timer_b toucan_b free-running timer register s 0x30 748c ? 0x30 748e ??reserved ?? 0x30 7490 s/u rxgmskhi_b toucan_b receive global mask high 32 s 0x30 7492 s/u rxgmsklo_b toucan_b receive global mask low 32 s 0x30 7494 s/u rx14mskhi_b toucan_b receive buffer 14 mask high 32 s 0x30 7496 s/u rx14msklo_b toucan_b receive buffer 14 mask low 3 s 0x30 7498 s/u rx15mskhi_b toucan_b receive buffer 15 mask high 32 s 0x30 749a s/u rx15msklo_b toucan_b receive buffer 15 mask low 32 s 0x30 749c ? 0x30 749e ??reserved ?? 0x30 74a0 s/u estat_b toucan_b error and status register 16 s table a-15. toucan a, b and c (can 2.0b controller) (continued) address access symbol register size reset a-32 mpc565/mpc566 reference manual motorola index of memory map tables 0x30 74a2 s/u imask_b toucan_b interrupt masks 16 s 0x30 74a4 s/u iflag_b toucan_b interrupt flags 16 s 0x30 74a6 s/u rxectr_b/ txectr_b toucan_b receive error counter/ toucan_b transmit error counter 16 s 0x30 7500 ? 0x30 750f s/u mbuff0_b 1 toucan_b message buffer 0. ? u 0x30 7510 ? 0x30 751f s/u mbuff1_b 1 toucan_b message buffer 1. ? u 0x30 7520 ? 0x30 752f s/u mbuff2_b 1 toucan_b message buffer 2. ? u 0x30 7530 ? 0x30 753f s/u mbuff3_b 1 toucan_b message buffer 3. ? u 0x30 7540 ? 0x30 754f s/u mbuff4_b 1 toucan_b message buffer 4. ? u 0x30 7550 ? 0x30 755f s/u mbuff5_b 1 toucan_b message buffer 5. ? u 0x30 7560 ? 0x30 756f s/u mbuff6_b 1 toucan_b message buffer 6. ? u 0x30 7570 ? 0x30 757f s/u mbuff7_b 1 toucan_b message buffer 7. ? u 0x30 7580 ? 0x30 758f s/u mbuff8_b 1 toucan_b message buffer 8. ? u 0x30 7590 ? 0x30 759f s/u mbuff9_b 1 toucan_b message buffer 9. ? u 0x30 75a0 ? 0x30 75af s/u mbuff10_b 1 toucan_b message buffer 10. ? u 0x30 75b0 ? 0x30 75bf s/u mbuff11_b 1 toucan_b message buffer 11. ? u 0x30 75c0 ? 0x30 75cf s/u mbuff12_b 1 toucan_b message buffer 12. ? u 0x30 75d0 ? 0x30 75df s/u mbuff13_b 1 toucan_b message buffer 13. ? u 0x30 75e0 ? 0x30 75ef s/u mbuff14_b 1 toucan_b message buffer 14. ? u 0x30 75f0 ? 0x30 75ff s/u mbuff15_b 1 toucan_b message buffer 15. ? u to u c a n _ c 0x30 7880 s canmcr_c toucan_c module configuration register 16 s 0x30 7882 t cantcr_c toucan_c test register 16 s 0x30 7884 s canicr_c toucan_c interrupt configuration register 16 s table a-15. toucan a, b and c (can 2.0b controller) (continued) address access symbol register size reset motorola appendix a. internal memory map a-33 indexofmemorymaptables 0x30 7886 s/u canctrl0_c/ canctrl1_c toucan_c control register 0/ toucan_c control register 1 16 s 0x30 7888 s/u presdiv_c/ ctrl2_c toucan_c control and prescaler divider register/ toucan_c control register 2 16 s 0x30 788a s/u timer_c toucan_c free-running timer register s 0x30 788c ? 0x30 788e ??reserved ?? 0x30 7890 s/u rxgmskhi_c toucan_c receive global mask high 32 s 0x30 7892 s/u rxgmsklo_c toucan_c receive global mask low 32 s 0x30 7894 s/u rx14mskhi_c toucan_c receive buffer 14 mask high 32 s 0x30 7896 s/u rx14msklo_c toucan_c receive buffer 14 mask low 32 s 0x30 7898 s/u rx15mskhi_c toucan_c receive buffer 15 mask high 32 s 0x30 789a s/u rx15msklo_c toucan_c receive buffer 15 mask low 32 s 0x30 789c ? 0x30 789e ??reserved ?? 0x30 78a0 s/u estat_c toucan_c error and status register 16 s 0x30 78a2 s/u imask_c toucan_c interrupt masks 16 s 0x30 78a4 s/u iflag_c toucan_c interrupt flags 16 s 0x30 78a6 s/u rxectr_c/ txectr_c toucan_c receive error counter/ toucan_c transmit error counter 16 s 0x30 7900 ? 0x30 790f s/u mbuff0_c 1 toucan_c message buffer 0. ? u 0x30 7910 ? 0x30 791f s/u mbuff1_c 1 toucan_b message buffer 1. ? u 0x30 7920 ? 0x30 792f s/u mbuff2_c 1 toucan_c message buffer 2. ? u 0x30 7930 ? 0x30 793f s/u mbuff3_c 1 toucan_c message buffer 3. ? u 0x30 7940 ? 0x30 794f s/u mbuff4_c 1 toucan_c message buffer 4. ? u 0x30 7950 ? 0x30 795f s/u mbuff5_c 1 toucan_c message buffer 5. ? u 0x30 7960 ? 0x30 796f s/u mbuff6_c 1 toucan_c message buffer 6. ? u 0x30 7970 ? 0x30 797f s/u mbuff7_c 1 toucan_c message buffer 7. ? u 0x30 7980 ? 0x30 798f s/u mbuff8_c 1 toucan_c message buffer 8. ? u table a-15. toucan a, b and c (can 2.0b controller) (continued) address access symbol register size reset a-34 mpc565/mpc566 reference manual motorola index of memory map tables 0x30 7990 ? 0x30 799f s/u mbuff9_c 1 toucan_c message buffer 9. ? u 0x30 79a0 ? 0x30 79af s/u mbuff10_c 1 toucan_c message buffer 10. ? u 0x30 79b0 ? 0x30 79bf s/u mbuff11_c 1 toucan_c message buffer 11. ? u 0x30 79c0 ? 0x30 79cf s/u mbuff12_c 1 toucan_c message buffer 12. ? u 0x30 79d0 ? 0x30 79df s/u mbuff13_c 1 toucan_c message buffer 13. ? u 0x30 79e0 ? 0x30 79ef s/u mbuff14_c 1 toucan_c message buffer 14. ? u 0x30 79f0 ? 0x30 79ff s/u mbuff15_c 1 toucan_c message buffer 15. ? u 1 the last word of each of the mbuff arrays (address 0x....e) is reserved and may cause a rcpu exception if read. 2 see table 16-3 and table 16-4 for message buffer definitions. table a-16. uimb (u-bus to imb bus interface) address access symbol register size reset 0x30 7f80 s 1 1 s = supervisor mode only, t = test mode only umcr uimb module configuration register. see table 12-6 for bit descriptions. 32 h 0x30 7f84 ? 0x30 7f8c ? ? reserved 32 h 0x30 7f90 s/t utstcreg uimb test control register. reserved 32 h 0x30 7f94 ? 0x30 7f9c ? ? reserved 32 h 0x30 7fa0 s uipend pending interrupt request register. see section 12.5.3, ?pending interrupt request register (uipend),? and table 12-7 for bit descriptions. 32 h table a-17. calram_a and calram_b control registers address access symbol register size reset calram_a 0x38 0000 s crammcr_a calram_a module configuration register. see table 21-3 for bit descriptions. 32 s 0x38 0004 s cramtst_a calram_a test register. 32 s table a-15. toucan a, b and c (can 2.0b controller) (continued) address access symbol register size reset motorola appendix a. internal memory map a-35 indexofmemorymaptables 0x38 0008 s cram_rba0_a calram_a region base address register 1 32 s 0x38 000c s cram_rba1_a calram_a region base address register 1 32 s 0x38 0010 s cram_rba2_a calram_a region base address register 1 32 s 0x38 0014 s cram_rba3_a calram_a region base address register 1 32 s 0x38 0018 s cram_rba4_a calram_a region base address register 1 32 s 0x38 001c s cram_rba5_a calram_a region base address register 1 32 s 0x38 0020 s cram_rba6_a calram_a region base address register 1 32 s 0x38 0024 s cram_rba7_a calram_a region base address register 1 32 s 0x38 0028 s cram_olvcr_a calram_a overlay configuration register. see table 21-7 for bit descriptions. 32 s 0x38 002c s 2 readi_otr readi ownership trace register. see section 23.2.1.1, ?user mapped register,? for more information. 32 s calram_b 0x38 0040 s crammcr_b calram_b module configuration register. see table 21-3 for bit descriptions. 32 s 0x38 0044 s cramtst_b calram_b test register. see table 21-3 for bit descriptions. 32 s 0x38 0048 s cram_rba0_b calram_b region base address register 1 32 s 0x38 004c s cram_rba1_b calram_b region base address register 1 32 s 0x38 0050 s cram_rba2_b calram_b region base address register 1 32 s 0x38 0054 s cram_rba3_b calram_b region base address register 1 32 s 0x38 0058 s cram_rba4_b calram_b region base address register 1 32 s 0x38 005c s cram_rba5_b calram_b region base address register 1 32 s 0x38 0060 s cram_rba6_b calram_b region base address register 1 15 s 0x38 0064 s cram_rba7_b calram_b region base address register 1 32 s 0x38 0068 s cram_olvcr_b calram_a overlay configuration register. see table 21-7 for bit descriptions. 32 s 0x38 006c s 1 , 3 cram_otr_b calram_b ownership trace register. see section 21.4.4, ?calram ownership trace register (cramotr),? for more information. 32 s 1 see section 21.4.2, ?calram region base address registers (cram_rbax),? for more information. 2 this register is write only. 3 this register is not used on the mpc565. table a-17. calram_a and calram_b control registers (continued) address access symbol register size reset a-36 mpc565/mpc566 reference manual motorola index of memory map tables table a-18. calram_b and calram_a array address access symbol register size reset calram_b 0x3f 7000 ? 0x3f 7fff u,s cram_b calram array b. 4 kbytes ? calram_a 0x3f 8000 ? 0x3f ffff u,s cram_a calram array a. 32 kbytes ? motorola appendix b. clock and board guidelines b-1 appendix b clock and board guidelines the mpc565/mpc566 built-in pll, oscillator, and other analog and sensitive circuits require that the board design follow special layout guidelines to ensure proper operation of the chip clocks. this appendix describes how the clock supplies and external components should be connected in a system. these guidelines must be fulfilled to reduce switching noise which is generated on internal and external buses during operation. any noise injected into the sensitive clock and pll logic reduces clock performance. the usiu maintains a pll loss-of-lock warning indication that can be used to determine the clock stability in the mpc565/mpc566. b-2 mpc565/mpc566 reference manual motorola mpc565/mpc566 family power distribution b.1 mpc565/mpc566 family power distribution figure b-1. power distribution diagram ? 2.6 v vdd (external 2.6 v) vss (external gnd) nvddl (external 2.6 v) vss (internal gnd) vddsyn xfc vsssyn extal xtal kapwr vddsram1/2/3 keyed vdd 2.6 v kap 2.6 v cx(pf)4 cy(pf) >10 w 100 nf cxfc 100 nf3 100 nf 100 nf <10 w 1f 1nf 1nf 1f 100 nf r12 (main supply)1 vddf (external 2.6 v) 1. the main power supply may optionally supply operating current to reduce the keep-alive current requirements. see the circuit in section 8.11.1, ?system clock control register (sccr) . 2. resistor r 1 is currently not required. space should be left on the board to add it in the future if necessary. 3. all 100 nf capacitors should be placed close to the pin. 4. c l is a function of specific crystal c l =c x +c y . see motorola appendix b. clock and board guidelines b-3 mpc565/mpc566 family power distribution figure b-2. power distribution diagram ? 5 v and analog vddh (digital 5 v) vdda vssa vrh vrl anx (analog input) keyed vdd 5 v 100 nf 1uf 1nf ~10k w <10 w <10 w to from sensors 100 nf ~10 nf r21 sensors 100 nf analog ground plane altref 100 nf vflash mpc555 / mpc566 board 1. this size of resistor r 2 depends on the sensor load current. it should be sized to match the voltage at vrh. b-4 mpc565/mpc566 reference manual motorola pll and crystal oscillator external components b.2 pll and crystal oscillator external components b.3 crystal oscillator external components figure b-3. crystal oscillator circuit the load capacitances specified in table e-1 include all stray capacitance. tolerance of the capacitors is 10%. the oscillator capacitors c x and c y were calculated as follows: c a =c b =2c l c a =c x +c pa d +c socket c b =c y +c pad +c socket table b-1. external components value for different crystals (q1) component ndk cp32c 20 mhz kinseki cx-11f 20 mhz murata ccstc 4mhz units c l 1 1 c l according to crystal specification, c l =c x +c y . 614 ?pf r 1 3 1meg 3 1meg 3 1meg 3 ohm c x 616 ? 2 2 the murata ceramic resonator includes the load capacitors. (8pf should be selected) 3. resistor r 1 is currently not required. space should be left on the board to add it in the future if necessary. pf c y 616 ?pf extal xtal cx cy r11 vsssyn .resistorr 1 is currently not required. space should be left on the board to add it in the future if necessary. q 1 mpc555 / mpc566 board motorola appendix b. clock and board guidelines b-5 crystal oscillator external components where: c l is load capacitance c pa d is pad capacitance xtal pad capacitance is c pa d =~7pf extal pad capacitance is c pa d =~7pf c socket is socket and board trace capacitance socket capacitance c <=1pf board trace capacitance c <=1pf. this should be low since the crystal must be located very close to the chip. b.3.1 kapwr filtering kapwr pin is the mpc565/mpc566 keep-alive power. kapwr is used for the crystal oscillator circuit, and should be isolated from the noisy supplies. it is recommended that an rc filter be used on kapwr, or bypass capacitors which are located as close as possible to the part. figure b-4. rc filter example figure b-5. bypass capacitors example (alternative) kapwr vsssyn kap 2.6 v 100 nf 10 w mpc555 / mpc566 board kapwr vsssyn kap 2.6 v 100 nf 1f mpc555 / mpc566 board b-6 mpc565/mpc566 reference manual motorola crystal oscillator external components b.3.2 pll external components vddsyn and vsssyn are the pll dedicated power supplies. these supplies must be used only for the pll and isolated from all other noisy signals in the board. vddsyn could be isolated with rc filter (see figure b-1), or lc filter. the maximum noise allowed on vddsyn, and vsssyn is 50 mv with typical cut-off frequency of 500 hz. figure b-6. rc filter example figure b-7. lc filter example (alternative) b.3.3 pll off-chip capacitor c xfc c xfc is the pll feedback capacitor. it must be located as close as possible to the xfc and vddsyn pads. the maximum noise allowed on xfc is 50 mv peak-to-peak with a typical cut-off frequency of 500 hz. the required value for c xfc is determined by the following two cases: 0<(mf+1)<4 c xfc = (1130 * (mf+1) ? 80) pf vddsyn vsssyn keyed 100 nf 10 w vdd 2.6 v mpc555 / mpc566 board vddsyn vsssyn keyed 100 nf 8.2 mh vdd 2.6 v mpc555 / mpc566 board motorola appendix b. clock and board guidelines b-7 pll and clock oscillator external components layout requirements (mf+1) >= 4 c xfc = (2100 * (mf+1)) pf mf is the multiplication factor in the plprcr register (refer to section 8.11.2, ?pll, low-power, and reset-control register (plprcr)? for more information). figure b-8. pll off-chip capacitor example b.4 pll and clock oscillator external components layout requirements b.4.1 traces and placement traces connecting capacitors, crystal, resistor should be as short as possible. therefore, the components (crystal, resistor and capacitors) should be placed as close to the oscillator pins of the mpc565/mpc566 as possible. the voltage to the vddsyn pin should be well regulated and the pin should be provided with an extremely low impedance path from the vddsyn filter to the vddsyn pad. the vsssyn pin should be provided with an extremely low impedance path in the board. all the filters for the supplies should be located as close as possible to the chip package. it is recommended to design individual vsssyn plane to improve vsssyn quietness. b.4.2 grounding/guarding the traces from the oscillator pins and pll pins of the mpc565/mpc566 should be guarded from all other traces to reduce crosstalk. it can be provided by keeping other traces away from the oscillator circuit and placing a ground plane around the components and traces. xfc cxfc vddsyn mpc555 / mpc566 board b-8 mpc565/mpc566 reference manual motorola mios14 rtc oscillator b.5 mios14 rtc oscillator the basic time base for the mios14 real-time clock submodule, mrtcsm, is a 32.768-khz dedicated low power oscillator. this oscillator uses an external crystal connected between the xtal32 and extal32 pads as a reference frequency source. the dedicated 32.768-khz oscillator is in the chip periphery with the pads for the 32.768-khz crystal. the extal32 pin has an internal load capacitor, therefore an external load capacitor is not required on extal32. the c l on the xtal32 side of the crystal should be according to the crystal manufacturer, typically 12 pf. the mios rtc oscillator circuit is shown in figure b-9. 1. resistor r 1 is not currently required. space should be left on the board to add it in the future if necessary. figure b-9. mios rtc oscillator circuit extal32 xtal32 c l r 1 1 32.7 khz motorola appendix c. tpu3 rom functions c-1 appendix c tpu3 rom functions the following pages provide brief descriptions of the pre-programmed functions in the tpu3. for detailed descriptions, refer to the programming note for the individual function. the motorola tpu literature pack provides a list of available programming notes. c.1 overview the tpu3 contains 4 kbytes of microcode rom. it can have up to 8 kbytes of memory and a maximum of four entry tables (see figure c-1). this appendix defines the standard rom functions for the mpc565/mpc566. 1. the dptram is located at 0x30 2000 or 0x30 1000 until it is switched to emulation mode. in emulation mode, only the tpu3 can access the dptram. 2. dptram_c does not have bank 2 of memory. figure c-1. tpu3 memory map bank 1 bank 0 0 1ff entry code ad d - entry code code 3 ff bank 2 ad d - entry code bank 3 ad d - entry (unimplemented) tpu3rom bank 1 bank 0 0 entry code ad d - entry code code b a nk 2 2 ad d - entry dptram 1 7 ff 5 ff 3 ff 1ff c-2 mpc565/mpc566 reference manual motorola overview the tpu3 can address up to 8 kbytes of memory at any one time. it has 4 kbytes of internal rom, located in banks 0 and 1, and 6 kbytes of dual-ported sram (dptram), located in banks 0, 1, and 2. as only one type of memory can be used at a time, the tpu3 must either use the internal rom or the sram. functions from both memory types cannot be used in conjunction. a new feature of the tpu3 microcode rom is the two sixteen-function entry tables in the 4 kbytes of internal rom. the etbank field in the tpumcr2 register, written once after reset, determines which one of these entry tables the cpu selects. though the tpu3 can access either entry table, only one table can be used at a time and functions from the tables cannot be mixed. the default entry table, located in bank 0, is identical to the standard microcode rom in the tpu2, making any cpu code written for the tpu2 interchangable with the tpu3. the functions in the default entry table in bank 0 are listed in table c-1. the functions in the bank 1 entry table are identical to those in bank 0, except in three cases. function 1, spwm in the bank 0 table, has been replaced by rwtpin, a function that allows a read and write to the tpu3 timebases and corresponding pin. function 5, ppwa in the bank 0 table, is an identification function in the bank 1 table that provides the microcode rom revision number. function 7, mcpwm, has been removed and left open for future use. the functions in the bank 1 entry table are listed in table c-2. table c-1. bank 0 functions function number function 0xf pta (programmable time accumulator) 0xe qom (queued output match) 0xd tsm (table stepper motor) 0xc fqm (frequency measurement) 0xb uart (universal asynchronous receiver/transmitter) 0xa nitc (new input capture/input transition counter) 9 comm (multiphase motor commutation) 8 halld (hall effect decode) 7 mcpwm (multi-channel pulse width modulation) 6 fqd (fast quadrature decode) 5 ppwa (period/pulse width accumulator) 4 oc (output compare) 3 pwm (pulse width modulation) 2 dio (discrete input/output) 1 spwm (synchronized pulse width modulation) 0 siop (serial input/output port) motorola appendix c. tpu3 rom functions c-3 overview the cpu selects which entry table to use by setting the etbank field in the tpumcr2 register. this register is written once after reset. although one entry table is specified at start-up, it is possible, in some cases, to use functions from both tables without resetting the microcontroller. a customer may, for example, wish to use the id function from bank 1 to verify the tpu3 microcode version but then use the mcpwm function from bank 0. as a customer will typically only run the id function during system configuration, and not again after that, the bank 1 entry table can be changed to the bank 0 entry table using the soft reset feature of the tpu3. this procedure is described in the following steps: 1. set etbank field in tpumcr2 to 0b01 to select the entry table in bank 1 2. run the id function 3. stop the tpu3 by setting the stop bit in the tpumcr to one 4. reset the tpu3 by setting the softrst bit in the tpumcr2 register 5. wait at least nine clocks 6. clear the softrst bit in the tpumcr2 register the tpu3 stays in reset until the cpu clears the softrst bit. after the softrst bit has been cleared, the tpu3 will be reset and the entry table in bank 0 will be selected by default. to select the bank 0 entry table, write 0b00 to the etbank field in tpumcr2. always table c-2. bank 1 functions function number function 0xf pta (programmable time accumulator) 0xe qom (queued output match) 0xd tsm (table stepper motor) 0xc fqm (frequency measurement) 0xb uart (universal asynchronous receiver/transmitter) 0xa nitc (new input capture/input transition counter) 9 comm (multiphase motor commutation) 8 halld (hall effect decode) 7 reserved 6 fqd (fast quadrature decode) 5 id (identification) 4 oc (output compare) 3 pwm (pulse width modulation) 2 dio (discrete input/output) 1 rwtpin (read/write timers and pin) 0 siop (serial input/output port) c-4 mpc565/mpc566 reference manual motorola programmable time accumulator (pta) initialize any write-once register to ensure that an incorrect value is not accidentally written. the descriptions below document the functions listed in table c-1 (bank 0) and table c-2 (bank 1) of the tpu3 rom module. c.2 programmable time accumulator (pta) pta starts on a rising or falling edge and accumulates, over a programmable number of periods or pulses, a 32-bit sum of the total high time, low time, or input signal period. after the specified number of periods or pulses, the pta generates an interrupt request. one to 255 period measurements can be accumulated before the tpu3 interrupts the cpu, providing instantaneous or average frequency measurement capability. see motorola tpu progamming note programmable time accumulator tpu function (pta), (tpupn06/d) . table c-3 shows all of the host interface areas for the pta function. motorola appendix c. tpu3 rom functions c-5 programmable time accumulator (pta) table c-3. pta parameters control bits name options addresses 0123 channel function select xxxx ? pta function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see table c-1 and table c-2. 0 1 host sequence 00 ? high time accumulate 0x30yy14 ? 0x30yy16 01 ? low time accumulate 10 ? period accumulate, rising 11 ? period accumulate, falling 01 host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? not used 11 ? initialize 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11?highpriority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 channel_control 0x30yyw2 max_count period_count 0x30yyw4 last_time 0x30yyw6 accum 0x30yyw8 hw 0x30yywa lw 0x30yywc 0x30yywe = written by cpu = written by cpu and tpu w = channel number = written by tpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-6 mpc565/mpc566 reference manual motorola queued output match tpu3 function (qom) c.3 queued output match tpu3 function (qom) qom can generate single- or multiple-output match events from a table of offsets in parameter ram. loop modes allow complex pulse trains to be generated once, a specified number of times, or continuously. qom can be used with other tpu3 channels in a variety of ways: the function can be triggered by a link from the channel, the reference time for the sequence of matches can be obtained from it, or the channel can be used as a discrete output pin. qom can generate pulse-width modulated waveforms, including waveforms with high times of 0 or 100%. see motorola tpu3 progamming note queued output match tpu function (qom), (tpupn01/d). table c-5 shows all of the host interface areas for the qom function. the bit encodings shown in table c-4 describe the corresponding fields in parameter ram. table c-4. qom bit encoding a timebase selection 0 use tcr1 as timebase 1 use tcr2 as timebase edge selection 0 falling edge at match 1 rising edge at match b:c reference for first match 00 immediate tcr value 01 last event time 10 value pointed to by ref_addr 11 last event time motorola appendix c. tpu3 rom functions c-7 queued output match tpu3 function (qom) table c-5. qom parameters control bits name options addresses 0123 channel function select xxxx ? qom function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 andtable c-2. 0 1 host sequence 00 ? single-shot mode 0x30yy14 ? 0x30yy16 01 ? loop mode 10 ? continuous mode 11 ? continuous mode 01 host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize, no pin change 10 ? initialize, pin low 11 ? initialize, pin high 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11?highpriority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 ref_addr b last_off_addr a 0x30yyw2 loop_cnt (last_match_tm) off_ptr c 0x30yyw4 offset_1 0x30yyw6 offset_2 0x30yyw8 offset_3 0x30yywa offset_4 0x30yywc offset_5 1 0x30yywe offset_6 1 0x30yy(w=1)0 offset_7 1 0x30yy(w=1)2 offset_8 1 0x30yy(w=1)14 offset_14 1 1. not available on all channels. =writtenbycpu =writtenbycpuandtpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-8 mpc565/mpc566 reference manual motorola table stepper motor (tsm) c.4 table stepper motor (tsm) the tsm function provides acceleration and deceleration control of a stepper motor with up to 58 programmable step rates. tsm uses a table in parameter ram, rather than an algorithm, to define the stepper motor acceleration profile, allowing full defininition of the profile. in addition, a slew rate parameter allows fine control of the motor?s terminal running speed independent of the acceleration table. the cpu writes a desired position, and the tpu3 accelerates, slews, and decelerates the motor to the required position. full- and half-step support is provided for two-phase motors. see motorola tpu3 progamming note table stepper motor tpu function (tsm), (tpupn04/d). table c-6 and table c-7 show all of the host interface areas for the tsm function when operating in master or slave mode. motorola appendix c. tpu3 rom functions c-9 table stepper motor (tsm) table c-6. tsm parameters ? master mode control bits name options addresses 0123 channel function select xxxx ? tsm function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see table c-1 and table c-2. 0 1 host sequence x0 ? local mode acceleration table 0x30yy14 ? 0x30yy16 x1 ? split mode acceleration table 0x ? rotate pin_sequence once between steps 1x ? rotate pin_sequence twice between steps 01 host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize, pin low 10 ? initialize, pin high 11 ? move request (master only) 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11?highpriority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 desired_position 0x30yyw2 current_position 0x30yyw4 table_size channel_counter table_index 0x30yyw6 slew_period s 0x30yyw8 start_period a 0x30yywa pin_sequence 0x30yywc 0x30yywe = written by cpu = written by cpu and tpu w = channel number = written by tpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-10 mpc565/mpc566 reference manual motorola table stepper motor (tsm) table c-7. tsm parameters ? slave mode control bits name options addresses 0123 channel function select xxxx ? tsm function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see table c-1 and table c-2. 0 1 host sequence x0 ? rotate pin_sequence once 0x30yy14 ? 0x30yy16 between steps x1 ? split mode acceleration table 1x ? rotate pin_sequence once between steps 1x ? rotate pin_sequence twice between steps 01 host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize, pin low 10 ? initialize, pin high 11 ? move request (master only) 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11?highpriority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yy(w+1)0 accel_ratio_2 accel_ratio_1 0x30yy(w+1)2 accel_ratio_4 accel_ratio_3 0x30yy(w+1)4 accel_ratio_6 accel_ratio_5 0x30yy(w+1)6 accel_ratio_8 accel_ratio_7 0x30yy(w+1)8 accel_ratio_10 accel_ratio_9 0x30yy(w+1)a accel_ratio_12 accel_ratio_11 0x30yy(w+1)c 1 accel_ratio_14 1 accel_ratio_13 1 0x30yy(w+3)a 1 accel_ratio_36 1 accel_ratio_35 1 1. optional additional parameters not available in all cases. refer to motorola programming note tpupn04/d for details. = written by cpu = written by cpu and tpu w = channel number = written by tpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. motorola appendix c. tpu3 rom functions c-11 frequency measurement (fqm) c.5 frequency measurement (fqm) fqm counts the number of tpu-channel input pulses during a user-defined window period. the function has single-shot and continuous modes. in continuous mode, no pulses are lost between sample windows, and the user can select whether to detect pulses on the rising or falling edge. this function is intended for high-speed measurement. (measurement of slow pulses with noise rejection can be made with pta.) see motorola tpu progamming note frequent measurement tpu function (fqm), (tpupn03/d) . table c-8 shows all of the host interface areas for the fqm function. c-12 mpc565/mpc566 reference manual motorola frequency measurement (fqm) table c-8. fqm parameters control bits name options addresses 0123 c channel function select xxxx ? fqm function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see table c-1 and table c-2. 01 c host sequence 00 ? begin with falling edge, 0x30yy14 ? 0x30yy16 single-shot mode 01 ? begin with falling edge, continuous mode 10 ? begin with rising edge, single-shot mode 11 ? begin with rising edge, continuous mode 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? initialize 11 ?not used 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 0x30yyw2 0x30yyw4 chanel_control 0x30yyw6 window_size 0x30yyw8 pulse_count 0x30yywa in_window_accumulator 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = primary channel number =writtenbytpu = unused parameters for address offsets, y=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. motorola appendix c. tpu3 rom functions c-13 universal asynchronous receiver/transmitter (uart) c.6 universal asynchronous receiver/transmitter (uart) the uart uses one or two tpu3 channels to provide asynchronous communications. data word length is programmable from 1 to 14 bits. the function supports detection or generation of even, odd, and no parity. baud rate is freely programmable and can be higher than 100 kbaud. eight bidirectional uart channels running in excess of 9600 baud can be implemented on the tpu3. see motorola tpu3 progamming note asynchronous serial interface tpu function (uart), (tpupn07/d). table c-9 and table c-10 show all of the host interface areas for the uart function in transmitting and receiving modes. c-14 mpc565/mpc566 reference manual motorola universal asynchronous receiver/transmitter (uart) table c-9. uart transmitter parameters control bits name options addresses 0123 channel function select xxxx ? uart function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see tablec-1andtablec-2. 0 1 host sequence 00 ? no parity 0x30yy14 ? 0x30yy16 01 ? no parity 10 ? even parity 11 ? odd parity 01 host service request 00 ? not used 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? transmit 11 ? receive 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11?highpriority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 parity_temp 0x30yyw2 match_rate 0x30yyw4 tdre transmit_data_reg 0x30yyw6 data_size 0x30yyw8 actual_bit_count 0x30yywa shift_register 0x30yywc 0x30yywa = written by cpu =writtenbycpuandtpu w = channel number = written by tpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. motorola appendix c. tpu3 rom functions c-15 universal asynchronous receiver/transmitter (uart) table c-10. uart receiver parameters control bits name options addresses 0123 channel function select xxxx ? uart function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see tablec-1andtablec-2. 0 1 host sequence 00 ? no parity 0x30yy14 ? 0x30yy16 01 ? no parity 10 ? even parity 11 ? odd parity 01 host service request 00 ? not used 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? transmit 11 ? receive 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11?highpriority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpuc. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 parity_temp 0x30yyw2 match_rate 0x30yyw4 pe re transmit_data_reg 0x30yyw6 data_size 0x30yyw8 actual_bit_count 0x30yywa shift_register 0x30yywc 0x30yywa =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-16 mpc565/mpc566 reference manual motorola new input capture/transition counter (nitc) c.7 new input capture/transition counter (nitc) nitc allows, for a specified number of transitions, a tpu3 channel to: capture the value of a tcr (test configuration register) or any specified location in parameter ram and then generate an interrupt request to notify the bus master (times of the two most recent transitions remain in parameter ram), capture input continually or detect a specific number of transitions and end channel activity until reinitialization, or generate a link to other channels after the transitions have taken place. see motorola tpu progamming note new input capture/input transition counter tpu function (nitc), (tpupn08/d). table c-11 shows all of the host interface areas for the nitc function. motorola appendix c. tpu3 rom functions c-17 new input capture/transition counter (nitc) table c-11. nitc parameters control bits name options addresses 0123 channel function select xxxx ? nitc function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see tablec-1andtablec-2. 0 1 host sequence 00 ? single-shot mode, no links 0x30yy14 ? 0x30yy16 01 ? continuous mode, no links 10 ? single-shot mode, links 11 ? continuous mode, links 01 host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize tcr mode 10 ? initialize parameter mode 11 ? not used 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11?highpriority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 channel_control 0x30yyw2 start_link_ channel link_chan nel_count param_addr 0 0x30yyw4 max_count 0x30yyw6 trans_count 0x30yyw8 final_trans_time 0x30yywa last_trans_time 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-18 mpc565/mpc566 reference manual motorola multiphase motor commutation (comm) c.8 multiphase motor commutation (comm) the comm function generates phase commutation signals for a variety of brushless motors, including three-phase brushless direct current motors. it derives the commutation state directly from the position decoded in fqd, eliminating the need for hall effect sensors. the state sequence is implemented as a user-configurable state machine, providing a flexible approach with other general applications. a cpu offset parameter is provided to allow the cpu to advance or retard all swtiching angles on the fly. this feature is useful for torque maintenance at high speeds. see motorola tpu progamming note multiphase motor commutation tpu function (comm), (tpupn09/d). table c-12 shows all of the host interface areas for the comm function. motorola appendix c. tpu3 rom functions c-19 multiphase motor commutation (comm) table c-12. comm parameters control bits name options addresses 0123 c channel function select xxxx ? comm function number. assigned 0x30yy0c ? 0x30yy12 during microcode assembly. see table c-1 and table c-2. 01 c host sequence 00 ? sensorless match update mode 0x30yy14 ? 0x30yy16 01 ? sensorless match update mode 10 ? sensorless link update mode 11 ? sensorled mode 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? initialize or force state 11 ? initialize or force immediate state test 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel inerrput enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 start_link_ channel counter_addr 0x30yyw2 no_of_states state_no 0x30yyw4 offset 0x30yyw6 update_perio 0x30yyw8 upper 0x30yywa lower 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for pram address offset map. c-20 mpc565/mpc566 reference manual motorola hall effect decode (halld) c.9 hall effect decode (halld) the halld function decodes the sensor signals from a brushless motor (the function supports two- or three-sensor decoding) and a direction input from the cpu into a state number. the decoded state number is written into a comm channel, which outputs the required commutation drive signals. in addition to brushless motor applications, the function can have more general applications, such as decoding ?option? switches. see motorola tpu progamming note hall effect decode tpu function (halld), (tpupn10/d). table c-13 shows all of the host interface areas for the halld function. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yy(w + 1)0 length state 0 pin_config 0x30yy(w + 1)2 length state 1 pin_config 0x30yy(w + 1)4 length state 2 pin_config 0x30yy(w + 1)6 length state 3 pin_config 0x30yy(w + 1)8 length state 4 pin_config 0x30yy(w + 1)a length state 5 pin_config 0x30yy(w + 1)c length state 6 1 pin_config 0x30yy(w + 1)e length state 7 1 pin_config 0x30yy(w + 2)0 length state 8 1 pin_config 0x30yy(w + 2)2 length state 9 1 pin_config 0x30yy(w + 3)a length state 21 1 pin_config 1. not available on all channels. =writtenbycpu = written by cpu and tpu w = master channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for pram address offset map. table c-12. comm parameters (continued) control bits motorola appendix c. tpu3 rom functions c-21 hall effect decode (halld) table c-13. halld parameters control bits name options addresses 0123 c channel function select xxxx ? halld function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2 01 c host sequence 00 ? channel a 0x30yy14 ? 0x30yy16 01 ? channel b 10 ? channel b 11 ? channel c (3-channel mode only) 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? initialize, 2-channel mode 11 ? initialize, 3-channel mode 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11?highpriority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status x?notused 0x30yy20 for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 0x30yyw2 0x30yyw4 0x30yyw6 direction 1 0x30yyw8 state_no_addr 2 0x30yywa pinstate 0x30yywc 0x30yywe 1. channel a only. 2. one channel only (channel b in 2-channel mode, channel c in 3-channel mode. =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-22 mpc565/mpc566 reference manual motorola multichannel pulse-width modulation (mcpwm) c.10 multichannel pulse-width modulation (mcpwm) mcpwm generates pulse-width modulated outputs with full 0 to 100% duty cycle range independent of other tpu3 activity. this capability requires two tpu3 channels plus an external gate for one pwm. (a simple one-channel pwm capability is supported by the qom function.) multiple pwms generated by mcpwm have two types of high time alignment: edge aligned and center aligned. edge-aligned mode uses n + 1 tpu3 channels for n pwms, and center-aligned mode uses 2n + 1 channels. center-aligned mode allows a user to define ?dead time? so that two pwms can be used to drive an h-bridge without destructive current spikes. this feature is important for motor control applications. see motorola tpu progamming note multichannel pwm tpu function (mcpwm), (tpupn05/d). table c-14 through table c-19 shows the host interface areas for the mcpwm function in each mode. motorola appendix c. tpu3 rom functions c-23 multichannel pulse-width modulation (mcpwm) table c-14. mcpwm parameters ? master mode control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 01 c host sequence 00 ? edge-aligned mode 0x30yy14 ? 0x30yy16 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize as slave (inverted) 10 ? initialize, as slave (normal) 11?initializeasmaster 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 period 0x30yyw2 irq_rate period_count 0x30yyw4 last_rise_time 0x30yyw6 last_fall_time 0x30yyw8 rise_time_ptr 0x30yywa fall_time_ptr 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-24 mpc565/mpc566 reference manual motorola multichannel pulse-width modulation (mcpwm) table c-15. mcpwm parameters ? slave edge-aligned mode control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number. 0x30yy0a assigned during microcode assembly. see table c-1 and table c-2. 0 1 c host sequence 00 ? edge-aligned mode 0x30yy0c ? 0x30yy12 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy14 ? 0x30yy16 01 ? initialize as slave (inverted) 10 ? initialize as slave (normal) 11?initializeasmaster 01 c channel priority 00 ? disabled 0x30yy18 ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy1c ? 0x30yy1e 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=41 for tpa_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 period 0x30yyw2 high_time 0x30yyw4 0x30yyw6 high_time_ptr 0x30yyw8 rise_time_ptr 0x30yywa fall_time_ptr 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. motorola appendix c. tpu3 rom functions c-25 multichannel pulse-width modulation (mcpwm) table c-16. mcpwm parameters ? slave ch a non-inverted center-aligned mode control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number. 0x30yy0a assigned during microcode assembly. see table c-1 and table c-2. 0 1 c host sequence 00 ? edge-aligned mode 0x30yy0c ? 0x30yy12 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy14 ? 0x30yy16 01 ? initialize as slave (inverted) 10 ? initialize as slave (normal) 11?initializeasmaster 01 c channel priority 00 ? disabled 0x30yy18 ? 0x30yy1a 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy1c ? 0x30yy1e 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these addresses, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 period 0x30yyw2 nxt_b_rise_time 0x30yyw4 nxt_b_fall_time 0x30yyw6 dead_time high_time_ptr 0x30yyw8 rise_time_ptr 0x30yywa fall_time_ptr 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-26 mpc565/mpc566 reference manual motorola multichannel pulse-width modulation (mcpwm) table c-17. mcpwm parameters ? slave ch b non-inverted center-aligned mode control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 0 1 c host sequence 00 ? edge-aligned mode 0x30yy14 ? 0x30yy16 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize as slave (inverted) 10 ? initialize as slave (normal) 11?initializeasmaster 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 high_time 0x30yyw2 current_high_time 0x30yyw4 temp_storage 0x30yyw6 0x30yyw8 b_fall_time_ptr 0x30yywa b_rise_time_ptr 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. motorola appendix c. tpu3 rom functions c-27 multichannel pulse-width modulation (mcpwm) table c-18. mcpwm parameters ? slave ch a inverted center-aligned mode control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number 0x30yy0a assigned during microcode assembly. see table c-1 and table c-2. 0 1 c host sequence 00 ? edge-aligned mode 0x30yy0c ? 0x30yy12 01 ? slave a type center-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy14 ? 0x30yy16 01 ? initialize as slave (inverted) 10 ? initialize as slave (normal) 11?initializeasmaster 01 c channel priority 00 ? disabled 0x30yy18 ? 0x30yy1a 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy1c ? 0x30yy1e 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 period 0x30yyw2 nxt_b_rise_time 0x30yyw4 nxt_b_fall_time 0x30yyw6 dead_time high_time_ptr 0x30yyw8 rise_time_ptr 0x30yywa fall_time_ptr 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-28 mpc565/mpc566 reference manual motorola multichannel pulse-width modulation (mcpwm) table c-19. mcpwm parameters ? slave ch b non-inverted center-aligned mode control bits name options addresses 0123 c channel function select xxxx ? mcpwm function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 0 1 c host sequence 00 ? edge-aligned mode 0x30yy14 ? 0x30yy16 01 ? slave a type cente-aligned mode 10 ? slave b type center-aligned mode 11 ? slave c type center-aligned mode 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? initialize as slave (inverted) 10 ? initialize as slave (normal) 11?initializeasmaster 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 high_time 0x30yyw2 current_high_time 0x30yyw4 temp_storage 0x30yyw6 0x30yyw8 b_fall_time_ptr 0x30yywa b_rise_time_ptr 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. motorola appendix c. tpu3 rom functions c-29 fast quadrature decode tpu3 function (fqd) c.11 fast quadrature decode tpu3 function (fqd) fqd is a position-feedback function for motor control. it provides the cpu with a 16-bit free-running position counter by decoding the two signals from a slotted encoder. fqd incorporates a ?speed switch? that disables one of the channels at high speed, allowing faster signals to be decoded. furthermore, every counter update provides a time stamp that is useful for interpolating position and determining velocity at low speed or in instances that implement low-resolution encoders. the itc function handles the third index channel provided by some encoders. see motorola tpu progamming note fast quadrature decode tpu function (fqd), (tpupn02/d). table c-20 and table c-21 show the host interface areas for the fqd function for primary and secondary channels. c-30 mpc565/mpc566 reference manual motorola fast quadrature decode tpu3 function (fqd) table c-20. fqd parameters ? primary channel control bits name options addresses 0123 c channel function select xxxx ? fqd function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 01 c host sequence 00 ? primary channel (normal mode) 0x30yy14 ? 0x30yy16 01 ? secondary channel (normal mode) 10 ? primary channel (fast mode) 11 ? secondary channel (fast mode) 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? read tcr1 11 ? initialize 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable x?notused 0x30yy0a 0 c channel interrupt status xx ? not used 0x30yy20 for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 edge_time 0x30yyw2 position_count 0x30yyw4 tcr1_value 0x30yyw6 chan_pinstate 0x30yyw8 corr_pinstate_addr 0x30yywa edge_time_lsb_addr 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. motorola appendix c. tpu3 rom functions c-31 fast quadrature decode tpu3 function (fqd) table c-21. fqd parameters ? secondary channel control bits name options addresses 0123 c channel function select xxxx ? fqd function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 01 c host sequence 00 ? primary channel (normal mode) 0x30yy14 ? 0x30yy16 01 ? secondary channel (normal mode) 10 ? primary channel (fast mode) 11 ? secondary channel (fast mode) 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? read tcr1 11 ? initialize 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c channel interrupt enable x?notused 0x30yy0a 0 c channel interrupt status xx ? not used 0x30yy20 for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 0x30yyw2 0x30yyw4 tcr1_value 0x30yyw6 chan_pinstate 0x30yyw8 corr_pinstate_addr 0x30yywa edge_time_lsb_addr 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-32 mpc565/mpc566 reference manual motorola period/pulse-width accumulator (ppwa) c.12 period/pulse-width accumulator (ppwa) the period/pulse-width accumulator (ppwa) algorithm accumulates a 16-bit or 24-bit sum of either the period or the pulse width of an input signal over a programmable number of periods or pulses (from one to 255). after an accumulation period, the algorithm can generate a link to a sequential block of up to eight channels. the user specifies a starting channel of the block and number of channels within the block. generation of links depends on the mode of operation. any channel can be used to measure an accumulated number of periods of an input signal. a maximum of 24 bits can be used for the accumulation parameter. from one to 255 period measurements can be made and summed with the previous measurement(s) before the tpu3 interrupts the cpu, allowing instantaneous or average frequency measurement, and the latest complete accumulation (over the programmed number of periods). the pulse width (high-time portion) of an input signal can be measured (up to 24 bits) and added to a previous measurement over a programmable number of periods (one to 255). this provides an instantaneous or average pulse-width measurement capability, allowing the latest complete accumulation (over the specified number of periods) to always be available in a parameter. by using the output compare function in conjunction with ppwa, an output signal can be generated that is proportional to a specified input signal. the ratio of the input and output frequency is programmable. one or more output signals with different frequencies, yet proportional and synchronized to a single input signal, can be generated on separate channels. see motorola tpu progamming note period/pulse-width accumulator tpu function (ppwa), (tpupn11/d). table c-22 shows the host interface areas and parameter ram for the ppwa function. motorola appendix c. tpu3 rom functions c-33 period/pulse-width accumulator (ppwa) table c-22. ppwa parameters control bits name options addresses 0123 c channel function select xxxx ? ppwa function number 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 01 c host sequence 00 ? accumulate 24-bit periods, no links 0x30yy14 ? 0x30yy16 01 ? accumulate 16-bit periods, links 10 ? accumulate 24-bit pulse widths, no links 11 ? accumulate 16-bit pulse widths, links 01 c host service request 00 ? not used 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? initialize 11 ? not used 01 c channel priority 00 ? channel disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 start_link_ channel link_channel_ count 1 channel_control 0x30yyw2 max_count 2 period_count 0x30yyw4 last_accum 0x30yyw6 accum 0x30yyw8 accum_rate ppwa_ub 0x30yywa ppwa_lw 0x30yywc 0x30yywe 1. the tpu does not check the value of link_channel_count. if this parameter is not >0 and < 8, results are unpredictable. 2. max_count may be written at any time by the host cpu, but if the value written is < period_count, a period or pulse-width accumulation is terminated. if this happens, the number of periods over which the accumulation is performed will not correspond to max_count. =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-34 mpc565/mpc566 reference manual motorola output compare (oc) c.13 output compare (oc) the output compare (oc) function generates a rising edge, falling edge, or a toggle of the previous edge: immediately upon cpu initiation (generating a pulse with a length equal to a programmable delay time), after a programmable delay time, or continuously. upon receiving a link from a channel, oc references, without cpu interaction, a specifiable period and calculates an offset that is equal to the period x the ratio, where the ratio is a supplied parameter. this algorithm generates, with each high/low time, a 50% duty-cycle continuous square equal to the calculated offset. due to offset calculation, there is an initial link time before continuous pulse generation begins. see motorola tpu progamming note output compare tpu function (oc), (tpupn12/d). table c-23 shows the host interface areas and parameter ram for the oc function. motorola appendix c. tpu3 rom functions c-35 output compare (oc) table c-23. oc parameters control bits name options addresses 0123 c channel function select xxxx?ocfunctionnumber. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 01 c host sequence 0x ? matches and pulses scheduled 0x30yy14 ? 0x30yy16 x1 ? only read tcr1, tcr2 01 c host service request 00 ? no host service request 0x30yy18 ? 0x30yy1a 01 ? host-initiated pulse 10 ? not used 11 ? initialize, continuous pulses 01 c channel priority 00 ? channel disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 channel_control 0x30yyw2 offset 0x30yyw4 ratio ref_addr1 0 0x30yyw6 ref_addr2 0 ref_addr3 0 0x30yyw8 ref_time 0x30yywa actual_match_time 0x30yywc tcr1 0x30yywe tcr2 c = written by cpu c = written by cpu and tpu w = channel number c = written by tpu c = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-36 mpc565/mpc566 reference manual motorola pulse-width modulation (pwm) c.14 pulse-width modulation (pwm) the tpu3 can generate a pulse-width modulation (pwm) waveform with any duty cycle from 0 to 100% (within the resolution and latency capability of the tpu3). to define the pwm, the cpu provides one parameter that indicates the period and another that indicates the high time. updates to one or both of these parameters can effect waveform change immediately, or coherently at the next low-to-high pin transition. see motorola tpu progamming note pulse-width modulation tpu function (pwm), (tpupn17/d) . table c-24 shows the host interface areas and parameter ram for the pwm function. motorola appendix c. tpu3 rom functions c-37 pulse-width modulation (pwm) table c-24. pwm parameters control bits name options addresses 0123 c channel function select xxxx ? pwm function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 01 c host sequence xx ? not used 0x30yy14 ? 0x30yy16 01 c host service request 00 ? not used 0x30yy18 ? 0x30yy1a 01 ? immediate update of pwm 10 ? initialize 11 ? not used 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 c interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 c interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 channel_control 0x30yyw2 oldris 0x30yyw4 pwmhi (1, 3) 0x30yyw6 pwmper (2, 3) 0x30yyw8 pwmris 0x30yywa 0x30yywc 0x30yywe c = written by cpu c = written by cpu and tpu w = channel number c = written by tpu c = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-38 mpc565/mpc566 reference manual motorola discrete input/output (dio) c.15 discrete input/output (dio) the dio function allows a tpu3 channel to be used as a digital i/o pin. when a pin is used as a discrete input, a parameter indicates the current input level and the previous 15 levels of a pin. bit 15, the most significant bit of the parameter, indicates the most recent state. bit 14 indicates the next most recent state, and so on. the programmer can update the parameter when a transition occurs, when the cpu makes a request, or when a rate specified in another parameter is matched. when a pin is used as a discrete output, it is set high or low only upon request by the cpu. see motorola tpu progamming note discrete input/output tpu function (dio), (tpupn18/d). table c-25 shows the host interface areas for the dio function. motorola appendix c. tpu3 rom functions c-39 discrete input/output (dio) table c-25. dio parameters control bits name options addresses 0123 c channel function select xxxx ? dio function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 01 c host sequence 00 ? update on transition 0x30yy14 ? 0x30yy16 01 ? update at match rate 10 ? update on hsr 11 11 ? not used 01 c host service request 00 ? not used 0x30yy18 ? 0x30yy1a 01 ? drive pin high 10 ? drive pin low 11 ? initialize 01 0x30yy1c ? 0x30yy1e c channel priority 00 ? disabled 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 channel_control 0x30yyw2 pin_level 0x30yyw4 match_rate 0x30yyw6 0x30yyw8 0x30yywa 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-40 mpc565/mpc566 reference manual motorola synchronized pulse-width modulation (spwm) c.16 synchronized pulse-width modulation (spwm) the spwm function generates a pulse-width modulated waveform (pwm). the cpu can change the period or high time of the waveform at any time. three different operating modes allow the function to maintain complex timing relationships between channels without cpu intervention. the spwm output waveform duty cycle excludes 0% and 100%. if it is not necessary for a pwm to maintain a time relationship to another pwm, the pwm function should be used instead. see motorola tpu progamming note synchronized pulse-width modulation tpu function (spwm), (tpupn19/d). table c-26 shows all of the host interface areas for the spwm function. motorola appendix c. tpu3 rom functions c-41 synchronized pulse-width modulation (spwm) table c-26. spwm parameters control bits name options addresses 0123 c channel function select xxxx ? spwm function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 01 c host sequence 00 ? mode 0 0x30yy14 ? 0x30yy16 01 ? mode 1 10 ? mode 2 11 ? not used 01 c host service request 00 ? no host service request 0x30yy18 ? 0x30yy1a 01 ? not used 10 ? initialize 11 ? immediate update (mode 1) 01 c channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 lastrise channel_control 0x30yyw2 nextrise 0x30yyw4 high_time 0x30yyw6 period 0x30yyw8 ref_addr1 0x30yywa delay 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-42 mpc565/mpc566 reference manual motorola read/write timers and pin tpu3 function (rwtpin) c.17 read/write timers and pin tpu3 function (rwtpin) the rwtpin tpu3 function enables the cpu to read, via locations in pram, both the tcr1 and tcr2 timer counters, and than selectively load tcr1 or tcr2 with a cpu-supplied value contained in pram. the function also allows control of the pin state and direction of the rwtpin channel. a pin-state parameter is maintained in pram and is updated upon every service request. it can contain a value of the current pin state whether the pin is programmed as an input or output. parameter ram (mode 1) address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 lastrise channel_control 0x30yyw2 nextrise 0x30yyw4 high_time 0x30yyw6 delay 0x30yyw8 ref_addr1 ref_addr2 0x30yywa ref_value 0x30yywc 0x30yywe parameter ram (mode 2) address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 lastrise channel_control 0x30yyw2 nextrise 0x30yyw4 high_time 0x30yyw6 period 0x30yyw8 start_link_ channel link_channel_ count ref_addr1 0x30yywa delay 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. table c-26. spwm parameters (continued) control bits motorola appendix c. tpu3 rom functions c-43 read/write timers and pin tpu3 function (rwtpin) the function also receives links. upon receipt, it will read the two tcrs into pram, updating the pin-state parameter and generating a maskable interrupt request to the cpu. the cpu can control the channel pin, the tcrs, or both. to control the channel pin only, the ?read tcr? option is used and the values returned ignored. because this function controls the tcrs without affecting the channel pin, it can run on a tpu3 channel whose pin is controlled by a function running on another channel (for example, a slave stepper-motor channel). see motorola tpu progamming note using the tpu function library and tpu emulation mode, (tpupn00/d). table c-27 shows all of the host interface areas for the pta function. c-44 mpc565/mpc566 reference manual motorola id tpu3 function (id) c.18 id tpu3 function (id) this is a simple function that returns the version of the tpu3 rom on the current device. table c-27. rwtpin parameters control bits name options addresses 0123 channel function select xxxx?rwtpinfunctionnumber. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 0 1 host sequence xx ? not used 0x30yy14 ? 0x30yy16 01 host service request 00 ? no action 0x30yy18 ? 0x30yy1a 01 ? read tcrs and read/write pin 10 ? write tcr1, read tcrs and read/write pin 11 ? write tcr2, read tcrs and read/write pin 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 0x30yyw2 0x30yyw4 channel_control 0x30yyw6 channel_pin_state 0x30yyw8 tcr1_value 0x30yywa tcr2_value 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. motorola appendix c. tpu3 rom functions c-45 id tpu3 function (id) table c-28 shows all of the host interface areas for the id function. table c-28. id parameters control bits name options addresses 0123 channel function select xxxx ? id function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 0 1 host sequence xx ? not used 0x30yy14 ? 0x30yy16 01 host service request 00 ? no action 0x30yy18 ? 0x30yy1a 01 ? read tpu rom version 10 ? not used 11 ? not used 01 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 tpu3_id rom_revision 0x30yyw2 0x30yyw4 0x30yyw6 0x30yyw8 0x30yywa 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. c-46 mpc565/mpc566 reference manual motorola serial input/output port (siop) c.19 serial input/output port (siop) the serial input/output port (siop) tpu3 function uses two or three tpu3 channels to form a uni- or bidirectional synchronous serial port that can be used to communicate with a wide variety of devices. it can be used to add serial capabilities to a device without a serial port, or to extend the capabilities of one with a hardware-synchronous port. the siop tpu3 function has been designed to closely resemble the siop hardware port found on some motorola mcus. siop operates in master mode (the tpu3 always generates the clock) and has the following programmable features: 1. choice of one-channel clock-only, two-channel clock + transmit, two-channel clock + receive, or three-channel clock + transmit + receive operating modes 2. freely programmable baud-rate period over a 15-bit range of tcr1 counts 3. selection of msb or lsb first shift direction 4. variable transfer size from 1 to 16 bits 5. programmable clock polarity when a transfer of data is complete, the siop function notifies the host cpu by issuing an interrupt request. the arrangement of the multiple siop channels is fixed: the data-out channel is the channel above the clock channel and the data-in channel is the channel below the clock channel. in clock-only or uni-directional mode, the unused tpu3 channels are free to run other tpu3 functions. two possible siop configurations are show in figure c-2 figure c-2. two possible siop configurations c.19.1 parameters table c-29 shows the host interface areas and parameter ram for the siop function. the following sections describe these parameters. da t a o ut-chan x+1 clo c k o ut-chan x d ata in-chan x-1 76543210 76543210 d ata out-chan x+1 clo c k o u t -chan x 7 6 5 4 3 2 1 089 8-bit bidirectional transfer, msb first with data valid on clock rising edge 10-bit output only transfer, lsb first with data valid on clock falling edge motorola appendix c. tpu3 rom functions c-47 serial input/output port (siop) note only the clock channel requires any programming. the data-in and data-out channels are entirely under tpu3 microcode control. c-48 mpc565/mpc566 reference manual motorola serial input/output port (siop) table c-29. siop parameters control bits name options addresses 0123 c channel function select xxxx ? siop function number. 0x30yy0c ? 0x30yy12 assigned during microcode assembly. see table c-1 and table c-2. 01 c host sequence 00 ? clock channel active only, 0x30yy14 ? 0x30yy16 no data transfer 01 ? d out channels active, no data receive 10 ? clock and d in channels active, no data transmit 11 ? full bidirectional transmit and receive 01 c host service request 00 ? no host service (reset condition) 0x30yy18 ? 0x30yy1a 01 ? no action 10 ? no action 11 ? initialize clock channel and start transfer 10 channel priority 00 ? disabled 0x30yy1c ? 0x30yy1e 01 ? low priority 10 ? medium priority 11 ? high priority 0 channel interrupt enable 0 ? channel interrupt disabled 0x30yy0a 1 ? channel interrupt enabled 0 channel interrupt status 0 ? channel interrupt not asserted 0x30yy20 1 ? channel interrupt asserted for these address, yy=40 for tpu_a, 44 for tpu_b, and 5c for tpu_c. parameter ram address offsets bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30yyw0 s channel_control 0x30yyw2 half-period 0x30yyw4 bit_count 0x30yyw6 xfer_size 0x30yyw8 data 0x30yywa 0x30yywc 0x30yywe =writtenbycpu = written by cpu and tpu w = channel number =writtenbytpu = unused parameters for address offsets, yy=41 for tpu_a, 45 for tpu_b, and 5d for tpu_c. see table 18-22 for the pram address offset map. motorola appendix c. tpu3 rom functions c-49 serial input/output port (siop) c.19.1.1 chan_control this 9-bit, cpu-written parameter is used to set up the clock polarity for the siop data transfer. the valid values for chan_control for this function are given in the table below. chan_control must be written by the host before issuing the host service request (hsr) to initialize the function. c.19.1.2 bit_d bit_d is a cpu-written bit that determines the direction of shift of the siop data. if bit_d is zero, then siop_data is right shifted (lsb first). if bit_d is one then siop_data is left shifted (msb first). c.19.1.3 half_period this cpu-written parameter defines the baud rate of the siop function. the value contained in half_period is the number of tcr1 counts for a half-siop clock period (for example, for a 50 baud rate, with a tcr1 period of 240 ns, the value [(1/50)/2]/240 ns = 42) should be written to half_period. the range for half_period is 1 to 0x8000, although the minimum value in practice will be limited by other system conditions. see the notes in section c.19.1.6, ?siop_data? for information on the use and performance of the siop function. c.19.1.4 bit_count the tpu3 uses this parameter to count down the number of bits remaining during a transfer in progress. during the siop initialization state, bit_count is loaded with the value contained in xfer_size and then decremented as the data is transferred. when it reaches zero, the transfer is complete and the tpu3 issues an interrupt request to the cpu. c.19.1.5 xfer_size this cpu-written parameter determines the number of bits that make up a data transfer. during initialization, xfer_size is copied into bit_count. xfer_size is shown as a 5-bit parameter to match the maximum size of 16 bits in siop_data, although the tpu3 uses the whole word location. for normal use, xfer_size should be in the 1- to 16-bit range. table c-30. siop function valid chan_control options chan_control 1 876543210 1 other values of chan_control may result in indeterminate operation. resulting action 0 1 0 0 0 1 1 0 1 data valid on clock falling edge. 010001110 datavalidonclockrisingedge. c-50 mpc565/mpc566 reference manual motorola serial input/output port (siop) c.19.1.6 siop_data this parameter is the data register for all siop transfers. data is shifted out of one end of siop_data and shifted in at the other end, the shift direction being determined by the value of bit_d. in output-only mode, zero will be shifted into siop_data and in input-only mode, the data shifted out is ignored. in clock-only mode, siop_data is still shifted. note the tpu3 does not ?justify? the data position in siop_data (for example, if an 8-bit bidirectional transfer is made, shifting lsb first, then the bottom byte of siop_data will be shifted out and the input data will be shifted into the upper byte of siop_data). note siop_data is not buffered. the cpu should only access it between completion of one transfer and the start of the next. c.19.2 host cpu initialization of the siop function the cpu initializes the siop function by: 1. disabling the channel by clearing the two channel-priority bits 2. selecting the siop function on the channel by writing the assigned siop function number to the function-select bits 3. writing chan_control in the clock channel parameter ram 4. writing half_period, bit_d, and xfer_size in the clock-channel parameter ram to determine the speed, shift direction, and size of the transfer 5. writing siop_data if the data output is to be used 6. selecting the required operating mode via the two host-sequence bits 7. issuing a host service request type 0b11 8. enabling service by assigning h, m, or l priority to the clock channel via the two channel-priority bits the tpu3 then starts the data transfer, and issues an interrupt request when the transfer is complete. once the function has been initialized, the cpu only needs to write siop_data with the new data and issue a hsr 0b11 to initiate a new transfer. in input-only or clock-only modes, just the hsr 0b11 is required. motorola appendix c. tpu3 rom functions c-51 serial input/output port (siop) c.19.3 siop function performance like all tpu3 functions, the performance limit of the siop function depends, because of the operational nature of the scheduler, on the service time (latency) associated with other active tpu3 channels. where two channels are used for a uni-directional system and no other tpu3 channels are active, the maximum baud rate is approximately 230 at a bus speed of 16.77 mhz. a three-channel bidirectional system under the same conditions has a maximum baud rate of approximately 200. when more tpu3 channels are active, these performance figures will be degraded; however, the scheduler assures that the worst-case latency in any tpu3 application can be closely approximated. tpu3 reference manual guidelines and information given in the siop-state timing table should be used to perform an analysis on any proposed tpu3 application that appears to approach the tpu?s performance limits. c.19.3.1 xfer_size greater than 16 xfer_size is normally programmed to be in the 1- to 16-bit range to match the size of siop_data, and has thus been shown as a 5-bit value in the host interface diagram. however, the tpu3 actually uses all 16 bits of the xfer_size parameter when loading bit_count. in some unusual circumstances this can be used to an advantage. if an input device is producing a data stream of greater than 16 bits then manipulation of xfer_size will allow selective capturing of the data. in clock-only mode, the extended xfer_size can be used to generate up to 0xffff clocks. c.19.3.2 data positioning as stated above, the tpu3 does not ?justify? the data position in siop_data. therefore, in the case of a byte transfer, the data output will be sourced from one byte and the data input will shift into the other byte. this is true for all data sizes except 16 bits, in which case the full siop_data register is used for both data output and input. table c-31. siop state timing 1 1 execution times do not include the time slot transition time (tst = 10 or 14 cpu clocks). state number and name max. cpu clock cycles number of ram accesses by tpu3 s1 siop_init hsq = x0 x1 28 38 7 7 s2 data_out hsq = x0 x1 14 24 4 4 s3 data_in hsq = 0x 1x 14 28 4 6 c-52 mpc565/mpc566 reference manual motorola serial input/output port (siop) c.19.3.3 data timing in the example given in figure c-3, the data output transitions are shown as being completely synchronous with the relevant clock edge and it is assumed that the data input is latched exactly on the opposite clock edge. this is the simplest way to show the examples, but is not strictly true. since the tpu3 is a multi-tasking system, and the data channels are manipulated directly by microcode software while servicing the clock edge, there is a finite delay between the relevant clock edge and the data-out being valid or the data-in being latched. this delay is equivalent to the latency in servicing the clock channel due to other tpu3 activity and is shown as ?td? in the timing diagram. td is the delay between the clock edge and the next output data being valid and also the delay between the opposite clock edge and the input data being read. for the vast majority of applications, the delay td will not present a problem and can be ignored. only for a system which heavily loads the tpu3 should the worst case latency be calculated for the siop clock channel + actual siop service time ( = td) and ensure that the baud rate is chosen such that half_period - td is not less that the minimum setup time of the receiving device. a transmitting device must also hold data valid for a minimum time of td after the clock. figure c-3. siop function data transition example data out cha n x+1 clo c k cha n x data in cha n x-1 td td motorola appendix d. memory access timing d-1 appendix d memory access timing table d-1 lists all possible memory access timings for internal and external memory combinations. the clock values show the number of clocks from the moment an address is valid on a specific bus, until data is back on that same bus. the following assumptions were used when compiling the information: the arbitration time was ignored. the values assume that the bus (or buses) involved in a transaction was in the idle state when the transaction needs that bus. the uimb works in a mode of 1:1. this is relevant for imb access values. in the case of 2:1 mode, the clock latency for a cycle on the imb should be doubled (each imb access takes two clocks). the basic delay of an external bus to a u-bus is four clocks (external master case). all imb accesses are assumed to be 16-bit accesses only. if 32-bit accesses are used, then each such imb access is split into two separate 16-bit cycles with normal imb performance for each. d-2 mpc565/mpc566 reference manual motorola table d-1. memory access times using different buses internal buses external ram/flash show cycle flash ram decram imb siu internal memory mapped external non-mapped internal memory write read rcpu load/store 3/4 1 1 ?/? indicates on/off page flash access. 1654+n 2 2 n is the number of read cycle clocks from external address valid till external data valid. in the case of zero wait states, n=2. 4+n 2 2 rcpu instruction fetches 2-1-1-1-1.. . 3 3 3 assuming bbc is parked on the u-bus 2 ? ?2+n 2+n ?1 4 4 until address is valid on external pins peripheral mode (only external master is active) 4/5 6 6 7 6 slave mode (both external and internal cpus are active) 5/6 7 6 8 7 table d-2. instruction timing examples for different buses note: l = l-bus, u = u-bus, e = e-bus, c = cmf (flash), imb = internal memory bus, dc = decram access number of clocks total 12345678910111213 load/store -> ebus l u e 6 1 eul load/store -> imb 16 bits l u imb 6 imb u l instruction fetch-> cmf new page 3 consecutive accesses c,u 2 u 2 c,u 1 u c,u 1 u instruction fetch-> decram (decompression off) u icdu icdu u motorola appendix d. memory access timing d-3 note: shaded areas = address phase ; non-shaded areas = data phase instruction fetch-> cmf new page load/store -> imb c,u 2 u l u imb 6 imb u l instruction fetch-> cmf new page load/store -> imb c u 6 u l u imb 6 imb u l external bus-> cmf new page e u 5 ue external bus-> imb e u imb 7 imb u e instruction fetch-> cmf 2 consecutive accesses and external bus-> cmf c,u 2 u c? 3 ??????? u11 u e retry e 4 u8 ue 1 n is the number of read cycle clocks from external address valid until external data valid. in the case of zero wait states, n=2. 2 core instruction fetch data bus is usually the u-bus 3 8 clocks are dedicated for external accesses, and internal accesses are denied. 4 assuming the external master immediately retries table d-2. instruction timing examples (continued)for different buses note: l = l-bus, u = u-bus, e = e-bus, c = cmf (flash), imb = internal memory bus, dc = decram access number of clocks total 12345678910111213 d-4 mpc565/mpc566 reference manual motorola motorola appendix e. electrical characteristics e-1 appendix e electrical characteristics this section contains detailed information on power considerations, dc/ac electrical characteristics, and ac timing characteristics of the mpc565 / mpc566. the mpc565 / mpc566 is designed to operate at 40 mhz, or optionally up to 56 mhz. ) table e-1. absolute maximum ratings (vss = 0v) rating symbol min. value max. value unit 1 2.6-v supply voltage 1 v ddl -0.3 3.0 2 v 2 flash supply voltages 3 v flash -0.3 5.6 v 3 flash core voltage 1 v ddf -0.3 3.0 v 4 oscillator, keep-alive reg. supply voltage 1 kapwr -0.3 3.0 v 5 sram supply voltage 1 v ddsram1, v ddsram2, v ddsram3 -0.3 3.0 v 6 clock synthesizer supply voltage 1 v ddsyn -0.3 3.0 v 7 32-khz rtc oscillator supply voltage 1 v ddrtc -0.3 3.0 v 8 qadc supply voltage 4 v dda -0.3 5.6 v 9 5-v supply voltage v ddh -0.3 5.6 v 10 dc input voltages 5, 6 v in v ss -0.3 5.6 v 11 reference v rh , with reference to v rl v rh -0.3 5.6 v 12 reference altref, with reference to v rl v arh -0.3 5.6 v 13 v ss differential voltage v ss ?v ssa -0.1 0.1 v 15 v ref differential voltage v rh ?v rl -5.6 5.6 v 16 v rl to v ssa differential voltage v rl ?v ssa -0.3 0.3 v 17 maximum input current per pin 7, 8, 9 i ma -25 10 25 11 ma 18 qadc maximum input current per pin i max -25 11 25 11 ma 19 operating temperature range ? ambient (packaged), m temperature range. t a -40 (t l ) +125 (t h ) c 19a operating temperature range ? ambient (packaged), c temperature range. t a -40 (t l ) +85 (t h ) c e-2 mpc565/mpc566 reference manual motorola package functional operating conditions are given in section e.5, ?dc electrical characteristics.? absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or v dd ). e.1 package the mpc565 / mpc566 is available in packaged form. the package is a 388-ball pbga having a 1.0 mm ball pitch, motorola case outline 1164-01 (see figure 2-7). 20 operating temperature range ? solder ball (packaged any perimeter solder ball) 11 t sb -40 (t l ) +135 (t h ) c 21 operating temperature range (die form) t j -40 +150 c 22 storage temperature range t stg -55 +150 c 23 maximum solder temperature 12 t sdr ?235 c 24 moisture sensitivity level 13 msl ? 3 ? 1 for internal digital supply of v ddl =2.6-vtypical. 2 2.6 volt supply pins can withstand up to 3.6 volts for acumulative time of 24 hours over the lifetime of the de- vice. 3 during operation the value of v flash must be 5.0 v motorola appendix e. electrical characteristics e-3 emi characteristics e.2 emi characteristics e.2.1 reference documents the document referenced for the emc testing of mpc565 / mpc566 is sae j1752/3 issued 1995-03 e.2.2 definitions and acronyms emc ? electromagnetic compatibility emi ? electromagnetic interference tem cell ? transverse electromagnetic mode cell e.2.3 emi testing specifications 1. scan range: 150 khz ? 1000 mhz 2. operating frequency: 56 mhz 3. operating voltages: 2.6 v, 5.0 v 4. max spikes: tbd dbuv 5. i/o port waveforms: per j1752/3 6. temperature: 25 c e.3 thermal characteristics table e-2. thermal characteristics characteristic symbol value unit bga package thermal resistance, junction to ambient ? natural convection r e-4 mpc565/mpc566 reference manual motorola thermal characteristics an estimation of the chip junction temperature, t j , in c can be obtained from the equation: t j =t a +(r ja xp d ) where: t a = ambient temperature (c) r ja = package junction to ambient resistance (c/w) p d = power dissipation in package the junction to ambient thermal resistance is an industry standard value which provides a quick and easy estimation of thermal performance. unfortunately, the answer is only an estimate; test cases have demonstrated that errors of a factor of two are possible. as a result, more detailed thermal characterization is supplied. historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: r ja =r jc +r ca where: r ja = junction to ambient thermal resistance (c/w) r jc = junction to case thermal resistance (c/w) r ja = case to ambient thermal resistance (c/w) r jc is device related and cannot be influenced. the user controls the thermal environment to change the case to ambient thermal resistance, r ca . for instance, the air flow can be changed around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. this description is most useful for ceramic packages with heat sinks where about 90% of the heat flow is through the case to the heat sink to ambient. for most packages, a better model is required. the simplest thermal model of a package which has demonstrated reasonable accuracy (about 20 percent) is a two resistor model consisting of a junction to board and a junction to case thermal resistance. the junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. the junction to board thermal resistance describes the thermal performance when most of the 4 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and the board thermal resistance. 5 per jesd51-6 with the board horizontal. 6 thermal resistance between the die and the printed circuit board (four layer (2s2p) board, natural con- vection). 7 indicates the thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. 8 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per eia/jesd51-2. motorola appendix e. electrical characteristics e-5 thermal characteristics heat is conducted to the printed circuit board. it has been observed that the thermal performance of most plastic packages and especially pbga packages is strongly dependent on the board. temperature. if the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation: t j =t b +(r jb xp d ) where: t b = board temperature (c) r jb = package junction to board resistance (c/w) p d = power dissipation in package ( ? ) if the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. for this method to work, the board and board mounting must be similar to the test board used to determine the junction to board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. when the board temperature is not known, a thermal simulation of the application is needed. the simple two-resistor model can be used with the thermal simulation of the application (2), or a more accurate and complex model of the package can be used in the thermal simulation. consultation on the creation of the complex model is available. to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j =t t +( jt xp d ) where: t t = thermocouple temperature on top of package (c) jt = thermal characterization parameter p d = power dissipation in package the thermal characterization parameter is measured per jesd51-2 specification published by jedec using a 40 gauge type-t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about one mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. e-6 mpc565/mpc566 reference manual motorola esd protection e.3.1 thermal references semiconductor equipment and materials international 805 east middlefield road mountain view, ca 94043 (415) 964-5111 mil-spec and eia/jesd (jedec) specifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at www.jedec.org. 1. c.e. triplett and b. joiner, ? an experimental characterization of a 272 pbga within an automotive engine controller module ,? proceedings of semitherm, san diego, 1998, pp. 47-54. 2. b.joinerandv.adams,? measurement and simulation of junction to board thermal resistance and its application in thermal modeling ,? proceedings of semitherm, san diego, 1999, pp. 212-220. e.4 esd protection table e-3. esd protection characteristics symbol value units esd for human body model (hbm) 1 1 all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrat- ed circuits. 2000 v hbm circuit description r1 1500 ? ? motorola appendix e. electrical characteristics e-7 dc electrical characteristics e.5 dc electrical characteristics note: (v dd =2.6v e-8 mpc565/mpc566 reference manual motorola dc electrical characteristics 17 2.6-v output high voltage v dd =v ddl 2.6-v output high voltage (ioh = -1ma) 2.6-v output high voltage (ioh = -2ma) voh2.6 voh2.6a 2.3 2.1 ?v 18 5-v output high voltage v dd =v ddh (ioh= -2ma) all 5-v only outputs except tpu. voh5 v ddh ?0.7 ?v 19 5-v output high voltage v dd =v ddh (ioh= -5ma) for tpu pins only vohtp5 v ddh ? 0.65 ?v 20 muxed 2.6-v/ 5-v pins (gpio muxed with addr, data) 2.6-v output high voltage (ioh = -1ma) 2.6-v output high voltage (ioh = -2ma) 5-v output high voltage (ioh = -2ma) voh2.6m voh2.6ma voh5m 2.3 2.1 v ddh ?0.7 ?v 21 2.6-v output low voltage v dd =v ddl (iol = 3.2ma) vol2.6 ? 0.5 v 22 5-v output low voltage v dd =v ddh (iol = 2ma) all 5-v only outputs except tpu vol5 ? 0.45 v 23 5-v output low voltage v dd =v ddh -tpu pins only iol = 2ma iol = 10ma voltp5 ? 0.45 1.0 v 24 muxed 2.6-v/ 5-v pins (gpio muxed with addr, data) 2.6-v output low voltage (iol = 3.2ma) 5-v output low voltage (iol = 2ma) vol2.6m vol5m 0.5 0.45 v 25 output low current (@ vol2.6= 0.4 v) iol2.6 2.0 ? ma 26 output high current (@ voh2.6= 2.1 v) output high current (@ voh2.6= 2.3 v) ioh2.6 ioh2.6a 2.0 1.0 ?ma 27 clkout load capacitance ? sccr com & cqds com[0:1]= 0b01, cqds = 0b1 com[0:1]= 0b01 cqds = 0b0 com[0:1]= 0b00 cqds = 0bx c clk ? 25 50 90 pf pf pf 29 capacitance for input, output, and bidirectional pins: vin=0v,f=1mhz(exceptqadc) cin ? 7 pf 30 load capacitance for bus pins only 8 com[0:1] of sccr = 0b11 com[0:1] of sccr = 0b10 cl ? 25 50 pf 31 total input capacitance pqa not sampling pqb not sampling c in ? ? 15 15 pf 32 hysteresis(onlyirq,tpu,mios,gpio,qadc(digital inputs) and hreset, sreset, poreset) 9 vh 0.5 ? v operating current (2.6-v supplies) @ 40 mhz 10 v dd /q vddl /n vddl i ddl ?120 kapwr (crystal frequency: 20 mhz) i ddkap ?5 kapwr (crystal frequency: 4 mhz) i ddkap ?2 33 v ddsyn i ddsyn ?2ma v ddrtc (crystal frequency: 32 khz) i ddrtc ?10 v ddf (read, program, or erase) i ddf ?35 v ddf (two-module program or erase) i ddfprog ?70 v ddfstop i ddfstop ?10 table e-4. dc electrical characteristics (continued) characteristic symbol min max unit motorola appendix e. electrical characteristics e-9 dc electrical characteristics 33 cont. v ddfdisabled 13 v ddsram1 v ddsram2 v ddsram3 i ddfdisb i ddsram1 i ddsram2 i ddsram3 ? 100 25 25 25 a 34 operating current (5-v supplies)@ 40 mhz 11 v ddh v dda 11 v flashf5 (program or erase) v flashf5read v flashf5 (stopped) v flashf5 (disabled) i ddh5 i dda i ddf5 i ddf5r si ddf5 si ddf5d ? 20 5 10 12 3 1 ma 100 a operating current (2.6-v supplies)@ 56 mhz 11 v dd /q vddl /n vddl i ddl ?230 kapwr (crystal frequency: 20 mhz) i ddkap ?5 kapwr (crystal frequency: 4 mhz) i ddkap ?2 35 v ddsyn i ddsyn ?2ma v ddrtc (crystal frequency: 32 khz) i ddrtc ?10 v ddf (read, program, or erase) i ddf ?35 v ddf (two-module program or erase) i ddfprog2 ?70 v ddfstop i ddfstop ?10 v ddfdisabled v ddsram1 v ddsram2 v ddsram3 i ddfdisb i ddsram1 i ddsram2 i ddsram3 ? 100 25 25 25 a 36 operating current (5-v supplies)@ 56 mhz 11 v ddh v dda 15 v flashf5 (program or erase) v flashf5read v flashf5 (stopped) v flashf5 (disabled) i ddh5 i dda i ddf5 i ddf5r si ddf5 si ddf5d ? 20 5.0 10 12 4 1 100 ma ma ma ma ma a 37 qadc64 low power stop mode (v dda )i dda ?10 e-10 mpc565/mpc566 reference manual motorola dc electrical characteristics 44 qadc operating voltage v dda 4.75 5.25 v 45 clock synthesizer operating voltage difference 21 v ddsyn v dd ?0.2 v v dd +0.2v 15 v 46 real time clock operating voltage difference 21 v ddrtc v dd ?0.2 v v dd +0.2v 15 v 47 v ss differential voltage v ss ?v ssa -100 100 mv 48 qadc64 reference voltage low 17 v rl v ssa v ssa +0.1 v 49 qadc64 reference voltage high26 v rh 3.0 v dda v 50 qadc64 v ref differential voltage v rh ?v rl 3.0 5.25 v 51 qadc64 reference supply current, dc qadc64 reference supply current, transient i ref i reft ? ? 500 4.0 motorola appendix e. electrical characteristics e-11 dc electrical characteristics 7 maximum leakage occurs at maximum operating temperature. current decreases by approximately one-half for each eight to 12 c, in the ambient temperature range of 50 to 125 c. 8 all bus pins support two drive strengths capabilities, 25 pf and 50 pf. current drive is less at the 25-pf capacitive load. both modes achieve 40-mhz (or, optionally, 56-mhz) timing. 9 only irq, tpu, mios, gpio, qadc (when digital inputs) and reset pins have hysteresis, thus there is no hysteresis specification on all other pins 10 all power consumption specifications assume 50-pf loads and running a typical application. of the power consumption of some modules could go up is they are exercised heavier, but the power consumption of other modules would decrease. 11 current measured at maximum system clock frequency with qadc active. 12 transient currents can reach 50ma. 13 kapwr and v ddsram can be powered-up prior to any other supply or at the same time as the other 2.6 v supplies. 14 this parameter is periodically sampled rather than 100% tested 15 up to 0.5 v during power up/down. 16 17 to obtain full-range results, v ssa e-12 mpc565/mpc566 reference manual motorola oscillator and pll electrical characteristics e.6 oscillator and pll electrical characteristics note: (v dd =2.6v 0.1 v, v ddh =5.0v 0.25 v, t a =t l to t h ) e.7 flash electrical characteristics note: (v ddf =2.6v 0.1 v, v flash =5.0v 0.25 v, t a =t l to t h ,t b =t l to t h ) table e-5. oscillator and pll characteristic symbol min typical max unit 1 oscillator startup time (for typical crystal capacitive load) 4-mhz crystal 20-mhz crystal oscstart4 oscstart20 10 10 ms ms 2 pll lock time t lock 1000 1 1 assumes stable power and oscillator. input clocks 3 pll operating range 2 2 f vcoout is 2x the system frequency. f vcoout 30 112 mhz 4 crystal operating range, modck=0b010,0b110 modck[1:3] = 0b001, 0b011, 0b100, 0b101, 0b111 f crystal 2 15 5 25 mhz mhz 5 pll jitter pll jitter (averaged over 10 s) f jit f jit10 -1% -0.3% +1% +0.3% ? 6 limp mode clock out frequency ? 3 3 3 estimated value, real values to be characterized and updated. 11 17 3 mhz 7 oscillator bias current (xtal) 4mhz 20 mhz i bias ? 0.3 1.5 ma ma 8 oscillator drive (xtal) i osc 7?ma 9 oscillator bias resistor r osc 0.5 1 3 m table e-6. array program and erase characteristics symbol meaning value units minimum typical 1 1 typical program and erase times assume nominal supply values and 25 c. maximum t erase block erase time 2 2 erase time specification does not include pre-programming operation 312s t erasem module erase time 2 13 60 s t prog word programming time 3, 4 3 word size is 32 bits. 4 the maximum hardware programming time of the entire flash (not including the shadow rows) is 20 sx(512 kbytes / 4 bytes per word), or 131,072 x 2words, (no software overhead). 15 20 s motorola appendix e. electrical characteristics e-13 power-up/down sequencing note: (v ddf =2.6v this section applies to only cdr3 devices such as the mpc565 / mpc566 . the supply symbols used in this section are described in table e-9. table e-7. censor cell program and erase characteristics symbol meaning value units minimum typical 1 1 typical set and clear times assume nominal supply values and 25 c. maximum t clear censor bit clear time 2 2 clear time specification does not include pre-set operation. 13 60 s t set censor bit set time 115 250 to 0 to 1. maximum number of program/erase cycles per block to guarantee data retention. 1,000 censor set/clear cycles 2 2 a censor set/clear cycle is defined as switching the bits from 1 to 0 to 1. minimum number of program/erase cycles per bit before failure. 100 array and censor data retention minimum data retention at an average of 85 c junction temperature. minimum data retention at an average of 125 c junction temperature. min15years 3 min10years 3 3 maximum total time @ 150 c junction temperature e-14 mpc565/mpc566 reference manual motorola power-up/down sequencing . there are two power-up/down options. choosing which one is required for an application will depend upon circuitry connected to 2.6-v compliant pins and dual 2.6-v/5-v compliant pins. power-up/down option a is required if 2.6-v compliant pins and dual 2.6-v/5-v compliant pins are connected to the 5-v supply with a pull-up resistor or driven by 5-v logic during power-up/down. in applications for which this scenario is not true the power-up/down option b may be implemented. option b is less stringent and easier to ensure over a variety of applications. refer to table 2-1 for a list of 2.6 v and dual 2.6v/5 v compliant pins. the power consumption during power-up/down sequencing will stay below the operating power consumption specifications when following these guidelines. note: the v ddhi ramp voltage should be kept below 50v/ms and the v ddlo ramp rate less that 25v/ms. e.8.1 power-up/down option a the option a power-up sequence (excluding v ddka )is 1. v ddhi v ddlo + 3.1 v (v ddhi cannot lead v ddlo by more than 3.1 v) 2. v ddhi v ddlo - 0.5 v (v ddhi cannot lag v ddlo by more than 0.5 v) table e-9 power supply pin groups symbol types of power pins v ddhi (high voltage supply group) supply to the 5-v pads for output driver (v ddh ) supply to the analog (qadc64e) circuitry (v dda ) high voltage supply to the flash module (v flash ) v ddlo (low voltage supply pins) supply to low voltage pad drivers (qvddl, nvddl) supply to all low voltage internal logic (v dd ) supply to low voltage flash circuitry (v ddf ) supply to system pll v ddka (low voltage keep-alive supply pins 1 1 any supply in the v ddka group can be powered with the v ddlo if the function which it supplies is not required during ?keep-alive?. supply to sram arrays only (v ddsram1 ,v ddsram2 , v ddsram3 ) supply to low power counter and 32 khz crystal (v ddrtc ) supply to oscillator and other circuitry for keep-alive functions (kapwr). motorola appendix e. electrical characteristics e-15 power-up/down sequencing the first step in the sequence is required is due to gate-to-drain stress limits for transistors in the pads of 2.6-v compliant pins and dual 2.6-v/5-v compliant pins. damage can occur if gate-to-drain voltage potential is greater than 3.1 v. this is only a concern at power-up/down. the second step in the sequence is required is due to esd diodes in the pad logic for dual 2.6-v/5-v compliant pins and 2.6-v pins. the diodes are forward biased when v ddlo is greater than v ddhi and will start to conduct current. figure e-1 illustrates the power-up sequence if no keep-alive supply is required. figure e-2 illustrates the power-up sequence if a keep-alive supply is required. the keep-alive supply should be powered-up at the same instant or before both the high voltage and low voltage supplies are powered-up. figure e-1. option a power-up sequence without keep-alive supply figure e-2. option a power-up sequence with keep-alive supply the option a power-down sequence (excluding v ddka )is 1. v ddhi v ddlo + 3.1 v (v ddhi cannot lag v ddlo by more than 3.1 v) v ddhi v ddlo v ddhi cannot lead v ddlo by more than 3.1 v 3.1-v lead v ddhi cannot lag v ddlo by more than 0.5 v 0.5-v lag v ddhi v ddlo 3.1-v lead 0.5-v lag v ddka v ddhi cannot lead v ddlo by more than 3.1 v v ddhi cannot lag v ddlo by more than 0.5 v e-16 mpc565/mpc566 reference manual motorola power-up/down sequencing 2. v ddhi v ddlo - 0.5 v (v ddhi cannot lead v ddlo by more than 0.5 v) figure e-3 illustrates the power-down sequence if no keep-alive supply is required. figure e-4 illustrates the power-down sequence if a keep-alive supply is required. figure e-3. option a power-down sequence without keep-alive supply figure e-4. option a power-down sequence with keep-alive supply v ddh i v ddlo 3.1-v max ramp down rates may differ with load, so care should be taken maintain v ddhi with respect to v ddlo . v ddhi cannot lag v ddlo by more than 3.1 v. v ddhi motorola appendix e. electrical characteristics e-17 power-up/down sequencing e.8.2 power-up/down option b a less stringent power-up sequence may be implemented if 2.6-v compliant pins and dual 2.6-v/5-v compliant pins are not connected to the 5-v supply with a pull-up resistor or driven by 5-v logic during power-up/down. the option b power-up sequence (excluding v ddka )is: 1. v ddhi >v ddlo - 0.5 v (v ddhi cannot lag v ddlo by more than 0.5 v) thus the v ddhi supply group can be fully powered-up prior to power-up of the v ddlo supply group, with no adverse affects to the device. the requirement that v ddhi cannot lag v ddlo by more than 0.5 v is due to esd diodes in the pad logic for dual 2.6-v/5-v compliant pins and 2.6-v pins. the diodes are forward biased when v ddlo is greater than v ddhi and will start to conduct current. figure e-5 illustrates the power-up sequence if no keep-alive supply is required. figure e-6 illustrates the power-up sequence if a keep-alive supply is required. the keep-alive supply should be powered-up at the same time or before both the high voltage and low voltage supplies are powered-up. figure e-5. option b power-up sequence without keep-alive supply v ddhi v ddlo v ddhi cannot lag v ddlo by more than 0.5 v 0.5-v lag e-18 mpc565/mpc566 reference manual motorola power-up/down sequencing figure e-6. option b power-up sequence with keep-alive supply the option b power-down sequence (excluding v ddka )is: 1. the v ddlo supply group can be fully powered-down prior to power-down of the v ddhi supply group, with no adverse affects to the device. for power-down, the low voltage supply should come down before the high voltage supply, although with varying loads, the high voltage may actually get ahead. figure e-7 illustrates the power-down sequence if no keep-alive supply is required. figure e-8 illustrates the power-down sequence if a keep-alive supply is required. figure e-7. option b power-down sequence without keep-alive supply v ddhi v ddlo v ddhi cannot lag v ddlo by more than 0.5 v 0.5-v lag v ddka v ddhi v ddlo ramp down rates may differ with load. 0.5-v lag v ddhi cannot lead v ddlo by more than 0.5v v ddhi 5.25v motorola appendix e. electrical characteristics e-19 issues regarding power sequence figure e-8. option b power-down sequence with keep-alive supply e.9 issues regarding power sequence e.9.1 application of poreset or hreset when vdd hi is rising and vdd lo is at 0.0 v, as vdd hi reaches 1.6 v, all 5 v drivers are tristated. before vdd hi reaches 1.6v, all 5 v outputs are unknown. if vdd lo is rising and vdd hi is at least 3.1v greater than vdd lo , then the 5 v drivers can come out of tristate when vdd lo reaches 1.1v, and the 2.6 v drivers can start driving when vdd lo reaches 0.5 v. for these reasons, the poreset or hreset signal must be asserted during power-up before vdd lo is above 0.5 v. if the poreset or hreset signal is not asserted before this condition, there is a possibility of disturbing the programmed state of the flash. in addition, the state of the pads are indeterminant until poreset or hreset propagates through the device to initialize all circuitry. e.9.2 keep-alive ram poreset or hreset must be asserted during power-down prior to any supply dropping out of specified operating conditions. an additional constraint is placed on poreset assertion since it is an asynchronous input. to assure that the assertion of poreset does not potentially cause stores to keep-alive ram to be corrupted (store single or store multiple) or non-coherent (store multiple), either of the following solutions is recommended: assert hreset at least 0.5 s prior to when poreset is asserted. v ddhi v ddlo ramp down rates may differ with load. 0.5-v lag v ddhi cannot lead v ddlo by more than 0.5v v ddkap e-20 mpc565/mpc566 reference manual motorola issues regarding power sequence assert irq [0] (non-maskable interrupt) at least 0.5 s prior to when poreset is asserted. the service routine for irq [0] should not perform any writes to keep-alive ram. the amount of delay that should be added to poreset assertion is dependent upon the frequency of operation and the maximum number of store multiples executed that are required to be coherent. if store multiples of more than 28 registers are needed and if the frequency of operation is lower that 56 mhz, the delay added to poreset assertion will need to be greater than 0.5 s. in addition, if kapwr features are being used, poreset should not be driven low while the v ddhi and v ddlo supplies are off. motorola appendix e. electrical characteristics e-21 ac timing e.10 ac timing figure e-9. generic timing examples clkout 5-v outputs 5-v inputs 5-v inputs v ol v oh v ih v il v il v ih v ih v il v il v ih a b cd cd a. maximum output delay specification b. minimum output hold time c. minimum input setup time specification d. minimum input hold time specification 5-v outputs a b addr/data/ctrl v dd /2 a b a b addr/data/ctrl outputs v dd /2 addr/data/ctrl c d cd v ol v oh v ol v oh v ol v oh v dd /2 v dd /2 v dd /2 addr/data/ctrl inputs v dd v dd /2 v dd /2 v dd /2 v dd /2 e-22 mpc565/mpc566 reference manual motorola ac timing table e-10. bus operation timing note: (v dd =2.6v motorola appendix e. electrical characteristics e-23 ac timing 8 clkout to signal valid a[0:31] rd/wr burst d[0:31] 4 6.25 14 4.5 11 ns 8a clkout to signal valid tsiz[0:1] rsv at[0:3] bdip ptr retry 6.25 13 4.5 9.5 ns 8b clkout to signal valid 2 br bg vfls[0:1] vf[0:2] iwp[0:2] frz lwp[0:1] sts valid. 6.25 14 4.5 10.5 ns 8c slave mode clkout to signal valid d[0:31] 14 11 ns 8d clkout to data pre-discharge time 16 16 ns 8e clkout to data pre-discharge start 33ns 9clkouttohighz a[0:31] rd/wr burst d[0:31] tsiz[0:1] rsv at[0:3] ptr retry 6.25 13 4.5 9.5 ns 10 clkout to ts ,bb assertion 7.25 14 5.5 10.5 ns 10a clkout to ta ,bi assertion (when driven by the memory controller) 8.5 8.5 ns table e-10. bus operation timing (continued) note: (v dd =2.6v e-24 mpc565/mpc566 reference manual motorola ac timing 10b clkout to retry assertion (when driven by the memory controller) 10 10 ns 11 clkout to ts ,bb negation 7.25 14 5.5 10.5 ns 11a clkout to ta ,bi negation (when driven by the memory controller) 211211ns 11b clkout to retry negation (when driven by the memory controller) 211211ns 12 clkout to ts ,bb high z 6.25 20 4.5 16 ns 12a clkout to ta ,bi high z (when driven by the memory controller) 15 15 ns 13 clkout to tea assertion 8.5 8.5 ns 14 clkout to tea high z 15 15 ns 15 input valid to clkout (setup time) ta tea bi 3 12 8.5 ns 15a input valid to clkout (setup time) kr cr retry 10 7.25 ns 15b input valid to clkout (setup time) bb bg br 2 86.5ns 16 clkout to signal invalid (hold time) ta tea bi bb bg br 2, 3 22ns table e-10. bus operation timing (continued) note: (v dd =2.6v motorola appendix e. electrical characteristics e-25 ac timing 16a clkout to signal invalid (hold time) retry kr cr 22ns 17 signal valid to clkout rising edge (setup time) d[0:31] 4 66ns 17b signal valid to clkout rising edge (short setup time, sst = 1) d[0:31] 4 33 18 clkout rising edge to signal invalid (hold time) d[0:31] 4 22ns 19 clkout rising edge to cs asserted -gpcm- acs = 00 7.25 15 6.5 11.5 ns 19a clkout falling edge to cs asserted -gpcm- acs = 10, trlx = 0 or 1 86ns 19b clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0 or 1 6.25 14 5.5 10.5 ns 19c clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf = 1 6.25 17 6.69 12.69 ns 20 clkout rising edge to cs negated -gpcm- read access or write access when csnt = 0 or write access when csnt = 1 and acs = 00 1817ns 21 a[0:31] to cs asserted -gpcm- acs = 10, trlx = 0 0.75 1 ns 21a a[0:31] to cs asserted -gpcm- acs = 11, trlx = 0 86ns 22 clkout rising edge to oe ,we [0:3]/be [0:3] asserted 1816ns table e-10. bus operation timing (continued) note: (v dd =2.6v e-26 mpc565/mpc566 reference manual motorola ac timing 23 clkout rising edge to oe n egated 1816ns 24 a[0:31] to cs asserted -gpcm- acs = 10, trlx = 1 23 16.42 ns 24a a[0:31] to cs asserted -gpcm- acs = 11, trlx = 1 28 20 ns 25 clkout rising edge to we [0:3]/be [0:3] negated -gpcm-write access csnt = ?0? 7.5 6 ns 25a clkout falling edge to we [0:3]/be [0:3] negated -gpcm-write access trlx = ?0? or ?1?, csnt = ?1, ebdf = 0?. 6.25 14 5.5 10.5 ns 25b clkout falling edge to cs negated -gpcm-write access trlx = ?0? or ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 6.25 14 5.5 10.5 ns 25c clkout falling edge to we [0:3]/be [0:3] negated -gpcm-write access trlx = ?0?, csnt = ?1, ebdf = 1?. 6.25 17 5.5 12.69 ns 25d clkout falling edge to cs negated -gpcm-write access trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 6.25 17 6.25 17 ns 26 we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, csnt = ?0? 32.25ns 26a we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, trlx = ?0?, csnt = ?1?, ebdf = 0 85.71ns table e-10. bus operation timing (continued) note: (v dd =2.6v motorola appendix e. electrical characteristics e-27 ac timing 26b cs negated to d[0:31], high z -gpcm- write access, acs = ?00?, trlx = ?0? & csnt = ?0? 32.25ns 26c cs negated to d[0:31], high z -gpcm- write access, trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 85.71ns 26d we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, ebdf = 0 28 20 ns 26e cs negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 0 28 20 ns 26f we [0:3]/be [0:3] negated to d[0:31] highz -gpcm- write access, trlx = ?0?, csnt = ?1?, ebdf = 1 53.75ns 26g cs negated to d[0:31] high z -gpcm- write access, trlx = ?0?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 53.75ns 26h we [0:3]/be [0:3] negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, ebdf = 1 24 17.25 ns 26i cs negated to d[0:31] high z -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = ?10? or acs=?11?, ebdf = 1 24 17.25 ns 27 cs ,we [0:3]/be [0:3] negated to a[0:31] invalid -gpcm- write access 5 0.75 1 ns table e-10. bus operation timing (continued) note: (v dd =2.6v e-28 mpc565/mpc566 reference manual motorola ac timing 27a we [0:3]/be [0:3] negated to a[0:31] invalid -gpcm- write access, trlx=?0?, csnt = ?1?. cs negated to a[0:31] invalid -gpcm- write access, trlx=?0?, csnt = ?1?, acs = 10,acs = =?11?, ebdf = 0 85.71ns 27b we [0:3]/be [0:3] negated to a[0:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?. cs negated to a[0:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 0 28 20 ns 27c we [0:3]/be [0:3]negated to a[0:31] invalid -gpcm- write access, trlx=?0?, csnt = '1?. cs negated to a[0:31] invalid -gpcm- write access, trlx=?0?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 1 43ns 27d we [0:3]/be [0:3] negated to a[0:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?. cs negated to a[0:31] invalid -gpcm- write access, trlx=?1?, csnt = '1?, acs = 10,acs = =?11?, ebdf = 1 24 17.25 ns 28 a[0:31], tsiz[0:1], rd/wr , burst ,validto clkout rising edge. (slave mode setup time) 96ns 28a slave mode d[0:31] valid to clkout rising edge 55ns table e-10. bus operation timing (continued) note: (v dd =2.6v motorola appendix e. electrical characteristics e-29 ac timing note the d[0:31] input timings 17 and 18 refer to the rising edge of the clkout in which the ta input signal is asserted. figure e-10. clkout pin timing 29 ts valid to clkout rising edge (setup time) 75ns 30 clkout rising edge to ts valid (hold time). 55ns 1 56-mhz operation is available as an option. some parts (without the 56-mhz option) will operate at a maximum frequency of 40 mhz. 2 the timing for br output is relevant when the mpc565/mpc566 is selected to work with external bus arbiter. the timing for bg output is relevant when the mpc565/mpc566 is selected to work with internal bus arbiter. 3 the setup times required for ta ,tea ,andbi are relevant only when they are supplied by the external device (and not the memory controller). 4 the maximum value of spec 8 for data[0:31] pins must be extended by 1.1 ns if the pins have been precharged to greater than v ddl . this is the case if an external slave device on the bus is running at the max. value of vdatapc. this is currently specified at 3.45 v. the 1.1 ns addition to spec 8 reflectls the expected timing degradation for 3.45 v. 5 the timing 27 refers to cs when acs = ?00? and to we [0:3]/be [0:3] when csnt = ?0?. table e-10. bus operation timing (continued) note: (v dd =2.6v e-30 mpc565/mpc566 reference manual motorola ac timing figure e-11. synchronous output signals timing 8 8a 7b 9 9 7a 7 8b clkout output signals output signals output signals motorola appendix e. electrical characteristics e-31 ac timing figure e-12. predischarge timing 8e clkout data 8d 0v <3.1v 5.25v 2.6v sp8e: clkout to predischarge drivers enabled sp8d: clkout to data below 3.1v ts e-32 mpc565/mpc566 reference manual motorola ac timing figure e-13. synchronous active pull-up and open drain outputs signals timing 10 12 11 10a 12a 11a 13 14 clkout ts ,bb ta ,bi tea motorola appendix e. electrical characteristics e-33 ac timing figure e-14. synchronous input signals timing 15 16 15a 16a 15b 16 clkout ta ,bi tea ,kr , retry ,cr bb ,bg ,br e-34 mpc565/mpc566 reference manual motorola ac timing figure e-15. input data timing in normal case 15a 16 17 18 d[0:31] ta clkout motorola appendix e. electrical characteristics e-35 ac timing figure e-16. external bus read timing (gpcm controlled ? acs = ?00?) 8 10 19 22 11 20 23 17 18 25 clkout ts a[0:31] csx oe we [0:3]/be [0:3] d[0:31] e-36 mpc565/mpc566 reference manual motorola ac timing figure e-17. external bus read timing (gpcm controlled ? trlx = ?0? acs = ?10?) 8 10 19a 22 11 20 23 17 18 21 clkout ts a[0:31] csx oe d[0:31] motorola appendix e. electrical characteristics e-37 ac timing figure e-18. external bus read timing (gpcm controlled ? trlx = ?0? acs = ?11?) 19c 19b 8 10 22 11 20 23 17 18 21a clkout ts a[0:31] csx oe d[0:31] e-38 mpc565/mpc566 reference manual motorola ac timing figure e-19. external bus read timing (gpcm controlled ? trlx = ?1?, acs = ?10?, acs = ?11?) 8 19a 11 20 23 17 18 24 24a 19b 19c 10 clkout ts a[0:31] csx oe d[0:31] motorola appendix e. electrical characteristics e-39 ac timing figure e-20. address show cycle bus timing 11 10 8 9 clkout ts a[0:31] e-40 mpc565/mpc566 reference manual motorola ac timing figure e-21. address and data show cycle bus timing 8 10 11 9 8 27 d[0:31] clkout ts a[0:31] csx we [0:3]/be [0:3] motorola appendix e. electrical characteristics e-41 ac timing figure e-22. external bus write timing (gpcm controlled ? trlx = ?0?, csnt = ?0?) 8 10 19 22 11 20 25 9 23 8 26 26b 27 d[0:31] oe we [0:3]/be [0:3] csx a[0:31] ts clkout e-42 mpc565/mpc566 reference manual motorola ac timing figure e-23. external bus write timing (gpcm controlled ? trlx = ?0?, csnt = ?1?) 8 10 19 22 11 20 9 23 8 26a 25a 25b 26c 27a 27c 25d 26g 26g 25c d[0:31] oe we [0:3]/be [0:3] csx a[0:31] clkout ts motorola appendix e. electrical characteristics e-43 ac timing figure e-24. external bus write timing (gpcm controlled ? trlx = ?1?, csnt = ?1?) 8 10 19 22 11 20 9 23 8 26d 25a 25b 26e 26b 27b 27d 25d 26i 26h 25c clkout ts a[0:31] csx we [0:3]/be [0:3] oe d[0:31] e-44 mpc565/mpc566 reference manual motorola ac timing figure e-25. external master read from internal registers timing 29 28 30 10a 12a 11a 13 14 9 8 10b 11b clkout ts a[0:31], tsiz[0:1], rd/wr , burst, ta , bi tea d[0:31] retry bdip motorola appendix e. electrical characteristics e-45 ac timing figure e-26. external master write to internal registers timing 29 28 30 10a 12a 11a 13 14 28a 18 10b 11b clkout ts a[0:31], tsiz[0:1], rd/wr , burst ta , bi tea , d[0:31] retry e-46 mpc565/mpc566 reference manual motorola ac timing figure e-27. interrupt detection timing for external edge sensitive lines e.10.1 debug port timing table e-11. interrupt timing note: (t a =t l to t h ) characteristic 40 mhz 56 mhz unit min max min max 33 irq x pulse width low tc tc ns 34 irq xpulsewidthhigh tc tc ns 35 irq x edge to edge time 100 100 ns table e-12. debug port timing note: (t a =t l to t h ) characteristic 40 mhz 56 mhz unit min max min max 36 dsck cycle time 50 ? 37.4 ? ns 37 dsck clock pulse width 25 ? 18.7 ? ns 38 dsck rise and fall times 0 7 0 7 ns 35 33 34 35 clkout irqx motorola appendix e. electrical characteristics e-47 ac timing figure e-28. debug port clock input timing 39 dsdi input data setup time 15 ? 15 ? ns 40 dsdi data hold time 5 ? 5 ? ns 41dscklowtodsdodatavalid 018018ns 42 dsck low to dsdo invalid 0 ? 0 ? ns table e-12. debug port timing (continued) note: (t a =t l to t h ) characteristic 40 mhz 56 mhz unit min max min max 36 36 37 37 38 38 dsck e-48 mpc565/mpc566 reference manual motorola ac timing figure e-29. debug port timings 40 42 41 39 dsck dsdi dsdo motorola appendix e. electrical characteristics e-49 pin electrical characteristics e.11 pin electrical characteristics e.11.1 ac electrical characteristics the ac electrical characteristics (56 mhz) are described in the following tables and figures figure e-30. auxiliary port data input timing diagram table e-13. readi ac electrical characteristics note: (v dd =2.6v e-50 mpc565/mpc566 reference manual motorola pin electrical characteristics figure e-31. auxiliary port data output timing diagram mdo and mseo data is held valid until the next mcko low transition. when rsti is asserted, evti is used to enable or disable the auxiliary port. because mcko probably is not active at this point, the timing must be based on the system clock. since the system clock is not realized on the connector, its value must be known by the tool. figure e-32. enable auxiliary from rsti figure e-33. disable auxiliary from rsti mcko output data valid mdo, mseo 4 11 rsti evti 13 14 rsti evti 13 14 motorola appendix e. electrical characteristics e-51 reset timing e.12 reset timing table e-14. reset timing note: (v dd =2.6v e-52 mpc565/mpc566 reference manual motorola reset timing figure e-34. reset timing ? configuration from data bus 46 48 49 45 47 49a hreset rstconf d[0:31] (in) motorola appendix e. electrical characteristics e-53 reset timing figure e-35. reset timing ? data bus weak drive during configuration 50 51 52 43 55a clkout hreset rstconf d[0:31] (out) (weak) e-54 mpc565/mpc566 reference manual motorola reset timing figure e-36. reset timing ? debug port configuration 53 44 54 54 53 55 dsck, dsdi sreset clkout motorola appendix e. electrical characteristics e-55 ieee 1149.1 electrical characteristics e.13 ieee 1149.1 electrical characteristics figure e-37. jtag test clock input timing table e-15. jtag timing note: (t a =t l to t h ) characteristic expression 10 mhz unit min max 56 tck cycle time 1 (jtag clock) 1 jtagtiming(tck)isonlytestedat10mhz. 100 ? ns 57 tck clock pulse width measured at v dd /2 50 ? ns 58 tck rise and fall times 0 10 ns 59 tms, tdi data setup time 5 ns 60 tms, tdi data hold time 25 ns 61 tck low to tdo data valid 20 ns 62 tck low to tdo data invalid 0 ns 63 tck low to tdo high impedance 20 ns 66 tck falling edge to output valid 50 ns 67 tck falling edge to output valid out of high impedance 50 ns 68 tck falling edge to output high impedance 50 ns 69 boundary scan input valid to tck rising edge 50 ns 70 tckrisingedgetoboundaryscaninputinvalid 50 ns 56 57 57 58 tck e-56 mpc565/mpc566 reference manual motorola ieee 1149.1 electrical characteristics figure e-38. jtag test access port timing diagram 60 62 59 61 63 tck tms, tdi tdo motorola appendix e. electrical characteristics e-57 ieee 1149.1 electrical characteristics figure e-39. boundary scan (jtag) timing diagram 66 67 68 69 70 output signals tck output signals output signals e-58 mpc565/mpc566 reference manual motorola qadc64e electrical characteristics e.14 qadc64e electrical characteristics table e-16. qadc64e conversion characteristics (v dd =2.6v ? ? ? ? ? motorola appendix e. electrical characteristics e-59 qadc64e electrical characteristics 8 input signals with large slew rates or high frequency noise components cannot be converted accurately. these signals may affect the conversion accuracy of other channels. 9 accuracy tested and guaranteed at v arh ?v rl =1.0vto0.75xv dda v. see specification 52 in table e-4 on page e-7. 10 this parameter is periodically sampled rather than 100% tested. 11 absolute error includes 1/2 count (~2.5 mv) of inherent quantization error and circuit (differential, integral, and offset) error. specification assumes that adequate low-pass filtering is present on analog input pins ? capacitive filter with 0.01 ? = <= >= e-60 mpc565/mpc566 reference manual motorola qsmcm electrical characteristics e.15 qsmcm electrical characteristics table e-17. qspi timing note: (t a =t l to t h, 50 pf load on all qspi pins unless otherwise noted) num function symbol min max unit 108 operating frequency 1 master slave f op ? ? f sys /4 f sys /4 hz hz 109 cycle time master slave t qcyc 4*tc 4*tc 510 * tc 2 ? ns ns 110 enable lead time master slave t lead 2*tc 2*tc 128 * tc ? ns ns 111 enable lag time master slave t lag ? 2*tc sck/2 ? ns ns 112 clock (sck) high or low time master slave 3 t sw 2*tc? 60 2*tc? n 255 * tc ? ns ns 113 sequential transfer delay master slave (does not require deselect) t td 17*tc 13*tc 8192 * tc - ns ns 114 data setup time (inputs) master slave t su 30 20 - - ns ns 115 data hold time (inputs) master slave t hi 0 20 - - ns ns 116 slave access time t a ?tcns 117 slave miso disable time t dis ?2*tcns 118 data valid (after sck edge) master slave t v ? ? 50 50 ns ns 119 data hold time (outputs) master slave t ho 0 0 ? ? ns ns 120 sck, mosi, miso, txd, rxd rise time input ? output ? up to 50 pf, slrc bit of pdmcr = ?0? (slow) up to 200 pf, slrc bit of pdmcr = ?1? (fast) t ri t ro ? ? ? 1 200 21 motorola appendix e. electrical characteristics e-61 qsmcm electrical characteristics figure e-40. qspi timing ? master, cpha = 0 121 sck, mosi, miso, txd, rxd fall time input ? output ? up to 50 pf, slrc bit of pdmcr = ?0? (slow) up to 200 pf, slrc bit of pdmcr = ?1? (fast) t ri t fo ? ? ? 1 200 21 e-62 mpc565/mpc566 reference manual motorola qsmcm electrical characteristics figure e-41. qspi timing ? master, cpha = 1 figure e-42. qspi timing ? slave, cpha = 0 msb msb msb out data lsb out port data port data data lsb in msb in 111 110 113 120 121 109 112 109 115 112 120 121 114 119 118 121 120 pcs[3:0] output miso input mosi output sck cpol=0 output sck cpol=1 output data lsbout pd msbout msb in msb out msb in data lsb in ss input sck cpol=0 input sck cpol=1 input miso output mosi input 111 110 121 120 113 112 109 111 120 121 116 119 118 119 117 114 115 121 motorola appendix e. electrical characteristics e-63 gpio electrical characteristics figure e-43. qspi timing ? slave, cpha = 1 e.16 gpio electrical characteristics table e-18. gpio timing note: (t a =t l to t h ) gpio applies to all pins used as gpio: sgpioa[8:31], sqpiod[0:31], sgpioc[0:7], qgpio[0:6], qgpo[1:2], mpio[0:15], a_pqa[0:7], b_pqa[0:7], a_pqb[0:7], b_pqb[0:7] num rating symbol min max unit 122 rise time input output 1 (slr[0]ofpdmcr=0), 50 pf to 200 pf load output 1 (slr[0] of pdmcr = 0), 20 nf load 2 output(slr[0]ofpdmcr=1), 50 pf load 1 this parameter is tested during initial characterization and is not tested in production. 2 care should be taken to insure that the total power dissipation of the device remain below the absolute maximum rating under this condition. see table e-1 on page e-1. t ri t ro ? 90 2000 3 1 600 7500 25 e-64 mpc565/mpc566 reference manual motorola tpu3 electrical characteristics e.17 tpu3 electrical characteristics figure e-44. tpu3 timing table e-19. tpu3 timing note: (t a =t l to t h ) num rating symbol min max unit 124 slew rate of tpu output channel valid 1, 2 (slr[0] of pdmcr = 0, 50 pf to 200 pf load ) (slr[0] of pdmcr = 0, 20 nf load ) 3 (slr[0] of pdmcr = 1, 50 pf load ) 1 ac timing is shown with respect to 10% v dd &90%v dd levels. 2 timing not valid for external t2clk input. 3 care should be taken to insure that the total power dissipation of the device remain below the absolute maximum rating under this condition. see table e-1 on page e-1. t chtov 92 2000 3 650 7550 25 ns ns ns 125 clkout high to tpu output channel hold t chtoh 015ns 126 tpu input channel pulse width 4 4 t cyc is defined as the clkout period. t tipw 4?t cyc tpu i/o tim clkout tpu output tpu input 125 126 124 motorola appendix e. electrical characteristics e-65 toucan electrical characteristics e.18 toucan electrical characteristics e.19 mios timing characteristics all mios output pins are slew rate controlled. slew rate control circuitry adds 90 ns as minimum to the output timing and 650 ns as a maximum. this slew rate is from 10% v dd to 90% v dd , an additional 100 ns should be added for total 0 to v dd slew rate. table e-20. toucan timing 1 note: (t a =t l to t h ) 1 ac timing is shown is tested to the 3-v levels outlined in table e-4 on page e-7. num rating symbol min max unit 127 cntx0 (delay from iclock) t cntx0 19 ns 128 cnrx0 (set-up to iclock rise) t cnrx0 0ns 129 rise time input output ? 50 pf load, slrc bit of pdmcr = ?0? 200 pf load, slrc bit of pdmcr = ?0? 50 pf, slrc bit of pdmcr = ?1? t ri t ro 1 50 100 25 e-66 mpc565/mpc566 reference manual motorola mios timing characteristics figure e-45. mcpsm enable to vs_pclk pulse timing diagram e.19.1 mpwmsm timing characteristics table e-22. mpwmsm timing characteristics note: all delays are in system clock periods. characteristic symbol min max pwmsm output resolution t pwmr ? 1 1 minimum output resolution depends on mpwmsm and mcpsm prescaler settings. 2.0 2 2 maximum resolution is obtained by setting cpsmpsl[3:0] =0x2 and mpwmscr_cp[7:0] =0xff. pwm output pulse 3 3 excluding the case where the output is always ?0?. t pwmo 2.0 ? mpwmi input pin to mpwmscr_pin status set t pin 12 cpsm enable to output set 4 4 with mpwmsm enabled before enabling the mcpsm. please also see note 1 on the mcpsm timing information. t pwmp (mpwmperr - mpwmpulr + 1) * (256 - mpwmscr_cp) * mcpsmscr_psl + 1 mpwmsm enable to output set (min) 5 5 the exact timing from mpwmsm enable to the pin being set depends on the timing of the register write and the mcpsm vs_pclk. t pwme (mpwmperr - mpwmpulr) * (256 - mpwmscr_cp) * mcpsmscr_psl + 3 + (255 - mpwmscr_cp) * mcpsmscr_psl 6 6 when mcpsmscr_psl = 0x0000, this gives a prescale value of 16 and it is 16 which should be used in these calculations. when mcpsmscr_psl = 0x0001, the cpsm is inactive. mpwmsm enable to output set (max) 5 t pwme t pwme (min) + mcpsmscr_psl - 1 6 interrupt flag to output pin reset (period start) 7 7 the interrupt is set before the output pin is reset (signifying the start of a new period). t flgp (256 - mpwmscr_cp) * mcpsmscr_psl - 1 6 bit (pren) miob vs_pclk t cpsmc prescaler enable note 1: fsys is the internal system clock for the imb3 bus. note 2: the numbers associated with the fsys ticks refer to the imb3 internal state. note 3: vs_pclk is the mios prescaler clock which is distributed around the mios to counter modules such as the mmcsm and mpwmsm. motorola appendix e. electrical characteristics e-67 mios timing characteristics figure e-46. mpwmsm minimum output pulse example timing diagram note f sys is the internal system clock for the imb3 bus. figure e-47. mcpsm enable to mpwmo output pin rising edge timing diagram f sys mpwmo output pin min t pwmo f sys bit (pren) miob vs_pclk t pwmp prescaler enable 341 mpwmo output pin e-68 mpc565/mpc566 reference manual motorola mios timing characteristics figure e-48. mpwmsm enable to mpwmo output pin rising edge timing diagram figure e-49. mpwmsm interrupt flag to mpwmo output pin falling edge timing diagram e.19.2 mmcsm timing characteristics table e-23. mmcsm timing characteristics note: note: all delays are in system clock periods. characteristic symbol min max mmcsm input pin period t pper 4? mmcsm pin low time t plo 2? mmcsm pin high time t phi 2? clock pin to counter bus increment. t pccb 12 load pin to new counter bus value t plcb 12 clock pin to pinc delay t pinc 12 load pin to pinl delay t pinl 12 bit t pwme mpwmscr enable 341 mpwmo output pin f sys t flgp mpsmo pin output motorola appendix e. electrical characteristics e-69 mios timing characteristics figure e-50. mmcsm minimum input pin (either load or clock) timing diagram note f sys is the internal system clock for the imb3 bus. counter bus resolution t cbr ? 1 2 2 counter bus overflow reload to interrupt flag t cbflg 1 mcpsm enable to counter bus increment. t mcmp (256 - mmcsmscr_cp) * mcpsmscr_psl + 2 mmcsm enable to counter bus increment (min) 3 t mcme 4 + mcpsmscr_psl* (255 - mmcsmscr_cp) 3 mmcsm enable to counter bus increment (max) 3 t mcme 4 + mcpsmscr_psl * (255 - mmcsmscr_cp) + (mcpsmscr_psl - 1) 3 1 minimum output resolution depends on mmcsm and mcpsm prescaler settings. 2 maximum resolution is obtained by setting cpsmpsl[3:0] =0x2 and mmcsmscr_cp[7:0] =0xff. 3 the exact timing from mmcsm enable to the pin being set depends on the timing of the mmcsmscr register write and the mcpsm vs_pclk. the mmcsm enable is taken to mean the mmcsmscr_cls[1:0] being writtento2?b11. table e-23. mmcsm timing characteristics (continued) note: note: all delays are in system clock periods. characteristic symbol min max f sys mmcsm pin t phi min t plo min t pper min e-70 mpc565/mpc566 reference manual motorola mios timing characteristics figure e-51. mmcsm clock pin to counter bus increment timing diagram figure e-52. mmcsm load pin to counter bus reload timing diagram figure e-53. mmcsm counter bus reload to interrupt flag setting timing diagram f sys mmcsm clock pin t pccb counter bus[15:0] a a+1 f sys mmcsm load pin t plcb counter bus[15:0] a b f sys mmcsm interrupt flag t cbflg counter bus[15:0] ffff 5afe fffe a mmcsmml[15:0] 5afe a motorola appendix e. electrical characteristics e-71 mios timing characteristics figure e-54. mmcsm prescaler clock select to counter bus increment timing diagram e.19.3 mdasm timing characteristics table e-24. mdasm timing characteristics note: note: all delays are in system clock periods. characteristics symbol min max input modes: (ipwm, ipm, ic, dis) mdasm input pin period t pper 4? mdasm pin low time t plo 2? mdasm pin high time t phi 2? input capture resolution t capr ?2 input pin to counter bus capture delay t pcap 13 1 1 if the counter bus capture occurs when the counter bus is changing then the capture is delayed one cycle. in situations where the counter bus is stable when the input capture occurs the t pcap has a maximum delay of two cycles (the one-cycle uncertainty is due to the synchronizer). input pin to interrupt flag delay t pflg 23 input pin to pin delay t pin 12 counter bus resolution t cbr ?2 2 2 maximum resolution is obtained by setting cpsmpsl[3:0] =0x2 and mdasmscr_cp[7:0] =0xff. output modes: (oc, opwm) output pulse width 3 3 maximum output resolution and pulse width depends on counter (e.g., mmcsm) and mcpsm prescaler settings. t pulw 2? compare resolution 3 t comr ?2 2 counter bus to pin change t cbp 3 counter bus to interrupt flag set. t cbflg 3 f sys mmcsmscr_cls[1:0] t mcme counter bus[15:0] a a+1 34 2 11 00 11 e-72 mpc565/mpc566 reference manual motorola mios timing characteristics figure e-55. mdasm minimum input pin timing diagra note f sys is the internal system clock for the imb3 bus. figure e-56. mdasm input pin to counter bus capture timing diagram figure e-57. mdasm input pin to mdasm interrupt flag timing diagram f sys mdai input pin t phi min t plo min t pper min f sys mdai input pin t pcap counter bus[15:0] a mdasmar[15:0] xxxx a f sys mdai input pin t pflg mdasm interrupt flag motorola appendix e. electrical characteristics e-73 mios timing characteristics figure e-58. mdasm minimum output pulse width timing diagram figure e-59. counter bus to mdasm output pin change timing diagram figure e-60. counter bus to mdasm interrupt flag setting timing diagram f sys mdao output pin t pulw min f sys mdao output pin t cbp counter bus[15:0] 5afd 5afe 5afc mdasmar[15:0] 5afe f sys mdasm interrupt flag t cbflg counter bus[15:0] 5afd 5afe 5afc mdasmar[15:0] 5afe e-74 mpc565/mpc566 reference manual motorola mpiosm timing characteristics e.20 mpiosm timing characteristics figure e-61. mpiosm input pin to mpiosm_dr (data register) timing diagram note f sys is the internal system clock for the imb3 bus. table e-25. mpiosm timing characteristics note: note: all delays are in system clock periods. characteristic symbol min max input mode mpiosm input pin period t pper ? 1 1 the minimum input pin period, pin low and pin high times depend on the rate at which the mpiosm_dr register is polled. ? mpiosm pin low time t plo ? 1 ? mpiosm pin high time t phi ? 1 ? input pin to mpiosm_dr delay t pdr 01 output mode output pulse width 2 2 the minimum output pulse width depends on how quickly the cpu updates the value inside the miopsm_dr register. t pulw ? 2 ? f sys mpiosm input pins t pdr mpiosm_dr ffa5 005a ffa5 005a index motorola index index-1 a a(0 31),, 9-4 accesses clock requirements, 13-51 ackerr, 16-35 acknowledge error (ackerr), 16-35 address -mark wakeup, 14-65 address space, 13-13 address type (at0-at3),, 9-39 ale, 22-54 alee, 22-56 alignment exception, 3-53 alu?bfu, 3-6 an, 13-8 analog front-end multiplexer, 13-36 input considerations, 13-73 pins, 13-72 power pins, 13-67 reference pins, 13-71 section contents, 13-4 submodule block diagram, 13-35 supply filtering and grounding, 13-69 pins, 13-67 to digital converter operation, 13-35 arbitration,, 9-32 at (0 3),, 9-4 atomic update primitives,, 3-47 atomic,, 9-32 b bar, 3-64 base id mask bits, 16-34 baud clock, 14-58 bb,, 9-7 bdip,, 9-5 be bit, 3-23 beginning of queue 2 (bq2), 13-22 bg,, 9-7 bi,, 9-7 binary divider, 13-49 -weighted capacitors, 13-36 bit stuff error (stufferr), 16-35 biterr, 16-35 bits, 14-20 bits per transfer enable (bitse), 14-27 field (bits), 14-20 bitse, 14-27, 14-43 bit-time, 14-57 biu, 13-4, 13-51 biusm biutest ? biusm test configuration register, 17-14, 17-15 selecting the time base bus, 17-14, 17-15 biutest ? biusm test configuration register, 17-14, 17-15 bkpt (tpu asserted), 18-16 blc, 18-15 boffint, 16-36 boundary conditions, 13-40 bpu, 3-5 bq2, 13-22, 13-40 br,, 9-7 branch prediction, 3-5 processing unit, 3-5 trace enable, 3-23 branch latch control (blc), 18-15 branch processing unit, 3-5 break frame, 14-57 breakpoint asserted flag (bkpt), 18-16 flag (pcbk), 18-16 breakpoint counter a value and control register, 22-52 breakpoint counter b value and control register, 22-53 brknomsk, 22-51 burst indicator (burst),, 9-38 burst inhibit (bi),, 9-42 burst read cycle (illustration),, 9-20 index-2 mpc565/mpc566 reference manual motorola burst transfer,, 9-17 burst write cycle (illustration),, 9-25 burst,, 9-4 bus monitor, 6-20 off interrupt (boffint), 16-36 bus busy (bb),, 9-34 bus exception control cycles,, 9-47 bus grant (bg),, 9-33 bus interface bus control signals,, 9-2 bus operation address transfer phase related signals,, 9-37 arbitration phase,, 9-32 basic transfer protocol,, 9-8 burst mechanism,, 9-18 burst transfer,, 9-17 bus exception control cycles,, 9-47 single beat transfer single beat read flow,, 9-9 single beat write flow,, 9-9, 9-11 single beat transfer,, 9-8 storage reservation,, 9-44 termination signals,, 9-42 bus operations,, 9-8 bus transfer signals,, 9-1 features,, 9-1 signal descriptions,, 9-4 bus interface unit (biu), 13-4 components, 13-51 bus request (br),, 9-33 bus signals (illustration),, 9-3 busy, 16-5, 16-17 byp, 13-31 bytes field, 3-20 c c bit, 3-16 ca bit, 3-20 cache control instructions,, 3-47 can2.0b system, 16-3 canctrl0, 16-29 canctrl1, 16-30 canctrl2, 16-32 canicr, 16-28 carry, 3-20 ccl, 18-15 ccw, 13-4, 13-27 c f , 13-75 cfsr, 18-18 cgbmsk, 22-50 ch, 18-17, 18-20, 18-21, 18-22 chan, 13-31 channel, 18-19 channel assignments (multiplexed), 13-31 conditions latch (ccl), 18-15 interrupt enable /disable field (ch), 18-17 request level (cirl), 18-17 status (ch), 18-22 number (chan), 13-31 orthogonality, 18-4 priority registers, 18-21 register breakpoint flag (chbk), 18-16 charge sharing, 13-76 chbk, 18-16 chbmsk, 22-50 checkstop enable, 3-51 chstp bit, 22-54 chstpe, 22-56 chstpe bit, 3-51 cie1, 13-19 cie2, 13-21 cier, 18-17, 18-21 cirl, 18-17 cisr, 18-9, 18-21 class, instruction,, 3-43 clkout to ta, bi assertion (when driven by the memory controller), g-23, g-24 clkout,, 9-8 clks, 18-15 clock block diagram, 13-49 frequency, 13-49 generation, 13-48 phase (cpha), 14-20 polarity (cpol), 14-20 requirements, 13-51 cmpa?cmpd, 22-45 cmpe?cmpf, 22-46 cmpg?cmph, 22-47 cnrx/tx pins, 16-2 cntc, 22-53 cntv, 22-53 code, 16-4 coherency, 13-46, 13-52, 18-5 comm, d-18 command ram, 14-26 command word pointer (cwp), 13-27 comparator, 13-37 comparator a?d value registers, 22-45 comparator e?f value registers, 22-46 motorola index index-3 comparator g?h value registers, 22-47 compare instructions, 3-19 compare size, 22-50 compare type, 22-47, 22-49 completed queue pointer (cptqp), 14-25 condition register, 3-17, 3-19 cont, 14-27 contention,, 9-38 continue (cont), 14-27 continuous transfer mode, 14-18 control registers 0 (qacr0), 13-9 1 (qacr1), 13-9 2 (qacr2), 13-9 qadc64e control register 1 (qacr1), 13-19 qadc64e control register 2 (qacr2), 13-21 controlling termination of a bus cycle for a bus error,, 9-47 conversion command word table (ccw), 13-4, 13-27, 13-38 cycle times, 13-35 stages, 13-29 count register, 3-20 counta, 22-52 countb, 22-53 cpha, 14-20, 14-39 cpol, 14-20, 14-39 cpr, 18-21 cptqp, 14-25, 14-28 cpu wait states, 13-51 cr, 3-5, 3-17, 3-20 and compare instructions, 3-19 cr,, 9-5 cr0 field, 3-18 cr1 field, 3-18 crcerr, 16-35 crwe, 22-50 crwf, 22-50 csg, 22-50 csh, 22-50 cta, 22-47 ctb, 22-47 ctc, 22-47 ctd, 22-47 cte, 22-49 ctf, 22-49 ctg, 22-49 cth, 22-49 ctr, 3-5 cwp, 13-27 cyclic redundancy check error (crcerr), 16-35 d d(0 31),, 9-6 dac, 13-4 dae/source instruction service register, 3-24 dar, 3-24, 3-52, 3-63, 3-64 dar,, 3-52, 3-63 data frame, 14-57 data address register, 3-24 data storage interrupt,, 3-52 dcnr, 18-22 ddrqs,14-12,14-38,14-42 debug enable register, 22-55 dec, 3-25 dece, 22-54 decee, 22-56 decrementer register, 3-25 decrementer exception, 3-57 delay after transfer (dt), 14-27, 14-40 before sck (dsckl), 14-22 der, 22-55 development port trap enable selection, 22-48 digital control section contents, 13-4, ??-13-34, 13-38-?? input/output port (pqa), 13-66 to analog converter (dac), 13-4, 13-36 dio, d-38 disable tpu2 pins field (dtpu), 18-24 disabled mode, 13-42 discrete input/output (dio), d-38 div2, 18-23 div8 clock, 18-8 divide by two control field (div2), 18-23 diw0en, 22-48 diw1en, 22-48 diw2en, 22-48 diw3en, 22-48 dlw0en, 22-52 dlw1en, 22-52 double -buffered, 14-59, 14-63 dpi, 22-55 dptram, 19-6 dsck, 14-27 dsckl, 14-22 dscr, 18-14 dsisr, 3-24, 3-52, 3-54, 3-63, 3-64 dssr, 18-16 index-4 mpc565/mpc566 reference manual motorola dt, 14-27 dtl, 14-22 dtpu, 18-24 e ea, 3-37 ebrk, 22-55 ecr, 22-53 ee bit, 3-23, 3-28 effective address, 3-37 eid, 3-28 eie, 3-28 eieio,, 3-48 ele bit, 3-23 empty, 16-5 emu, 18-5, 18-13 emulation control (emu), 18-13 support, 18-5 encoded one of three channel priority levels (ch), 18-21 time function for each channel (channel), 18-19 type of host service (ch), 18-20 ending queue pointer (endqp), 14-23 end-of- frame (eof), 16-18 end-of-queue condition, 13-29 endqp, 14-23, 14-28 entry table bank select field (etbank), 18-23 eof, 16-18 eoq, 13-40 ep bit, 3-23 errint, 16-36 error conditions, 14-64 counters, 16-10 interrupt (errint), 16-36 resulting from leakage, 13-75 estat, 16-34 etbank, 18-23 etrig,13-67,13-71 event timing, 18-4 exception cause register, 22-53 exception prefix, 3-23 exceptions, 3-37 alignment, 3-53 classes, 3-38 decrementer, 3-57 external interrupt, 3-52 little endian mode, 3-23 ordered, 3-38 precise, 3-39 program, 3-55 system call, 3-58 unordered, 3-38 vector table, 3-39 execution units, 3-4 extended message format, 16-1 frames, 16-4 external interrupt disable, 3-28 enable, 3-28 leakage, 13-76 trigger continuous-scan mode, 13-47 trigger pins, 13-67 trigger single-scan mode, 13-43, 13-44 external interrupt, 3-52 enable, 3-23, 3-28 exti, 22-54 extie, 22-56 f fast quadrature decode tpu function (fqd), d-29 fault confinement state (fcs), 16-10, 16-35 fcs, 16-10, 16-35 fe,14-55,14-64 fe bits, 3-23, 3-24 fe flag, 3-16 features bus interface,, 9-1 fetch serialized, 22-1 fex bit, 3-15 fg bit, 3-16 fi bit, 3-16 final sample time, 13-35 fl bit, 3-16 floating-point available, 3-23 condition code, 3-16 enabled exception summary, 3-15 equal or zero, 3-16 exception mode, 3-23, 3-24 exception summary, 3-15 fraction inexact, 3-16 fraction rounded, 3-16 greater than or positive, 3-16 inexact exception, 3-15 enable, 3-16 invalid operation exception enable, 3-16 for *0, 3-16 for /, 3-15 for -, 3-15 for 0/0, 3-15 motorola index index-5 for invalid compare, 3-16 for invalid integer convert, 3-16 for invalid square root, 3-16 for snan, 3-15 for software request, 3-16 summary, 3-15 less than or negative, 3-16 overflow exception, 3-15 enable, 3-16 registers, 3-13 result class descriptor, 3-16 result flags, 3-16 rounding control, 3-17 status and control register, 3-14 underflow exception, 3-15 unit, 3-5 unordered or nan, 3-16 zero divide exception, 3-15 enable, 3-16 formerr, 16-35 fp bit, 3-23 fpcc bit, 3-16 fprf field, 3-16 fprs, 3-13 fpsck, 18-23 fpscr, 3-14 fpu, 3-5 fpuve, 22-54 fpuvee, 22-56 f qclk ,13-49 fqd, d-29 fqm, d-11 fr, 3-16 frame, 14-57 size, 14-64 frames overload, 16-18 remote, 16-17 framing error (fe) flag, 14-55, 14-64 freez ack, 16-19 freeze assertion response (frz) qsm, 14-7 tpu, 18-15 freeze enable (frz), 13-10 mode, 13-11 freeze (internal signal), 13-12, 13-30 frequency measurement (fqm), d-11 parameters, d-13 frz, 13-10, 16-13, 18-15 frzack, 16-13 fu bit, 3-16 full, 16-5 function library for tpu, 18-5 fx bit, 3-15 g general sprs, 3-27 general-purpose registers (gprs), 3-13 global registers, 13-9 h hall effect decode (halld), d-20 halld, d-20 halt, 14-24, 16-13 halt acknowledge flag (halta), 14-25 qspi (halt), 14-24 halta, 14-25 halta and modf interrupt enable (hmie), 14-46 halta/modf interrupt enable (hmie) bit, 14-24 hang on t4 (hot4), 18-15 hmie, 14-24 hot4, 18-15 hsqr, 18-19 hssr, 18-20 i ibrk, 22-55 i-bus watchpoint programming, 22-48 i-bus support control register, 22-47 ictrl, 22-47 id extended (ide) field, 16-6 high field, 16-6 low field, 16-6 ide, 16-6 identifier (id), 16-1 bit field, 16-6 idle, 14-55, 14-64, 16-35 idle can status (idle), 16-35 frame, 14-57 -line detect type (ilt), 14-52 detected (idle), 14-55, 14-64 detection process, 14-64 interrupt enable (ilie), 14-53, 14-65 type (ilt) bit, 14-64 iflag, 16-37 ignore first match, 22-48 iifm, 22-48 index-6 mpc565/mpc566 reference manual motorola ilie,14-53,14-65 illegal and reserved instructions,, 3-43 ilsci, 14-11 ilt, 14-52, 14-64 imask, 16-37 imb, 13-48 implementation dependent software emulation interrupt,, 3-61 implementation specific data tlb error interrupt,, 3-62 implementation specific debug interrupt,, 3-63 implementation specific instruction tlb error interrupt,, 3-61 imul?idiv, 3-6 information processing time (ipt), 16-9 initial sample time, 13-35 input sample time (ist), 13-31 instruction pipeline, 3-41 sequencer, 3-3 set summary, 3-31 timing, 3-40 instruction fetch show cycle control, 22-1 instruction storage interrupt,, 3-52 instructions cache control,, 3-47 storage control,, 3-49 instructions, partially executed,, 3-65 integer exception register, 3-19 integer unit, 3-5, 3-6 interchannel communication, 18-5 intermission, 16-18 interrupt register (qadcint), 13-9, 13-14 interrupt level of sci (ilsci), 14-11 interrupts toucan, 16-21 tpu, 18-6 interrupts,, 3-49 inter-transfer delay, 14-17 interval timer single-scan mode, 13-44 invalid and preferred instructions,, 3-43 ipt, 16-9 irq, 18-6 isctl, 22-1 ist, 13-31 isync,, 3-47 iu, 3-5, 3-6 iw, 22-48 k kr/retry,, 9-5 l lbrk, 22-55 lbuf, 16-31 l-bus support control register 1, 22-49 control register 2, 22-50 lctrl1, 22-49 lctrl2, 22-50 le bit, 3-24 least significant bit (lsb), 13-37 length of delay after transfer (dtl), 14-22 link register, 3-20 little endian mode, 3-24 load/store unit, 3-5, 3-6 lock /release/busy mechanism, 16-17 loop mode (loops), 14-52 loopq, 14-23 loops, 14-52 low power stop (lpstop) qsm, 14-7 lowest buffer transmitted first (lbuf), 16-31 low-power stop mode enable (stop) tpu, 18-13 lr,3-5,3-20,18-22 lsb, 13-37 lsu, 3-5, 3-6 lw0en, 22-51 lw0ia, 22-51 lw0iadc, 22-51 lw0la, 22-51 lw0ladc, 22-51 lw0ld, 22-51 lw0lddc, 22-51 lw1en, 22-51 lw1ia, 22-51 lw1iadc, 22-51 lw1la, 22-51 lw1ladc, 22-51 lw1ld, 22-51 lw1lddc, 22-51 m m, 14-52, 14-57 ma, 13-16 machine motorola index index-7 check enable, 3-23 state register, 3-22 status save/restore register 0, 3-26 status save/restore register 1, 3-27 machine check enable, 3-51 machine check exception enable, 3-51 machine status save/restore register 1, 3-27 mask examples for normal/extended messages, 16-8 registers (rx), 16-7 master /slave mode select (mstr), 14-20 master external arbitration phase,, 9-32 mce, 22-54 mcee, 22-56 mcie bit, 3-51 mcpwm, d-22 me bit, 3-23, 3-51 message buffer address map, 16-26 code for rx/tx buffers, 16-5 deactivation, 16-15 structure, 16-3 format error (formerr), 16-35 miso,14-38,14-42 mmcsmcnt mmcsm up-counter register, 17-25 mmcsmmml mmcsm modulus latch register, 17-25 mode fault flag (modf), 14-24, 14-31 select (m), 14-52 mode fault flag (modf), 14-46 modes disabled, 13-42 freeze, 13-11 reserved, 13-42 scan. see scan modes stop, 13-11 modf, 14-24, 14-31, 14-46 module configuration register (qadc64e), 13-10 module configuration register (qadcmcr), 13-9 module configuration register (qadcmcr), 13-10 modulus counter, 14-58 mosi,14-38,14-42 most significant bit (msb), 13-37 mq1, 13-20 mq2, 13-22 msb, 13-37 msr, 3-22, 3-50, 3-51, 3-53, 3-54, 3-56, 3-57, 3-58, 3-59, 3-60, 3-61, 3-62, 3-63, 3-64 mstr, 14-20 multichannel pulse-width modulation (mcpwm), d-22 parameters slave channel a non-inverted center aligned mode, d-40 slave edge-aligned mode, d-23 multimaster operation, 14-31 multiphase motor commutation (comm), d-18 parameters, d-18 multiple end-of-queue, 13-40 multiplexed analog inputs, 13-8 mux, 13-16 n negative stress, 13-76 new queue pointer value (newqp), 14-23 new input capture/transistion counter (nitc), d-16 parameters, d-16 newqp, 14-23, 14-28 nf, 14-55, 14-64 ni bit, 3-17 nitc, d-16 noise error flag (nf), 14-55 errors, 14-64 flag (nf), 14-64 non-ieee floating-point operation, 3-17 nonoptional instructions,, 3-43 non-recoverable interrupt, 3-28 not active, 16-5 not ready (notrdy), 16-23 notrdy, 16-19, 16-23 nri, 3-28 o oc, d-34 oe bit, 3-16 op0,, 9-30 op1,, 9-30 op2,, 9-30 op3,, 9-30 open drain drivers, 13-67 operand placement (effects),, 3-47 operand representation (illustration),, 9-30 operating environment architecture (book 3) branch processor,, 3-48 fixed-point processor index-8 mpc565/mpc566 reference manual motorola special purpose registers,, 3-49 fixed-point processor,, 3-49 interrupts,, 3-49 optional facilities and instructions,, 3-65 storage control instructions,, 3-49 timer facilities,, 3-65 optional instructions,, 3-43 or, 14-55 ordered exceptions, 3-38 output compare (oc), d-34 ov (overflow) bit, 3-20 overload frames, 16-18 overrun, 16-5 overrun error (or), 14-55 ox bit, 3-15 p p, 13-30 parity (pf) flag, 14-64 checking, 14-59 enable (pe), 14-52 error(pf)bit,14-55 errors, 14-64 type (pt), 14-52 type (pt) bit, 14-59 pause (p), 13-30, 13-38 pcbk, 18-16 pcs, 14-27 to sck delay (dsck), 14-27 pcs0/ss, 14-43 pcs3-pcs0/ss ,14-46 pe, 14-52 period /pulse-width accumulator (ppwa), d-32 periodic interrupt timer, 6-22 periodic/interval timer, 13-50 continuous-scan mode, 13-48 peripheral chip-selects (pcs), 14-27, 14-41 peripheral chip-select 3-0/slave select (pcs3-pcso/ss ), 14-46 pf, 14-55, 14-64 phase buffer segment 1/2 (pseg1/2) bit field, 16-32 phase-lock loop,, 9-8 pie1, 13-19 pie2, 13-21 pit, 6-22 pll,, 9-8 pointer, 14-18 port a data register (portqa), 13-15 b data register (portqb), 13-15 port size device interfaces (illustration),, 9-31 port width,, 9-2 portqa, 13-15 portqb, 13-15 portqs, 14-12 positive stress, 13-76 ppwa, d-32 pqa, 13-15, 13-66 pqb, 13-15 pqspar,14-12,14-38,14-42 pr bit, 3-8, 3-23 pre, 22-54 precise exceptions, 3-39 pree, 22-56 prescaler, 13-49 clock (psck), 18-14 clock high time (psh), 13-18 control for tcr1, 18-6 for tcr2, 18-8 divide factor field, 16-32 register (presdiv), 16-9, 16-31 presdiv (bit field), 16-32 presdiv (register), 16-9, 16-31 privilege level, 3-8, 3-23 processor version register, 3-28 program, 3-55 exception, 3-55 programmable channel service priority, 18-5 transfer length, 14-17 programmable time accumulator (pta), d-4 parameters, d-4, d-43, d-45 propagation segment time (propseg), 16-31 propseg, 16-13, 16-31 psck, 18-14 pseg1, 16-32 pseg2, 16-9, 16-13, 16-32 psegs1, 16-13 psh, 13-18 pt,14-52,14-59 pta, d-4 ptr,,9-5,9-39 pulse-width modulation (pwm), d-36 parameters, d-36 pvr, 3-28 pwm, d-36 q qacr0, 13-9 motorola index index-9 qacr1, 13-9, 13-19 qacr2, 13-9, 13-21 qadc64e right justified, unsigned result word table (rjurr), 13-34 qadcint, 13-9, 13-14 qadcmcr, 13-9, 13-10 qadctest, 13-9 qasr, 13-9, 13-24 qclk, 13-48 frequency, 13-49 qddr, 14-15, 14-46 qilr, 14-10 qom, d-6 qpar, 14-13 qpdr, 14-13, 14-46 qsm pin function, 14-12 qspi, 14-16 operating modes, 14-30 operation, 14-28 ram, 14-25 registers pin control registers, 14-11 port qs data direction register (ddrqs) ,14-12 data register (portqs) ,14-12 qspi control register 0 (spcr0), 14-19 control register 1 (spcr1), 14-21 control register 2 (spcr2), 14-22 control register 3 (spcr3), 14-23 status register (spsr), 14-23 sci control register 0 (sccr0), 14-51 control register 1 (sccr1), 14-51 data register (scdr), 14-55 status register (scsr), 14-53 sci, 14-46 operation, 14-56 pins, 14-56 registers, 14-50 qsm data direction register (qddr), 14-15, 14-46 qsm interrupt level register (qilr), 14-10 qsm pin assignment register (qpar), 14-13 qsm port data register (qpdr), 14-13, 14-46 qsmcmmcr bit settings, 14-10 qspi, 14-16 block diagram, 14-17 enable (spe), 14-21 finished flag (spif), 14-24 initialization operation, 14-32 loop mode (loopq), 14-23 master operation flow, 14-33 operating modes, 14-30 master mode, 14-30, 14-38 wraparound mode, 14-42 slave mode, 14-30, 14-42 operation, 14-28 peripheral chip-selects, 14-41 ram, 14-25 command ram, 14-26 receive ram, 14-26 transmit ram, 14-26 qspi enable (spe), 14-46 qspi status register (spsr), 14-46 queue, 13-38 1 completion interrupt enable (cie1), 13-19 1 operating mode (mq1), 13-20 1 pause interrupt enable (pie1), 13-19 1 single-scan enable bit (sse1), 13-20 2 completion software interrupt enable (cie2), 13-21 2 operating mode (mq2), 13-22 2 pause software interrupt enable (pie2), 13-21 2 single-scan enable bit (sse2), 13-22 pointers completed queue pointer (cptqp), 14-28 end queue pointer (endqp), 14-28 new queue pointer (newqp), 14-28 priority, 13-38 priority schemes, 13-53, 13-63 queued serial peripheral interface (qspi), 14-16 queued output match tpu function (qom), d-6 r raf, 14-54 rd/wr,, 9-4 rdrf, 14-54, 14-64 re,14-51,14-53,14-63 re bit, 3-24, 3-28 read cycle, data bus requirements,, 9-31 read/write (rd/wr),, 9-38 receive data register full (rdrf), 14-54 error status flag (rxwarn), 16-35 ram, 14-26 time sample clock (rt), 14-58, 14-63 receiver active (raf), 14-54 data register (rdrf) flag, 14-64 enable (re), 14-53, 14-63 interrupt enable (rie), 14-52 index-10 mpc565/mpc566 reference manual motorola wakeup (rwu), 14-53, 14-65 receiver enable (re), 14-51 reception of transmitted frames, 16-15 recoverable exception, 3-24, 3-28 register diagrams cmd (dlcmd2 command register), 15-39 ilr (dlcmd2 interrupt level register), 15-34 ipr (dlcmd2 interrupt pending register), 15-33 ivr (dlcmd2 interrupt vector register), 15-35 mcr (dlcmd2 module configuration register), 15-31 mdasmarar mdasm dataa register, 17-44 mdasmarbr mdasm datab register, 17-45 mdasmscr mdasm status/control register, 17-46 mmcsmcnt mmcsm up-counter register, 17-25 mmcsmmml mmcsm modulus latch register, 17-25 mmcsmscr mmcsm status/control register, 17-26 module configuration (qadcmcr), 13-10 mpiosmddr mpiosm data direction register, 17-69 mpiosmdr mpiosm data register, 17-68 mptcpr mrtcsm prescaler counter buffer register, 17-93 mptcsm mrtcsm status/control register, 17-93 mptcsmfrch mrtcsm 32-bit counter high buffer register, 17-92 mptcsmfrcl mrtcsm 32-bit counter low buffer register, 17-93 mpwmcntr mpwmsm counter register, 17-63 mpwmperr mpwmsm period register, 17-61 mpwmpulr mpwmsm pulse width register, 17-62 mpwmscr mpwmsm status/control register, 17-64 rdata (dlcmd2 receive data register), 15-37, 15-47 sctl (dlcmd2 sysmbol timing control and pre-scaler register), 15-35 stat (dlcmd2 status register), 15-44 tdata (dlcmd2 transmit data register), 15-43 registers bbcmcr bbc module configuration register, 4-33 calram_otr calram ownership trace register, 21-22 cmd (dlcmd2 command register), 15-39 cmpa?cmpd, 22-45 cmpe?cmpf, 22-46 cmpg?cmph, 22-47 conversion command word table (ccw), 13-30 counta, 22-52 countb, 22-53 cram_rbax calram region base address register, 21-20 crammcr calram module configuration register, 6-39, 7-12, 20-20, 21-17 cramovl calram overlay configuration register, 21-21 dccr0-dccr15 decompressor class configuration registers, 4-41 der, 22-55 ecr, 22-53 eibadr external interrupt relocation table base address register, 4-39 ictrl, 22-47 ilr (dlcmd2 interrupt level register), 15-34 interrupt (qadcint), 13-14 ipr (dlcmd2 interrupt pending register), 15-33 ivr (dlcmd2 interrupt vector register), 15-35 lctrl1, 22-49 lctrl2, 22-50 left justified, unsigned result format (ljurr), 13-34 mcpsm register organization, 17-18, 17-68, 17-92 mcpsmcr mcpsm status/control register, 17-18 mcr (dlcmd2 module configuration register), 15-31 mdasmar mdasm dataa register, 17-44 mdasmbr mdasm datab register, 17-45 mdasmscr mdasm status/control register, 17-46 mi_gra global region atribute register, 4-38 mi_ra 0-3 region attribute register, 4-36 mi_rba 0-3 region base address register, 4-35 mios14er0 interrupt enable register, 17-72 mios14lvl1 register, 17-13 mios14mcr module configuration register, 17-15 mios14rer1 interrupt enable register, 17-74 mios14rpr0 request pending register, 17-73 mios14rpr1 request pending register, 17-75 mios14rsr1 interrupt status register, 17-74 mios14sr0 interrupt status register, 17-72 mios14tpcr test and pin control register, 17-14, 17-15 mmcsmcnt mmcsm up-counter register, 17-25 mmcsmmml mmcsm modulus latch register, 17-25 mmcsmscr mmcsm status/control register, 17-26 module configuration (qadc64e), 13-10 mpiosmddr mpiosm data direction register, 17-69 mpiosmdr mpiosm data register, 17-68 mpwmcntr mpwmsm counter register, 17-63, 17-64 mpwmperr mpwmsm period register, 17-61 motorola index index-11 mpwmpulr mpwmsm pulse width register, 17-62 mrtcpr mrtcsm prescaler counter buffer register, 17-93 mrtcsm mrtcsm status/controlr register, 17-93 mrtcsmfrch mrtcsm 32-bit counter high buffer register, 17-92 mrtcsmfrcl mrtcsm 32-bit counter low buffer register, 17-93 pdmcr pads module configuration register, 2-6 pdmcr2 (pads module configuration register), 2-8 port a data register (portqa), 13-15 port b data register (portqb), 13-15 portqb port b data registerr, 13-16 qacr0 control register, 13-17 qadc64e control register 1 (qacr1), 13-19 qadc64e control register 2 (qacr2), 13-21 qadc64e left justified, signed result format (ljsrr), 13-34 qadc64e module configuration register, 13-10 qadc64e portqa port a data register, 13-16, 13-17 qadc64e portqb port b data register, 13-16, 13-17 qadc64e right justified, unsigned result format (rjurr), 13-34 rdata (dlcmd2 receive data register), 15-37, 15-47 sccr system clock and reset control register, 8-30 sctl (dlcmd2 sysmbol timing control and pre-scaler register), 15-35 stat (dlcmd2 status register), 15-44 status (qasr), 13-24 status (qasr0), 13-24 status (qasr1), 13-26 tdata (dlcmd2 transmit data register), 15-43 test (ramtst), 19-6 registers special purpose added registers,, 3-49 unsupported registers,, 3-49 special purpose,, 3-49 remote frames, 16-17 transmission request (rtr), 16-5, 16-6 reservation protocol for a multi-level (local) bus,, 9-45 reserved mode, 13-42 reset status register, 7-5 resistor-divider chain, 13-36 resolution time, 13-35 result word table, 13-4, 13-33, 13-38 resynchronization jump width (rjw) bit field, 16-32 retry,, 9-47 r f , 13-75 rie, 14-52 rjurr, 13-34 rjw, 16-13, 16-32 rn field, 3-17 rsr, 7-5 rsv,, 9-39 rt, 14-63 rtr, 16-5, 16-6, 16-18 rwu, 14-53, 14-65 rx14mskhi, 16-34 rx14msklo, 16-34 rx15mskhi, 16-34 rx15msklo, 16-34 rxectr, 16-38 rxgmskhi, 16-33 rxgmsklo, 16-33 rxwarn, 16-35 s s0, 14-10 samp, 16-31 sample amplifier bypass (byp), 13-31 sampling mode (samp), 16-31 sar, 13-37 sbk, 14-53, 14-60 scan modes continuous-scan modes external trigger, 13-47 periodic timer continuous-scan mode, 13-48 software initiated, 13-46 single-scan modes external trigger, 13-43, 13-44 interval timer, 13-44 software initiated, 13-43 scbr, 14-51 sccr0, 14-51 sccr1, 14-51 scdr, 14-55 sci, 14-38, 14-46 baud clock, 14-58 rate (scbr), 14-51 equation, 14-51 idle-line detection, 14-64 internal loop, 14-66 operation, 14-56 parity checking, 14-59 pins, 14-56 receiver block diagram, 14-49 operation, 14-63 index-12 mpc565/mpc566 reference manual motorola wakeup, 14-65 registers, 14-50 sccr0, 14-51 sccr1, 14-51 sci baud rates, 14-59 sci submodule, 14-15 scsr, 14-50 transmitter block diagram, 14-48 operation, 14-59 sci control register 0 (sccr0), 14-51 sci control register 1 (sccr1), 14-51 sci status register (scsr), 14-50 sck, 14-13, 14-37, 14-42 actual delay before sck (equation), 14-40 baud rate (equation), 14-39 s-clock, 16-9 scsr, 14-53 se bit, 3-23 see, 22-54 send break (sbk), 14-53, 14-60 sequencer, instruction, 3-3 serial clock baud rate (spbr), 14-20 communication interface (sci), 14-46 formats, 14-57 mode (m) bit, 14-57 shifter, 14-60 serial clock (sck), 14-13 serialization fetch, 22-1 service request breakpoint flag (srbk), 18-16 sglr, 18-22 simplified mnemonics, 3-37 single-step trace enable, 3-23 siu signals,, 9-4 siw0en, 22-48 siw1en, 22-48 siw2en, 22-48 siw3en, 22-48 slave select (ss), 14-46 slave select signal (ss), 14-42, 14-43 slw0en, 22-52 slw1en, 22-52 snooping external bus activity,, 3-47 so bit, 3-20 sof, 16-10 soft reset control field (soft_rst), 18-23 soft_rst, 18-23 softrst, 16-13 software initiated continuous-scan mode, 13-46 single-scan mode, 13-43 software trap enable selection, 22-48 spbr, 14-20 spcr0, 14-19 spcr1, 14-21 spcr2, 14-22 spcr3, 14-23 spe,14-21,14-46 special-purpose registers, general, 3-27 spi finished interrupt enable (spifie), 14-23 spif, 14-24 spifie, 14-23 sprg0?sprg3, 3-27 sprgs, 3-27 sprs general, 3-27 spsr, 14-23, 14-46 spwm, d-40 sram supervisor space only, 14-10 srbk, 18-16 srr, 16-6 srr0, 3-26, 3-50, 3-51, 3-59, 3-60, 3-61, 3-62, 3-63, 3-64 srr1, 3-27, 3-50, 3-51, 3-53, 3-54, 3-56, 3-57, 3-58, 3-59, 3-60, 3-61, 3-62, 3-63, 3-64 ss, 14-46 ss,14-42,14-43 sse1, 13-20 sse2, 13-22 standard message format, 16-1 frames, 16-4 star-point ground system, 13-70 start bit (beginning of data frame), 14-57 -of-frame (sof) symbol, 16-10 state machine, 13-49, 14-63 status register (qasr), 13-9, 13-24 stf, 18-13 stop, 13-10, 13-11, 16-20, 18-13 stop clocks to tcrs (clks), 18-15 enable (stop), 13-10 enable (stop) bit qsm, 14-7 toucan, 16-20 tpu, 18-13 flag (stf), 18-13 mode, 13-11 sci end of data frame bit, 14-57 storage control instructions,, 3-49 storage reservation,, 9-44 stress conditions, 13-76 motorola index index-13 sts,, 9-5 stufferr, 16-35 subqueue, 13-38 substitute remote request (srr), 16-6 successive approximation register (sar), 13-37 summary overflow, 3-20 supervisor /unrestricted data space (supv), 13-10 /unrestricted data space (supv) tpu, 18-14 supervisor mode and sram, 14-10 supv,13-10,13-12 susg, 22-50 sush, 22-50 synchronized pulse-width modulation (spwm), d-40 syse, 22-54 sysee, 22-56 system call exception, 3-58 system clock output,, 9-8 system reset interrupt,, 3-49 t t1, 13-54 t2, 13-54 t2cfilter, 18-24 t2cg, 18-8, 18-13 t2clk pin filter control (t2cfilter), 18-24 t2csl, 18-14 ta,, 9-6 table stepper motor (tsm), d-8 tb, 3-21 tbl, 3-21, 3-25 tbrs1, tbrs0 - bits in biumcr, 17-14, 17-15 tbu, 3-21, 3-25 tc, 14-54, 14-60 tcie, 14-52, 14-61 tcnmcr, 16-26 tcr, 18-14 tcr1p, 18-13 tcr2 clock/gate control (t2cg), 18-13 tdre, 14-54 te, 14-51, 14-53 tea,, 9-6 termination signals,, 9-42 test register (qadctest), 13-9 test register (ramtst), 19-6 ticr, 18-16, 18-25 tie, 14-52, 14-61 time quanta clock, 16-9 stamp, 16-4, 16-12 time base, 3-21 timebasebus selecting, 17-14, 17-15 timebase,, 3-48 timer, 16-33 timer count register 1 prescaler control (tcr1p), 18-13 synchronize mode (tsync), 16-31 timing, instruction, 3-40 tor, 13-54 toucan address map, 16-22 bit timing configuration, 16-9 operation, 16-9 external pins, 16-2 initialization sequence, 16-13 interrupts, 16-21 message buffer address map, 16-26 operation, 16-3 receive process, 16-15 registers control register 0 (canctrl0), 16-29 control register 1 (ctrl1), 16-9 control register 1(canctrl1), 16-30 control register 2 (canctrl2), 16-32 control register 2 (ctrl2), 16-9 error and status register (estat), 16-34 free running timer register (timer), 16-33 interrupt configuration register (canicr), 16-28 flag register (iflag), 16-37 mask register (imask), 16-37 module configuration register (tcnmcr), 16-26 receive buffer 14 mask registers (rx14mskhi/lo), 16-34 buffer 15 mask registers (rx15mskhi/lo), 16-34 global mask registers (rxgmsklo/hi, 16-33 rx/tx error counter registers (rxectr/txectr), 16-38 test configuration register (cantcr), 16-28 special operating modes, 16-18 auto power save mode, 16-21 debug mode, 16-18 low-power stop mode, 16-19 transmit process, 16-14 tpu address map, 18-9 components, 18-2 freeze flag (tpuf), 18-16 function library, 18-5 host interface, 18-3 index-14 mpc565/mpc566 reference manual motorola interrupts, 18-6 microengine, 18-3 operation, 18-4 coherency, 18-5 emulation support, 18-5 event timing, 18-4 interchannel communication, 18-5 programmable channel service priority, 18-5 parameter ram, 18-3, 18-26 address map, 18-26 registers channel function select registers (cfsr), 18-18 interrupt enable register (cier) , 18-6, 18-17 status register (cisr) , 18-6, 18-21 priority registers (cpr), 18-21 decoded channel number register (dcnr), 18-22 development support control register (dscr), 18-14 support status register (dssr), 18-16 host sequence registers (hsqr), 18-19 service request registers (hssr), 18-20 link register (lr), 18-22 module configuration register (tpumcr), 18-13 service grant latch register (sglr), 18-22 test configuration register (tcr), 18-14 tpu interrupt configuration register (ticr), 18-16, 18-25 scheduler, 18-3 time bases, 18-2 timer channels, 18-2 tpu reference manual , 18-4, 18-20 tpu2 module configuration register 2 (tpumcr2), 18-23 tpuf, 18-16 tpumcr, 18-13 tpumcr2, 18-23 tr, 22-54 trace interrupt,, 3-59 transaction (bus),, 9-8 transfer length options, 14-41 time, 13-35 transfer acknowledge (ta),, 9-42 transfer error acknowledge (tea),, 9-42 transfer size (tsiz),, 9-39 transfer start (ts),, 9-38 transfers, alignment and packaging,, 9-30 transfers, burst-inhibited,, 9-18 transfers, termination signals,, 9-42 transmission complete (tc) flag, 14-60 interrupt enable (tcie), 14-61 transmit /receive status (tx/rx), 16-35 bit error (biterr), 16-35 complete bit (tc), 14-54 interrupt enable (tcie), 14-52 data register empty (tdre) flag, 14-54 error status flag (txwarn), 16-35 interrupt enable (tie), 14-52, 14-61 pin configuration control (txmode), 16-29 ram, 14-26 transmitter enable (te), 14-51 transmitter enable (te), 14-53, 14-59 tre, 22-56 trigger event, 13-28, 13-54 overrun error (tor), 13-54 ts,, 9-5 tsiz(0 1),, 9-4 tsiz0,, 9-1 tsiz1,, 9-1 tsm, d-8 t sr ,13-11 tsync, 16-31 tx/rx, 16-35 txectr, 16-38 txmode, 16-29 txwarn, 16-35 u uart, d-13 universal asynchronous receiver/transmitter (uart), d-13 parameters receiver parameters, d-14 transmitter parameters, d-13 unordered exceptions, 3-38 user instruction set architecture book 1 instruction fetching,, 3-44 user instruction set architecture (book 1) branch instructions,, 3-44 branch processor,, 3-44 computation modes,, 3-43 exceptions,, 3-43 motorola index index-15 fixed point-processor,, 3-44 instruction classes,, 3-43 load/store processor,, 3-45 reserved fields,, 3-43 using the tpu function library and tpu emulation mode ,18-5 ux bit, 3-15 v v cf , 13-75 v dda , 13-67, 13-71 ve bit, 3-16 vector table, exception, 3-39 vector table, exceptions, 3-39 v ih , 13-67 v il , 13-67 virtual environment architecture (book 2) operand placement effects,, 3-47 storage control instructions,, 3-47 timebase,, 3-48 voltage inputs, 13-66 reference pins, 13-71 v rh ,13-33,13-37,13-71,13-76 v rl ,13-37,13-71,13-76 v src , 13-75 v ssa ,13-67,13-71 vx bit, 3-15 vxcvi bit, 3-16 vxidi, 3-15 vximz bit, 3-16 vxisi, 3-15 vxsnan, 3-15 vxsoft bit, 3-16 vxsqrt bit, 3-16 vxvc bit, 3-16 vxzdz bit, 3-15 w wake,14-52,14-65 wake interrupt (wakeint), 16-36 wakeint, 16-20, 16-36 wakemsk, 16-20 wakeup address mark (wake), 14-52, 14-65 wired-or mode for qspi pins (womq), 14-20 for sci pins (woms), 14-52, 14-60 womq, 14-20 woms,14-52,14-60 wrap enable (wren), 14-23 to (wrto), 14-23 wraparound mode, 14-18 master, 14-42 wren, 14-23 write cycle data bus contents,, 9-32 wrto, 14-23 x xe bit, 3-16 xer, 3-19 xx bit, 3-15 z ze bit, 3-16 zx bit, 3-15 index-16 mpc565/mpc566 reference manual motorola |
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